From patchwork Tue Feb 6 05:18:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati PSSNV X-Patchwork-Id: 770827 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 587CC7F481; Tue, 6 Feb 2024 05:18:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707196734; cv=none; b=EiXeMm4AphYpWZhdsdyRzE7bWZLXzVnZzpCU5tFY9esJevrtSD1Y1OgJZ1eo2BP7ZBN2pXlzpy2IDsNzn/ai0XhgHyxOtZsmESR6YvZYJ5z7hBHgPGQUSbVROBTuGLs2wNPvwcTpSBHBbRCE71+Mdg2LxKVVpmwKse12dBEVkR8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707196734; c=relaxed/simple; bh=6h+LmYtuCU1+Fyu2YzlhuNMivgqKk9rPIHhCCb7JA58=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=CW7Jpwr417elKCGXkKC4WumYYY2nVxzKlZ+3saQWkm8Fc/jR1MJ+XiEsnSzQtKuDtqbg0AarAc/VKN4boK1XrbqGzc0r1VAJNwU8UxPfrdnIuKuH2y/KSI61w8Fw/+uj9hswJvZdfGzLjdVlBaqj45oSXqWHFTryBbngrdEkXtc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=G+DcUUhG; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="G+DcUUhG" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 4164owEr017716; Tue, 6 Feb 2024 05:18:47 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=wawvOBpPwBzbJDFoHDNSPf/5AKOqwPS5VS5YrxtE/Ts=; b=G+ DcUUhGG9+20UGunOlCE6Ovh80hyXCOeGbbHCUGSZLEfvd+e3P4TWN9UbWop64SiR zBrhGzIOxXJjeOzeOtxck94Jy8NvYiVKOgsn7cXCcVMvM5TwKCDnUjvC8ONKE8pi Urr+4GTpgrrHK/WvA1ntxwlMsDSc+WApqgiPkzpOms9PxtFudBBIYTThYqJow1D0 CK5QkhH2xle2Inpi9fs5PcQdAKNqL/kotBH0raEubEt2Z1nxAeEphkvezm5JypIY Qges5cX0FcRYq428doAiAs1X0j4BvxCNnkTTC3zeLek25ki20IYFQguPdj9ngWxm D4NobqpiZNBF4qHB3eEw== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3w2v72ahj4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 06 Feb 2024 05:18:47 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 4165Ik8M007501 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 6 Feb 2024 05:18:46 GMT Received: from hu-kriskura-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 5 Feb 2024 21:18:41 -0800 From: Krishna Kurapati To: Krzysztof Kozlowski , Rob Herring , Bjorn Andersson , Wesley Cheng , Konrad Dybcio , "Greg Kroah-Hartman" , Conor Dooley , Thinh Nguyen , Felipe Balbi CC: , , , , , , Krishna Kurapati Subject: [PATCH v14 1/9] dt-bindings: usb: Add bindings for multiport properties on DWC3 controller Date: Tue, 6 Feb 2024 10:48:17 +0530 Message-ID: <20240206051825.1038685-2-quic_kriskura@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240206051825.1038685-1-quic_kriskura@quicinc.com> References: <20240206051825.1038685-1-quic_kriskura@quicinc.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Ieq114dGrTVtzDuTKPPHRKalu9Q1HU4C X-Proofpoint-ORIG-GUID: Ieq114dGrTVtzDuTKPPHRKalu9Q1HU4C X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-05_18,2024-01-31_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 phishscore=0 clxscore=1015 spamscore=0 mlxscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 mlxlogscore=735 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401310000 definitions=main-2402060035 Add bindings to indicate properties required to support multiport on Synopsys DWC3 controller. Signed-off-by: Krishna Kurapati Reviewed-by: Bjorn Andersson --- .../devicetree/bindings/usb/snps,dwc3.yaml | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml index 8f5d250070c7..9227e200bcab 100644 --- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml @@ -85,15 +85,16 @@ properties: phys: minItems: 1 - maxItems: 2 + maxItems: 8 phy-names: minItems: 1 - maxItems: 2 - items: - enum: - - usb2-phy - - usb3-phy + maxItems: 8 + oneOf: + - items: + enum: [ usb2-phy, usb3-phy ] + - items: + pattern: "^usb[23]-[0-3]$" power-domains: description: From patchwork Tue Feb 6 05:18:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati PSSNV X-Patchwork-Id: 770826 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 728B67FBB2; Tue, 6 Feb 2024 05:19:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707196746; cv=none; b=m2AQ3OOMbx3FnYpR8kk1SijUVcs2ech1sse053OJIsFYmOaDqDyd00lThwLoPOz3xTf1uMh6lPNK2ImdrCadZtV0IcdZb8TXyRQlJhufOkUhgSvbStGVv1L4ufTTC/yRFDzJezbae+DdF8phDOVNWNx9MQCIrAqBaRGtXrffULo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707196746; c=relaxed/simple; bh=genjBk3uvlsaAJU2yoYHfO+ITR5u2b7rhyQVgSXjeaI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=IdDczZERg7fkUoKWKsCfZrh140hR8rPuKbuYTRTBJ7/olJUW66Qt+xNuPEOV0Wf83rP9ndNYB2mxlzS+w3ogqjMiE0XsO/+/cDkk1j7KazGGRkvwGTxOJr27aqTh6zVyooxyqJ8LoXmXLJe48HCNHorjdzz7b1SDdaR8dPB8x1A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=WlAS455d; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="WlAS455d" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 4164xaI5031651; Tue, 6 Feb 2024 05:18:59 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=+y0cDrTLtTyYxuXcifRN7tNYkgbdfiJfM2ekZ4zgrFI=; b=Wl AS455dnBkV/zhE4I8p8MDy22DEJ2qUhHsw6gjhGyJ1brBIBDKs8DYSpa0L+miLIl me3755BZ74+lW3pZAGYhhTTUk5s7sfuKwKcAG70CWqJ3Z9HK1ASfsrbqQ4SsKpVR G5ilZ63ISemNgm8ruTcIeJZhdW/gYVisx/4kezWOkfd4RWQ9c/NSPg489QOLCM7m kCbE9PYladxN3BX8iDHrg7mFbJg11az1ryClR0K57/xTNv+yiBXMXLoN/PxS33Ls lltypJTvVKm4qtK/slRT3BS9RCyM1kS57rq2x1+x3spbtIXdbNSYHk7sjaa0WExy Z3jfQmQPxXq9sJ8ztn9w== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3w3e7g0125-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 06 Feb 2024 05:18:59 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 4165Iwfg026025 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 6 Feb 2024 05:18:58 GMT Received: from hu-kriskura-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 5 Feb 2024 21:18:53 -0800 From: Krishna Kurapati To: Krzysztof Kozlowski , Rob Herring , Bjorn Andersson , Wesley Cheng , Konrad Dybcio , "Greg Kroah-Hartman" , Conor Dooley , Thinh Nguyen , Felipe Balbi CC: , , , , , , Krishna Kurapati , Johan Hovold , Johan Hovold Subject: [PATCH v14 3/9] usb: dwc3: core: Skip setting event buffers for host only controllers Date: Tue, 6 Feb 2024 10:48:19 +0530 Message-ID: <20240206051825.1038685-4-quic_kriskura@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240206051825.1038685-1-quic_kriskura@quicinc.com> References: <20240206051825.1038685-1-quic_kriskura@quicinc.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: CUgJNCvzaQBnG66iT1RDAKlIF5FiX3w8 X-Proofpoint-ORIG-GUID: CUgJNCvzaQBnG66iT1RDAKlIF5FiX3w8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-05_18,2024-01-31_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 adultscore=0 mlxscore=0 mlxlogscore=894 lowpriorityscore=0 bulkscore=0 spamscore=0 clxscore=1015 priorityscore=1501 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401310000 definitions=main-2402060035 On some SoC's like SA8295P where the tertiary controller is host-only capable, GEVTADDRHI/LO, GEVTSIZ, GEVTCOUNT registers are not accessible. Trying to access them leads to a crash. For DRD/Peripheral supported controllers, event buffer setup is done again in gadget_pullup. Skip setup or cleanup of event buffers if controller is host-only capable. Suggested-by: Johan Hovold Signed-off-by: Krishna Kurapati Acked-by: Thinh Nguyen Reviewed-by: Johan Hovold Reviewed-by: Bjorn Andersson --- drivers/usb/dwc3/core.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 965eaad195fb..c47fec10b231 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -486,6 +486,13 @@ static void dwc3_free_event_buffers(struct dwc3 *dwc) static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length) { struct dwc3_event_buffer *evt; + unsigned int hw_mode; + + hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0); + if (hw_mode == DWC3_GHWPARAMS0_MODE_HOST) { + dwc->ev_buf = NULL; + return 0; + } evt = dwc3_alloc_one_event_buffer(dwc, length); if (IS_ERR(evt)) { @@ -507,6 +514,9 @@ int dwc3_event_buffers_setup(struct dwc3 *dwc) { struct dwc3_event_buffer *evt; + if (!dwc->ev_buf) + return 0; + evt = dwc->ev_buf; evt->lpos = 0; dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), @@ -524,6 +534,9 @@ void dwc3_event_buffers_cleanup(struct dwc3 *dwc) { struct dwc3_event_buffer *evt; + if (!dwc->ev_buf) + return; + evt = dwc->ev_buf; evt->lpos = 0; From patchwork Tue Feb 6 05:18:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati PSSNV X-Patchwork-Id: 770825 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A88A80030; Tue, 6 Feb 2024 05:19:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707196758; cv=none; b=YRfLkoibg7xGiFndUwo7jDuBxw38/NkJNFQ0MmukBHK1jjOAEL1e43k5voCiMpxLnqqTB80pavL7R9BuDGLirDyftEW3yg8zp4ffpJyZeJlaFfEE4YRez+V35NLOpS0PUdu0+RhoJRf4avY5uAnvv3iswvgASjkejPYiIlZCND0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707196758; c=relaxed/simple; bh=d6RUi8RWHKHem8D5tyy6xIBkwzP4qMJxgZ5mnLqETPM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=b6sFHpO2MamnDdMtrMQ/JLyXsdxmYAP5IRO28StgZhyyWB4Mu6m1ggtYz4njD6hOwsuhcqKDu8/ddT7LI6xC9O53uR406hw6C93YI6JfHwVVT8QxPTSvXAi4pMSszMTA2RB9Dsotkbi2oQXFz7YgIGoGOoQ/3QJb93bp5V9peu0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=g5qPkAvr; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="g5qPkAvr" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 4160fAwU032520; Tue, 6 Feb 2024 05:19:11 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=1lJSNc5F2+6JWs6y/i6NpltceXCQVsqpr3M1ktGw2k8=; b=g5 qPkAvrwRZrkLdfbkknvdJm0Jj0mXHFFwRjgt+B8aNAsbxeRLReHAWYMm4gXpDIdt YBI+dsqiOno1IPzPe+ok7R+MjumK8RoB+yFjjx+S/bjVo0GarYikFrm4ZqC2YbLZ NfEj/wycQmJhYKZnLTloFedf+fEaQPQBk+8ZAG8Mgs8N6cYxUrt+RqBt1h5xsEpZ 2krnEdvOtyB2YrOMRSDenh/s7TePb7vQCocAtc0gbDU7CpkouP6D9QwfbMWVGItM slJik8mw3wH8JdYC0csb57yQ9tYuEuAu/D+RfTKQRs+WH/UkpGvFwK6l4azva+Du wNoaR2l3X6b9oeVXywcg== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3w3a1brg00-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 06 Feb 2024 05:19:11 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 4165JASN010090 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 6 Feb 2024 05:19:10 GMT Received: from hu-kriskura-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 5 Feb 2024 21:19:05 -0800 From: Krishna Kurapati To: Krzysztof Kozlowski , Rob Herring , Bjorn Andersson , Wesley Cheng , Konrad Dybcio , "Greg Kroah-Hartman" , Conor Dooley , Thinh Nguyen , Felipe Balbi CC: , , , , , , Krishna Kurapati Subject: [PATCH v14 5/9] dt-bindings: usb: qcom, dwc3: Add bindings for SC8280 Multiport Date: Tue, 6 Feb 2024 10:48:21 +0530 Message-ID: <20240206051825.1038685-6-quic_kriskura@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240206051825.1038685-1-quic_kriskura@quicinc.com> References: <20240206051825.1038685-1-quic_kriskura@quicinc.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: PmLPAFLS2hzo0ydDlMg1_RKulnlahFQb X-Proofpoint-ORIG-GUID: PmLPAFLS2hzo0ydDlMg1_RKulnlahFQb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-05_18,2024-01-31_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=639 phishscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 priorityscore=1501 suspectscore=0 impostorscore=0 clxscore=1015 mlxscore=0 malwarescore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401310000 definitions=main-2402060035 Add the compatible string for SC8280 Multiport USB controller from Qualcomm. There are 4 power event irq interrupts supported by this controller (one for each port of multiport). Added all the 4 as non-optional interrupts for SC8280XP-MP Also each port of multiport has one DP and oen DM IRQ. Add all DP/DM IRQ's related to 4 ports of SC8280XP Teritiary controller. Also added ss phy irq for both SS Ports. Signed-off-by: Krishna Kurapati Reviewed-by: Bjorn Andersson Reviewed-by: Rob Herring --- .../devicetree/bindings/usb/qcom,dwc3.yaml | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml index 63d150b216c5..cc7cf592c029 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml @@ -30,6 +30,7 @@ properties: - qcom,sc7180-dwc3 - qcom,sc7280-dwc3 - qcom,sc8280xp-dwc3 + - qcom,sc8280xp-dwc3-mp - qcom,sdm660-dwc3 - qcom,sdm670-dwc3 - qcom,sdm845-dwc3 @@ -282,6 +283,7 @@ allOf: contains: enum: - qcom,sc8280xp-dwc3 + - qcom,sc8280xp-dwc3-mp - qcom,x1e80100-dwc3 then: properties: @@ -470,6 +472,37 @@ allOf: - const: dm_hs_phy_irq - const: ss_phy_irq + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-dwc3-mp + then: + properties: + interrupts: + maxItems: 18 + interrupt-names: + items: + - const: pwr_event_1 + - const: pwr_event_2 + - const: pwr_event_3 + - const: pwr_event_4 + - const: hs_phy_1 + - const: hs_phy_2 + - const: hs_phy_3 + - const: hs_phy_4 + - const: dp_hs_phy_1 + - const: dm_hs_phy_1 + - const: dp_hs_phy_2 + - const: dm_hs_phy_2 + - const: dp_hs_phy_3 + - const: dm_hs_phy_3 + - const: dp_hs_phy_4 + - const: dm_hs_phy_4 + - const: ss_phy_1 + - const: ss_phy_2 + additionalProperties: false examples: From patchwork Tue Feb 6 05:18:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati PSSNV X-Patchwork-Id: 770824 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7904811FB; Tue, 6 Feb 2024 05:19:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707196771; cv=none; b=qgZRRKM5UC0sAHeKYMaB2TaQUH8I5Od/8zfHqQk8M4h5hWGZE8VzYh9nmIxflTmDcJKmnjppRM2Zyg2julEZ1xBxVTVCbf/OVYfyk6ppwxD/7IaryBHCeSm/dpT0tSD/peo9q4/NC0+z1hBH1wA70ydh67oAjjnEy1spsodQ1UI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707196771; c=relaxed/simple; bh=K6vv5PUv7Hvs2Nb47hS9AI/MSIxACvXEuFq55bLagLk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jpAsLAkeEV9kiN4pgpcLM3kLNCqxLQiGJbaY3FFX6waTwUs/gpeldMKRLWisyRZcG3fYslMbEfBDSfiffzNCTMeUFvNQjG5ofxqml0EJS9iUBs1Crq9/x5+g3U7Zk3fjDd87H6B7gD2IlqAq9+hm05OcZgMXy8Do9Ui2STkyYAQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=BQChPMIQ; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="BQChPMIQ" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 4164VVpZ025246; Tue, 6 Feb 2024 05:19:23 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=A5LORlwoq8/VmItymSyQS74CIvvcuo3DBsXKTBRhhTU=; b=BQ ChPMIQb/sL1mqVm6aupPh09grqXnpRy6+684GSkeFF/pmnZqwLAsh4R1dwHCOzbi pmtwihCT8MVTC3LXVZ0FPpcatQKKziFiZpLM0wyQPo6pLvs/mU7LqAGVSlaH3M+3 aVnB98xMr6ywNYwHKQN0hph3hqppbaKPk6yN4u0Q2R35DCN8Zn9YwQ7GlRrNmKza 93N/goSAERS0J1lnMwnD07rh3GHzY1BPTsFoSQ+OXDqVwt+qVCO1A3ASuVzt58Di GNrTJPTK7n0QY0wIppoU/MTnENJaEi4kwXHrC6/sz/kN8p2Y9NH1KcMqqInzEvV8 h5rOl/ZgLASr0mTxoRMw== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3w31wnsp1w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 06 Feb 2024 05:19:23 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 4165JMpv026417 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 6 Feb 2024 05:19:22 GMT Received: from hu-kriskura-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 5 Feb 2024 21:19:17 -0800 From: Krishna Kurapati To: Krzysztof Kozlowski , Rob Herring , Bjorn Andersson , Wesley Cheng , Konrad Dybcio , "Greg Kroah-Hartman" , Conor Dooley , Thinh Nguyen , Felipe Balbi CC: , , , , , , Krishna Kurapati Subject: [PATCH v14 7/9] usb: dwc3: qcom: Refactor IRQ handling in glue driver Date: Tue, 6 Feb 2024 10:48:23 +0530 Message-ID: <20240206051825.1038685-8-quic_kriskura@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240206051825.1038685-1-quic_kriskura@quicinc.com> References: <20240206051825.1038685-1-quic_kriskura@quicinc.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: mzYQx3B5EGQj9NX0pZIjfNz6wlnx-WS9 X-Proofpoint-GUID: mzYQx3B5EGQj9NX0pZIjfNz6wlnx-WS9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-05_18,2024-01-31_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 phishscore=0 mlxlogscore=794 spamscore=0 lowpriorityscore=0 impostorscore=0 bulkscore=0 clxscore=1015 malwarescore=0 suspectscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401310000 definitions=main-2402060035 On multiport supported controllers, each port has its own DP/DM and SS (if super speed capable) interrupts. As per the bindings, their interrupt names differ from standard ones having "_x" added as suffix (x indicates port number). Refactor dwc3_qcom_setup_irq() call to parse multiport interrupts along with non-multiport ones. Signed-off-by: Krishna Kurapati Reviewed-by: Bjorn Andersson Acked-by: Thinh Nguyen --- drivers/usb/dwc3/dwc3-qcom.c | 222 +++++++++++++++++++++++++---------- 1 file changed, 161 insertions(+), 61 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c index 08df29584366..a20d63a791bd 100644 --- a/drivers/usb/dwc3/dwc3-qcom.c +++ b/drivers/usb/dwc3/dwc3-qcom.c @@ -53,17 +53,33 @@ #define APPS_USB_AVG_BW 0 #define APPS_USB_PEAK_BW MBps_to_icc(40) +#define NUM_PHY_IRQ 4 + +enum dwc3_qcom_phy_index { + DP_HS_PHY_IRQ_INDEX, + DM_HS_PHY_IRQ_INDEX, + SS_PHY_IRQ_INDEX, + QUSB2_PHY_IRQ_INDEX, +}; + struct dwc3_acpi_pdata { u32 qscratch_base_offset; u32 qscratch_base_size; u32 dwc3_core_base_size; - int qusb2_phy_irq_index; - int dp_hs_phy_irq_index; - int dm_hs_phy_irq_index; - int ss_phy_irq_index; + /* + * The phy_irq_index corresponds to ACPI indexes of (in order) + * DP/DM/SS/QUSB2 IRQ's respectively. + */ + int phy_irq_index[NUM_PHY_IRQ]; bool is_urs; }; +struct dwc3_qcom_port { + int dp_hs_phy_irq; + int dm_hs_phy_irq; + int ss_phy_irq; +}; + struct dwc3_qcom { struct device *dev; void __iomem *qscratch_base; @@ -74,9 +90,7 @@ struct dwc3_qcom { struct reset_control *resets; int qusb2_phy_irq; - int dp_hs_phy_irq; - int dm_hs_phy_irq; - int ss_phy_irq; + struct dwc3_qcom_port port_info[DWC3_MAX_PORTS]; enum usb_device_speed usb2_speed; struct extcon_dev *edev; @@ -91,6 +105,7 @@ struct dwc3_qcom { bool pm_suspended; struct icc_path *icc_path_ddr; struct icc_path *icc_path_apps; + u8 num_ports; }; static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val) @@ -375,16 +390,16 @@ static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom) dwc3_qcom_disable_wakeup_irq(qcom->qusb2_phy_irq); if (qcom->usb2_speed == USB_SPEED_LOW) { - dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq); + dwc3_qcom_disable_wakeup_irq(qcom->port_info[0].dm_hs_phy_irq); } else if ((qcom->usb2_speed == USB_SPEED_HIGH) || (qcom->usb2_speed == USB_SPEED_FULL)) { - dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq); + dwc3_qcom_disable_wakeup_irq(qcom->port_info[0].dp_hs_phy_irq); } else { - dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq); - dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq); + dwc3_qcom_disable_wakeup_irq(qcom->port_info[0].dp_hs_phy_irq); + dwc3_qcom_disable_wakeup_irq(qcom->port_info[0].dm_hs_phy_irq); } - dwc3_qcom_disable_wakeup_irq(qcom->ss_phy_irq); + dwc3_qcom_disable_wakeup_irq(qcom->port_info[0].ss_phy_irq); } static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom) @@ -401,20 +416,20 @@ static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom) */ if (qcom->usb2_speed == USB_SPEED_LOW) { - dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq, - IRQ_TYPE_EDGE_FALLING); + dwc3_qcom_enable_wakeup_irq(qcom->port_info[0].dm_hs_phy_irq, + IRQ_TYPE_EDGE_FALLING); } else if ((qcom->usb2_speed == USB_SPEED_HIGH) || (qcom->usb2_speed == USB_SPEED_FULL)) { - dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq, - IRQ_TYPE_EDGE_FALLING); + dwc3_qcom_enable_wakeup_irq(qcom->port_info[0].dp_hs_phy_irq, + IRQ_TYPE_EDGE_FALLING); } else { - dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq, - IRQ_TYPE_EDGE_RISING); - dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq, - IRQ_TYPE_EDGE_RISING); + dwc3_qcom_enable_wakeup_irq(qcom->port_info[0].dp_hs_phy_irq, + IRQ_TYPE_EDGE_RISING); + dwc3_qcom_enable_wakeup_irq(qcom->port_info[0].dm_hs_phy_irq, + IRQ_TYPE_EDGE_RISING); } - dwc3_qcom_enable_wakeup_irq(qcom->ss_phy_irq, 0); + dwc3_qcom_enable_wakeup_irq(qcom->port_info[0].ss_phy_irq, 0); } static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup) @@ -535,6 +550,74 @@ static int dwc3_qcom_get_irq(struct platform_device *pdev, return ret; } +static int dwc3_qcom_get_irq_index(const char *irq_name) +{ + /* + * Parse IRQ index based on prefixes from interrupt name. + * Return -1 incase of an invalid interrupt name. + */ + int irq_index = -1; + + if (strncmp(irq_name, "dp_hs_phy", strlen("dp_hs_phy")) == 0) + irq_index = DP_HS_PHY_IRQ_INDEX; + else if (strncmp(irq_name, "dm_hs_phy", strlen("dm_hs_phy")) == 0) + irq_index = DM_HS_PHY_IRQ_INDEX; + else if (strncmp(irq_name, "ss_phy", strlen("ss_phy")) == 0) + irq_index = SS_PHY_IRQ_INDEX; + else if (strncmp(irq_name, "qusb2_phy", strlen("qusb2_phy")) == 0) + irq_index = QUSB2_PHY_IRQ_INDEX; + return irq_index; +} + +static int dwc3_qcom_get_port_index(const char *irq_name, int irq_index) +{ + int port_index = -1; + + switch (irq_index) { + case DP_HS_PHY_IRQ_INDEX: + if (strcmp(irq_name, "dp_hs_phy_irq") == 0) + port_index = 1; + else + sscanf(irq_name, "dp_hs_phy_%d", &port_index); + break; + case DM_HS_PHY_IRQ_INDEX: + if (strcmp(irq_name, "dm_hs_phy_irq") == 0) + port_index = 1; + else + sscanf(irq_name, "dm_hs_phy_%d", &port_index); + break; + case SS_PHY_IRQ_INDEX: + if (strcmp(irq_name, "ss_phy_irq") == 0) + port_index = 1; + else + sscanf(irq_name, "ss_phy_%d", &port_index); + break; + case QUSB2_PHY_IRQ_INDEX: + port_index = 1; + break; + } + + if (port_index <= 0 || port_index > DWC3_MAX_PORTS) + port_index = -1; + + return port_index; +} + +static int dwc3_qcom_get_acpi_index(struct dwc3_qcom *qcom, int irq_index, + int port_index) +{ + const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata; + + /* + * Currently multiport supported targets don't have an ACPI variant. + * So return -1 if we are not dealing with first port of the controller. + */ + if (!pdata || port_index != 1) + return -1; + + return pdata->phy_irq_index[irq_index]; +} + static int dwc3_qcom_request_irq(struct dwc3_qcom *qcom, int irq, const char *name) { @@ -554,44 +637,67 @@ static int dwc3_qcom_request_irq(struct dwc3_qcom *qcom, int irq, static int dwc3_qcom_setup_irq(struct platform_device *pdev) { struct dwc3_qcom *qcom = platform_get_drvdata(pdev); - const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata; + struct device_node *np = pdev->dev.of_node; + const char **irq_names; + int port_index; + int acpi_index; + int irq_count; + int irq_index; int irq; int ret; + int i; - irq = dwc3_qcom_get_irq(pdev, "qusb2_phy", - pdata ? pdata->qusb2_phy_irq_index : -1); - if (irq > 0) { - ret = dwc3_qcom_request_irq(qcom, irq, "hs_phy_irq"); - if (ret) - return ret; - qcom->qusb2_phy_irq = irq; - } + irq_count = of_property_count_strings(np, "interrupt-names"); + if (irq_count < 0) + return -EINVAL; - irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq", - pdata ? pdata->dp_hs_phy_irq_index : -1); - if (irq > 0) { - ret = dwc3_qcom_request_irq(qcom, irq, "dp_hs_phy_irq"); - if (ret) - return ret; - qcom->dp_hs_phy_irq = irq; - } + irq_names = devm_kcalloc(&pdev->dev, irq_count, sizeof(*irq_names), GFP_KERNEL); + if (!irq_names) + return -ENOMEM; - irq = dwc3_qcom_get_irq(pdev, "dm_hs_phy_irq", - pdata ? pdata->dm_hs_phy_irq_index : -1); - if (irq > 0) { - ret = dwc3_qcom_request_irq(qcom, irq, "dm_hs_phy_irq"); - if (ret) - return ret; - qcom->dm_hs_phy_irq = irq; - } + ret = of_property_read_string_array(np, "interrupt-names", + irq_names, irq_count); + if (!ret) + return ret; - irq = dwc3_qcom_get_irq(pdev, "ss_phy_irq", - pdata ? pdata->ss_phy_irq_index : -1); - if (irq > 0) { - ret = dwc3_qcom_request_irq(qcom, irq, "ss_phy_irq"); - if (ret) - return ret; - qcom->ss_phy_irq = irq; + for (i = 0; i < irq_count; i++) { + irq_index = dwc3_qcom_get_irq_index(irq_names[i]); + if (irq_index == -1) { + dev_err(&pdev->dev, "Unknown interrupt-name \"%s\" found\n", irq_names[i]); + continue; + } + port_index = dwc3_qcom_get_port_index(irq_names[i], irq_index); + if (port_index == -1) { + dev_err(&pdev->dev, "Invalid interrupt-name suffix \"%s\"\n", irq_names[i]); + continue; + } + + acpi_index = dwc3_qcom_get_acpi_index(qcom, irq_index, port_index); + + irq = dwc3_qcom_get_irq(pdev, irq_names[i], acpi_index); + if (irq > 0) { + ret = dwc3_qcom_request_irq(qcom, irq, irq_names[i]); + if (ret) + return ret; + + switch (irq_index) { + case DP_HS_PHY_IRQ_INDEX: + qcom->port_info[port_index - 1].dp_hs_phy_irq = irq; + break; + case DM_HS_PHY_IRQ_INDEX: + qcom->port_info[port_index - 1].dm_hs_phy_irq = irq; + break; + case SS_PHY_IRQ_INDEX: + qcom->port_info[port_index - 1].ss_phy_irq = irq; + break; + case QUSB2_PHY_IRQ_INDEX: + qcom->qusb2_phy_irq = irq; + break; + } + + if (qcom->num_ports < port_index) + qcom->num_ports = port_index; + } } return 0; @@ -1053,20 +1159,14 @@ static const struct dwc3_acpi_pdata sdm845_acpi_pdata = { .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET, .qscratch_base_size = SDM845_QSCRATCH_SIZE, .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE, - .qusb2_phy_irq_index = 1, - .dp_hs_phy_irq_index = 4, - .dm_hs_phy_irq_index = 3, - .ss_phy_irq_index = 2 + .phy_irq_index = {4, 3, 2, 1}, }; static const struct dwc3_acpi_pdata sdm845_acpi_urs_pdata = { .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET, .qscratch_base_size = SDM845_QSCRATCH_SIZE, .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE, - .qusb2_phy_irq_index = 1, - .dp_hs_phy_irq_index = 4, - .dm_hs_phy_irq_index = 3, - .ss_phy_irq_index = 2, + .phy_irq_index = {4, 3, 2, 1}, .is_urs = true, }; From patchwork Tue Feb 6 05:18:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Kurapati PSSNV X-Patchwork-Id: 770823 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A278F81AA3; Tue, 6 Feb 2024 05:19:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707196781; cv=none; b=tI6KtVuXag+Gh2fIev8IoNRGA7z7wknx/KAXxzWj0wZcqILL79b+7e1zfkox3ePQ4U1Ro2A0aCfMD1mgQactx2UM2MrFGQv03Cs/oWzsw8epxByFQ2rlLKDUtGqa0D91ffh46WyZ0XVvV3/iRkQuoYBiPySdMCcY9qaMjHz8ypU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707196781; c=relaxed/simple; bh=ZWXdXoRoci2I2JY1vAA8SZHj20GPexRSHmRz/CFI7BI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=nqdgLN+ejHU8EKuTJOjMfY0q0rHmI/0HiCN/gDwih1k7RKeV9Lpqpamo+ip0gr5XmZpxZZTM31D8OyJYJ8yfXeDGbIAMh1IG1s5fhQuG5kTpVJnBgAlQCNqo/bIYcMPbt5r5i195l7SOrMypvyrPbB3wzX+BcEvUfVSZohibnDg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=G28tMiBQ; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="G28tMiBQ" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 4163mc8U008538; Tue, 6 Feb 2024 05:19:35 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=jR0CDxm9qu95XIEKbUM20OhmF4Uf8b9WqGbgZ5c0X/U=; b=G2 8tMiBQxiWmeuehouUYkhsJrsDrtHWmez4eez0uSmsovrA+yGJdbtflqtQYXQ21N8 zC8MSFoYZjjBT55PedTkUNvJJ72O9jnEe/cWKJM33XDGoP2dQd8dIwF9Gx71utvv I4LYNm+VJ7Ve+x7x1rSwNtRoa52vxasao7oiDHJPZHyecgOy/kE2qeuQf4rDMX8f uEpSmQVKh7696b1EJqeQ/du1s31hx2dMnkcb52atrJqdggYq5+m27yVf2Pzld8xN FJn3YXxxGgKBWEfZ6X12eEGKTgs22ski0SR5tPJi74jlcSxljRqmoyxFRmTL1PyA j5oX26V6NshW/kFRg9ZA== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3w2v25ae8q-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 06 Feb 2024 05:19:34 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 4165JYtI003589 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 6 Feb 2024 05:19:34 GMT Received: from hu-kriskura-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 5 Feb 2024 21:19:29 -0800 From: Krishna Kurapati To: Krzysztof Kozlowski , Rob Herring , Bjorn Andersson , Wesley Cheng , Konrad Dybcio , "Greg Kroah-Hartman" , Conor Dooley , Thinh Nguyen , Felipe Balbi CC: , , , , , , Krishna Kurapati Subject: [PATCH v14 9/9] usb: dwc3: qcom: Add multiport suspend/resume support for wrapper Date: Tue, 6 Feb 2024 10:48:25 +0530 Message-ID: <20240206051825.1038685-10-quic_kriskura@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240206051825.1038685-1-quic_kriskura@quicinc.com> References: <20240206051825.1038685-1-quic_kriskura@quicinc.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Hjm0P1XVd4Dcj1VoXvHrux-UxDqqINnW X-Proofpoint-GUID: Hjm0P1XVd4Dcj1VoXvHrux-UxDqqINnW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-05_18,2024-01-31_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 mlxscore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 mlxlogscore=778 malwarescore=0 clxscore=1015 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2401310000 definitions=main-2402060035 Power event IRQ stat registers are present for each port connected to controller. Add support for modifying all power event irq stat registers present in wrapper. Signed-off-by: Krishna Kurapati Reviewed-by: Bjorn Andersson Acked-by: Thinh Nguyen --- drivers/usb/dwc3/dwc3-qcom.c | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c index 572dc3fdae12..e789745a9468 100644 --- a/drivers/usb/dwc3/dwc3-qcom.c +++ b/drivers/usb/dwc3/dwc3-qcom.c @@ -37,7 +37,11 @@ #define PIPE3_PHYSTATUS_SW BIT(3) #define PIPE_UTMI_CLK_DIS BIT(8) -#define PWR_EVNT_IRQ_STAT_REG 0x58 +#define PWR_EVNT_IRQ1_STAT_REG 0x58 +#define PWR_EVNT_IRQ2_STAT_REG 0x1dc +#define PWR_EVNT_IRQ3_STAT_REG 0x228 +#define PWR_EVNT_IRQ4_STAT_REG 0x238 + #define PWR_EVNT_LPM_IN_L2_MASK BIT(4) #define PWR_EVNT_LPM_OUT_L2_MASK BIT(5) @@ -109,6 +113,13 @@ struct dwc3_qcom { u8 num_ports; }; +static const u32 pwr_evnt_irq_stat_reg_offset[DWC3_MAX_PORTS] = { + PWR_EVNT_IRQ1_STAT_REG, + PWR_EVNT_IRQ2_STAT_REG, + PWR_EVNT_IRQ3_STAT_REG, + PWR_EVNT_IRQ4_STAT_REG, +}; + static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val) { u32 reg; @@ -444,9 +455,11 @@ static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup) if (qcom->is_suspended) return 0; - val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG); - if (!(val & PWR_EVNT_LPM_IN_L2_MASK)) - dev_err(qcom->dev, "HS-PHY not in L2\n"); + for (i = 0; i < qcom->num_ports; i++) { + val = readl(qcom->qscratch_base + pwr_evnt_irq_stat_reg_offset[i]); + if (!(val & PWR_EVNT_LPM_IN_L2_MASK)) + dev_err(qcom->dev, "Port-%d HS-PHY not in L2\n", i + 1); + } for (i = qcom->num_clocks - 1; i >= 0; i--) clk_disable_unprepare(qcom->clks[i]); @@ -491,9 +504,12 @@ static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup) if (ret) dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret); - /* Clear existing events from PHY related to L2 in/out */ - dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG, - PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK); + for (i = 0; i < qcom->num_ports; i++) { + /* Clear existing events from PHY related to L2 in/out */ + dwc3_qcom_setbits(qcom->qscratch_base, + pwr_evnt_irq_stat_reg_offset[i], + PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK); + } qcom->is_suspended = false;