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([82.78.167.154]) by smtp.gmail.com with ESMTPSA id l30-20020a05600c1d1e00b0040e541ddcb1sm8307234wms.33.2024.02.05.03.27.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Feb 2024 03:27:10 -0800 (PST) From: Claudiu X-Google-Original-From: Claudiu To: wsa+renesas@sang-engineering.com, ulf.hansson@linaro.org, yoshihiro.shimoda.uh@renesas.com, masaharu.hayakawa.ry@renesas.com, takeshi.saito.xv@renesas.com Cc: linux-mmc@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, claudiu.beznea@tuxon.dev, Claudiu Beznea Subject: [PATCH v3] mmc: renesas_sdhi: Fix change point of data handling Date: Mon, 5 Feb 2024 13:27:02 +0200 Message-Id: <20240205112702.213050-1-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Claudiu Beznea On latest kernel revisions it has been noticed (on a RZ/G3S system) that when booting Linux and root file system is on eMMC, at some point in the booting process, when the systemd applications are started, the "mmc0: tuning execution failed: -5" message is displayed on console. On kernel v6.7-rc5 this is reproducible in 90% of the boots. This was missing on the same system with kernel v6.5.0-rc1. It was also noticed on kernel revisions v6.6-rcX on a RZ/G2UL based system but not on the kernel this fix is based on (v6.7-rc5). Investigating it on RZ/G3S lead to the conclusion that every time the issue is reproduced all the probed TAPs are OK. According to datasheet, when this happens the change point of data need to be considered for tuning. Previous code considered the change point of data happens when the content of the SMPCMP register is zero. According to RZ/V2M hardware manual, chapter "Change Point of the Input Data" (as this is the most clear description that I've found about change point of the input data and all RZ hardware manual are similar on this chapter), at the time of tuning, data is captured by the previous and next TAPs and the result is stored in the SMPCMP register (previous TAP in bits 22..16, next TAP in bits 7..0). If there is a mismatch b/w the previous and the next TAPs, it indicates that there is a change point of the input data. To comply with this, the patch checks if this mismatch is present and updates the priv->smpcmp mask only if it is not. Previous code checked if the value of SMPCMP register was zero. However, on RZ/G3S, this leads to failues as it may happen, e.g., the following: CMPNGU=0x0e, CMPNGD=0x0e, SMPCMP=0x000e000e. Along with it, as mmc_send_tuning() may return with error even before the MMC command reach the controller (and because at that point cmd_error = 0), the update of priv->smpcmp mask has been done only if the return value of mmc_send_tuning(mmc, opcode, &cmd_error) is 0 (success). This change has been checked on the devices with the following DTSes by doing 100 consecutive boots and checking for the tuning failure message: - r9a08g045s33-smarc.dts - r8a7742-iwg21d-q7.dts - r8a7743-iwg20d-q7.dts - r8a7744-iwg20d-q7.dts - r8a7745-iwg22d-sodimm.dts - r8a77470-iwg23s-sbc.dts - r8a774a1-hihope-rzg2m-ex.dts - r8a774b1-hihope-rzg2n-ex.dts - r8a774c0-ek874.dts - r8a774e1-hihope-rzg2h-ex.dts - r9a07g043u11-smarc-rzg2ul.dts - r9a07g044c2-smarc-rzg2lc.dts - r9a07g044l2-smarc-rzg2l.dts - r9a07g054l2-smarc-rzv2l.dts Fixes: 5fb6bf51f6d1 ("mmc: renesas_sdhi: improve TAP selection if all TAPs are good") Signed-off-by: Claudiu Beznea --- Changes in v3: - set priv->smpcmp if cmpngu_data == cmpngd_data and return code of mmc_send_tuning() is zero - removed workaround introduced previously in renesas_sdhi_select_tuning() as it is not needed with the code from v3 - update patch description Changes in v2: - read the SH_MOBILE_SDHI_SCC_SMPCMP register only on success path of mmc_send_tuning() drivers/mmc/host/renesas_sdhi_core.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c index c675dec587ef..8871521e1274 100644 --- a/drivers/mmc/host/renesas_sdhi_core.c +++ b/drivers/mmc/host/renesas_sdhi_core.c @@ -18,6 +18,7 @@ * */ +#include #include #include #include @@ -312,6 +313,8 @@ static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8) #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24) #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(8) | BIT(24)) +#define SH_MOBILE_SDHI_SCC_SMPCMP_CMPNGU_DATA GENMASK(23, 16) +#define SH_MOBILE_SDHI_SCC_SMPCMP_CMPNGD_DATA GENMASK(7, 0) #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4) #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31) @@ -703,11 +706,18 @@ static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode) /* Set sampling clock position */ sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num); - if (mmc_send_tuning(mmc, opcode, &cmd_error) == 0) - set_bit(i, priv->taps); + if (mmc_send_tuning(mmc, opcode, &cmd_error) == 0) { + u32 val, cmpngu_data, cmpngd_data; + + val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP); + cmpngu_data = FIELD_GET(SH_MOBILE_SDHI_SCC_SMPCMP_CMPNGU_DATA, val); + cmpngd_data = FIELD_GET(SH_MOBILE_SDHI_SCC_SMPCMP_CMPNGD_DATA, val); + + if (cmpngu_data == cmpngd_data) + set_bit(i, priv->smpcmp); - if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0) - set_bit(i, priv->smpcmp); + set_bit(i, priv->taps); + } if (cmd_error) mmc_send_abort_tuning(mmc, opcode);