From patchwork Sat Feb 3 04:05:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 770284 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE3B910A09; Sat, 3 Feb 2024 04:04:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706933046; cv=none; b=Nf2DJ1Y5P2NM8NuoHzFFi6Qn2SSD3pU5CcZRsTHbIwvWYwclRpBaM5kdhFo8R02Herj6VtnWa+gL48yPFmzOtll2iyDZ4knmtztmr8Ga+lvLViwtAZ8QYxCE8gWyj3/Hor5EihC49HvFNSz5uRI2gKgnv3K4fafWy3+VaZzU/eQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706933046; c=relaxed/simple; bh=+cMc8OL/bddGbgnV2+93XfCuqy+4YOnvUbLH8EZgxrc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=ZT9pUdL9MRBCw9ULaJttkdeBZBDRLWajMz0ZYKGhP0Iyo37HmgQipMGjzdZDwwzsYYD8XmKz5SlnMOLeBX7p8dc63RRWSz9mhv3RoFBrouTcuzxx1Tobi0E0aoqNd57RtdcIk2zqedtMmrTBYEJ/4l32k2gxH1bFV3kFUTI6T5M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=j53Z1fsd; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="j53Z1fsd" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706933045; x=1738469045; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=+cMc8OL/bddGbgnV2+93XfCuqy+4YOnvUbLH8EZgxrc=; b=j53Z1fsdXb3zOXIW03PK5qh+cXDvWCYOxaIpzAKiyJJ4fgBr3gVHKsEm s4y0R7THlt6uUskSZwCO9WkZ49DhWPC8UeK95RhnxCg0vxqzNr8rh/kL8 U8XL3TRwUPPbLb+tNYgg9p8wePRCljiOJRW6Q4ejKNreuKqhfW9mETmy7 ZzPPX42MdRovaCj04Kr33KYscPymj3s7ETpoQFr3ZLr8dr/dVy9YjpqPh ljf4nlW55NCPYoYZpr2ZkNUrXIp3+xeC7JRFks7kYENvKlZRhL3j7jAix Juo/8jYbRrNN/Nz+ck7UJKCVRX9FzoXAd6wSy+R235nBBXROuJlS0TMqi A==; X-IronPort-AV: E=McAfee;i="6600,9927,10971"; a="4181413" X-IronPort-AV: E=Sophos;i="6.05,238,1701158400"; d="scan'208";a="4181413" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Feb 2024 20:04:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10971"; a="823382501" X-IronPort-AV: E=Sophos;i="6.05,238,1701158400"; d="scan'208";a="823382501" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orsmga001.jf.intel.com with ESMTP; 02 Feb 2024 20:04:03 -0800 From: Ricardo Neri To: "Rafael J. Wysocki" Cc: Len Brown , Srinivas Pandruvada , Stanislaw Gruszka , Zhao Liu , Zhuocheng Ding , x86@kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri Subject: [PATCH 1/9] thermal: intel: hfi: Relocate bit definitions of HFI registers Date: Fri, 2 Feb 2024 20:05:07 -0800 Message-Id: <20240203040515.23947-2-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240203040515.23947-1-ricardo.neri-calderon@linux.intel.com> References: <20240203040515.23947-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: From: Zhao Liu KVM needs the definition of several HFI registers for the virtualization of HFI. Move the necessary definitions to msr-index.h While here, use BIT_ULL() and GENMASK_ULL() since the relevant registers have 64 bits. Also, remove the "_BIT" suffix for consistency in naming. No functional changes. Cc: Len Brown Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Stanislaw Gruszka Cc: Zhuocheng Ding Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Zhao Liu Signed-off-by: Ricardo Neri --- arch/x86/include/asm/msr-index.h | 4 ++++ drivers/thermal/intel/intel_hfi.c | 10 +++------- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index f1bd7b91b3c6..46983fb0b5b3 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1143,7 +1143,11 @@ /* Hardware Feedback Interface */ #define MSR_IA32_HW_FEEDBACK_PTR 0x17d0 +#define HW_FEEDBACK_PTR_VALID BIT_ULL(0) +#define HW_FEEDBACK_PTR_RESERVED_MASK GENMASK_ULL(11, 1) + #define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1 +#define HW_FEEDBACK_CONFIG_HFI_ENABLE BIT_ULL(0) /* x2APIC locked status */ #define MSR_IA32_XAPIC_DISABLE_STATUS 0xBD diff --git a/drivers/thermal/intel/intel_hfi.c b/drivers/thermal/intel/intel_hfi.c index 3b04c6ec4fca..9aaca74bdfa3 100644 --- a/drivers/thermal/intel/intel_hfi.c +++ b/drivers/thermal/intel/intel_hfi.c @@ -48,10 +48,6 @@ #include "../thermal_netlink.h" -/* Hardware Feedback Interface MSR configuration bits */ -#define HW_FEEDBACK_PTR_VALID_BIT BIT(0) -#define HW_FEEDBACK_CONFIG_HFI_ENABLE_BIT BIT(0) - /* CPUID detection and enumeration definitions for HFI */ #define CPUID_HFI_LEAF 6 @@ -356,7 +352,7 @@ static void hfi_enable(void) u64 msr_val; rdmsrl(MSR_IA32_HW_FEEDBACK_CONFIG, msr_val); - msr_val |= HW_FEEDBACK_CONFIG_HFI_ENABLE_BIT; + msr_val |= HW_FEEDBACK_CONFIG_HFI_ENABLE; wrmsrl(MSR_IA32_HW_FEEDBACK_CONFIG, msr_val); } @@ -366,7 +362,7 @@ static void hfi_set_hw_table(struct hfi_instance *hfi_instance) u64 msr_val; hw_table_pa = virt_to_phys(hfi_instance->hw_table); - msr_val = hw_table_pa | HW_FEEDBACK_PTR_VALID_BIT; + msr_val = hw_table_pa | HW_FEEDBACK_PTR_VALID; wrmsrl(MSR_IA32_HW_FEEDBACK_PTR, msr_val); } @@ -377,7 +373,7 @@ static void hfi_disable(void) int i; rdmsrl(MSR_IA32_HW_FEEDBACK_CONFIG, msr_val); - msr_val &= ~HW_FEEDBACK_CONFIG_HFI_ENABLE_BIT; + msr_val &= ~HW_FEEDBACK_CONFIG_HFI_ENABLE; wrmsrl(MSR_IA32_HW_FEEDBACK_CONFIG, msr_val); /* From patchwork Sat Feb 3 04:05:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 769732 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C270F9E5; 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a="4181415" X-IronPort-AV: E=Sophos;i="6.05,238,1701158400"; d="scan'208";a="4181415" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Feb 2024 20:04:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10971"; a="823382506" X-IronPort-AV: E=Sophos;i="6.05,238,1701158400"; d="scan'208";a="823382506" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orsmga001.jf.intel.com with ESMTP; 02 Feb 2024 20:04:03 -0800 From: Ricardo Neri To: "Rafael J. Wysocki" Cc: Len Brown , Srinivas Pandruvada , Stanislaw Gruszka , Zhao Liu , Zhuocheng Ding , x86@kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri Subject: [PATCH 2/9] thermal: intel: hfi: Introduce the hfi_table structure Date: Fri, 2 Feb 2024 20:05:08 -0800 Message-Id: <20240203040515.23947-3-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240203040515.23947-1-ricardo.neri-calderon@linux.intel.com> References: <20240203040515.23947-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: From: Zhao Liu The virtualization of HFI requires to parse the HFI table of the host system. Instead of exposing several pointers to the various section of the table, create a single data structure that describes the table and can be shared more cleanly. A separate data structure that represents an HFI table improves readability as it makes it clear that the table is one of several attributes of an HFI instance. No functional changes. Cc: Len Brown Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Stanislaw Gruszka Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Suggested-by: Ricardo Neri Co-developed-by: Zhuocheng Ding Signed-off-by: Zhuocheng Ding Signed-off-by: Zhao Liu Signed-off-by: Ricardo Neri --- drivers/thermal/intel/intel_hfi.c | 47 ++++++++++++++++++------------- 1 file changed, 28 insertions(+), 19 deletions(-) diff --git a/drivers/thermal/intel/intel_hfi.c b/drivers/thermal/intel/intel_hfi.c index 9aaca74bdfa3..eeabdf072efd 100644 --- a/drivers/thermal/intel/intel_hfi.c +++ b/drivers/thermal/intel/intel_hfi.c @@ -97,12 +97,25 @@ struct hfi_hdr { } __packed; /** - * struct hfi_instance - Representation of an HFI instance (i.e., a table) - * @local_table: Base of the local copy of the HFI table + * struct hfi_table - Representation of an HFI table + * @base_addr: Base address of the local copy of the HFI table * @timestamp: Timestamp of the last update of the local table. * Located at the base of the local table. * @hdr: Base address of the header of the local table * @data: Base address of the data of the local table + */ +struct hfi_table { + union { + void *base_addr; + u64 *timestamp; + }; + void *hdr; + void *data; +}; + +/** + * struct hfi_instance - Representation of an HFI instance (i.e., a table) + * @local_table: Local copy of HFI table for this instance * @cpus: CPUs represented in this HFI table instance * @hw_table: Pointer to the HFI table of this instance * @update_work: Delayed work to process HFI updates @@ -112,12 +125,7 @@ struct hfi_hdr { * A set of parameters to parse and navigate a specific HFI table. */ struct hfi_instance { - union { - void *local_table; - u64 *timestamp; - }; - void *hdr; - void *data; + struct hfi_table local_table; cpumask_var_t cpus; void *hw_table; struct delayed_work update_work; @@ -175,7 +183,7 @@ static void get_hfi_caps(struct hfi_instance *hfi_instance, s16 index; index = per_cpu(hfi_cpu_info, cpu).index; - caps = hfi_instance->data + index * hfi_features.cpu_stride; + caps = hfi_instance->local_table.data + index * hfi_features.cpu_stride; cpu_caps[i].cpu = cpu; /* @@ -292,7 +300,7 @@ void intel_hfi_process_event(__u64 pkg_therm_status_msr_val) * where a lagging CPU entered the locked region. */ new_timestamp = *(u64 *)hfi_instance->hw_table; - if (*hfi_instance->timestamp == new_timestamp) { + if (*hfi_instance->local_table.timestamp == new_timestamp) { thermal_clear_package_intr_status(PACKAGE_LEVEL, PACKAGE_THERM_STATUS_HFI_UPDATED); raw_spin_unlock(&hfi_instance->event_lock); return; @@ -304,7 +312,7 @@ void intel_hfi_process_event(__u64 pkg_therm_status_msr_val) * Copy the updated table into our local copy. This includes the new * timestamp. */ - memcpy(hfi_instance->local_table, hfi_instance->hw_table, + memcpy(hfi_instance->local_table.base_addr, hfi_instance->hw_table, hfi_features.nr_table_pages << PAGE_SHIFT); /* @@ -339,11 +347,12 @@ static void init_hfi_cpu_index(struct hfi_cpu_info *info) static void init_hfi_instance(struct hfi_instance *hfi_instance) { /* The HFI header is below the time-stamp. */ - hfi_instance->hdr = hfi_instance->local_table + - sizeof(*hfi_instance->timestamp); + hfi_instance->local_table.hdr = hfi_instance->local_table.base_addr + + sizeof(*hfi_instance->local_table.timestamp); /* The HFI data starts below the header. */ - hfi_instance->data = hfi_instance->hdr + hfi_features.hdr_size; + hfi_instance->local_table.data = hfi_instance->local_table.hdr + + hfi_features.hdr_size; } /* Caller must hold hfi_instance_lock. */ @@ -439,7 +448,7 @@ void intel_hfi_online(unsigned int cpu) * if needed. */ mutex_lock(&hfi_instance_lock); - if (hfi_instance->hdr) + if (hfi_instance->local_table.hdr) goto enable; /* @@ -459,9 +468,9 @@ void intel_hfi_online(unsigned int cpu) * Allocate memory to keep a local copy of the table that * hardware generates. */ - hfi_instance->local_table = kzalloc(hfi_features.nr_table_pages << PAGE_SHIFT, - GFP_KERNEL); - if (!hfi_instance->local_table) + hfi_instance->local_table.base_addr = kzalloc(hfi_features.nr_table_pages << PAGE_SHIFT, + GFP_KERNEL); + if (!hfi_instance->local_table.base_addr) goto free_hw_table; init_hfi_instance(hfi_instance); @@ -512,7 +521,7 @@ void intel_hfi_offline(unsigned int cpu) if (!hfi_instance) return; - if (!hfi_instance->hdr) + if (!hfi_instance->local_table.hdr) return; mutex_lock(&hfi_instance_lock); From patchwork Sat Feb 3 04:05:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 770283 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCECDF9FD; Sat, 3 Feb 2024 04:04:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706933047; cv=none; b=rAoPNJKfdblkP07BDaA97EBWiTsL0XuetURcYkUWLiIKVp18vgvjWucZOWa96wWXNM5920C/oboFxDh9kxn/mRHbtdOXb/rgBQAK5PojpV7m7LfPTiBVzzF++zW92c+UBTXjAAYZN2pBGCTM/AJ1v4uBND4C/6Yga+uWMyE56rI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706933047; c=relaxed/simple; bh=Pcpg+RONIxK6V+cB6JOTzMh7v9Tu8BTb7TgeuU7pUV4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=UoOcj6OSj8ar1gji3u3ak/0u/5rC1GFQtqN8Wc1SChEJW2HbOnbhijcSb5NTXXaVO0Gb7pusjvFN+3clH8NIlq7fpP93kImBo9OGCBdPMZlaD4+vv5mG8QWVMMFnGqyPBHIQQem3EuvOSUMNwCwnEofo98ES8vB3helgCvTZpuc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=kX/rc4Fk; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="kX/rc4Fk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706933046; x=1738469046; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=Pcpg+RONIxK6V+cB6JOTzMh7v9Tu8BTb7TgeuU7pUV4=; b=kX/rc4Fkf/tBAyaX0uyKsX0onz6aoBcXH0IYYm0cuGgpIbJn78sGb5VT 68fYXO/MCUyiCz+JAAapKaRFCyUWVTaaUueX6ahjY271jNVPf2+cX1Omz XFiNlNMn9I+2WMwlNK1ghcN/ZWQg8+P5rbn3SgDVIjZqh5h1SQb30y3VB JBwaubJTYPwMb7ghGwFBvzSwmzgZB/bNa4FoKR5g1Xq2i2aMIUBh4zYgU hnzyFO6NHPvQEGrUo2i/cmN4oJITmWWZAH+ujQOLn65aIUEH2pvkvuld6 9koOEgsqY4GVgaZ2NwLlCaFjd4+KNbrDOkO5VDKrr7APGGXn+uxfszbgT A==; X-IronPort-AV: E=McAfee;i="6600,9927,10971"; a="4181417" X-IronPort-AV: E=Sophos;i="6.05,238,1701158400"; d="scan'208";a="4181417" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Feb 2024 20:04:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10971"; a="823382511" X-IronPort-AV: E=Sophos;i="6.05,238,1701158400"; d="scan'208";a="823382511" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orsmga001.jf.intel.com with ESMTP; 02 Feb 2024 20:04:03 -0800 From: Ricardo Neri To: "Rafael J. Wysocki" Cc: Len Brown , Srinivas Pandruvada , Stanislaw Gruszka , Zhao Liu , Zhuocheng Ding , x86@kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri Subject: [PATCH 3/9] thermal: intel: hfi: Move selected data structures to a header file Date: Fri, 2 Feb 2024 20:05:09 -0800 Message-Id: <20240203040515.23947-4-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240203040515.23947-1-ricardo.neri-calderon@linux.intel.com> References: <20240203040515.23947-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: From: Zhuocheng Ding The virtualization of HFI needs the definitions of HFI capabilities and the HFI table. Move these definitions into a header file under arch/x86. No changes in the relocated structures. Cc: Len Brown Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Stanislaw Gruszka Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Zhuocheng Ding Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu Signed-off-by: Ricardo Neri --- MAINTAINERS | 1 + arch/x86/include/asm/hfi.h | 70 +++++++++++++++++++++++++++++++ drivers/thermal/intel/intel_hfi.c | 66 +---------------------------- 3 files changed, 72 insertions(+), 65 deletions(-) create mode 100644 arch/x86/include/asm/hfi.h diff --git a/MAINTAINERS b/MAINTAINERS index 8999497011a2..8bc873ba82fa 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21788,6 +21788,7 @@ L: linux-pm@vger.kernel.org S: Supported Q: https://patchwork.kernel.org/project/linux-pm/list/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git thermal +F: arch/x86/include/asm/hfi.h F: Documentation/ABI/testing/sysfs-class-thermal F: Documentation/admin-guide/thermal/ F: Documentation/devicetree/bindings/thermal/ diff --git a/arch/x86/include/asm/hfi.h b/arch/x86/include/asm/hfi.h new file mode 100644 index 000000000000..ed8a548a376e --- /dev/null +++ b/arch/x86/include/asm/hfi.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_X86_HFI_H +#define _ASM_X86_HFI_H + +/* CPUID detection and enumeration definitions for HFI */ + +union hfi_capabilities { + struct { + u8 performance:1; + u8 energy_efficiency:1; + u8 __reserved:6; + } split; + u8 bits; +}; + +union cpuid6_edx { + struct { + union hfi_capabilities capabilities; + u32 table_pages:4; + u32 __reserved:4; + s32 index:16; + } split; + u32 full; +}; + +/** + * struct hfi_hdr - Header of the HFI table + * @perf_updated: Hardware updated performance capabilities + * @ee_updated: Hardware updated energy efficiency capabilities + * + * Properties of the data in an HFI table. + */ +struct hfi_hdr { + u8 perf_updated; + u8 ee_updated; +} __packed; + +/** + * struct hfi_table - Representation of an HFI table + * @base_addr: Base address of the local copy of the HFI table + * @timestamp: Timestamp of the last update of the local table. + * Located at the base of the local table. + * @hdr: Base address of the header of the local table + * @data: Base address of the data of the local table + */ +struct hfi_table { + union { + void *base_addr; + u64 *timestamp; + }; + void *hdr; + void *data; +}; + +/** + * struct hfi_features - Supported HFI features + * @nr_table_pages: Size of the HFI table in 4KB pages + * @cpu_stride: Stride size to locate the capability data of a logical + * processor within the table (i.e., row stride) + * @hdr_size: Size of the table header + * + * Parameters and supported features that are common to all HFI instances + */ +struct hfi_features { + size_t nr_table_pages; + unsigned int cpu_stride; + unsigned int hdr_size; +}; + +#endif /* _ASM_X86_HFI_H */ diff --git a/drivers/thermal/intel/intel_hfi.c b/drivers/thermal/intel/intel_hfi.c index eeabdf072efd..ee8950a60f72 100644 --- a/drivers/thermal/intel/intel_hfi.c +++ b/drivers/thermal/intel/intel_hfi.c @@ -41,6 +41,7 @@ #include #include +#include #include #include "intel_hfi.h" @@ -48,29 +49,8 @@ #include "../thermal_netlink.h" -/* CPUID detection and enumeration definitions for HFI */ - #define CPUID_HFI_LEAF 6 -union hfi_capabilities { - struct { - u8 performance:1; - u8 energy_efficiency:1; - u8 __reserved:6; - } split; - u8 bits; -}; - -union cpuid6_edx { - struct { - union hfi_capabilities capabilities; - u32 table_pages:4; - u32 __reserved:4; - s32 index:16; - } split; - u32 full; -}; - /** * struct hfi_cpu_data - HFI capabilities per CPU * @perf_cap: Performance capability @@ -84,35 +64,6 @@ struct hfi_cpu_data { u8 ee_cap; } __packed; -/** - * struct hfi_hdr - Header of the HFI table - * @perf_updated: Hardware updated performance capabilities - * @ee_updated: Hardware updated energy efficiency capabilities - * - * Properties of the data in an HFI table. - */ -struct hfi_hdr { - u8 perf_updated; - u8 ee_updated; -} __packed; - -/** - * struct hfi_table - Representation of an HFI table - * @base_addr: Base address of the local copy of the HFI table - * @timestamp: Timestamp of the last update of the local table. - * Located at the base of the local table. - * @hdr: Base address of the header of the local table - * @data: Base address of the data of the local table - */ -struct hfi_table { - union { - void *base_addr; - u64 *timestamp; - }; - void *hdr; - void *data; -}; - /** * struct hfi_instance - Representation of an HFI instance (i.e., a table) * @local_table: Local copy of HFI table for this instance @@ -133,21 +84,6 @@ struct hfi_instance { raw_spinlock_t event_lock; }; -/** - * struct hfi_features - Supported HFI features - * @nr_table_pages: Size of the HFI table in 4KB pages - * @cpu_stride: Stride size to locate the capability data of a logical - * processor within the table (i.e., row stride) - * @hdr_size: Size of the table header - * - * Parameters and supported features that are common to all HFI instances - */ -struct hfi_features { - size_t nr_table_pages; - unsigned int cpu_stride; - unsigned int hdr_size; -}; - /** * struct hfi_cpu_info - Per-CPU attributes to consume HFI data * @index: Row of this CPU in its HFI table From patchwork Sat Feb 3 04:05:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 769731 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2E21101C2; Sat, 3 Feb 2024 04:04:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706933048; cv=none; b=ir/oDAjRXSF/ITrHBM20FfROQ7a0y70lwpecKGGrhzQVDVYH1QStqrAP/jIf5eoOxO65UiEsU1APaAf/8cg+MPVYP4nltBCj/kBk6iQA+zyiCLwLa3g8WyAdL+UQo4YY+3rwBcbglkC8QUmdgOctSxcnjzVF6s+36CULpJuMrtY= ARC-Message-Signature: i=1; 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02 Feb 2024 20:04:04 -0800 From: Ricardo Neri To: "Rafael J. Wysocki" Cc: Len Brown , Srinivas Pandruvada , Stanislaw Gruszka , Zhao Liu , Zhuocheng Ding , x86@kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Zhao Liu Subject: [PATCH 4/9] thermal: intel: hfi: Introduce Intel Thread Director classes Date: Fri, 2 Feb 2024 20:05:10 -0800 Message-Id: <20240203040515.23947-5-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240203040515.23947-1-ricardo.neri-calderon@linux.intel.com> References: <20240203040515.23947-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: On Intel hybrid parts, each type of CPU has specific performance and energy efficiency capabilities. The Intel Thread Director technology extends the Hardware Feedback Interface (HFI) to provide performance and energy efficiency data for advanced classes of instructions. Add support to parse per-class capabilities. Cc: Len Brown Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Stanislaw Gruszka Cc: Zhao Liu Cc: Zhuocheng Ding Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Acked-by: Rafael J. Wysocki Signed-off-by: Ricardo Neri --- Patch cherry-picked from the IPC classes patchset. --- --- arch/x86/include/asm/hfi.h | 8 +++++++- drivers/thermal/intel/intel_hfi.c | 22 +++++++++++++++++----- 2 files changed, 24 insertions(+), 6 deletions(-) diff --git a/arch/x86/include/asm/hfi.h b/arch/x86/include/asm/hfi.h index ed8a548a376e..02ee56dbaeb6 100644 --- a/arch/x86/include/asm/hfi.h +++ b/arch/x86/include/asm/hfi.h @@ -28,7 +28,8 @@ union cpuid6_edx { * @perf_updated: Hardware updated performance capabilities * @ee_updated: Hardware updated energy efficiency capabilities * - * Properties of the data in an HFI table. + * Properties of the data in an HFI table. There exists one header per each + * HFI class. */ struct hfi_hdr { u8 perf_updated; @@ -54,16 +55,21 @@ struct hfi_table { /** * struct hfi_features - Supported HFI features + * @nr_classes: Number of classes supported * @nr_table_pages: Size of the HFI table in 4KB pages * @cpu_stride: Stride size to locate the capability data of a logical * processor within the table (i.e., row stride) + * @class_stride: Stride size to locate a class within the capability + * data of a logical processor or the HFI table header * @hdr_size: Size of the table header * * Parameters and supported features that are common to all HFI instances */ struct hfi_features { + unsigned int nr_classes; size_t nr_table_pages; unsigned int cpu_stride; + unsigned int class_stride; unsigned int hdr_size; }; diff --git a/drivers/thermal/intel/intel_hfi.c b/drivers/thermal/intel/intel_hfi.c index ee8950a60f72..3c399f3d059f 100644 --- a/drivers/thermal/intel/intel_hfi.c +++ b/drivers/thermal/intel/intel_hfi.c @@ -57,7 +57,7 @@ * @ee_cap: Energy efficiency capability * * Capabilities of a logical processor in the HFI table. These capabilities are - * unitless. + * unitless and specific to each HFI class. */ struct hfi_cpu_data { u8 perf_cap; @@ -277,8 +277,8 @@ static void init_hfi_cpu_index(struct hfi_cpu_info *info) } /* - * The format of the HFI table depends on the number of capabilities that the - * hardware supports. Keep a data structure to navigate the table. + * The format of the HFI table depends on the number of capabilities and classes + * that the hardware supports. Keep a data structure to navigate the table. */ static void init_hfi_instance(struct hfi_instance *hfi_instance) { @@ -498,18 +498,30 @@ static __init int hfi_parse_features(void) /* The number of 4KB pages required by the table */ hfi_features.nr_table_pages = edx.split.table_pages + 1; + /* + * Capability fields of an HFI class are grouped together. Classes are + * contiguous in memory. Hence, use the number of supported features to + * locate a specific class. + */ + hfi_features.class_stride = nr_capabilities; + + /* For now, use only one class of the HFI table */ + hfi_features.nr_classes = 1; + /* * The header contains change indications for each supported feature. * The size of the table header is rounded up to be a multiple of 8 * bytes. */ - hfi_features.hdr_size = DIV_ROUND_UP(nr_capabilities, 8) * 8; + hfi_features.hdr_size = DIV_ROUND_UP(nr_capabilities * + hfi_features.nr_classes, 8) * 8; /* * Data of each logical processor is also rounded up to be a multiple * of 8 bytes. */ - hfi_features.cpu_stride = DIV_ROUND_UP(nr_capabilities, 8) * 8; + hfi_features.cpu_stride = DIV_ROUND_UP(nr_capabilities * + hfi_features.nr_classes, 8) * 8; return 0; } From patchwork Sat Feb 3 04:05:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 770282 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C45110965; Sat, 3 Feb 2024 04:04:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706933049; cv=none; b=hZUB5Ock4utN/vL6iNsIK9FypiqKTP1WRwJrlwZlzzKZYfPgE2Nqia2I3CQXfIOZ+gNPVjziBeZGgILH1Ad7KOwbaKcBd4tSzXE2LDybcn+a+saNoUltF51D0Gw/H95aB2t3kiqvDnYG+jmcnXJUAR2ZXXxLt1AZrtrpWN0Xaok= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706933049; c=relaxed/simple; bh=JlsbRLvxWX+gGq/dnjUfG92Wdmp50mFvi0KtQuzOgEU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=pmC1Kof71kMMHkoLqlQNsgPI5LXiJ06i2T7n/6bwWXk2O6jprJuBeaSgr/TGSHwzj4HSTK+uS5wXNOraRc9lC40mG1E0CFamOqFPnCIs4n+jV18qP8P/H7+EQ+tTekjMpseHcqiOwdd8gQ9gp6g4Maf2a7wLyhWX6XXG2AedQ+I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=h7ZZsHHI; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="h7ZZsHHI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706933048; x=1738469048; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=JlsbRLvxWX+gGq/dnjUfG92Wdmp50mFvi0KtQuzOgEU=; b=h7ZZsHHImybnN36YkxJohrwAnhA2StDdyuOAwEErJTungc/J4LoU59L8 n1OlfBu/y1U9J+5Vyr12zMbmyCkFJM9irL2fW/MD+R/mzMgsULCGmozLQ Rie3J90tuPsChgD7Sak1oJJ6mzoNf7e6IQfdusClhPKBbn05NNPgD8OAW nnGKMU2CFkwyKDaq7piRgp33wloWP1cz8L3BRi33iC3/OSpmewGhdci5W Sz5JHi04j75zzbzWGoaKGu41klI87UoAsmPtr/TCEfCrDiPcKzIcw8+7F RwxEBkYHzwZlWPkvOfBzhc+aatRGRCpqCO8N1sgcw5+xIGhylv8/ZDz2R Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10971"; a="4181421" X-IronPort-AV: E=Sophos;i="6.05,238,1701158400"; d="scan'208";a="4181421" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Feb 2024 20:04:05 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10971"; a="823382518" X-IronPort-AV: E=Sophos;i="6.05,238,1701158400"; d="scan'208";a="823382518" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orsmga001.jf.intel.com with ESMTP; 02 Feb 2024 20:04:04 -0800 From: Ricardo Neri To: "Rafael J. Wysocki" Cc: Len Brown , Srinivas Pandruvada , Stanislaw Gruszka , Zhao Liu , Zhuocheng Ding , x86@kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Zhao Liu Subject: [PATCH 5/9] x86/cpufeatures: Add the Intel Thread Director feature definitions Date: Fri, 2 Feb 2024 20:05:11 -0800 Message-Id: <20240203040515.23947-6-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240203040515.23947-1-ricardo.neri-calderon@linux.intel.com> References: <20240203040515.23947-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Intel Thread Director (ITD) provides hardware resources to classify the current task. The classification reflects the instructions per cycle of such current task. ITD extends the Hardware Feedback Interface table to provide performance and energy efficiency capabilities for each of the supported classes of tasks. Cc: Len Brown Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Stanislaw Gruszka Cc: Zhao Liu Cc: Zhuocheng Ding Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ricardo Neri --- Patch cherry-picked from the IPC classes patchset. --- --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/cpuid-deps.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index fdf723b6f6d0..8104f4791abd 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -360,6 +360,7 @@ #define X86_FEATURE_HWP_EPP (14*32+10) /* HWP Energy Perf. Preference */ #define X86_FEATURE_HWP_PKG_REQ (14*32+11) /* HWP Package Level Request */ #define X86_FEATURE_HFI (14*32+19) /* Hardware Feedback Interface */ +#define X86_FEATURE_ITD (14*32+23) /* Intel Thread Director */ /* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */ #define X86_FEATURE_NPT (15*32+ 0) /* Nested Page Table support */ diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-deps.c index e462c1d3800a..2ab036125a56 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -82,6 +82,7 @@ static const struct cpuid_dep cpuid_deps[] = { { X86_FEATURE_XFD, X86_FEATURE_XGETBV1 }, { X86_FEATURE_AMX_TILE, X86_FEATURE_XFD }, { X86_FEATURE_SHSTK, X86_FEATURE_XSAVES }, + { X86_FEATURE_ITD, X86_FEATURE_HFI }, {} }; From patchwork Sat Feb 3 04:05:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 769730 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BE69B10A21; Sat, 3 Feb 2024 04:04:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706933049; cv=none; b=ddCNTjHSERtq4ShEqG1lKr4+m50gsa1FoEKo8J2DAjznnlFz7+T4ySFZsPMof/Tj5Jv5eLEvJY8WmPlbf1eQQa2wYqhLhvRKUjaLgxhlpCHqKnyK2B2eUEooYRHsw7ceUJGtbLqZ+HTxzcZ6oz9KaesrrHw1l/x5E0D5wlhbXJA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706933049; c=relaxed/simple; bh=IlogMVxWMm4Bo2Pqh8c/KfMxkwWVK/uFmsNIQCeHpVw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=tVxKC5haXVQPxGuXNovBrkZZe4ag9R9NwsSaV9GT2xWJU6nsVb50d/QwADrR+H/+wpwPM9dDvlt+Wo7TJuKt8hDGOQLW+mg/qUw6c2coSYbBFZ66gaoywkaD/K903aGPUjmNpyVEneBTOuVTr+E/9UrlXFyGOJPUZrOtMScB8AY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=MhkgxMV4; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MhkgxMV4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706933048; x=1738469048; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=IlogMVxWMm4Bo2Pqh8c/KfMxkwWVK/uFmsNIQCeHpVw=; b=MhkgxMV42y+JBsXc+KOk88jYniwaFTMaKk3dUBin4fQjKKxodtQB5Ak3 99LwE2MI1IWFbXK4eHvc4U759v8VpLmzBTRYndXoVUxt/uITBy8Lotnpu flRlr4wdecaarMxO5MIVqSRg5gITfcxBfbinfHVWnXfW2Sy4jvk3wJLB4 II2UyIAxJEp1qqcmWhUa4Xi0+2hFvpl/hdlhQsq65ry5/kDA1tPBTEDaV cFSqR8XypNCjbtPdOt/UPNMn1ve3FlP8CJf1yvkhDDmH3dt3DLaDqoaAM bRV8BGWIWYQdzt23L8z3N61t8rmZTKBZ3lOHtqXjeStcLNLUA+KqO5dsE Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10971"; a="4181423" X-IronPort-AV: E=Sophos;i="6.05,238,1701158400"; d="scan'208";a="4181423" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Feb 2024 20:04:05 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10971"; a="823382522" X-IronPort-AV: E=Sophos;i="6.05,238,1701158400"; d="scan'208";a="823382522" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orsmga001.jf.intel.com with ESMTP; 02 Feb 2024 20:04:04 -0800 From: Ricardo Neri To: "Rafael J. Wysocki" Cc: Len Brown , Srinivas Pandruvada , Stanislaw Gruszka , Zhao Liu , Zhuocheng Ding , x86@kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Zhao Liu Subject: [PATCH 6/9] thermal: intel: hfi: Enable Intel Thread Director Date: Fri, 2 Feb 2024 20:05:12 -0800 Message-Id: <20240203040515.23947-7-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240203040515.23947-1-ricardo.neri-calderon@linux.intel.com> References: <20240203040515.23947-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Enable Intel Thread Director (ITD) from the CPU hotplug callback: globally from CPU0 and then enable the thread-classification hardware in each logical processor individually. Also, initialize the number of classes supported. Currently, a bare-metal machine does not use ITD, but KVM uses the attributes of the bare-metal machine to virtualize HFI. Cc: Len Brown Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Stanislaw Gruszka Cc: Zhao Liu Cc: Zhuocheng Ding Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Acked-by: Rafael J. Wysocki # intel_hfi.c Signed-off-by: Ricardo Neri --- Discussion: This patch conflicts with a patchset from Stanislaw Gruszka to enable HFI only if there are user space entities listening to the thermal netlink events. ITD requires that HFI is enabled to function. ITD needs to be unconditionally enabled for virtual machines. Options to resolve this conflict include a command-line argument for users wanting to virtualize HFI or a CONFIG_ option for the same effect. QEMU could also learn to listen to thermal netlink event. A blunter option is to unconditionally enable HFI when KVM is enabled at build time. --- Patch cherry-picked from the IPC classes patchset. --- --- arch/x86/include/asm/hfi.h | 9 ++++++ arch/x86/include/asm/msr-index.h | 6 ++++ drivers/thermal/intel/intel_hfi.c | 52 +++++++++++++++++++++++++++++-- 3 files changed, 65 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/hfi.h b/arch/x86/include/asm/hfi.h index 02ee56dbaeb6..b7fda3e0e8c8 100644 --- a/arch/x86/include/asm/hfi.h +++ b/arch/x86/include/asm/hfi.h @@ -23,6 +23,15 @@ union cpuid6_edx { u32 full; }; +union cpuid6_ecx { + struct { + u32 dont_care0:8; + u32 nr_classes:8; + u32 dont_care1:16; + } split; + u32 full; +}; + /** * struct hfi_hdr - Header of the HFI table * @perf_updated: Hardware updated performance capabilities diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 46983fb0b5b3..d74932a0778d 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1148,6 +1148,12 @@ #define MSR_IA32_HW_FEEDBACK_CONFIG 0x17d1 #define HW_FEEDBACK_CONFIG_HFI_ENABLE BIT_ULL(0) +#define HW_FEEDBACK_CONFIG_ITD_ENABLE BIT_ULL(1) + +#define MSR_IA32_HW_FEEDBACK_THREAD_CONFIG 0x17d4 +#define HW_FEEDBACK_THREAD_CONFIG_ENABLE BIT_ULL(0) + +#define MSR_IA32_HW_FEEDBACK_CHAR 0x17d2 /* x2APIC locked status */ #define MSR_IA32_XAPIC_DISABLE_STATUS 0xBD diff --git a/drivers/thermal/intel/intel_hfi.c b/drivers/thermal/intel/intel_hfi.c index 3c399f3d059f..b69fa234b317 100644 --- a/drivers/thermal/intel/intel_hfi.c +++ b/drivers/thermal/intel/intel_hfi.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -298,6 +299,10 @@ static void hfi_enable(void) rdmsrl(MSR_IA32_HW_FEEDBACK_CONFIG, msr_val); msr_val |= HW_FEEDBACK_CONFIG_HFI_ENABLE; + + if (cpu_feature_enabled(X86_FEATURE_ITD)) + msr_val |= HW_FEEDBACK_CONFIG_ITD_ENABLE; + wrmsrl(MSR_IA32_HW_FEEDBACK_CONFIG, msr_val); } @@ -319,6 +324,10 @@ static void hfi_disable(void) rdmsrl(MSR_IA32_HW_FEEDBACK_CONFIG, msr_val); msr_val &= ~HW_FEEDBACK_CONFIG_HFI_ENABLE; + + if (cpu_feature_enabled(X86_FEATURE_ITD)) + msr_val &= ~HW_FEEDBACK_CONFIG_ITD_ENABLE; + wrmsrl(MSR_IA32_HW_FEEDBACK_CONFIG, msr_val); /* @@ -337,6 +346,30 @@ static void hfi_disable(void) } } +static void hfi_enable_itd_classification(void) +{ + u64 msr_val; + + if (!cpu_feature_enabled(X86_FEATURE_ITD)) + return; + + rdmsrl(MSR_IA32_HW_FEEDBACK_THREAD_CONFIG, msr_val); + msr_val |= HW_FEEDBACK_THREAD_CONFIG_ENABLE; + wrmsrl(MSR_IA32_HW_FEEDBACK_THREAD_CONFIG, msr_val); +} + +static void hfi_disable_itd_classification(void) +{ + u64 msr_val; + + if (!cpu_feature_enabled(X86_FEATURE_ITD)) + return; + + rdmsrl(MSR_IA32_HW_FEEDBACK_THREAD_CONFIG, msr_val); + msr_val &= ~HW_FEEDBACK_THREAD_CONFIG_ENABLE; + wrmsrl(MSR_IA32_HW_FEEDBACK_THREAD_CONFIG, msr_val); +} + /** * intel_hfi_online() - Enable HFI on @cpu * @cpu: CPU in which the HFI will be enabled @@ -377,6 +410,8 @@ void intel_hfi_online(unsigned int cpu) init_hfi_cpu_index(info); + hfi_enable_itd_classification(); + /* * Now check if the HFI instance of the package/die of @cpu has been * initialized (by checking its header). In such case, all we have to @@ -460,6 +495,8 @@ void intel_hfi_offline(unsigned int cpu) if (!hfi_instance->local_table.hdr) return; + hfi_disable_itd_classification(); + mutex_lock(&hfi_instance_lock); cpumask_clear_cpu(cpu, hfi_instance->cpus); @@ -505,8 +542,14 @@ static __init int hfi_parse_features(void) */ hfi_features.class_stride = nr_capabilities; - /* For now, use only one class of the HFI table */ - hfi_features.nr_classes = 1; + if (cpu_feature_enabled(X86_FEATURE_ITD)) { + union cpuid6_ecx ecx; + + ecx.full = cpuid_ecx(CPUID_HFI_LEAF); + hfi_features.nr_classes = ecx.split.nr_classes; + } else { + hfi_features.nr_classes = 1; + } /* * The header contains change indications for each supported feature. @@ -535,11 +578,16 @@ static void hfi_do_enable(void) /* No locking needed. There is no concurrency with CPU online. */ hfi_set_hw_table(hfi_instance); hfi_enable(); + + hfi_enable_itd_classification(); } static int hfi_do_disable(void) { /* No locking needed. There is no concurrency with CPU offline. */ + + hfi_disable_itd_classification(); + hfi_disable(); return 0; From patchwork Sat Feb 3 04:05:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 770281 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41F6E1118E; Sat, 3 Feb 2024 04:04:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706933049; cv=none; b=RAoWzbenFhp0TUS7L+AK/iTtMhU5xqZbefBd6PRZP1Ty7iXf8289f/Syxcf87fyzuIO6XUpYLxcHIHswjlQE3pOR1uY9Wx5Zj/nxvmeRkIG7hUWR4d4mpE47imXS+TGhLnPGEW7Lhk8mtrM2gE6Kx+08YdUIPTQzJuRE4LSeOnw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706933049; c=relaxed/simple; bh=tPRApoSMpWENCgHFmpqWBaJZ2dE2sWiZiCQc9GL+JjM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=NrudZEWEGeH0VPhKDZ1pdvpcflhlgzBFB/XxzGJID4kw/yxsSybB3nZsyyRxt2Z5mi7+oBdeLVbaBEUbvVpJDa10sDixR1K6LencxNjLyNfSDwXRsyLgEyHlEOr6cv+SnC73Vm2ooGYwrGheZ41ueJyy0jq9rTcKB+WhXVQU1IA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=afX2aAjk; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="afX2aAjk" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706933048; x=1738469048; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=tPRApoSMpWENCgHFmpqWBaJZ2dE2sWiZiCQc9GL+JjM=; b=afX2aAjkOfwaueMyp9j7cKzUj3/E96MvypnEnOTkMe+aiu30OowaQioX WFKImsflvZT5OerpcbVRexIhfphsXKicAIi/wcVt/RJaHxMLG03j2n/We p7+jBQLo4SqvMMvzYQKVh4U3+LpPxYoQJ4GizlQptdumx/HHeITAenzpz o06qDd4/y5vZScYGVZ/wowgy6fZwEcFGXMXTS9QUtXsISR/f4CFim3CKA m7t2aYnpHLXu6UcFxnCX3Rb5KePGwT2Zt+NIA5P3MQY/Q/cIjgtPz8Pq0 y5T6fRunNGBk1pOoh1yvpu6FnK1dL6lQGei28QjYNOBcmJRBCygFaaI8h w==; X-IronPort-AV: E=McAfee;i="6600,9927,10971"; a="4181425" X-IronPort-AV: E=Sophos;i="6.05,238,1701158400"; d="scan'208";a="4181425" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Feb 2024 20:04:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10971"; a="823382525" X-IronPort-AV: E=Sophos;i="6.05,238,1701158400"; d="scan'208";a="823382525" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orsmga001.jf.intel.com with ESMTP; 02 Feb 2024 20:04:05 -0800 From: Ricardo Neri To: "Rafael J. Wysocki" Cc: Len Brown , Srinivas Pandruvada , Stanislaw Gruszka , Zhao Liu , Zhuocheng Ding , x86@kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Zhao Liu Subject: [PATCH 7/9] x86/cpufeatures: Add feature bit for HRESET Date: Fri, 2 Feb 2024 20:05:13 -0800 Message-Id: <20240203040515.23947-8-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240203040515.23947-1-ricardo.neri-calderon@linux.intel.com> References: <20240203040515.23947-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: The HRESET instruction isolates the classification of individual tasks when they run sequentially on the same logical processor. It resets the classification history that the logical processor maintains. Cc: Len Brown Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Stanislaw Gruszka Cc: Zhao Liu Cc: Zhuocheng Ding Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ricardo Neri --- Patch cherry-picked from the IPC classes patchset. --- --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/msr-index.h | 3 +++ 2 files changed, 4 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 8104f4791abd..3b42479c049d 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -326,6 +326,7 @@ #define X86_FEATURE_FSRC (12*32+12) /* "" Fast short REP {CMPSB,SCASB} */ #define X86_FEATURE_LKGS (12*32+18) /* "" Load "kernel" (userspace) GS */ #define X86_FEATURE_AMX_FP16 (12*32+21) /* "" AMX fp16 Support */ +#define X86_FEATURE_HRESET (12*32+22) /* Hardware history reset instruction */ #define X86_FEATURE_AVX_IFMA (12*32+23) /* "" Support for VPMADD52[H,L]UQ */ #define X86_FEATURE_LAM (12*32+26) /* Linear Address Masking */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index d74932a0778d..65b1bfb9c304 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1155,6 +1155,9 @@ #define MSR_IA32_HW_FEEDBACK_CHAR 0x17d2 +/* Hardware History Reset */ +#define MSR_IA32_HW_HRESET_ENABLE 0x17da + /* x2APIC locked status */ #define MSR_IA32_XAPIC_DISABLE_STATUS 0xBD #define LEGACY_XAPIC_DISABLED BIT(0) /* From patchwork Sat Feb 3 04:05:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 769729 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C70A11C82; Sat, 3 Feb 2024 04:04:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706933050; cv=none; b=DLqrchm8LHid9bD5tON25lrML8TEku746iSseSo7pi1TQ3p0lKTs9n8FgUubPw6pK7Aj7QvFl04uG3KD4BdlgDf8+pOKhT27zHb2V43HGZRV1SZC5yOgcd5++oJYQRwvM1ljd72t6DdHAE2I3ikv+K5sLg1B66NFJbaNA87ny/g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706933050; c=relaxed/simple; bh=b0WZrZfGAqqetqqX3SCPK7BemWXSqpe0nj9hC32/ijk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=KLrWA3yuHJV+hyCfg3JNIzxX6zHGCtMRBRA173/Mzn6QrQt0KS8MJpRNJ81s3nhoAI6eFx6QXo/1Vhwm64isihwBP73Dv8y1u7+4acLanJ13h41G4A00k8WvB5Ga2PDK7nJRfzTY/HoAt1R4U1i/WCMD24WldZMcSuwlYW/Boug= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=dEq3RbJa; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="dEq3RbJa" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706933049; x=1738469049; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=b0WZrZfGAqqetqqX3SCPK7BemWXSqpe0nj9hC32/ijk=; b=dEq3RbJalQFdDrkY8yCAwhF8VYVFRQFX8Aq/iTwuyDLXZhl7hpGanTCG VS2l/AjMadHawxZnfgD3vMGDV/Vkbubtf5kfaMify+b5V6D4QT1pMQhL/ YDrfJHmnxH/ujFwMZPP7xyWBVOZWv851SRIXrKqT2YfkoIblw9G9JPZBW fTTAdBTer0AB5h8p/Rm62Ds7rqkMb7xmIkosoWKTqFRugctZPqEbNGldI TSPQvK1jfSbpsnbnyazowtvbrSojTm3L1wrSwdj2Nt+MljJspl16KoCbp QY9A1O9AmTVmeSMYl2H3bz9D01cuKDbm7fd6mys5JsRtM+iHNmUT4avtI g==; X-IronPort-AV: E=McAfee;i="6600,9927,10971"; a="4181427" X-IronPort-AV: E=Sophos;i="6.05,238,1701158400"; d="scan'208";a="4181427" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Feb 2024 20:04:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10971"; a="823382528" X-IronPort-AV: E=Sophos;i="6.05,238,1701158400"; d="scan'208";a="823382528" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orsmga001.jf.intel.com with ESMTP; 02 Feb 2024 20:04:05 -0800 From: Ricardo Neri To: "Rafael J. Wysocki" Cc: Len Brown , Srinivas Pandruvada , Stanislaw Gruszka , Zhao Liu , Zhuocheng Ding , x86@kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Zhao Liu Subject: [PATCH 8/9] x86/hreset: Configure history reset Date: Fri, 2 Feb 2024 20:05:14 -0800 Message-Id: <20240203040515.23947-9-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240203040515.23947-1-ricardo.neri-calderon@linux.intel.com> References: <20240203040515.23947-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Configure the MSR that controls the behavior of HRESET on each logical processor. Cc: Len Brown Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Stanislaw Gruszka Cc: Zhao Liu Cc: Zhuocheng Ding Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ricardo Neri --- Patch cherry-picked from the IPC classes patchset --- --- arch/x86/kernel/cpu/common.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 0b97bcde70c6..bce8719b47c9 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -381,6 +381,26 @@ static __always_inline void setup_umip(struct cpuinfo_x86 *c) cr4_clear_bits(X86_CR4_UMIP); } +static u32 hardware_history_features __ro_after_init; + +static __always_inline void setup_hreset(struct cpuinfo_x86 *c) +{ + if (!cpu_feature_enabled(X86_FEATURE_HRESET)) + return; + + /* + * Use on all CPUs the hardware history features that the boot + * CPU supports. + */ + if (c == &boot_cpu_data) + hardware_history_features = cpuid_ebx(0x20); + + if (!hardware_history_features) + return; + + wrmsrl(MSR_IA32_HW_HRESET_ENABLE, hardware_history_features); +} + /* These bits should not change their value after CPU init is finished. */ static const unsigned long cr4_pinned_mask = X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP | @@ -1872,10 +1892,11 @@ static void identify_cpu(struct cpuinfo_x86 *c) /* Disable the PN if appropriate */ squash_the_stupid_serial_number(c); - /* Set up SMEP/SMAP/UMIP */ + /* Set up SMEP/SMAP/UMIP/HRESET */ setup_smep(c); setup_smap(c); setup_umip(c); + setup_hreset(c); /* Enable FSGSBASE instructions if available. */ if (cpu_has(c, X86_FEATURE_FSGSBASE)) { From patchwork Sat Feb 3 04:05:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ricardo Neri X-Patchwork-Id: 770280 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.15]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7D96912B60; Sat, 3 Feb 2024 04:04:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.15 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706933051; cv=none; b=CtUy9XbI8Ca8AswS82SpYv478PgkLggsHsLEqKAg1Qyf/8Itq7FJSz3Y5yGumweO/ll/H0n0mkdV4PX/VQtED2GGD86JekZsXMfQHyJJA2Ey1VLKDPLZvoNZHZlCT1V3oHUIQlZTZq7CCNRu9YaQYAPMiZR+j0p/ngXSPSFOt10= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706933051; c=relaxed/simple; bh=jJ7cQQxTyIeHFxzXpC9coCnefq+U00MraPSXDdxbmwE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=X7C3C6MTUjnSsWmhyfQhwtuVFvpuVBR95Cz51MBj/LN2J9X33aNweaHasYbzoeZV0Z4bcQpGeVnsuI9TRuEyxL7A5rXRoCTX9uDN9ujvsJ9NDRJAwRDvXi6mWOjep0kxCkoWxvAGYnemI4xF7QTcPquOn10EZtvZxpxL4tUU19U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=G5IAEj6c; arc=none smtp.client-ip=198.175.65.15 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="G5IAEj6c" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706933050; x=1738469050; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=jJ7cQQxTyIeHFxzXpC9coCnefq+U00MraPSXDdxbmwE=; b=G5IAEj6cyNfUeUb4Eey9F6TvwsSh0P70Rr5op+aWnED/3GZSZn0pTkv3 U6TBvVbQwciai1/9scahZgt+hzivyFmPYUGggM5Rrx32RKbzwGO6CV797 RQp0Fgf9teXWc88QjI1E82ysmQaArSopOEncD/u0l5e9MAGyT/OB6FeHt IaDx3d07rNP2JMzu2cHvfSCPTmQQLMpGsuXllYe/cfeM/mDW4t2Wee7X3 8QK3/ZsNB4N6JWKH6V/a0yRIBNcOzsdF74oBkeA7kUgRtGHO19wHxMmQ+ eN96FtO4NYJggKTgg4X09t2UyT1fA+qPIfIz6gA6FiD/A+rlPmtkM5ni1 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10971"; a="4181429" X-IronPort-AV: E=Sophos;i="6.05,238,1701158400"; d="scan'208";a="4181429" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Feb 2024 20:04:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10971"; a="823382531" X-IronPort-AV: E=Sophos;i="6.05,238,1701158400"; d="scan'208";a="823382531" Received: from ranerica-svr.sc.intel.com ([172.25.110.23]) by orsmga001.jf.intel.com with ESMTP; 02 Feb 2024 20:04:05 -0800 From: Ricardo Neri To: "Rafael J. Wysocki" Cc: Len Brown , Srinivas Pandruvada , Stanislaw Gruszka , Zhao Liu , Zhuocheng Ding , x86@kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Ricardo Neri , Zhao Liu Subject: [PATCH 9/9] x86/cpu: Introduce interface to reset hardware history Date: Fri, 2 Feb 2024 20:05:15 -0800 Message-Id: <20240203040515.23947-10-ricardo.neri-calderon@linux.intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240203040515.23947-1-ricardo.neri-calderon@linux.intel.com> References: <20240203040515.23947-1-ricardo.neri-calderon@linux.intel.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: KVM needs an interface to reset the history of vCPU at context switch. When called, hardware will start the classification of the next task from scratch. Cc: Len Brown Cc: Rafael J. Wysocki Cc: Srinivas Pandruvada Cc: Stanislaw Gruszka Cc: Zhao Liu Cc: Zhuocheng Ding Cc: x86@kernel.org Cc: linux-pm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ricardo Neri --- Patch cherry-picked from the IPC classes patchset. Removed calls to reset_hardware_history() from context switch. Now KVM will call it directly when needed. --- * Measurements of the cost of the HRESET instruction Methodology: I created a tight loop with interrupts and preemption disabled. I recorded the value of the TSC counter before and after executing HRESET or RDTSC. I repeated the measurement 100,000 times. I performed the experiment using an Alder Lake S system. I set the frequency of the CPUs at a fixed value. The table below compares the cost of HRESET with RDTSC (expressed in the elapsed TSC count). The cost of the two instructions is comparable. PCore ECore Frequency (GHz) 5.0 3.8 HRESET (avg) 28.5 44.7 HRESET (stdev %) 3.6 2.3 RDTSC (avg) 25.2 35.7 RDTSC (stdev %) 3.9 2.6 --- arch/x86/include/asm/hreset.h | 30 ++++++++++++++++++++++++++++++ arch/x86/kernel/cpu/common.c | 8 ++++++++ 2 files changed, 38 insertions(+) create mode 100644 arch/x86/include/asm/hreset.h diff --git a/arch/x86/include/asm/hreset.h b/arch/x86/include/asm/hreset.h new file mode 100644 index 000000000000..d68ca2fb8642 --- /dev/null +++ b/arch/x86/include/asm/hreset.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_X86_HRESET_H + +/** + * HRESET - History reset. Available since binutils v2.36. + * + * Request the processor to reset the history of task classification on the + * current logical processor. The history components to be + * reset are specified in %eax. Only bits specified in CPUID(0x20).EBX + * and enabled in the IA32_HRESET_ENABLE MSR can be selected. + * + * The assembly code looks like: + * + * hreset %eax + * + * The corresponding machine code looks like: + * + * F3 0F 3A F0 ModRM Imm + * + * The value of ModRM is 0xc0 to specify %eax register addressing. + * The ignored immediate operand is set to 0. + * + * The instruction is documented in the Intel SDM. + */ + +#define __ASM_HRESET ".byte 0xf3, 0xf, 0x3a, 0xf0, 0xc0, 0x0" + +void reset_hardware_history(void); + +#endif /* _ASM_X86_HRESET_H */ diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index bce8719b47c9..ab9809520164 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -57,6 +57,7 @@ #include #include #include +#include #include #include #include @@ -383,6 +384,13 @@ static __always_inline void setup_umip(struct cpuinfo_x86 *c) static u32 hardware_history_features __ro_after_init; +void reset_hardware_history(void) +{ + asm_inline volatile (ALTERNATIVE("", __ASM_HRESET, X86_FEATURE_HRESET) + : : "a" (hardware_history_features) : "memory"); +} +EXPORT_SYMBOL(reset_hardware_history); + static __always_inline void setup_hreset(struct cpuinfo_x86 *c) { if (!cpu_feature_enabled(X86_FEATURE_HRESET))