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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id v11-20020a170902d08b00b001d94665e9d3sm2658034plv.45.2024.02.02.23.06.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Feb 2024 23:07:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL v2 12/58] target/loongarch: Rename MMU_IDX_* Date: Sat, 3 Feb 2024 17:06:52 +1000 Message-Id: <20240203070654.982407-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240203070654.982407-1-richard.henderson@linaro.org> References: <20240203070654.982407-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c31; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The expected form is MMU_FOO_IDX, not MMU_IDX_FOO. Rename to match generic code. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/loongarch/cpu.h | 8 ++++---- target/loongarch/cpu.c | 2 +- target/loongarch/cpu_helper.c | 4 ++-- target/loongarch/tcg/translate.c | 2 +- target/loongarch/tcg/insn_trans/trans_privileged.c.inc | 2 +- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 5dfcfeb3a4..47fd110e81 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -404,15 +404,15 @@ struct LoongArchCPUClass { */ #define MMU_PLV_KERNEL 0 #define MMU_PLV_USER 3 -#define MMU_IDX_KERNEL MMU_PLV_KERNEL -#define MMU_IDX_USER MMU_PLV_USER -#define MMU_IDX_DA 4 +#define MMU_KERNEL_IDX MMU_PLV_KERNEL +#define MMU_USER_IDX MMU_PLV_USER +#define MMU_DA_IDX 4 int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch); static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY - return MMU_IDX_USER; + return MMU_USER_IDX; #else return loongarch_cpu_mmu_index(env_cpu(env), ifetch); #endif diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index e96159943a..49ced9888e 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -382,7 +382,7 @@ int loongarch_cpu_mmu_index(CPUState *cs, bool ifetch) if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) { return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); } - return MMU_IDX_DA; + return MMU_DA_IDX; } static void loongarch_la464_initfn(Object *obj) diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index f68d63f466..b0658773b0 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -171,8 +171,8 @@ int get_physical_address(CPULoongArchState *env, hwaddr *physical, int *prot, target_ulong address, MMUAccessType access_type, int mmu_idx) { - int user_mode = mmu_idx == MMU_IDX_USER; - int kernel_mode = mmu_idx == MMU_IDX_KERNEL; + int user_mode = mmu_idx == MMU_USER_IDX; + int kernel_mode = mmu_idx == MMU_KERNEL_IDX; uint32_t plv, base_c, base_v; int64_t addr_high; uint8_t da = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, DA); diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c index 235515c629..58674cb268 100644 --- a/target/loongarch/tcg/translate.c +++ b/target/loongarch/tcg/translate.c @@ -125,7 +125,7 @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase, if (ctx->base.tb->flags & HW_FLAGS_CRMD_PG) { ctx->mem_idx = ctx->plv; } else { - ctx->mem_idx = MMU_IDX_DA; + ctx->mem_idx = MMU_DA_IDX; } /* Bound the number of insns to execute to those left on the page. */ diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc index 01d457212b..7e4ec93edb 100644 --- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc @@ -323,7 +323,7 @@ TRANS(iocsrwr_d, IOCSR, gen_iocsrwr, gen_helper_iocsrwr_d) static void check_mmu_idx(DisasContext *ctx) { - if (ctx->mem_idx != MMU_IDX_DA) { + if (ctx->mem_idx != MMU_DA_IDX) { tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next + 4); 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id v11-20020a170902d08b00b001d94665e9d3sm2658034plv.45.2024.02.02.23.07.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Feb 2024 23:07:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Song Gao Subject: [PULL v2 35/58] tcg/loongarch64: Set vector registers call clobbered Date: Sat, 3 Feb 2024 17:06:53 +1000 Message-Id: <20240203070654.982407-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240203070654.982407-1-richard.henderson@linaro.org> References: <20240203070654.982407-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Because there are more call clobbered registers than call saved registers, we begin with all registers as call clobbered and then reset those that are saved. This was missed when we introduced the LSX support. Cc: qemu-stable@nongnu.org Fixes: 16288ded944 ("tcg/loongarch64: Lower basic tcg vec ops to LSX") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2136 Signed-off-by: Richard Henderson Reviewed-by: Song Gao Message-Id: <20240201233414.500588-1-richard.henderson@linaro.org> --- tcg/loongarch64/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index bab0a173a3..dcf0205458 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -2327,7 +2327,7 @@ static void tcg_target_init(TCGContext *s) tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS; - tcg_target_call_clobber_regs = ALL_GENERAL_REGS; + tcg_target_call_clobber_regs = ALL_GENERAL_REGS | ALL_VECTOR_REGS; tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0); tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1); tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2); From patchwork Sat Feb 3 07:06:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 769522 Delivered-To: patch@linaro.org Received: by 2002:adf:9bca:0:b0:33a:e5bd:fedd with SMTP id e10csp1258761wrc; Fri, 2 Feb 2024 23:08:58 -0800 (PST) X-Google-Smtp-Source: AGHT+IGVXWlwQ9NstPLJ5KEn+/DTJa77eGRIaO9kI7RrGNYxgGJcYS8zYmfbBgLANZ7dzeni9v4L X-Received: by 2002:a05:690c:c11:b0:604:1693:80df with SMTP id cl17-20020a05690c0c1100b00604169380dfmr5271385ywb.10.1706944138001; Fri, 02 Feb 2024 23:08:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706944137; cv=none; d=google.com; s=arc-20160816; b=RvswAvNwz9sA9pnbmNa8oJ0WMAcjW63NDryzXNOombeSbncVHOzf7SXRpX2ntUkrGs wU5cE9DwG24jxdGjUjGiDRVahe4kKo+J820uPwcWkznZYpg+XouuKzoQhf+mY7a0hb9G c0NI9Nmoev11bG07W1WUlYzH3f0p43FQaSmiUppj5K51zsIMWnYHUGTk5YAU99CTbvYw kpyMZWMP6Yk0AD2vJZlP1rDmfps0uqVwyy1K1OVlwwsbQ667KpA1bruORft7+5DHjusN BIiD3fGHJRlITGdh2ZtzB+ntOv14zoAMNNlmClIbOCbWJGGNi9+ot44L61GTc2sSoc7W bLgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=0lmpwsvp9czCO9AH20iwRSLsPYqByt2xj1o0sfwNIkQ=; fh=fVtSwAUcY0ERD0mb6bR/AlHzeLp+3vRQciV8fWEf7BQ=; b=qLqe/wkfNmr0Dz4APdbliGxePp/oT366KiOtVKmVLh1W//pafFRf0cIUDCC8L3aYwO QTrIrQlANDxdGQWjqDcyt4cHYvqntB0NNXKXgU47IVLs4jHtC06GL6aLzck9zOhSs/mf CRlFaxV6/JObYj7ATX1xFZrQ249z6VcGcFWh2lgMmAVIprQ3uM+ZWoGp6pc44/+Ztclq lHbeTCr9MNRfpMcZiquO6Ok/oktiGv2EvxM4KoFjOXpRDRbI1DczOCVUaRf1SO96JNVj 2c9LTYf26u9ClC/Z840r6dJWUr9m7wMMff5j1lEuelQ8DCAbaBXWfzn36me9ca3KHhyH BTzQ==; darn=linaro.org ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=II7WZVTU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=0; AJvYcCVVcoKSklZXsdrfklmQX8VHM+LTdOmCDRIjaudpj9GSDSNQchS/+W4iQYhBOeGUMUQaWQzEsa3h17Wxut59WN5C Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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([103.210.27.218]) by smtp.gmail.com with ESMTPSA id v11-20020a170902d08b00b001d94665e9d3sm2658034plv.45.2024.02.02.23.07.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Feb 2024 23:07:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PULL v2 58/58] linux-user/aarch64: Add padding before __kernel_rt_sigreturn Date: Sat, 3 Feb 2024 17:06:54 +1000 Message-Id: <20240203070654.982407-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240203070654.982407-1-richard.henderson@linaro.org> References: <20240203070654.982407-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Without this padding, an unwind through the signal handler will pick up the unwind info for the preceding syscall. This fixes gcc's 30_threads/thread/native_handle/cancel.cc. Cc: qemu-stable@nongnu.org Fixes: ee95fae075c6 ("linux-user/aarch64: Add vdso") Resolves: https://linaro.atlassian.net/browse/GNU-974 Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée Message-Id: <20240202034427.504686-1-richard.henderson@linaro.org> --- linux-user/aarch64/vdso-be.so | Bin 3216 -> 3224 bytes linux-user/aarch64/vdso-le.so | Bin 3216 -> 3224 bytes linux-user/aarch64/vdso.S | 4 ++++ 3 files changed, 4 insertions(+) diff --git a/linux-user/aarch64/vdso-be.so b/linux-user/aarch64/vdso-be.so index 6084f3d1a701316004894fcdd739c4e1e0463b68..808206ade824b09d786f6cc34f7cddf80b63130e 100755 GIT binary patch delta 121 zcmbOrIYV-SKI4pu2Kk&{7{Gw#%fuBAMC1c?^>~k}v|avdxNjSSLfftVb3bgJ!|2S& z_-6A1CJrVZc?IUH8G;R$7#SF@Om<{a*v!K!&BXX-vIe^~TWO|cva$K*Om;sOMw`hy ZxXl@VO#Z-a&zLdUfXALuXmSCM0s#EKC)of1 delta 116 zcmbOsIYDxQKI4Rm2Kk&H7{Gw#!^9O2L>8U?-5V_M@!kH(Sx4vJn|*ujLPgija~Pc& z8DDIEz{J5c`3;N8W)W6tCdL<&4cM*OEF8_CVnO!c?IUH8G;R$7#SF@Om<{a*v!K!!o>JyvLd?^n`3BUW_royOm=q`Mw`hS dxy>1WOn%92&zLb;lgFM@hy!9z%j7~Xc>tTxDQW-! delta 108 zcmbOsIYDxQ2IGW@n)#d`SQx