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[209.51.188.17]) by mx.google.com with ESMTPS id l13-20020a05622a050d00b0042a98c2228fsi4300790qtx.302.2024.01.29.07.19.31 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 29 Jan 2024 07:19:32 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GV1Thag2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rUTPK-0007HR-CR; Mon, 29 Jan 2024 10:18:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rUTPG-00074d-6j for qemu-devel@nongnu.org; Mon, 29 Jan 2024 10:18:42 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rUTPD-0007QQ-JF for qemu-devel@nongnu.org; Mon, 29 Jan 2024 10:18:41 -0500 Received: by mail-wm1-x336.google.com with SMTP id 5b1f17b1804b1-40efcb37373so855215e9.2 for ; Mon, 29 Jan 2024 07:18:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706541518; x=1707146318; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xiohzvoKQkqdcbtLDUjaO0ftHSX88xmuo15mOgH42V4=; b=GV1Thag2jowJxNoR0Ucdjqkn6n5HzSZ461t5w2PRS1UF83J170gzO87dzjKLdlGmYj BetKva+mwTJVvzWUV+JKcz2CalxWfjoHbUAvxRnpgOLaVKNEne/q88DLefUDmc5UYZFz XS+Lwkogir2QeTgJecYb93tfOdy41P71Qf1UfE8nAmGmAA5lem+ihJKxZALqax6Q6Tyg AijzGNJTZV8Mfr96TsodzkodScsgq+l0+x+kIBjL85juXHRi74qmSluCopUXL/6m3saM TOQM36VVh+8DnH15xMbHRw9nrGlr2yP3HzV0QHlMcBaDFoE+kzaqSFs07cCHVwLyD180 h3hg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706541518; x=1707146318; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xiohzvoKQkqdcbtLDUjaO0ftHSX88xmuo15mOgH42V4=; b=Rlwonbu+tRW7BpVeqsMGFDOvhHW99LtXNaITmqSkPDVZIDl2MgAAUuLuf0/8pdaIG0 cNMnQhwzQqIoVxf1lo10HnkltJaH+sc+fHIjHEnuIccOqPl7GnpfsRKPUbY9znv4uSoq eEcPpBeyNMuoTWPq7l+IQDHWNAAt+fTwRwHRhUwSsJfubpDFUWrz3HuKS1rh7YWAu9Ql QTgzTQix17jylUQAafb3Ron1UGeERLnd5kcJMfTaXsiD4Pp7HvXXC47sirjkmcFqbFjR NksWr7wZVLEx2lx4B4SOrMEXtXwixpuZnurQPCGZTILgzAltrUP3a1Cn6wJj0rrAZcYq FeLw== X-Gm-Message-State: AOJu0Yz3PpGC8GrYKZm6a81BywrjW5kW18wOyu6uuJXMZomcjhJK6TMX +R62yfU8vlpTWhgXYFaUaXMWsAqo+x7nazjSn2hFDItaKayq7O5CBHNjQB+ZqsBEDyqC0ZDPVzD B X-Received: by 2002:a5d:49d1:0:b0:33a:e756:bd21 with SMTP id t17-20020a5d49d1000000b0033ae756bd21mr3058604wrs.43.1706541517878; Mon, 29 Jan 2024 07:18:37 -0800 (PST) Received: from m1x-phil.lan ([176.187.219.39]) by smtp.gmail.com with ESMTPSA id ba1-20020a0560001c0100b0033ae593e830sm5764355wrb.23.2024.01.29.07.18.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 29 Jan 2024 07:18:37 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Tyrone Ting , Subbaraya Sundeep , Alistair Francis , Igor Mitsyanko , Hao Wu , "Edgar E. Iglesias" , Peter Maydell , Rob Herring , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Gavin Shan Subject: [PATCH v3 1/9] hw/arm/exynos: Add missing QOM parent for CPU cores Date: Mon, 29 Jan 2024 16:18:20 +0100 Message-ID: <20240129151828.59544-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129151828.59544-1-philmd@linaro.org> References: <20240129151828.59544-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org QDev objects created with qdev_new() need to manually add their parent relationship with object_property_add_child(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan --- hw/arm/exynos4210.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 6c428d8eeb..57c77b140c 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -556,6 +556,7 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) for (n = 0; n < EXYNOS4210_NCPUS; n++) { Object *cpuobj = object_new(ARM_CPU_TYPE_NAME("cortex-a9")); + object_property_add_child(OBJECT(s), "cpu[*]", cpuobj); /* By default A9 CPUs have EL3 enabled. This board does not currently * support EL3 so the CPU EL3 property is disabled before realization. */ From patchwork Mon Jan 29 15:18:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 767386 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp937859wro; Mon, 29 Jan 2024 07:19:32 -0800 (PST) X-Google-Smtp-Source: AGHT+IH42XK/NDk8iwdrpLzCPXceVD4JY4/7dPQAE/1PLySha/sH56k3KLWcyb6iCfn7rrvrbT15 X-Received: by 2002:ae9:e608:0:b0:783:e734:b557 with SMTP id z8-20020ae9e608000000b00783e734b557mr5647180qkf.27.1706541572698; Mon, 29 Jan 2024 07:19:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706541572; cv=none; d=google.com; s=arc-20160816; b=BBkfrEbMF5QenJHnrXh/f+6LDrvgoV08m0A8iVXaAVCnIgV3nSiUxwprGARlxNKvcb 1EDB8HD6woWk8ZiLIqcHYD9AAOqhNQWPoqFKgE63XhmrGth9qqS+Wf96n1mDnOONOU03 UYd3rC/FMMJmjRDdwHSxNj2/4/Hnjh0nT4hS7HvLJXq+1HgGbl8ETc7H7SqCqozFyMdd I1skzwKaX6JUTmS+xi3oAu+X7JU+ztoci9UriEujopPdSy7PAcc+5SHevZgiTsVHJyto jx7ya5yZziwmd0b8JFxCEdPMEPO1eRaQ8oaHVm6KptibuWf9JJ8M3XZMIbKUl/HwibvX QF7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=r+KuOhvBtJ6ncQuNPO3pijGi7HTXapiP3L5g0Ir3MJk=; fh=36wJ/nYrPLZmRQQgalgeL37C59AM5Zbikh1oCIbsvWY=; b=wxFUV2WtFJCU2+fYVrSif0/qBp9sTpLhvVj51dBgnJ5wV2zZ8XYoLRnmSljxqUM30c Dv4P/MOj7wj5dFf7Aj2pKtvOhrH+4cA4gY9JXIcX9tAFxPc/qj6tQsY4EzPv+K8tko7T Lr2CYOLKc5YtxrqvnSPpmewlxmmzVMQ9727VCdnE50nzbhUCbxPG24kPQzXhEwndmTMW Boim58JE4Cu0Uc1LI9j8cW52aM9xU1pJjEmyBgxh5Jg2Jv2Z2TzXJFAqmBQuUDD4HHOp Uu1XDRpmoUed8rhApcfAcX1gpmoTbhXrYIlIYpkOMPBzVdvlnwMEk0saTbyMDAYx4qf4 p//w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=R4kZi0YQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , Peter Maydell , Rob Herring , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Gavin Shan Subject: [PATCH v3 2/9] hw/arm/exynos: Check for CPU types in machine_run_board_init() Date: Mon, 29 Jan 2024 16:18:21 +0100 Message-ID: <20240129151828.59544-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129151828.59544-1-philmd@linaro.org> References: <20240129151828.59544-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Restrict MachineClass::valid_cpu_types[] to the single valid CPU type. Instead of ignoring invalid CPU type requested by the user: $ qemu-system-arm -M nuri -cpu cortex-a7 -S -monitor stdio QEMU 8.2.50 monitor - type 'help' for more information (qemu) info qom-tree /machine (nuri-machine) /soc (exynos4210) /cpu[0] (cortex-a9-arm-cpu) ... We now display an error: $ qemu-system-arm -M nuri -cpu cortex-a7 qemu-system-arm: Invalid CPU model: cortex-a7 The only valid type is: cortex-a9 Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan --- hw/arm/exynos4_boards.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c index b0e13eb4f0..01c7618a67 100644 --- a/hw/arm/exynos4_boards.c +++ b/hw/arm/exynos4_boards.c @@ -34,6 +34,7 @@ #include "hw/qdev-properties.h" #include "hw/boards.h" #include "hw/irq.h" +#include "target/arm/cpu-qom.h" #define SMDK_LAN9118_BASE_ADDR 0x05000000 @@ -150,12 +151,18 @@ static void smdkc210_init(MachineState *machine) arm_load_kernel(s->soc.cpu[0], machine, &exynos4_board_binfo); } +static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-a9"), + NULL +}; + static void nuri_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); mc->desc = "Samsung NURI board (Exynos4210)"; mc->init = nuri_init; + mc->valid_cpu_types = valid_cpu_types; mc->max_cpus = EXYNOS4210_NCPUS; mc->min_cpus = EXYNOS4210_NCPUS; mc->default_cpus = EXYNOS4210_NCPUS; @@ -174,6 +181,7 @@ static void smdkc210_class_init(ObjectClass *oc, void *data) mc->desc = "Samsung SMDKC210 board (Exynos4210)"; mc->init = smdkc210_init; + mc->valid_cpu_types = valid_cpu_types; mc->max_cpus = EXYNOS4210_NCPUS; mc->min_cpus = EXYNOS4210_NCPUS; mc->default_cpus = EXYNOS4210_NCPUS; From patchwork Mon Jan 29 15:18:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 767393 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp938687wro; Mon, 29 Jan 2024 07:21:02 -0800 (PST) X-Google-Smtp-Source: AGHT+IH2YVLNqh8PAp8G3VTJbKCQfObYzpqOsAVDk2wiJDKa19/v9NVVSkSYUSv6T5FYmPD87C8j X-Received: by 2002:a05:620a:918:b0:783:82af:f516 with SMTP id v24-20020a05620a091800b0078382aff516mr4625387qkv.62.1706541661941; Mon, 29 Jan 2024 07:21:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706541661; cv=none; d=google.com; s=arc-20160816; b=iwqDpy8PMNfSrJFYlk5eQLYzksRuroEfGuXQdN99iKgqLhMOsHTbjB3g7ulfQzBTPA WoLj/grYykS63kdZnZSPSq73Rwqj8p7EeRwJZSU00sgGvsecvORgwDzuciIKXydL6gXF UYlc3bI+G9rKUUx2FJl73vH91FBzy9Lt1Sy3qIwxwlslHIxrX4lr9MKqezILVhMUH90o zz3Voa2w7i+wVepieGcXPxqxm1+jblBTGBIUlTpcQAFVhWGOXQ0G5tEoEDW/BbC6juZx bsrA+39UHy9suXTwuldTWKNSicp2hGH1qmfQB9IZH7CfNx7xmKB9/FTV5aX0Y3lNKI+G YoZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=jC58YmpOm3xZcOtP9AEc7xhs85+MVmwSSZ2Oh6qeQAw=; fh=36wJ/nYrPLZmRQQgalgeL37C59AM5Zbikh1oCIbsvWY=; b=v2yBY8mWBVxtkvtg6AeJ5Pui+gIYHN1rLVl8S1NEvVL8fcVw/A+yKkxb4Q4zLvEvQM fLdJilpLscoTCvsaa0Gxokx2ITqYqElnO51lOtfHFf8432sgP05Phqe346MTifofF3Rr Rk54SAcfj1lM43CEp22SxB/kWflv5rvZvCm+gVuP+AWbv2GHLTXrGlgn6Tmr0jFUjYA9 mp7elyawsVXWKCuJQi9qZicrcKCiSJp2w1naiVeZFFp1Q8gHQl2aTCLEIhgqwEEIPvuW 0nzIt8uR49c6DKVH7MIZPRJE4drqw2M1etZ36Wu1Y/10JZc51YOuI3CDVbT2jVT1OrMM v3LA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SvNVlvaK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , Peter Maydell , Rob Herring , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Gavin Shan Subject: [PATCH v3 3/9] hw/arm/highbank: Add missing QOM parent for CPU cores Date: Mon, 29 Jan 2024 16:18:22 +0100 Message-ID: <20240129151828.59544-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129151828.59544-1-philmd@linaro.org> References: <20240129151828.59544-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org QDev objects created with qdev_new() need to manually add their parent relationship with object_property_add_child(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan --- hw/arm/highbank.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index e6e27d69af..b8d702c82c 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -209,6 +209,7 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id) cpuobj = object_new(machine->cpu_type); cpu = ARM_CPU(cpuobj); + object_property_add_child(OBJECT(machine), "cpu[*]", cpuobj); object_property_set_int(cpuobj, "psci-conduit", QEMU_PSCI_CONDUIT_SMC, &error_abort); From patchwork Mon Jan 29 15:18:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 767394 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp938788wro; Mon, 29 Jan 2024 07:21:12 -0800 (PST) X-Google-Smtp-Source: AGHT+IEe2TIsN5y9DsOa20TYsAv+JD3vbs7tZ/qcFfQi7dCv+9iXvgNLuYza1W1k+p4twSX3QRDR X-Received: by 2002:a05:622a:50a:b0:42a:5b80:73f1 with SMTP id l10-20020a05622a050a00b0042a5b8073f1mr7046964qtx.79.1706541672437; Mon, 29 Jan 2024 07:21:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706541672; cv=none; d=google.com; s=arc-20160816; b=R22gJ8nPajAFIKJWOp5vhmosmMDk6h6HnDdd0w2xJGze33/Tk/v3ZyihUpk7bV2dmt qf8ddesIEokjkhcXsHKyz6NKHvBsLiVZ+PqXTvfbIoGtSCojDtizDKMT+5o8SfrgoO6N sQm1eDVXMYCNInjmz4P+d0PZzNI/MIqV9bdx1pANzhh33Ah8QRfayA5JAkcA8zwU4ITS JFudvAn1tLt1ctPX3XzCccTREyNIM+LCSKr2j6vanfafAl05tc5kYPUt/flYH7JJQgPj i6m8pHlyi4svKOUzw/U5IevtGm01AEmXQEbkID9Mlr6Gg6N41KDfzdeWC4jKp1hmUKZp pyUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=dcxTw0DrdmCPot2iJuF6Ul0G9M2q8XR4FUwWiq3hCFw=; fh=36wJ/nYrPLZmRQQgalgeL37C59AM5Zbikh1oCIbsvWY=; b=Zo3yU9tBne5ZCQpPJ4dkan7xcxyOnfJF0aJb5JpdY9twYaYajnOeSFiENaxlvPhywv p1lgB6Xo4Xl+5Ugo07BOZrlEdABiN592QubtYCMmzVniDqySK3ZAzAzra1DnP/U8YPnK bpkD2xqxKRcegE4jcEiF/We+n+byG3h39+Adh6BcglP9bVvNf3nA8fssEIqRYr0RvCFN HOQAtFsD2D85W07ybzqsC74hHnFugHd7BcPN8ZvsGON1S8zhAsvHaepS9yt2q6WLw1Wf v6aHW/xCMt7ogNDM/2gkTVqo07sH5ZGi8MXj5NMAPgcHhIprAaPfwES3BbB4wA7nL1vx D4og== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Kx01oTFg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , Peter Maydell , Rob Herring , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Gavin Shan Subject: [PATCH v3 4/9] hw/arm/highbank: Check for CPU types in machine_run_board_init() Date: Mon, 29 Jan 2024 16:18:23 +0100 Message-ID: <20240129151828.59544-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129151828.59544-1-philmd@linaro.org> References: <20240129151828.59544-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::131; envelope-from=philmd@linaro.org; helo=mail-lf1-x131.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Restrict MachineClass::valid_cpu_types[] to the single valid CPU types. Instead of ignoring invalid CPU type requested by the user: $ qemu-system-arm -M midway -cpu cortex-a7 -S -monitor stdio QEMU 8.2.50 monitor - type 'help' for more information (qemu) info qom-tree /machine (midway-machine) /cpu[0] (cortex-a15-arm-cpu) ... we now display an error: $ qemu-system-arm -M midway -cpu cortex-a7 qemu-system-arm: Invalid CPU model: cortex-a7 The only valid type is: cortex-a15 Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan --- hw/arm/highbank.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index b8d702c82c..0367050697 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -345,10 +345,15 @@ static void midway_init(MachineState *machine) static void highbank_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-a9"), + NULL + }; MachineClass *mc = MACHINE_CLASS(oc); mc->desc = "Calxeda Highbank (ECX-1000)"; mc->init = highbank_init; + mc->valid_cpu_types = valid_cpu_types; mc->block_default_type = IF_IDE; mc->units_per_default_bus = 1; mc->max_cpus = 4; @@ -364,10 +369,15 @@ static const TypeInfo highbank_type = { static void midway_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-a15"), + NULL + }; MachineClass *mc = MACHINE_CLASS(oc); mc->desc = "Calxeda Midway (ECX-2000)"; mc->init = midway_init; + mc->valid_cpu_types = valid_cpu_types; mc->block_default_type = IF_IDE; mc->units_per_default_bus = 1; mc->max_cpus = 4; From patchwork Mon Jan 29 15:18:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 767392 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp938579wro; Mon, 29 Jan 2024 07:20:52 -0800 (PST) X-Google-Smtp-Source: AGHT+IEB+E5i89Pj41AD93ERSO9d9+VJlaIusfpz145ge8oO2eI8aRzN2ydfmaifskA1O/C1IyWO X-Received: by 2002:a05:620a:44c2:b0:784:5c9:ba48 with SMTP id y2-20020a05620a44c200b0078405c9ba48mr873840qkp.65.1706541652228; Mon, 29 Jan 2024 07:20:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706541652; cv=none; d=google.com; s=arc-20160816; b=ADMhAEJf8+PGiR5aJpYhftrhE3GaaRCDDaJ5JHy3RJlYb9Kd4akcOx2ejr/s1Q3uv3 9Lgw4PvWvKga4UOMZgHSEwJ9+a0NBQ4hX0HaAHkzd1Crz+StoOWSzjXXRWaiT28lLdUS FSetYkrQ4yjbk5ksAPkoxF3YUTi4106dsdDfSKNKKkxNy4TLwhcITku/2shxeSZHPMlA NhUYZ03fX+lHbt5/AwcoosO/fwe1JTvNUe14Vyv3hYuT1WJVTDU+UrpHz+QLlZM2aJit IHq4OB7dklCS8wq0YIEzgVqLZysfJRD1yNyoYxwlon/vb8RG6I41+gZ3s1MguJBs5Gtu CsdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=qv6tmFjUz5yI+ezdbTnOo4SrqA0F8CpD3AVMoPUpbVM=; fh=Q7sPWZVumIp+YJDEXhcbqZA2VLBOzLVoxgbszpp+aBE=; b=tWF4n7+KEhCx1rIbPmsMeOQV3ZY6JiohExPQRhNryDe0Fneu4hmfl6wzCASJUC6yWS Z6trq5PA9g6j69/gl5o5REmgIKLUJk+yj0Cz254Ng1OXHcYg/9sb8YIarTkpHNPH+QB0 +x9aehvx8vTQyHBESe2TMxCR3YgzJhvzNMGffnsC2JeDyIa+JmCRKcRdBd9YIR6wEPbi qt/WcuARygGG9khtGqkF596qBUaepFW8lc1dvHM+ov2w9fMlyVMNDXp/0LIBj1XWTtL5 LkXsvu8FAtH9vTR+koPc7NUU9oDOWNrGTt46L4WY5J/t08uJxthriAvFC6m2+Mk2WTnJ P4oA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AKdcK66m; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , Peter Maydell , Rob Herring , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH v3 5/9] hw/arm/msf2: Simplify setting MachineClass::valid_cpu_types[] Date: Mon, 29 Jan 2024 16:18:24 +0100 Message-ID: <20240129151828.59544-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129151828.59544-1-philmd@linaro.org> References: <20240129151828.59544-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The M2Sxxx SoC family can only be used with Cortex-M3. Propagating the CPU type from the board level is pointless. Hard-code the CPU type at the SoC level. Remove the now ignored MachineClass::default_cpu_type field. Use the common code introduced in commit c9cf636d48 ("machine: Add a valid_cpu_types property") to check for valid CPU type at the board level. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- include/hw/arm/msf2-soc.h | 3 --- hw/arm/msf2-soc.c | 3 +-- hw/arm/msf2-som.c | 4 ---- 3 files changed, 1 insertion(+), 9 deletions(-) diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h index ce417a6266..9300664e8e 100644 --- a/include/hw/arm/msf2-soc.h +++ b/include/hw/arm/msf2-soc.h @@ -47,13 +47,10 @@ OBJECT_DECLARE_SIMPLE_TYPE(MSF2State, MSF2_SOC) #define MSF2_NUM_TIMERS 2 struct MSF2State { - /*< private >*/ SysBusDevice parent_obj; - /*< public >*/ ARMv7MState armv7m; - char *cpu_type; char *part_name; uint64_t envm_size; uint64_t esram_size; diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c index b5fe9f364d..d6eb9ec9ac 100644 --- a/hw/arm/msf2-soc.c +++ b/hw/arm/msf2-soc.c @@ -134,7 +134,7 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) armv7m = DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 81); - qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); + qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m3")); qdev_prop_set_bit(armv7m, "enable-bitband", true); qdev_connect_clock_in(armv7m, "cpuclk", s->m3clk); qdev_connect_clock_in(armv7m, "refclk", s->refclk); @@ -231,7 +231,6 @@ static Property m2sxxx_soc_properties[] = { * part name specifies the type of SmartFusion2 device variant(this * property is for information purpose only. */ - DEFINE_PROP_STRING("cpu-type", MSF2State, cpu_type), DEFINE_PROP_STRING("part-name", MSF2State, part_name), DEFINE_PROP_UINT64("eNVM-size", MSF2State, envm_size, MSF2_ENVM_MAX_SIZE), DEFINE_PROP_UINT64("eSRAM-size", MSF2State, esram_size, diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c index a269cf044b..5c415abe85 100644 --- a/hw/arm/msf2-som.c +++ b/hw/arm/msf2-som.c @@ -47,7 +47,6 @@ static void emcraft_sf2_s2s010_init(MachineState *machine) DeviceState *dev; DeviceState *spi_flash; MSF2State *soc; - MachineClass *mc = MACHINE_GET_CLASS(machine); DriveInfo *dinfo = drive_get(IF_MTD, 0, 0); qemu_irq cs_line; BusState *spi_bus; @@ -62,8 +61,6 @@ static void emcraft_sf2_s2s010_init(MachineState *machine) dev = qdev_new(TYPE_MSF2_SOC); object_property_add_child(OBJECT(machine), "soc", OBJECT(dev)); qdev_prop_set_string(dev, "part-name", "M2S010"); - qdev_prop_set_string(dev, "cpu-type", mc->default_cpu_type); - qdev_prop_set_uint64(dev, "eNVM-size", M2S010_ENVM_SIZE); qdev_prop_set_uint64(dev, "eSRAM-size", M2S010_ESRAM_SIZE); @@ -108,7 +105,6 @@ static void emcraft_sf2_machine_init(MachineClass *mc) mc->desc = "SmartFusion2 SOM kit from Emcraft (M2S010)"; mc->init = emcraft_sf2_s2s010_init; - mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3"); mc->valid_cpu_types = valid_cpu_types; } From patchwork Mon Jan 29 15:18:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 767390 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp938238wro; Mon, 29 Jan 2024 07:20:16 -0800 (PST) X-Google-Smtp-Source: AGHT+IFWP0mkW3fZdXxsJ5s2ziidB1KBtUycLuGpnddzZwg2hGFGoQHFLSSa18zIdz9RZPq8xivh X-Received: by 2002:ac8:7d4d:0:b0:42a:a079:f766 with SMTP id h13-20020ac87d4d000000b0042aa079f766mr3628868qtb.110.1706541616261; Mon, 29 Jan 2024 07:20:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706541616; cv=none; d=google.com; s=arc-20160816; b=yt+8IELZvfj9gJ+C7/SZRtFn4WNrk0wH8At9CMECtDVXIa7afVLCJ1+bJH2RYIzdsK JVjKlPAVGx/a+ceNVM2EuBxN+sDQPnDdm+QWXp7Z7GAM4StHjKjzZrVTmv7cr8cq79mx eCoKaAWfuSAt2ZAEBJFaYEMq/Z5BveeVoVhw8zBRsQPTo/+5sdIZlVFC+s3sswHsEHWF Ui6yyAdztHysUC0RkeKVwy9sn1VAwpGCZca6r2vIz5XWTRDWq72Zj5KA/zVFaV/Bb6vH nzaEwD5/8IpgDgxZ/wA8N8RDw0CQ6zCFOJq2DCyQZ9hsJR3e357wfpe3i45Gk2wybKCA wXxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=letmG5/Sw/UvLSNttdIXIs4OU6VOMo7YyUWWgNEfysU=; fh=Q7sPWZVumIp+YJDEXhcbqZA2VLBOzLVoxgbszpp+aBE=; b=ZKl5wY279IhcOQox9mIjfCZMthDoLXx6lmHfRehCXKHIjNXkekHU2131URF6IxidvG aDY8k9h0DodWzs2kpZIQOhWSetfX32bxRo4oYDKtczTUKHOh1qanf8CBtlMsVWHeXkyN ouXhoBdMbCPIsOvn+LfyvHRLqf3tH2KzPF2QHsWTsn98axJoICkaofMoEdB8Y/XstWwP TrVXBLFXVVtEOXxTigFEoKzP7rYMxDHyGQKiKD7EveA/uEjHiq7fftTDLOjyjRS1+MIJ ondC3Np93jgpLml77cwnZUiJL5WSXvmZ6ngakX93BAO29GEozX1+QI35bD9VuSk3y2qr xHGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=clGEcFZU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , Peter Maydell , Rob Herring , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH v3 6/9] hw/arm/musca: Simplify setting MachineClass::valid_cpu_types[] Date: Mon, 29 Jan 2024 16:18:25 +0100 Message-ID: <20240129151828.59544-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129151828.59544-1-philmd@linaro.org> References: <20240129151828.59544-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Musca boards use the embedded subsystems (SSE) tied to a specific Cortex core. Our models only use the Cortex-M33. Use the common code introduced in commit c9cf636d48 ("machine: Add a valid_cpu_types property") to check for valid CPU type at the board level. Remove the now unused MachineClass::default_cpu_type field. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/musca.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/arm/musca.c b/hw/arm/musca.c index 770ec1a15c..e2c9d49af5 100644 --- a/hw/arm/musca.c +++ b/hw/arm/musca.c @@ -605,7 +605,6 @@ static void musca_class_init(ObjectClass *oc, void *data) mc->default_cpus = 2; mc->min_cpus = mc->default_cpus; mc->max_cpus = mc->default_cpus; - mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m33"); mc->valid_cpu_types = valid_cpu_types; mc->init = musca_init; } From patchwork Mon Jan 29 15:18:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 767387 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp937856wro; Mon, 29 Jan 2024 07:19:32 -0800 (PST) X-Google-Smtp-Source: AGHT+IGzrHZmnBQTAz8QCT4+HNYRConj1S9lLBdvOjKiNqxLfO1gLI6cE0mlM8IIfh10zgMYACmN X-Received: by 2002:ad4:5969:0:b0:68c:5ac1:dd3b with SMTP id eq9-20020ad45969000000b0068c5ac1dd3bmr463517qvb.74.1706541572595; Mon, 29 Jan 2024 07:19:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706541572; cv=none; d=google.com; s=arc-20160816; b=Q4Cw0toeG2mA2gwnx+1AQ4lusWRvafCEJuuH3W7BtBCN7yibSgw94yWsRlBuld2A4g OuYUZsk6pn/ELnDjv2fpBStB4FA0AjEQ3MKUbVsFU2MuGCVhEqP3aAfH8305eE7G+iTN gFs6pYrkw7olba6OaMk1Zs93sHFlBWEI1FFOJ12EtzVsbI3L5I8lJKCrxJ7VWOCQ13Lf m0/zAxYuyINiIIuE4YQPnazKEpnYzmiJVPELo8WFxo2vm0t51Q2EoZ/7ru4wqXEnMYEe hi+hLbCgPh5e7BVou5UnJt1bzQ9OaYUvnuoyd9cUzZCtVN02o+RrfJzzm0cPR5UNIp/5 9gyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=MFN/VSnR85vSlwmoZKq2ZY9d+Yj3Zr7afXCJn+FdH7U=; fh=Q7sPWZVumIp+YJDEXhcbqZA2VLBOzLVoxgbszpp+aBE=; b=jENjUCpW02WD1kfbG/L+Ypxq9nPRN6aapx0RpQSjPFJJP0ikHkig6vvuPDtgEmu5ky 1Jw2vxJSBMqii+o+arnj7NlQszGituqmWTAkv8xncNh7BcJ4GvJ/UpLnU8HxfOn31zRk m+J8i9ztmvJVBQAuwTjirBRd8edELtNfzkWhLsBFfPOVNScxo/eyPhEUqUZBx6oBenMe V6hfBnbUkpsxlO74RzZoz5mEYITQkppMfI7nIZIKU6sHQ+MWIQQJhM+g6Ehb/t/rDOiv 5jqXOhqYpG4YfptR3a7IDSJ213v5zHC8TbropO5dzf7dnv7oDvXihAwNIMR6LzT8pyMx IMsQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZuckoVuL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , Peter Maydell , Rob Herring , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH v3 7/9] hw/arm/npcm7xx_boards: Simplify setting MachineClass::valid_cpu_types[] Date: Mon, 29 Jan 2024 16:18:26 +0100 Message-ID: <20240129151828.59544-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129151828.59544-1-philmd@linaro.org> References: <20240129151828.59544-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::130; envelope-from=philmd@linaro.org; helo=mail-lf1-x130.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The npcm7xx Soc is created with a Cortex-A9 core, see in hw/arm/npcm7xx.c: static void npcm7xx_init(Object *obj) { NPCM7xxState *s = NPCM7XX(obj); for (int i = 0; i < NPCM7XX_MAX_NUM_CPUS; i++) { object_initialize_child(obj, "cpu[*]", &s->cpu[i], ARM_CPU_TYPE_NAME("cortex-a9")); } The MachineClass::default_cpu_type field is ignored: delete it. Use the common code introduced in commit c9cf636d48 ("machine: Add a valid_cpu_types property") to check for valid CPU type at the board level. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/npcm7xx_boards.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index 2999b8b96d..e229efb447 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -465,7 +465,6 @@ static void npcm7xx_machine_class_init(ObjectClass *oc, void *data) mc->no_cdrom = 1; mc->no_parallel = 1; mc->default_ram_id = "ram"; - mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); mc->valid_cpu_types = valid_cpu_types; } From patchwork Mon Jan 29 15:18:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 767388 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp937997wro; Mon, 29 Jan 2024 07:19:47 -0800 (PST) X-Google-Smtp-Source: AGHT+IGuGWXqARzYlLiwIrtgnudiGQh80LLKG71Tv2/lTXVJjYAXE42O4sbdY1Gxr1egpBdJsqfW X-Received: by 2002:ac8:7f4b:0:b0:429:cfa7:4218 with SMTP id g11-20020ac87f4b000000b00429cfa74218mr6206195qtk.71.1706541586855; Mon, 29 Jan 2024 07:19:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706541586; cv=none; d=google.com; s=arc-20160816; b=lEGwtL2Gn5RRGu/XR5I04H513It9BIvuChqYlPIrdEd8pUH+tsSsIY1a6uMnHLj0+Y Mgp0Y7pWBPjqrrzrJEka2gfG91inrCZw49FXutFYZQhDESRo4C4hX3FrUTaaOaAMmQKw PDM1eNgA3AvfaUORl4Y8kyULin5r8UeT/aGw5hctcTS6psxUfnjVQTUxlLa0IHK1McmS FMFVoYSTLLyxIyCt5aaHglyIF5OzOezxYUo6huUJo3uKunbu6MNq8V0eO6AUHBS1crGT /gypz/QCU0rUwAfuwpL840CHDBObUbRn+tPtkXuQZiEETLIZQUo252oe78Mbhim1BIJQ wgFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=xtXJej6F9O2lSIbmdUvlDD/icBrkbUZ4loB0TQu2OEE=; fh=36wJ/nYrPLZmRQQgalgeL37C59AM5Zbikh1oCIbsvWY=; b=vPb1F+d/nnfIJqaOi6kW34Xr5YePpwdg0EnnsCtXiEnqEIkRkcQnLsCVpPqyc+XhFo oU/e4EbnRS8cxO+mmeQw4fuHgpI5OiJD76/awgcGRNZZ7CKgu/rdSVDgulQpE12AbaUZ Co0WtSWDfAUtE9oTUBGQIA1HUt0vryTQTAsphVG983L28IzMZdz8V2ueCXEVI+eHxtv3 NgNsXkUOhMo5T/SS5eKqHMMDyuQb6/kt+RtY7OIaZRFW50XlvuJHrjkLqY9It9DIJ04f nKadg0gyHdlsvBxjBQ/H+N/gC4l4p0MYlB8SGcbzHmVgOsGr/0Kn/w2erC19lNEIGxuC IOIw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HiM4rDVJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , Peter Maydell , Rob Herring , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Gavin Shan Subject: [PATCH v3 8/9] hw/arm/vexpress: Check for CPU types in machine_run_board_init() Date: Mon, 29 Jan 2024 16:18:27 +0100 Message-ID: <20240129151828.59544-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129151828.59544-1-philmd@linaro.org> References: <20240129151828.59544-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Leverage the common code introduced in commit c9cf636d48 ("machine: Add a valid_cpu_types property") to check for the single valid CPU type. Remove the now unused MachineClass::default_cpu_type field. Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/vexpress.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index f1b45245d5..1a14c1933e 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -783,22 +783,30 @@ static void vexpress_class_init(ObjectClass *oc, void *data) static void vexpress_a9_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-a9"), + NULL + }; MachineClass *mc = MACHINE_CLASS(oc); VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); mc->desc = "ARM Versatile Express for Cortex-A9"; - mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); + mc->valid_cpu_types = valid_cpu_types; vmc->daughterboard = &a9_daughterboard; } static void vexpress_a15_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-a15"), + NULL + }; MachineClass *mc = MACHINE_CLASS(oc); VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc); mc->desc = "ARM Versatile Express for Cortex-A15"; - mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); + mc->valid_cpu_types = valid_cpu_types; vmc->daughterboard = &a15_daughterboard; From patchwork Mon Jan 29 15:18:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 767389 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp938233wro; Mon, 29 Jan 2024 07:20:16 -0800 (PST) X-Google-Smtp-Source: AGHT+IHJc8stScKvosmWXyHUbMDHg635TfCVT0nN9yia+J91FurANLZMB9IK5KxK83kAl2W5Jr7A X-Received: by 2002:a05:6214:ccc:b0:68c:47ad:ef60 with SMTP id 12-20020a0562140ccc00b0068c47adef60mr4913059qvx.45.1706541615846; Mon, 29 Jan 2024 07:20:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706541615; cv=none; d=google.com; s=arc-20160816; b=hvwrFdhwG4N9J1D2glIgRdAhTMB17O5S5awX5IK4JazgU5M21V8wBdN6evC2cJdyLd xxC6oRSczOFCRLbtZplsNqFFY9UGJy8MJFVPEJEcd/L3fQZmRF7y0iNnczFwaTJ4g9F8 2wtk0ybevYa6YahO2HR5XIIGf2oahWcUCCFVLFOa/7faFB/cqw6Of7L4Kq464dJNicDL oqpita+YSKwo2211tHOJPnzqeA+RilJoZpDGGMRkRnnuAej3OA0UA7naQLattD7NeYML dycjTt3G9RD62tT6R0lI9/Es5RDGa3PNAfTHah+3AJMbGJaHrWJOso8A3PPoLbMIBtqv dqdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=zOazw+OwEfzfL7xWrU1RcBd6XD/48I1cQP0Tkf0Wbm4=; fh=36wJ/nYrPLZmRQQgalgeL37C59AM5Zbikh1oCIbsvWY=; b=rv9sWk/vg6g9psbDv/XFhBWblOLH0FChHUMOtdj09e8yqlvF3rQYdimfWfPWJ2jIHf d5eEpB7Wfl/BKt5XgPIHnSWjuHcPCskknJ2GquM5i39VMR4m5ZNcHgvwe/x3APuT/b+L 2GjfY8STzc6O4k6M1BntbGmLU+PWvPzRqAMw5SqU+SUbgp1MpUSktg3dK68hf/owgMdy 0f68NtmW+hTHhwDoZcbOrH6q/2HHUMoz5E+bkSmeaFyqTwB6sqq7r2zMMC77nV940ieS CguNv14dUzGbGD1PVpX5+Rn8YIH20nQWIgn3pEMyKvHaCkwX0cTCvIhjTj2hiuPgfRYd 5Q0w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UDWTdALg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , Peter Maydell , Rob Herring , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Gavin Shan Subject: [PATCH v3 9/9] hw/arm/zynq: Check for CPU types in machine_run_board_init() Date: Mon, 29 Jan 2024 16:18:28 +0100 Message-ID: <20240129151828.59544-10-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240129151828.59544-1-philmd@linaro.org> References: <20240129151828.59544-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Leverage the common code introduced in commit c9cf636d48 ("machine: Add a valid_cpu_types property") to check for the single valid CPU type. Remove the now unused MachineClass::default_cpu_type field. Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/xilinx_zynq.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 66d0de139f..c57bbccb70 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -355,13 +355,17 @@ static void zynq_init(MachineState *machine) static void zynq_machine_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-a9"), + NULL + }; MachineClass *mc = MACHINE_CLASS(oc); mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9"; mc->init = zynq_init; mc->max_cpus = 1; mc->no_sdcard = 1; mc->ignore_memory_transaction_failures = true; - mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); + mc->valid_cpu_types = valid_cpu_types; mc->default_ram_id = "zynq.ext_ram"; }