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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000044F4.mail.protection.outlook.com (10.167.241.74) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7228.16 via Frontend Transport; Fri, 26 Jan 2024 08:08:45 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Fri, 26 Jan 2024 02:08:42 -0600 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH 1/7] cpufreq: amd-pstate: remove set_boost callback for passive mode Date: Fri, 26 Jan 2024 16:08:04 +0800 Message-ID: <3404e063b86a5517b70d497b066c3fdeb5d8bef3.1706255676.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F4:EE_|DM4PR12MB5311:EE_ X-MS-Office365-Filtering-Correlation-Id: 71ebeea6-447c-4ae7-519d-08dc1e4604bc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jan 2024 08:08:45.4199 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 71ebeea6-447c-4ae7-519d-08dc1e4604bc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5311 From: Perry Yuan The following patches will enable `amd-pstate` CPU boost control method which will not need this common boost control callback anymore, so we remove the legacy set_boost interface from amd-pstate driver. Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 26 -------------------------- 1 file changed, 26 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 9a1e194d5cf8..8f308f56ade6 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -632,31 +632,6 @@ static int amd_get_lowest_nonlinear_freq(struct amd_cpudata *cpudata) return lowest_nonlinear_freq * 1000; } -static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state) -{ - struct amd_cpudata *cpudata = policy->driver_data; - int ret; - - if (!cpudata->boost_supported) { - pr_err("Boost mode is not supported by this processor or SBIOS\n"); - return -EINVAL; - } - - if (state) - policy->cpuinfo.max_freq = cpudata->max_freq; - else - policy->cpuinfo.max_freq = cpudata->nominal_freq; - - policy->max = policy->cpuinfo.max_freq; - - ret = freq_qos_update_request(&cpudata->req[1], - policy->cpuinfo.max_freq); - if (ret < 0) - return ret; - - return 0; -} - static void amd_pstate_boost_init(struct amd_cpudata *cpudata) { u32 highest_perf, nominal_perf; @@ -1391,7 +1366,6 @@ static struct cpufreq_driver amd_pstate_driver = { .exit = amd_pstate_cpu_exit, .suspend = amd_pstate_cpu_suspend, .resume = amd_pstate_cpu_resume, - .set_boost = amd_pstate_set_boost, .name = "amd-pstate", .attr = amd_pstate_attr, }; From patchwork Fri Jan 26 08:08:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 767292 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2060.outbound.protection.outlook.com [40.107.237.60]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD5DB679F1; Fri, 26 Jan 2024 08:08:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.237.60 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706256537; cv=fail; b=a+U0u0D0I810CpoRpM619q8Wh/E72i3PZDKdiArd8wQK/w7iNjSiaJK7wGGNqsJc6gYA4SDg0qt609pA8rEWPKEpUA6FaLW6yXGjRbFLSsy7q4YZUXUpY3gTidAKJNhnJ0HboTWrH/UvKTRJ+JdYaVnIAMLIXXW/uBoJ9rBXmmI= ARC-Message-Signature: i=2; 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Fri, 26 Jan 2024 08:08:52 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1PEPF000044F4.mail.protection.outlook.com (10.167.241.74) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7228.16 via Frontend Transport; Fri, 26 Jan 2024 08:08:52 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Fri, 26 Jan 2024 02:08:48 -0600 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH 3/7] cpufreq: amd-pstate: implement cpb_boost sysfs entry for boost control Date: Fri, 26 Jan 2024 16:08:06 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F4:EE_|IA0PR12MB8747:EE_ X-MS-Office365-Filtering-Correlation-Id: ef55b06a-48ae-4a8d-bd5a-08dc1e4608f6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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SFS:(13230031)(4636009)(346002)(376002)(396003)(136003)(39860400002)(230922051799003)(451199024)(1800799012)(186009)(64100799003)(82310400011)(46966006)(36840700001)(40470700004)(70206006)(2906002)(44832011)(5660300002)(16526019)(26005)(356005)(81166007)(36860700001)(478600001)(966005)(36756003)(336012)(82740400003)(2616005)(86362001)(426003)(41300700001)(83380400001)(7696005)(6666004)(54906003)(4326008)(8676002)(8936002)(47076005)(316002)(6636002)(110136005)(70586007)(40480700001)(40460700003)(36900700001)(309714004); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jan 2024 08:08:52.0606 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ef55b06a-48ae-4a8d-bd5a-08dc1e4608f6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8747 From: Perry Yuan With this new sysfs entry `cpb_boost`created, user can change CPU boost state dynamically under `active` and `passive` modes. And the highest perf and frequency will also be updated as the boost state changing. 0: check current boost state cat /sys/devices/system/cpu/amd_pstate/cpb_boost 1: disable CPU boost sudo bash -c "echo 0 > /sys/devices/system/cpu/amd_pstate/cpb_boost" 2: enable CPU boost sudo bash -c "echo 1 > /sys/devices/system/cpu/amd_pstate/cpb_boost" Link: https://bugzilla.kernel.org/show_bug.cgi?id=217931 Link: https://bugzilla.kernel.org/show_bug.cgi?id=217618 Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 97 ++++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 0dc9124140d4..b37bea7440b9 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1036,6 +1036,101 @@ static ssize_t status_store(struct device *a, struct device_attribute *b, return ret < 0 ? ret : count; } +static int amd_cpu_boost_update(struct amd_cpudata *cpudata, u32 on) +{ + struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpudata->cpu); + struct cppc_perf_ctrls perf_ctrls; + u32 highest_perf, nominal_perf; + int ret; + + if (!policy) + return -ENODATA; + + highest_perf = READ_ONCE(cpudata->highest_perf); + nominal_perf = READ_ONCE(cpudata->nominal_perf); + + if (boot_cpu_has(X86_FEATURE_CPPC)) { + u64 value = READ_ONCE(cpudata->cppc_req_cached); + + value &= ~GENMASK_ULL(7, 0); + value |= on ? highest_perf : nominal_perf; + WRITE_ONCE(cpudata->cppc_req_cached, value); + + wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); + + } else { + perf_ctrls.max_perf = on ? highest_perf : nominal_perf; + ret = cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1); + if (ret) { + pr_debug("failed to set energy perf value (%d)\n", ret); + return ret; + } + } + + if (on) + policy->cpuinfo.max_freq = cpudata->max_freq; + else + policy->cpuinfo.max_freq = cpudata->nominal_freq; + + policy->max = policy->cpuinfo.max_freq; + + if (cppc_state == AMD_PSTATE_PASSIVE) { + ret = freq_qos_update_request(&cpudata->req[1], + policy->cpuinfo.max_freq); + } + + cpufreq_cpu_release(policy); + + return ret; +} + +static ssize_t cpb_boost_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sysfs_emit(buf, "%u\n", global.cpb_boost); +} + +static ssize_t cpb_boost_store(struct device *dev, struct device_attribute *b, + const char *buf, size_t count) +{ + bool new_state; + ssize_t ret; + int cpu; + + mutex_lock(&amd_pstate_driver_lock); + if (!global.cpb_supported) { + pr_err("Boost mode is not supported by this processor or SBIOS\n"); + return -EINVAL; + } + + ret = kstrtobool(buf, &new_state); + if (ret) + return -EINVAL; + + global.cpb_boost = !!new_state; + + for_each_possible_cpu(cpu) { + + struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); + struct amd_cpudata *cpudata = policy->driver_data; + + if (!cpudata) { + pr_err("cpudata is NULL\n"); + ret = -ENODATA; + cpufreq_cpu_put(policy); + goto err_exit; + } + + amd_cpu_boost_update(cpudata, global.cpb_boost); + refresh_frequency_limits(policy); + cpufreq_cpu_put(policy); + } + +err_exit: + mutex_unlock(&amd_pstate_driver_lock); + return ret < 0 ? ret : count; +} + cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); @@ -1043,6 +1138,7 @@ cpufreq_freq_attr_ro(amd_pstate_highest_perf); cpufreq_freq_attr_rw(energy_performance_preference); cpufreq_freq_attr_ro(energy_performance_available_preferences); static DEVICE_ATTR_RW(status); +static DEVICE_ATTR_RW(cpb_boost); static struct freq_attr *amd_pstate_attr[] = { &amd_pstate_max_freq, @@ -1062,6 +1158,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = { static struct attribute *pstate_global_attributes[] = { &dev_attr_status.attr, + &dev_attr_cpb_boost.attr, NULL }; From patchwork Fri Jan 26 08:08:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 767291 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2054.outbound.protection.outlook.com [40.107.223.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 435E167E70; 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Fri, 26 Jan 2024 02:08:54 -0600 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH 5/7] cpufreq: amd-pstate: fix the MSR highest perf will be reset issue while cpb boost off Date: Fri, 26 Jan 2024 16:08:08 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F4:EE_|CY8PR12MB7489:EE_ X-MS-Office365-Filtering-Correlation-Id: b4297f0a-6abb-4ae5-cf16-08dc1e460c74 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: /WqGENfOFwcI1+4Sc+IMo58DIWa9HjicTz8vZEnvv3bIyYbwwAKxwaqGznvmzHEW3iW/OQfXC6YzOEuGvZ3Ebe/Ox1ALVeleQ4ejvgAnNlokIYyeVSrp/X0ZZL1PhOSz2qDW1XZzROPoKKOgAk4E20UbPMPt8n55Ql9Rm9kX+lG8fHIYqzstz56eSxLOql9k+gIzr6CX5dB2Om1BTTUPudCfC51WVuMZabmigB8CYNleC1Tn2XTV72kwayLoFuUaKuFEdNsDK2AkcSar4nG47KZoN9/jJpGycYnPclGZvxFw1dys2uUJm37YMNk3IDsukr3DBqiiJOGlPt2ve3vTfq+Ubx4YJnBJnQGZvWzrcrvHM724eNNgDqP616xxH06FmULgSmonwGhwvOjE6Ug9QpZ+HjAjAQRRMo1JLMXsSARfZwB9fhkGgvCtO2jARMMa+UsRmOKUjwi7/Xxryl7NI6fMYXRnBYUNNkMSogIuiqU53uXchG7wWyRygk/qB+tXKA8ndanY1XqGgjCfUjPpQSRCEO+NwouBOD3VG9vT2o5/Fd7wjsky8+8haY2zPA+dDDaNLZZ8qyaBu5hwi9Y7iqUjdn1StSRDHN0CJYdHxy0V+w5VLcY4oYfMnRZ4YJT6PgPYLzKqX7UtepSl1tuMA9GSFkVqhmQrcrAIkF+Zq1Z00lVD7cr7G5scuNHPjQFXsoL+1uFKlANKQO7HReS3+2SOWFEb9OdgsJhO8kk6edJHL+N8EkY9hx2mU6/J3uVQmLZ7mQQ/tMaIGG0ZI0pnJg== X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F4.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7489 From: Perry Yuan Select the min perf to fix the highest perf value while update pstate CPPC request MSR register, here we need to limit the max perf value when CPU boost is disabled in case of that highest perf value in the MSR will be reset to original highest perf value which cause the BOOST control failed. Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 3286d72f375e..5cbbc2999d9a 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -443,6 +443,7 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, u32 des_perf, u32 max_perf, bool fast_switch, int gov_flags) { u64 prev = READ_ONCE(cpudata->cppc_req_cached); + u64 nominal_perf = READ_ONCE(cpudata->nominal_perf); u64 value = prev; des_perf = clamp_t(unsigned long, des_perf, min_perf, max_perf); @@ -458,6 +459,10 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, value &= ~AMD_CPPC_DES_PERF(~0L); value |= AMD_CPPC_DES_PERF(des_perf); + /* limit the max perf when core performance boost feature is disabled */ + if (!global.cpb_boost) + max_perf = min_t(unsigned long, nominal_perf, max_perf); + value &= ~AMD_CPPC_MAX_PERF(~0L); value |= AMD_CPPC_MAX_PERF(max_perf); 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jan 2024 08:09:05.0026 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: adc8cd7d-251d-4dc8-04fd-08dc1e461066 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM3PR12MB9391 From: Perry Yuan Introduce AMD CPU frequency boosting control sysfs entry which userd for switching boost on and boost off. If core performance boost is disabled while a core is in a boosted P-state, the core automatically transitions to the highest performance non-boosted P-state The highest perf and frequency will be limited by the setting value. Signed-off-by: Perry Yuan --- Documentation/admin-guide/pm/amd-pstate.rst | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index 1cf40f69278c..d72dc407c4db 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -385,6 +385,17 @@ control its functionality at the system level. They are located in the to the operation mode represented by that string - or to be unregistered in the "disable" case. +``cpb_boost`` + Specifies whether core performance boost is requested to be enabled or disabled + If core performance boost is disabled while a core is in a boosted P-state, the + core automatically transitions to the highest performance non-boosted P-state. + AMD Core Performance Boost(CPB) is controlled by this new attribute file which + allow user to change all cores frequency boosting state. It supports both + ``active mode`` and ``passive mode`` control with below value write to it. + + "0" Disable Core performance Boosting + "1" Enable Core performance Boosting + ``cpupower`` tool support for ``amd-pstate`` ===============================================