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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Paolo Bonzini , =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH 01/33] cpu-exec: simplify jump cache management Date: Sun, 28 Jan 2024 14:41:41 +1000 Message-Id: <20240128044213.316480-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Paolo Bonzini Unless I'm missing something egregious, the jmp cache is only every populated with a valid entry by the same thread that reads the cache. Therefore, the contents of any valid entry are always consistent and there is no need for any acquire/release magic. Indeed ->tb has to be accessed with atomics, because concurrent invalidations would otherwise cause data races. But ->pc is only ever accessed by one thread, and accesses to ->tb and ->pc within tb_lookup can never race with another tb_lookup. While the TranslationBlock (especially the flags) could be modified by a concurrent invalidation, store-release and load-acquire operations on the cache entry would not add any additional ordering beyond what you get from performing the accesses within a single thread. Because of this, there is really nothing to win in splitting the CF_PCREL and !CF_PCREL paths. It is easier to just always use the ->pc field in the jump cache. I noticed this while working on splitting commit 8ed558ec0cb ("accel/tcg: Introduce TARGET_TB_PCREL", 2022-10-04) into multiple pieces, for the sake of finding a more fine-grained bisection result for https://gitlab.com/qemu-project/qemu/-/issues/2092. It does not (and does not intend to) fix that issue; therefore it may make sense to not commit it until the root cause of issue #2092 is found. Signed-off-by: Paolo Bonzini Tested-by: Alex Bennée Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-Id: <20240122153409.351959-1-pbonzini@redhat.com> Signed-off-by: Richard Henderson --- accel/tcg/tb-jmp-cache.h | 8 +++-- accel/tcg/cpu-exec.c | 66 ++++++++++++++-------------------------- 2 files changed, 28 insertions(+), 46 deletions(-) diff --git a/accel/tcg/tb-jmp-cache.h b/accel/tcg/tb-jmp-cache.h index bb424c8a05..4ab8553afc 100644 --- a/accel/tcg/tb-jmp-cache.h +++ b/accel/tcg/tb-jmp-cache.h @@ -13,9 +13,11 @@ #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) /* - * Accessed in parallel; all accesses to 'tb' must be atomic. - * For CF_PCREL, accesses to 'pc' must be protected by a - * load_acquire/store_release to 'tb'. + * Invalidated in parallel; all accesses to 'tb' must be atomic. + * A valid entry is read/written by a single CPU, therefore there is + * no need for qatomic_rcu_read() and pc is always consistent with a + * non-NULL value of 'tb'. Strictly speaking pc is only needed for + * CF_PCREL, but it's used always for simplicity. */ struct CPUJumpCache { struct rcu_head rcu; diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 67eda9865e..40c268bfa1 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -253,43 +253,29 @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, vaddr pc, hash = tb_jmp_cache_hash_func(pc); jc = cpu->tb_jmp_cache; - if (cflags & CF_PCREL) { - /* Use acquire to ensure current load of pc from jc. */ - tb = qatomic_load_acquire(&jc->array[hash].tb); - - if (likely(tb && - jc->array[hash].pc == pc && - tb->cs_base == cs_base && - tb->flags == flags && - tb_cflags(tb) == cflags)) { - return tb; - } - tb = tb_htable_lookup(cpu, pc, cs_base, flags, cflags); - if (tb == NULL) { - return NULL; - } - jc->array[hash].pc = pc; - /* Ensure pc is written first. */ - qatomic_store_release(&jc->array[hash].tb, tb); - } else { - /* Use rcu_read to ensure current load of pc from *tb. */ - tb = qatomic_rcu_read(&jc->array[hash].tb); - - if (likely(tb && - tb->pc == pc && - tb->cs_base == cs_base && - tb->flags == flags && - tb_cflags(tb) == cflags)) { - return tb; - } - tb = tb_htable_lookup(cpu, pc, cs_base, flags, cflags); - if (tb == NULL) { - return NULL; - } - /* Use the pc value already stored in tb->pc. */ - qatomic_set(&jc->array[hash].tb, tb); + tb = qatomic_read(&jc->array[hash].tb); + if (likely(tb && + jc->array[hash].pc == pc && + tb->cs_base == cs_base && + tb->flags == flags && + tb_cflags(tb) == cflags)) { + goto hit; } + tb = tb_htable_lookup(cpu, pc, cs_base, flags, cflags); + if (tb == NULL) { + return NULL; + } + + jc->array[hash].pc = pc; + qatomic_set(&jc->array[hash].tb, tb); + +hit: + /* + * As long as tb is not NULL, the contents are consistent. Therefore, + * the virtual PC has to match for non-CF_PCREL translations. + */ + assert((tb_cflags(tb) & CF_PCREL) || tb->pc == pc); return tb; } @@ -1012,14 +998,8 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc) */ h = tb_jmp_cache_hash_func(pc); jc = cpu->tb_jmp_cache; - if (cflags & CF_PCREL) { - jc->array[h].pc = pc; - /* Ensure pc is written first. */ - qatomic_store_release(&jc->array[h].tb, tb); - } else { - /* Use the pc value already stored in tb->pc. */ - qatomic_set(&jc->array[h].tb, tb); - } + jc->array[h].pc = pc; + qatomic_set(&jc->array[h].tb, tb); } #ifndef CONFIG_USER_ONLY From patchwork Sun Jan 28 04:41:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767205 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp347665wro; Sat, 27 Jan 2024 20:43:18 -0800 (PST) X-Google-Smtp-Source: AGHT+IHeQWBDdHxYLhAHix+LCJX8yCDLStudD/Jh6sL5vpA9phDl/zAV7DCDZL8XlFk9+8gpMY3w X-Received: by 2002:a05:622a:3cc:b0:42a:54cb:32c8 with SMTP id k12-20020a05622a03cc00b0042a54cb32c8mr3823569qtx.85.1706416997877; Sat, 27 Jan 2024 20:43:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706416997; cv=none; d=google.com; s=arc-20160816; b=GIGzt9TsW0nWJr8GdSo9VBJCphN9XrWeFuzAk+6IDnX82Rd+3rvP+poErfU1CpsJCr VDQMnV6Q8Zaxj+X2GXkUS4X5pAqpA2ZJxKOm6tTF8Naeo4/KCQ9tNnv0DsDdnqt8Tf93 JsVmDH92LMHXY/0WZXsJr67dXGGpCfVeK40JKwxj0PjmfgI+f0wNxNecGQWsFSYZ/MQ9 krNtdAtvi1HdCgPaQVDIj0CJn/5rK0S74/7paSBVCdPIdh5qrEhGBo/iowpn/td7GNrp mWBZWqsC/4/PopvghaoN5dH6WempGdPsW+IaCGFmn00ihXHDEepQF+m70mKBfZa/EkUj 42lA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=M8UjEMO1j2vm3/2aeEMHpkVHZcyY+4Tl4SZGy9Fx+X8=; fh=l3rThTWYtfg9kQ3pwkdseR7wGfUMT6wsJF5cqMswxYY=; b=cmCdKKINdAx1GoAKVEBR4uXS0cYg1CSfPCdnfAaAdJDmuSzu58x0iC+wIGm2n6GvrO PvKVS0x9OOOVt8HOcaVDxP3yF02bweQmm12YFtMVG3TfAwxXAs7eANoo8wC6ley5prR4 sJ9fnXoPHxywSCvEVL1aq29/ded+mUWghJQoQZaK7sSS1liyOXNKx2CdMZH4cClJQRrq gc0n3wpBvPJdKCxuJxBE64tF1SnPGSZa14BTFHNZiIfX47tAiWB7eDW27bD4wGahNgyK sDpPTAJjgOd/pavfKpLeNNlSfJKtwJsx+aZOaHevTkYV/HxxOEV/XyZN040OmcIEdEvF hPyQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xwpUCp6Z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PATCH 02/33] include/exec: Move vaddr defines to separate file Date: Sun, 28 Jan 2024 14:41:42 +1000 Message-Id: <20240128044213.316480-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Anton Johansson Needed to work around circular includes. vaddr is currently defined in cpu-common.h and needed by hw/core/cpu.h, but cpu-common.h also need cpu.h to know the size of the CPUState. [Maybe we can instead move parts of cpu-common.h w. hw/core/cpu.h to sort out the circular inclusion.] Signed-off-by: Anton Johansson Message-Id: <20240119144024.14289-7-anjo@rev.ng> Reviewed-by: Richard Henderson [rth: Add include of vaddr.h into cpu-common.h] Signed-off-by: Richard Henderson --- include/exec/cpu-common.h | 13 +------------ include/exec/vaddr.h | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+), 12 deletions(-) create mode 100644 include/exec/vaddr.h diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index fef3138d29..3109c6b67d 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -3,6 +3,7 @@ /* CPU interfaces that are target independent. */ +#include "exec/vaddr.h" #ifndef CONFIG_USER_ONLY #include "exec/hwaddr.h" #endif @@ -14,18 +15,6 @@ #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */ #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */ -/** - * vaddr: - * Type wide enough to contain any #target_ulong virtual address. - */ -typedef uint64_t vaddr; -#define VADDR_PRId PRId64 -#define VADDR_PRIu PRIu64 -#define VADDR_PRIo PRIo64 -#define VADDR_PRIx PRIx64 -#define VADDR_PRIX PRIX64 -#define VADDR_MAX UINT64_MAX - void cpu_exec_init_all(void); void cpu_exec_step_atomic(CPUState *cpu); diff --git a/include/exec/vaddr.h b/include/exec/vaddr.h new file mode 100644 index 0000000000..b9844afc77 --- /dev/null +++ b/include/exec/vaddr.h @@ -0,0 +1,18 @@ +/* Define vaddr. */ + +#ifndef VADDR_H +#define VADDR_H + +/** + * vaddr: + * Type wide enough to contain any #target_ulong virtual address. + */ +typedef uint64_t vaddr; +#define VADDR_PRId PRId64 +#define VADDR_PRIu PRIu64 +#define VADDR_PRIo PRIo64 +#define VADDR_PRIx PRIx64 +#define VADDR_PRIX PRIX64 +#define VADDR_MAX UINT64_MAX + +#endif From patchwork Sun Jan 28 04:41:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767224 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp348121wro; Sat, 27 Jan 2024 20:45:47 -0800 (PST) X-Google-Smtp-Source: AGHT+IHzimfYxeKe6inxmkWuu4H77I022laZvOjHUWjmgvCAMCt2vkeqVxwDovRUMvw/FPEY3/Ct X-Received: by 2002:a05:620a:5642:b0:783:2911:544b with SMTP id vw2-20020a05620a564200b007832911544bmr3055040qkn.82.1706417147538; Sat, 27 Jan 2024 20:45:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706417147; cv=none; d=google.com; s=arc-20160816; b=nvrkhUhKvggwJzGIjOkDKYQ1aVw2slkH5LUpEGx2GRsa0NglF2CMISYpDrzwyugdeN /Lo2xvIrXU6OpJprx6MPX8dvgVueHq4ZaR5AwcqS5RHkGLitsurKYsidKKmCbnvfRChP LtoTIvoBfgT95JyUUAw3kHLuo8+fp0G5dJMjuw20a4vQIhyrwyg2seLTZmOUNqTLKkWB TiXOR1Z86ApsDzdCQrfvFHdmx/I6pnXfHGa+/zYbKze92FDYFMW5DCaMyq+zdB5bajYE QC2TDgaNZmX2dkMl4FzcT9h6ZYwYRaEANiqFJmAL3+fnVEaMKdbWRVuhw3kjc3bPmDbb Os4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ADBUc3fCETku7gSMiSslG1Ep+CbDq8k+uqgwv8Xr0vk=; fh=l3rThTWYtfg9kQ3pwkdseR7wGfUMT6wsJF5cqMswxYY=; b=vnPIoq0KDwB5krqj/ayvrKz7rTMj2yfW9t6mXRM716a+8EykJ0vmO4A3TmdK86fP5z v5YHbLBuwblKdK8a38dzK8brIm6YPFvxonPkuAsBWe57ADvr+rnLJ1APIrVw0JWvx+/e 21pYnO/blvSI4hqA16W+tABlYk2HOYPWVRgjD+py9dwKHYAgp9b9NuAl3CE+MNn+2A9E 81peWGdbi/H0dZRChROuTchEmkEEQ3hVT0DM6Jtox9KPBB8M7NedgfmwlX99JWKMGndv FMwiSMJIdU0lrq9EaBzmbwE5PU/cclNjDjmkKrl8J4DcrQnNmggx7+cau+byqesi41p1 rjtQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GxFUAyKy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PATCH 03/33] hw/core: Include vaddr.h from cpu.h Date: Sun, 28 Jan 2024 14:41:43 +1000 Message-Id: <20240128044213.316480-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Anton Johansson cpu-common.h is only needed for vaddr Signed-off-by: Anton Johansson Message-Id: <20240119144024.14289-8-anjo@rev.ng> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 238c02c05e..db58f12233 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -22,8 +22,8 @@ #include "hw/qdev-core.h" #include "disas/dis-asm.h" -#include "exec/cpu-common.h" #include "exec/hwaddr.h" +#include "exec/vaddr.h" #include "exec/memattrs.h" #include "exec/tlb-common.h" #include "qapi/qapi-types-run-state.h" From patchwork Sun Jan 28 04:41:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767215 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp347941wro; Sat, 27 Jan 2024 20:44:53 -0800 (PST) X-Google-Smtp-Source: AGHT+IFHPlJh0obdxea9LlDiabnzPz28D7nQH+PB8HtfP91HS2yZhsOCpTizbBqvW8jpqs8UrtZr X-Received: by 2002:a05:620a:2955:b0:783:f898:48a with SMTP id n21-20020a05620a295500b00783f898048amr352861qkp.9.1706417093765; Sat, 27 Jan 2024 20:44:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706417093; cv=none; d=google.com; s=arc-20160816; b=xDPHDXTnjlhI8vls50+z9wLQwNiEDX0/lkeaaXS+fknrjNBPNOvAmQHmJjcDyKkF0A iygRhLeZLKc0zWLM8N0cM9hnwUhZFMK8ZuGBChDx88s/OJvNJA6oc0YWd6rjr/USCSRk wJ/ps/Aq31hGLtZkY8zkOdG95pG6hFMXSG8wT9ps+Bbja32n9rBkfF5PGTcewGNmQGe2 saRcthlJjGrK3SXThW1Ej+PlLwTn5oEK0A801Ixtj6HY/ZZwO9fMvhb89w7rMB1Wt7ky Bfm7gQMeiUOggapMaVe4oq2QE0YTFUeXuRrcJwuSFXvjRPi6zYk3KqeoIajVAyXCBMkk wzFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=9+/x34hZ0Savjf5fK/vjCGUP8dkpzXoOGlANXKjp7EA=; fh=l3rThTWYtfg9kQ3pwkdseR7wGfUMT6wsJF5cqMswxYY=; b=QPg+oTwjsL4N9qAVBcBHbFPMk+1UYMAw+dB6hog0nNnKPxNIa6Vg6OeNOhjFkaHeJ9 VHGset76rRc6dnc6YtRX686g4XCb3RqVkcyI5J1TZ91KTrVsJHVb/Pu4+2MGg16UvXpp AQeTR5c8VdA3tXk0XmbkG/dGIgdlAtPJSCqd0mxLpTFYogsEymQA4LX54RaSYqBtbggF OZVE2pKa2o2VHySC2x35r1Mro2vOOHWi2Jse0r6XfJIOT2iPux7ofy301tsTw7EE3ISv 4lhYGm2MwO6dtblNt6dRad8oNlbPlrxPROjpU1yU81W2JEfkwxSJzZJcXsDtff0QF234 cx7Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WKz9Ie4m; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PATCH 04/33] target: Use vaddr in gen_intermediate_code Date: Sun, 28 Jan 2024 14:41:44 +1000 Message-Id: <20240128044213.316480-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::f32; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Anton Johansson Makes gen_intermediate_code() signature target agnostic so the function can be called from accel/tcg/translate-all.c without target specifics. Signed-off-by: Anton Johansson Message-Id: <20240119144024.14289-9-anjo@rev.ng> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- include/exec/translator.h | 2 +- target/alpha/translate.c | 2 +- target/arm/tcg/translate.c | 2 +- target/avr/translate.c | 2 +- target/cris/translate.c | 2 +- target/hexagon/translate.c | 2 +- target/hppa/translate.c | 2 +- target/i386/tcg/translate.c | 2 +- target/loongarch/tcg/translate.c | 2 +- target/m68k/translate.c | 2 +- target/microblaze/translate.c | 2 +- target/mips/tcg/translate.c | 2 +- target/nios2/translate.c | 2 +- target/openrisc/translate.c | 2 +- target/ppc/translate.c | 2 +- target/riscv/translate.c | 2 +- target/rx/translate.c | 2 +- target/s390x/tcg/translate.c | 2 +- target/sh4/translate.c | 2 +- target/sparc/translate.c | 2 +- target/tricore/translate.c | 2 +- target/xtensa/translate.c | 2 +- 22 files changed, 22 insertions(+), 22 deletions(-) diff --git a/include/exec/translator.h b/include/exec/translator.h index 6d3f59d095..b0412ea6b6 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -33,7 +33,7 @@ * the target-specific DisasContext, and then invoke translator_loop. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc); + vaddr pc, void *host_pc); /** * DisasJumpType: diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 32333081d8..134eb7225b 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2971,7 +2971,7 @@ static const TranslatorOps alpha_tr_ops = { }; void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; translator_loop(cpu, tb, max_insns, pc, host_pc, &alpha_tr_ops, &dc.base); diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index b3660173d1..5fa8249723 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -9691,7 +9691,7 @@ static const TranslatorOps thumb_translator_ops = { /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc = { }; const TranslatorOps *ops = &arm_translator_ops; diff --git a/target/avr/translate.c b/target/avr/translate.c index cdffa04519..e5dd057799 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -2805,7 +2805,7 @@ static const TranslatorOps avr_tr_ops = { }; void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc = { }; translator_loop(cs, tb, max_insns, pc, host_pc, &avr_tr_ops, &dc.base); diff --git a/target/cris/translate.c b/target/cris/translate.c index b3974ba0bb..ee1402a9a3 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -3172,7 +3172,7 @@ static const TranslatorOps cris_tr_ops = { }; void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; translator_loop(cs, tb, max_insns, pc, host_pc, &cris_tr_ops, &dc.base); diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 95579ae243..a14211cf68 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -1154,7 +1154,7 @@ static const TranslatorOps hexagon_tr_ops = { }; void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 3ef39b1bd7..08d09d50d7 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -4631,7 +4631,7 @@ static const TranslatorOps hppa_tr_ops = { }; void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; translator_loop(cs, tb, max_insns, pc, host_pc, &hppa_tr_ops, &ctx.base); diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index e193c74472..2808903661 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -7088,7 +7088,7 @@ static const TranslatorOps i386_tr_ops = { /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c index 21f4db6fbd..235515c629 100644 --- a/target/loongarch/tcg/translate.c +++ b/target/loongarch/tcg/translate.c @@ -343,7 +343,7 @@ static const TranslatorOps loongarch_tr_ops = { }; void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 4a0b0b2703..5ec88c5f0d 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -6088,7 +6088,7 @@ static const TranslatorOps m68k_tr_ops = { }; void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; translator_loop(cpu, tb, max_insns, pc, host_pc, &m68k_tr_ops, &dc.base); diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 49bfb4a0ea..2e628647d1 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -1792,7 +1792,7 @@ static const TranslatorOps mb_tr_ops = { }; void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; translator_loop(cpu, tb, max_insns, pc, host_pc, &mb_tr_ops, &dc.base); diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 13e43fa3b6..e10232738c 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -15554,7 +15554,7 @@ static const TranslatorOps mips_tr_ops = { }; void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; diff --git a/target/nios2/translate.c b/target/nios2/translate.c index e806623594..3078372b36 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -1036,7 +1036,7 @@ static const TranslatorOps nios2_tr_ops = { }; void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; translator_loop(cs, tb, max_insns, pc, host_pc, &nios2_tr_ops, &dc.base); diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index ecff4412b7..d4cbc5eaea 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -1658,7 +1658,7 @@ static const TranslatorOps openrisc_tr_ops = { }; void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 329da4d518..049f636927 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7518,7 +7518,7 @@ static const TranslatorOps ppc_tr_ops = { }; void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 071fbad7ef..ab18899122 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1287,7 +1287,7 @@ static const TranslatorOps riscv_tr_ops = { }; void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; diff --git a/target/rx/translate.c b/target/rx/translate.c index c6ce717a95..2265bd14ac 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -2266,7 +2266,7 @@ static const TranslatorOps rx_tr_ops = { }; void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 8df00b7df9..a5fd9cccaa 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -6547,7 +6547,7 @@ static const TranslatorOps s390x_tr_ops = { }; void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc; diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 81f825f125..6a6d862b10 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -2317,7 +2317,7 @@ static const TranslatorOps sh4_tr_ops = { }; void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 9387299559..97184fa403 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -5327,7 +5327,7 @@ static const TranslatorOps sparc_tr_ops = { }; void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc = {}; diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 66553d1be0..f1156c39e7 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8472,7 +8472,7 @@ static const TranslatorOps tricore_tr_ops = { void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext ctx; translator_loop(cs, tb, max_insns, pc, host_pc, diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 87947236ca..e4772462b5 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1239,7 +1239,7 @@ static const TranslatorOps xtensa_translator_ops = { }; void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns, - target_ulong pc, void *host_pc) + vaddr pc, void *host_pc) { DisasContext dc = {}; translator_loop(cpu, tb, max_insns, pc, host_pc, From patchwork Sun Jan 28 04:41:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767208 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp347716wro; Sat, 27 Jan 2024 20:43:42 -0800 (PST) X-Google-Smtp-Source: AGHT+IGVFMRqOq6eLX4z3bjryRmLlBbUSSUkf0ymzdp8v6zbTz4RXtarwltc9as8OrYpX4JADkPB X-Received: by 2002:ac8:574c:0:b0:42a:94fe:e139 with SMTP id 12-20020ac8574c000000b0042a94fee139mr1831629qtx.13.1706417022604; Sat, 27 Jan 2024 20:43:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706417022; cv=none; d=google.com; s=arc-20160816; b=Dlv3gU2JW9zBG5c1IAal1DUcSH7wnPoe057tD11JlHQbY6vtsHG/UjZVVsmItsrRrJ Yjs6rYasO1lClo2hShH0CkTtrk6S7vz9jeh16eGBgsT+1tNQbA4W+NM1Q4/+nYIaVsoZ vroORBo4hqHBw3loLZACihk3gDmMu4y2jsyWlz2egtF1IO4H37roN0FvPRKpHb0RNNVG yv5gBdlcjQFB32APGcXRmP7TIXdDPS35qg0QiFumZ697lPbMKk6ogi3IiKHD5xU1XCuR AkH5pL6KFtnOzvOsDN5gPemm+OtHDbNnGr01jrN1TCWN4YlaksWhEFjYE5sMZuefkNpT FF6Q== ARC-Message-Signature: i=1; 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PATCH 05/33] include/exec: Use vaddr in DisasContextBase for virtual addresses Date: Sun, 28 Jan 2024 14:41:45 +1000 Message-Id: <20240128044213.316480-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Anton Johansson Updates target/ QEMU_LOG macros to use VADDR_PRIx for printing updated DisasContextBase fields. Signed-off-by: Anton Johansson Message-Id: <20240119144024.14289-10-anjo@rev.ng> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- include/exec/translator.h | 6 +++--- target/mips/tcg/translate.h | 3 ++- target/hexagon/translate.c | 3 ++- target/m68k/translate.c | 2 +- target/mips/tcg/translate.c | 12 ++++++------ 5 files changed, 14 insertions(+), 12 deletions(-) diff --git a/include/exec/translator.h b/include/exec/translator.h index b0412ea6b6..51624feb10 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -79,8 +79,8 @@ typedef enum DisasJumpType { */ typedef struct DisasContextBase { TranslationBlock *tb; - target_ulong pc_first; - target_ulong pc_next; + vaddr pc_first; + vaddr pc_next; DisasJumpType is_jmp; int num_insns; int max_insns; @@ -235,7 +235,7 @@ void translator_fake_ldb(uint8_t insn8, abi_ptr pc); * Translators can use this to enforce the rule that only single-insn * translation blocks are allowed to cross page boundaries. */ -static inline bool is_same_page(const DisasContextBase *db, target_ulong addr) +static inline bool is_same_page(const DisasContextBase *db, vaddr addr) { return ((addr ^ db->pc_first) & TARGET_PAGE_MASK) == 0; } diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index cffcfeab8c..93a78b8121 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -202,7 +202,8 @@ extern TCGv bcond; do { \ if (MIPS_DEBUG_DISAS) { \ qemu_log_mask(CPU_LOG_TB_IN_ASM, \ - TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \ + "%016" VADDR_PRIx \ + ": %08x Invalid %s %03x %03x %03x\n", \ ctx->base.pc_next, ctx->opcode, op, \ ctx->opcode >> 26, ctx->opcode & 0x3F, \ ((ctx->opcode >> 16) & 0x1F)); \ diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index a14211cf68..f163eefe97 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -234,7 +234,8 @@ static int read_packet_words(CPUHexagonState *env, DisasContext *ctx, g_assert(ctx->base.num_insns == 1); } - HEX_DEBUG_LOG("decode_packet: pc = 0x%x\n", ctx->base.pc_next); + HEX_DEBUG_LOG("decode_packet: pc = 0x%" VADDR_PRIx "\n", + ctx->base.pc_next); HEX_DEBUG_LOG(" words = { "); for (int i = 0; i < nwords; i++) { HEX_DEBUG_LOG("0x%x, ", words[i]); diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 5ec88c5f0d..f886190f88 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -1457,7 +1457,7 @@ DISAS_INSN(undef) * for the 680x0 series, as well as those that are implemented * but actually illegal for CPU32 or pre-68020. */ - qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %08x\n", + qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %" VADDR_PRIx "\n", insn, s->base.pc_next); gen_exception(s, s->base.pc_next, EXCP_ILLEGAL); } diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index e10232738c..12094cc1e7 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -4585,8 +4585,8 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, if (ctx->hflags & MIPS_HFLAG_BMASK) { #ifdef MIPS_DEBUG_DISAS - LOG_DISAS("Branch in delay / forbidden slot at PC 0x" - TARGET_FMT_lx "\n", ctx->base.pc_next); + LOG_DISAS("Branch in delay / forbidden slot at PC 0x%016" + VADDR_PRIx "\n", ctx->base.pc_next); #endif gen_reserved_instruction(ctx); goto out; @@ -9061,8 +9061,8 @@ static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op, if (ctx->hflags & MIPS_HFLAG_BMASK) { #ifdef MIPS_DEBUG_DISAS - LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx - "\n", ctx->base.pc_next); + LOG_DISAS("Branch in delay / forbidden slot at PC 0x%016" + VADDR_PRIx "\n", ctx->base.pc_next); #endif gen_reserved_instruction(ctx); return; @@ -11274,8 +11274,8 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc, if (ctx->hflags & MIPS_HFLAG_BMASK) { #ifdef MIPS_DEBUG_DISAS - LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx - "\n", ctx->base.pc_next); + LOG_DISAS("Branch in delay / forbidden slot at PC 0x%016" + VADDR_PRIx "\n", ctx->base.pc_next); #endif gen_reserved_instruction(ctx); return; From patchwork Sun Jan 28 04:41:46 2024 Content-Type: text/plain; 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PATCH 06/33] include/exec: typedef abi_ptr to vaddr Date: Sun, 28 Jan 2024 14:41:46 +1000 Message-Id: <20240128044213.316480-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Anton Johansson Signed-off-by: Anton Johansson Message-Id: <20240119144024.14289-11-anjo@rev.ng> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 6061e33ac9..eb8f3f0595 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -121,8 +121,8 @@ static inline bool guest_range_valid_untagged(abi_ulong start, abi_ulong len) h2g_nocheck(x); \ }) #else -typedef target_ulong abi_ptr; -#define TARGET_ABI_FMT_ptr TARGET_FMT_lx +typedef vaddr abi_ptr; +#define TARGET_ABI_FMT_ptr VADDR_PRIx #endif uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr); From patchwork Sun Jan 28 04:41:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767228 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp348180wro; Sat, 27 Jan 2024 20:46:07 -0800 (PST) X-Google-Smtp-Source: AGHT+IHzKfAR0gb+DhQV/sXethhKy4tAKdIDZ1wi7iEwVc4hcZfqO6cbgxtObJ5CeZyZDnJyVduv X-Received: by 2002:a05:6214:40b:b0:685:9a9f:9f77 with SMTP id z11-20020a056214040b00b006859a9f9f77mr4277333qvx.9.1706417167657; Sat, 27 Jan 2024 20:46:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706417167; cv=none; d=google.com; s=arc-20160816; b=fwBNK85S+hpkKL04pJUwnCaojTIa5rA/Ujky7AXZz61f2uyxnKBSOx6NJkIr9uIz9T IRqg3gW8Y+xy2nC+FgKG0aXR2pV0NnSCg6jUhIYY6BsG+b/EnOCuecpiS8QgdvEyPYVE 6HYujTjn8NW6W7+rrcDozDa4hokR9ffoVzWDV84Dgoz+PD7kOXaEWDGCPJiZ9Fd3hDKo 5ICVPO2MpJvd3N1E8VB3FS6aDzkQ4HPeAEwP6FiNV5QUa+Jsa3WevK6hTKHGCxoD/WBU onwrmfHytLW+JeIp4I2/NbItr8lhVRNJ5422bzMzEEdFNPQdJVHl2qVjJzrfi82n+qye DX3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=VODEHWMxMF5aJBZz0S2TC6sc+IupRmg6TxWrBBUh29E=; fh=l3rThTWYtfg9kQ3pwkdseR7wGfUMT6wsJF5cqMswxYY=; b=jbUoo6pg+Vty1fNFzgndnMbM8OhEWrnueUDpnTGS8v0DpQMGXhcspatyoGV7OVXVjz z0TX3Bwku5Q5f53k8f4b17au0WMieRdEX07aScwSQTQNzLPi5Jn0wXWuO1UXWfS3vsZr dV+8mfxPz0Vaa26qcBoYMUfFQkR2j0y+I4x8DSGwRkG2paW0ydDQQUUNSIDgLPY2hhTc P9X8Bk4Aa/m67W+uo22mlgd1UPhhfqH4UHtG5GL11FqYTOiQWWws6LklBDi/szOzRian b17y1dj3ZsOWZSqGd+Mx+zbXPeX5O3pnuBVkWADZBUni2X/FZd/gT9XlE2aUk6+vDsgc xg4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IgdA0baF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PATCH 07/33] target: Uninline cpu_mmu_index() Date: Sun, 28 Jan 2024 14:41:47 +1000 Message-Id: <20240128044213.316480-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::82e; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Anton Johansson Uninlines the target-defined cpu_mmu_index() function by moving its definition to target/*/cpu.c. This allows for compiling memory access functions in accel/tcg/cputlb.c without having to know target specifics. Signed-off-by: Anton Johansson Message-Id: <20240119144024.14289-13-anjo@rev.ng> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- include/exec/cpu-common.h | 10 ++++++++++ target/alpha/cpu.h | 9 --------- target/arm/cpu.h | 13 ------------- target/avr/cpu.h | 7 ------- target/cris/cpu.h | 4 ---- target/hexagon/cpu.h | 9 --------- target/hppa/cpu.h | 13 ------------- target/i386/cpu.h | 7 ------- target/loongarch/cpu.h | 12 ------------ target/m68k/cpu.h | 4 ---- target/microblaze/cpu.h | 15 --------------- target/mips/cpu.h | 5 ----- target/nios2/cpu.h | 6 ------ target/openrisc/cpu.h | 12 ------------ target/ppc/cpu.h | 8 -------- target/riscv/cpu.h | 3 --- target/rx/cpu.h | 5 ----- target/s390x/cpu.h | 31 ------------------------------- target/sh4/cpu.h | 10 ---------- target/sparc/cpu.h | 28 ---------------------------- target/tricore/cpu.h | 5 ----- target/xtensa/cpu.h | 5 ----- target/alpha/cpu.c | 8 ++++++++ target/arm/cpu.c | 5 +++++ target/avr/cpu.c | 5 +++++ target/cris/cpu.c | 4 ++++ target/hexagon/cpu.c | 9 +++++++++ target/hppa/cpu.c | 13 +++++++++++++ target/i386/cpu.c | 7 +++++++ target/loongarch/cpu.c | 12 ++++++++++++ target/m68k/cpu.c | 5 +++++ target/microblaze/cpu.c | 16 ++++++++++++++++ target/mips/cpu.c | 5 +++++ target/nios2/cpu.c | 6 ++++++ target/openrisc/cpu.c | 12 ++++++++++++ target/ppc/cpu.c | 9 +++++++++ target/riscv/cpu_helper.c | 2 +- target/rx/cpu.c | 5 +++++ target/s390x/cpu.c | 31 +++++++++++++++++++++++++++++++ target/sh4/cpu.c | 13 +++++++++++++ target/sparc/cpu.c | 28 ++++++++++++++++++++++++++++ target/tricore/cpu.c | 5 +++++ target/xtensa/cpu.c | 4 ++++ 43 files changed, 213 insertions(+), 212 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 3109c6b67d..4724135f30 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -34,6 +34,16 @@ void cpu_list_lock(void); void cpu_list_unlock(void); unsigned int cpu_list_generation_id_get(void); +/** + * cpu_mmu_index: + * @env: The cpu environment + * @ifetch: True for code access, false for data access. + * + * Return the core mmu index for the current translation regime. + * This function is used by generic TCG code paths. + */ +int cpu_mmu_index(CPUArchState *env, bool ifetch); + void tcg_iommu_init_notifier_list(CPUState *cpu); void tcg_iommu_free_notifier_list(CPUState *cpu); diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index ce806587ca..abf778735a 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -389,15 +389,6 @@ enum { #define TB_FLAG_UNALIGN (1u << 1) -static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch) -{ - int ret = env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_IDX; - if (env->flags & ENV_FLAG_PAL_MODE) { - ret = MMU_KERNEL_IDX; - } - return ret; -} - enum { IR_V0 = 0, IR_T0 = 1, diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ec276fcd57..b0edf2e540 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3268,19 +3268,6 @@ FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1) #define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH) #define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH) -/** - * cpu_mmu_index: - * @env: The cpu environment - * @ifetch: True for code access, false for data access. - * - * Return the core mmu index for the current translation regime. - * This function is used by generic TCG code paths. - */ -static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) -{ - return EX_TBFLAG_ANY(env->hflags, MMUIDX); -} - /** * sve_vq * @env: the cpu context diff --git a/target/avr/cpu.h b/target/avr/cpu.h index 7d5dd42575..d185d20dcb 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -184,13 +184,6 @@ static inline void set_avr_feature(CPUAVRState *env, int feature) env->features |= (1U << feature); } -#define cpu_mmu_index avr_cpu_mmu_index - -static inline int avr_cpu_mmu_index(CPUAVRState *env, bool ifetch) -{ - return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; -} - void avr_cpu_tcg_init(void); int cpu_avr_exec(CPUState *cpu); diff --git a/target/cris/cpu.h b/target/cris/cpu.h index d830dcac5b..3904e5448c 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -260,10 +260,6 @@ enum { /* MMU modes definitions */ #define MMU_USER_IDX 1 -static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch) -{ - return !!(env->pregs[PR_CCS] & U_FLAG); -} /* Support function regs. */ #define SFR_RW_GC_CFG 0][0 diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 5c11ae3445..3eef58fe8f 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -146,15 +146,6 @@ static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, *flags = hex_flags; } -static inline int cpu_mmu_index(CPUHexagonState *env, bool ifetch) -{ -#ifdef CONFIG_USER_ONLY - return MMU_USER_IDX; -#else -#error System mode not supported on Hexagon yet -#endif -} - typedef HexagonCPU ArchCPU; void hexagon_translate_init(void); diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 6a153405d2..7a181e8f33 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -281,19 +281,6 @@ static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env) return hppa_is_pa20(env) ? 0 : PA10_BTLB_FIXED + PA10_BTLB_VARIABLE; } -static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) -{ -#ifdef CONFIG_USER_ONLY - return MMU_USER_IDX; -#else - if (env->psw & (ifetch ? PSW_C : PSW_D)) { - return PRIV_P_TO_MMU_IDX(env->iaoq_f & 3, env->psw & PSW_P); - } - /* mmu disabled */ - return env->psw & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX; -#endif -} - void hppa_translate_init(void); #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 7f0786e8b9..6a5b180ccb 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2296,13 +2296,6 @@ uint64_t cpu_get_tsc(CPUX86State *env); #define MMU_NESTED_IDX 3 #define MMU_PHYS_IDX 4 -static inline int cpu_mmu_index(CPUX86State *env, bool ifetch) -{ - return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : - (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) - ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; -} - static inline int cpu_mmu_index_kernel(CPUX86State *env) { return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX : diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 0fa5e0ca93..64eac07a16 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -408,18 +408,6 @@ struct LoongArchCPUClass { #define MMU_IDX_USER MMU_PLV_USER #define MMU_IDX_DA 4 -static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch) -{ -#ifdef CONFIG_USER_ONLY - return MMU_IDX_USER; -#else - if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) { - return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); - } - return MMU_IDX_DA; -#endif -} - static inline bool is_la64(CPULoongArchState *env) { return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) == CPUCFG1_ARCH_LA64; diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index d13427b0fe..aca4aa610b 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -577,10 +577,6 @@ enum { /* MMU modes definitions */ #define MMU_KERNEL_IDX 0 #define MMU_USER_IDX 1 -static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch) -{ - return (env->sr & SR_S) == 0 ? 1 : 0; -} bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index b5374365f5..446af5dd4c 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -434,21 +434,6 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, MemTxResult response, uintptr_t retaddr); #endif -static inline int cpu_mmu_index(CPUMBState *env, bool ifetch) -{ - MicroBlazeCPU *cpu = env_archcpu(env); - - /* Are we in nommu mode?. */ - if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) { - return MMU_NOMMU_IDX; - } - - if (env->msr & MSR_UM) { - return MMU_USER_IDX; - } - return MMU_KERNEL_IDX; -} - #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_mb_cpu; #endif diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 1163a71f3c..4c9dc09a66 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1253,11 +1253,6 @@ static inline int hflags_mmu_index(uint32_t hflags) } } -static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch) -{ - return hflags_mmu_index(env->hflags); -} - #include "exec/cpu-all.h" /* Exceptions */ diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 2d79b5b298..4164a3432e 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -270,12 +270,6 @@ void do_nios2_semihosting(CPUNios2State *env); #define MMU_SUPERVISOR_IDX 0 #define MMU_USER_IDX 1 -static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch) -{ - return (env->ctrl[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX : - MMU_SUPERVISOR_IDX; -} - #ifndef CONFIG_USER_ONLY hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index b454014ddd..b1b7db5cbd 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -361,18 +361,6 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc, | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); } -static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) -{ - int ret = MMU_NOMMU_IDX; /* mmu is disabled */ - - if (env->sr & (ifetch ? SR_IME : SR_DME)) { - /* The mmu is enabled; test supervisor state. */ - ret = env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; - } - - return ret; -} - static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) { return (env->sr diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index f8101ffa29..59587a8aba 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1624,14 +1624,6 @@ int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val); /* MMU modes definitions */ #define MMU_USER_IDX 0 -static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch) -{ -#ifdef CONFIG_USER_ONLY - return MMU_USER_IDX; -#else - return (env->hflags >> (ifetch ? HFLAGS_IMMU_IDX : HFLAGS_DMMU_IDX)) & 7; -#endif -} /* Compatibility modes */ #if defined(TARGET_PPC64) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5f3955c38d..bca27278ed 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -498,7 +498,6 @@ target_ulong riscv_cpu_get_geilen(CPURISCVState *env); void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); bool riscv_cpu_vector_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); -int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); @@ -507,8 +506,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, bool probe, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); -#define cpu_mmu_index riscv_cpu_mmu_index - #ifndef CONFIG_USER_ONLY void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, unsigned size, diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 65f9cd2d0a..c53593d7aa 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -158,11 +158,6 @@ static inline void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc, *flags = FIELD_DP32(*flags, PSW, U, env->psw_u); } -static inline int cpu_mmu_index(CPURXState *env, bool ifetch) -{ - return 0; -} - static inline uint32_t rx_cpu_pack_psw(CPURXState *env) { uint32_t psw = 0; diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index fa3aac4f97..61c893b1b9 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -381,37 +381,6 @@ extern const VMStateDescription vmstate_s390_cpu; #define MMU_HOME_IDX 2 #define MMU_REAL_IDX 3 -static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch) -{ -#ifdef CONFIG_USER_ONLY - return MMU_USER_IDX; -#else - if (!(env->psw.mask & PSW_MASK_DAT)) { - return MMU_REAL_IDX; - } - - if (ifetch) { - if ((env->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) { - return MMU_HOME_IDX; - } - return MMU_PRIMARY_IDX; - } - - switch (env->psw.mask & PSW_MASK_ASC) { - case PSW_ASC_PRIMARY: - return MMU_PRIMARY_IDX; - case PSW_ASC_SECONDARY: - return MMU_SECONDARY_IDX; - case PSW_ASC_HOME: - return MMU_HOME_IDX; - case PSW_ASC_ACCREG: - /* Fallthrough: access register mode is not yet supported */ - default: - abort(); - } -#endif -} - #ifdef CONFIG_TCG #include "tcg/tcg_s390x.h" diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 0e6fa65bae..9211da6bde 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -273,16 +273,6 @@ void cpu_load_tlb(CPUSH4State * env); /* MMU modes definitions */ #define MMU_USER_IDX 1 -static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch) -{ - /* The instruction in a RTE delay slot is fetched in privileged - mode, but executed in user mode. */ - if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) { - return 0; - } else { - return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0; - } -} #include "exec/cpu-all.h" diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 12a11ecb26..51856152fa 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -708,34 +708,6 @@ static inline int cpu_supervisor_mode(CPUSPARCState *env1) } #endif -static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch) -{ -#if defined(CONFIG_USER_ONLY) - return MMU_USER_IDX; -#elif !defined(TARGET_SPARC64) - if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ - return MMU_PHYS_IDX; - } else { - return env->psrs; - } -#else - /* IMMU or DMMU disabled. */ - if (ifetch - ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0 - : (env->lsu & DMMU_E) == 0) { - return MMU_PHYS_IDX; - } else if (cpu_hypervisor_mode(env)) { - return MMU_PHYS_IDX; - } else if (env->tl > 0) { - return MMU_NUCLEUS_IDX; - } else if (cpu_supervisor_mode(env)) { - return MMU_KERNEL_IDX; - } else { - return MMU_USER_IDX; - } -#endif -} - static inline int cpu_interrupts_enabled(CPUSPARCState *env1) { #if !defined (TARGET_SPARC64) diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 2d4446cea5..220af69fc2 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -246,11 +246,6 @@ void fpu_set_state(CPUTriCoreState *env); #define MMU_USER_IDX 2 -static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) -{ - return 0; -} - #include "exec/cpu-all.h" FIELD(TB_FLAGS, PRIV, 0, 2) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 4b033ee924..6b8d0636d2 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -713,11 +713,6 @@ static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env) /* MMU modes definitions */ #define MMU_USER_IDX 3 -static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch) -{ - return xtensa_get_cring(env); -} - #define XTENSA_TBFLAG_RING_MASK 0x3 #define XTENSA_TBFLAG_EXCM 0x4 #define XTENSA_TBFLAG_LITBASE 0x8 diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index b8ed29e343..ce18bedcca 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -25,6 +25,14 @@ #include "cpu.h" #include "exec/exec-all.h" +int cpu_mmu_index(CPUAlphaState *env, bool ifetch) +{ + int ret = env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_IDX; + if (env->flags & ENV_FLAG_PAL_MODE) { + ret = MMU_KERNEL_IDX; + } + return ret; +} static void alpha_cpu_set_pc(CPUState *cs, vaddr value) { diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 593695b424..0ee9a879f0 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -49,6 +49,11 @@ #include "fpu/softfloat.h" #include "cpregs.h" +int cpu_mmu_index(CPUARMState *env, bool ifetch) +{ + return EX_TBFLAG_ANY(env->hflags, MMUIDX); +} + static void arm_cpu_set_pc(CPUState *cs, vaddr value) { ARMCPU *cpu = ARM_CPU(cs); diff --git a/target/avr/cpu.c b/target/avr/cpu.c index f5cbdc4a8c..ffb2234ecf 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -27,6 +27,11 @@ #include "tcg/debug-assert.h" #include "hw/qdev-properties.h" +int cpu_mmu_index(CPUAVRState *env, bool ifetch) +{ + return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; +} + static void avr_cpu_set_pc(CPUState *cs, vaddr value) { AVRCPU *cpu = AVR_CPU(cs); diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 9ba08e8b0c..1a8a544e31 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -27,6 +27,10 @@ #include "cpu.h" #include "mmu.h" +int cpu_mmu_index(CPUCRISState *env, bool ifetch) +{ + return !!(env->pregs[PR_CCS] & U_FLAG); +} static void cris_cpu_set_pc(CPUState *cs, vaddr value) { diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index c0cd739e15..fd8dafad31 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -26,6 +26,15 @@ #include "tcg/tcg.h" #include "exec/gdbstub.h" +int cpu_mmu_index(CPUHexagonState *env, bool ifetch) +{ +#ifdef CONFIG_USER_ONLY + return MMU_USER_IDX; +#else +#error System mode not supported on Hexagon yet +#endif +} + static void hexagon_v67_cpu_init(Object *obj) { } static void hexagon_v68_cpu_init(Object *obj) { } static void hexagon_v69_cpu_init(Object *obj) { } diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 14e17fa9aa..04f0b927b6 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -28,6 +28,19 @@ #include "fpu/softfloat.h" #include "tcg/tcg.h" +int cpu_mmu_index(CPUHPPAState *env, bool ifetch) +{ +#ifdef CONFIG_USER_ONLY + return MMU_USER_IDX; +#else + if (env->psw & (ifetch ? PSW_C : PSW_D)) { + return PRIV_P_TO_MMU_IDX(env->iaoq_f & 3, env->psw & PSW_P); + } + /* mmu disabled */ + return env->psw & PSW_W ? MMU_ABS_W_IDX : MMU_ABS_IDX; +#endif +} + static void hppa_cpu_set_pc(CPUState *cs, vaddr value) { HPPACPU *cpu = HPPA_CPU(cs); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 03822d9ba8..d0adfb381b 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -46,6 +46,13 @@ #include "disas/capstone.h" #include "cpu-internal.h" +int cpu_mmu_index(CPUX86State *env, bool ifetch) +{ + return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX : + (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK)) + ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; +} + static void x86_cpu_realizefn(DeviceState *dev, Error **errp); /* Helpers for building CPUID[2] descriptors: */ diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 064540397d..316a85bacd 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -31,6 +31,18 @@ #include "tcg/tcg.h" #endif +int cpu_mmu_index(CPULoongArchState *env, bool ifetch) +{ +#ifdef CONFIG_USER_ONLY + return MMU_IDX_USER; +#else + if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) { + return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); + } + return MMU_IDX_DA; +#endif +} + const char * const regnames[32] = { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 1421e77c2c..604cdd5faf 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -24,6 +24,11 @@ #include "migration/vmstate.h" #include "fpu/softfloat.h" +int cpu_mmu_index(CPUM68KState *env, bool ifetch) +{ + return (env->sr & SR_S) == 0 ? 1 : 0; +} + static void m68k_cpu_set_pc(CPUState *cs, vaddr value) { M68kCPU *cpu = M68K_CPU(cs); diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index bbb3335cad..f8891de41e 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -32,6 +32,22 @@ #include "fpu/softfloat-helpers.h" #include "tcg/tcg.h" +int cpu_mmu_index(CPUMBState *env, bool ifetch) +{ + MicroBlazeCPU *cpu = env_archcpu(env); + + /* Are we in nommu mode?. */ + if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) { + return MMU_NOMMU_IDX; + } + + if (env->msr & MSR_UM) { + return MMU_USER_IDX; + } + return MMU_KERNEL_IDX; +} + + static const struct { const char *name; uint8_t version_id; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index a0023edd43..34c0e40d32 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -35,6 +35,11 @@ #include "semihosting/semihost.h" #include "fpu_helper.h" +int cpu_mmu_index(CPUMIPSState *env, bool ifetch) +{ + return hflags_mmu_index(env->hflags); +} + const char regnames[32][3] = { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index a27732bf2b..976b8c50ad 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -26,6 +26,12 @@ #include "gdbstub/helpers.h" #include "hw/qdev-properties.h" +int cpu_mmu_index(CPUNios2State *env, bool ifetch) +{ + return (env->ctrl[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX : + MMU_SUPERVISOR_IDX; +} + static void nios2_cpu_set_pc(CPUState *cs, vaddr value) { Nios2CPU *cpu = NIOS2_CPU(cs); diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 381ebe00d3..fedeba3a3f 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -25,6 +25,18 @@ #include "fpu/softfloat-helpers.h" #include "tcg/tcg.h" +int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) +{ + int ret = MMU_NOMMU_IDX; /* mmu is disabled */ + + if (env->sr & (ifetch ? SR_IME : SR_DME)) { + /* The mmu is enabled; test supervisor state. */ + ret = env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; + } + + return ret; +} + static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) { OpenRISCCPU *cpu = OPENRISC_CPU(cs); diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c index e3ad8e0c27..53f1d5c370 100644 --- a/target/ppc/cpu.c +++ b/target/ppc/cpu.c @@ -27,6 +27,15 @@ #include "helper_regs.h" #include "sysemu/tcg.h" +int cpu_mmu_index(CPUPPCState *env, bool ifetch) +{ +#ifdef CONFIG_USER_ONLY + return MMU_USER_IDX; +#else + return (env->hflags >> (ifetch ? HFLAGS_IMMU_IDX : HFLAGS_DMMU_IDX)) & 7; +#endif +} + target_ulong cpu_read_xer(const CPUPPCState *env) { if (is_isa300(env)) { diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c7cc7eb423..ea54081130 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -33,7 +33,7 @@ #include "debug.h" #include "tcg/oversized-guest.h" -int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) +int cpu_mmu_index(CPURISCVState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY return 0; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index c5ffeffe32..b9f2bff9ce 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -26,6 +26,11 @@ #include "fpu/softfloat.h" #include "tcg/debug-assert.h" +int cpu_mmu_index(CPURXState *env, bool ifetch) +{ + return 0; +} + static void rx_cpu_set_pc(CPUState *cs, vaddr value) { RXCPU *cpu = RX_CPU(cs); diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 6acfa1c91b..bbb0b65bee 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -43,6 +43,37 @@ #define CR0_RESET 0xE0UL #define CR14_RESET 0xC2000000UL; +int cpu_mmu_index(CPUS390XState *env, bool ifetch) +{ +#ifdef CONFIG_USER_ONLY + return MMU_USER_IDX; +#else + if (!(env->psw.mask & PSW_MASK_DAT)) { + return MMU_REAL_IDX; + } + + if (ifetch) { + if ((env->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) { + return MMU_HOME_IDX; + } + return MMU_PRIMARY_IDX; + } + + switch (env->psw.mask & PSW_MASK_ASC) { + case PSW_ASC_PRIMARY: + return MMU_PRIMARY_IDX; + case PSW_ASC_SECONDARY: + return MMU_SECONDARY_IDX; + case PSW_ASC_HOME: + return MMU_HOME_IDX; + case PSW_ASC_ACCREG: + /* Fallthrough: access register mode is not yet supported */ + default: + abort(); + } +#endif +} + #ifndef CONFIG_USER_ONLY static bool is_early_exception_psw(uint64_t mask, uint64_t addr) { diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 806a0ef875..e99fba7778 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -28,6 +28,19 @@ #include "fpu/softfloat-helpers.h" #include "tcg/tcg.h" +int cpu_mmu_index(CPUSH4State *env, bool ifetch) +{ + /* + * The instruction in a RTE delay slot is fetched in privileged + * mode, but executed in user mode. + */ + if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) { + return 0; + } else { + return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0; + } +} + static void superh_cpu_set_pc(CPUState *cs, vaddr value) { SuperHCPU *cpu = SUPERH_CPU(cs); diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index befa7fc4eb..e2b1feac2f 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -29,6 +29,34 @@ //#define DEBUG_FEATURES +int cpu_mmu_index(CPUSPARCState *env, bool ifetch) +{ +#if defined(CONFIG_USER_ONLY) + return MMU_USER_IDX; +#elif !defined(TARGET_SPARC64) + if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ + return MMU_PHYS_IDX; + } else { + return env->psrs; + } +#else + /* IMMU or DMMU disabled. */ + if (ifetch + ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0 + : (env->lsu & DMMU_E) == 0) { + return MMU_PHYS_IDX; + } else if (cpu_hypervisor_mode(env)) { + return MMU_PHYS_IDX; + } else if (env->tl > 0) { + return MMU_NUCLEUS_IDX; + } else if (cpu_supervisor_mode(env)) { + return MMU_KERNEL_IDX; + } else { + return MMU_USER_IDX; + } +#endif +} + static void sparc_cpu_reset_hold(Object *obj) { CPUState *s = CPU(obj); diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 8acacdf0c0..a2bb1038ff 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -24,6 +24,11 @@ #include "qemu/error-report.h" #include "tcg/debug-assert.h" +int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) +{ + return 0; +} + static inline void set_feature(CPUTriCoreState *env, int feature) { env->features |= 1ULL << feature; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 99c0ca130f..7d69cef8cc 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -39,6 +39,10 @@ #include "exec/memory.h" #endif +int cpu_mmu_index(CPUXtensaState *env, bool ifetch) +{ + return xtensa_get_cring(env); +} static void xtensa_cpu_set_pc(CPUState *cs, vaddr value) { From patchwork Sun Jan 28 04:41:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767206 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp347666wro; Sat, 27 Jan 2024 20:43:18 -0800 (PST) X-Google-Smtp-Source: AGHT+IFW3L7k/18tPZIPUxQJUGMLrav1K9q9fz4+FkZKdVZ9L4ZoI7gflUSUUcruaDkSxW7nKlbW X-Received: by 2002:a05:6214:2c:b0:68c:4774:a9db with SMTP id b12-20020a056214002c00b0068c4774a9dbmr312658qvr.48.1706416997932; Sat, 27 Jan 2024 20:43:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706416997; cv=none; d=google.com; s=arc-20160816; b=dVRBFNkS37QeBuIkaC9TkPVqEMCkKud2psiwib2LBipnNGUUt3ZecqUjMYckz8z+OD kKEaiWTEbIqaCsWLxy+SyBG0rl3ECYpU8S3rNdmzTCtxjyrSXwZv3tMMe+RisiMkWjt2 TaKtEPgB8iu05TKWC3PbRlKVJtI+EU8gd/u8dVFccIbhoPXU0n0uTPrzyTVTWBTDdHPH /KU80+2zXeqAsbWNUGzZdvKlJVLO83PwFN2XNDpZjVGDTLyGmlC8HF4benR2AKC3dVuB x1Ffe79LLcbhWgL0kQRYHXpSv5u78URgKkkGEftE++N6B0UEUWcPCKkqF+Xw95ebg4bw LvHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=5fv+pc/a9zag0QS85JnFIDYR2iyAM3R7hb/CB3POH4c=; fh=l3rThTWYtfg9kQ3pwkdseR7wGfUMT6wsJF5cqMswxYY=; b=bDQ01RATiteT59jjbqlXMX1fuMVy4o0x8xJMmBjo+4yNhJiS7RFN6jxb4d2TVSwgLv 3wDJ1yFGi2NL8GRAth2Ouai7N9WAI0H9vLnUpubcZ58nBLrnHwVYJUcNmgLttg3dw/X3 bhYIaOzGF/D5pTJueTHrzXDbuqDKfD+1Bbpt8pBF2cB9E1QWT+1sEEZ1NlMaJcvqeabR GF2WwQCDuoXbtvMfoyAWg8ILy73vvJoPqX75qNYAbNL6iOTQnavmpK/aSLxHEaIlw0vj OL+cMCxYLBwU2iI3dpsvr6/ErEqGZrFNUO2xyeLQ2tUs4wckgSs/JvucCulyXyPXacBQ 5zBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WoUSTUWF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PATCH 08/33] target: Uninline cpu_get_tb_cpu_state() Date: Sun, 28 Jan 2024 14:41:48 +1000 Message-Id: <20240128044213.316480-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Anton Johansson Required to compile accel/tcg/translate-all.c once for softmmu targets. The function gets quite big for some targets so uninlining makes sense. Signed-off-by: Anton Johansson Message-Id: <20240119144024.14289-14-anjo@rev.ng> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- include/exec/cpu-common.h | 3 ++ target/alpha/cpu.h | 11 ------- target/arm/cpu.h | 3 -- target/avr/cpu.h | 18 ----------- target/cris/cpu.h | 10 ------ target/hexagon/cpu.h | 12 ------- target/hppa/cpu.h | 42 ------------------------ target/i386/cpu.h | 14 -------- target/loongarch/cpu.h | 12 ------- target/m68k/cpu.h | 16 --------- target/microblaze/cpu.h | 8 ----- target/mips/cpu.h | 9 ------ target/nios2/cpu.h | 12 ------- target/openrisc/cpu.h | 10 ------ target/ppc/cpu.h | 13 -------- target/riscv/cpu.h | 3 -- target/rx/cpu.h | 9 ------ target/s390x/cpu.h | 24 -------------- target/sh4/cpu.h | 15 --------- target/sparc/cpu.h | 33 ------------------- target/tricore/cpu.h | 12 ------- target/xtensa/cpu.h | 68 --------------------------------------- target/alpha/cpu.c | 11 +++++++ target/avr/cpu.c | 18 +++++++++++ target/cris/cpu.c | 10 ++++++ target/hexagon/cpu.c | 12 +++++++ target/hppa/cpu.c | 42 ++++++++++++++++++++++++ target/i386/cpu.c | 14 ++++++++ target/loongarch/cpu.c | 12 +++++++ target/m68k/cpu.c | 16 +++++++++ target/microblaze/cpu.c | 7 ++++ target/mips/cpu.c | 9 ++++++ target/nios2/cpu.c | 12 +++++++ target/openrisc/cpu.c | 10 ++++++ target/ppc/helper_regs.c | 17 +++++----- target/rx/cpu.c | 9 ++++++ target/s390x/cpu.c | 22 +++++++++++++ target/sh4/cpu.c | 15 +++++++++ target/sparc/cpu.c | 33 +++++++++++++++++++ target/tricore/cpu.c | 12 +++++++ target/xtensa/cpu.c | 68 +++++++++++++++++++++++++++++++++++++++ 41 files changed, 344 insertions(+), 362 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 4724135f30..1a8fad9222 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -44,6 +44,9 @@ unsigned int cpu_list_generation_id_get(void); */ int cpu_mmu_index(CPUArchState *env, bool ifetch); +void cpu_get_tb_cpu_state(CPUArchState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags); + void tcg_iommu_init_notifier_list(CPUState *cpu); void tcg_iommu_free_notifier_list(CPUState *cpu); diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index abf778735a..2b0173577c 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -458,17 +458,6 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, MemTxResult response, uintptr_t retaddr); #endif -static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) -{ - *pc = env->pc; - *cs_base = 0; - *pflags = env->flags & ENV_FLAG_TB_MASK; -#ifdef CONFIG_USER_ONLY - *pflags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; -#endif -} - #ifdef CONFIG_USER_ONLY /* Copied from linux ieee_swcr_to_fpcr. */ static inline uint64_t alpha_ieee_swcr_to_fpcr(uint64_t swcr) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b0edf2e540..a4ec37c8ed 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3313,9 +3313,6 @@ static inline bool arm_cpu_bswap_data(CPUARMState *env) } #endif -void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags); - enum { QEMU_PSCI_CONDUIT_DISABLED = 0, QEMU_PSCI_CONDUIT_SMC = 1, diff --git a/target/avr/cpu.h b/target/avr/cpu.h index d185d20dcb..284041a87a 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -193,24 +193,6 @@ enum { TB_FLAGS_SKIP = 2, }; -static inline void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) -{ - uint32_t flags = 0; - - *pc = env->pc_w * 2; - *cs_base = 0; - - if (env->fullacc) { - flags |= TB_FLAGS_FULL_ACCESS; - } - if (env->skip) { - flags |= TB_FLAGS_SKIP; - } - - *pflags = flags; -} - static inline int cpu_interrupts_enabled(CPUAVRState *env) { return env->sregI != 0; diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 3904e5448c..6df53f49c4 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -273,14 +273,4 @@ enum { #include "exec/cpu-all.h" -static inline void cpu_get_tb_cpu_state(CPUCRISState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc = env->pc; - *cs_base = 0; - *flags = env->dslot | - (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG - | X_FLAG | PFIX_FLAG)); -} - #endif diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 3eef58fe8f..1d42c33827 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -134,18 +134,6 @@ struct ArchCPU { FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1) -static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - uint32_t hex_flags = 0; - *pc = env->gpr[HEX_REG_PC]; - *cs_base = 0; - if (*pc == env->gpr[HEX_REG_SA0]) { - hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); - } - *flags = hex_flags; -} - typedef HexagonCPU ArchCPU; void hexagon_translate_init(void); diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 7a181e8f33..b449ceea6b 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -314,48 +314,6 @@ hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr); #define TB_FLAG_PRIV_SHIFT 8 #define TB_FLAG_UNALIGN 0x400 -static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) -{ - uint32_t flags = env->psw_n * PSW_N; - - /* TB lookup assumes that PC contains the complete virtual address. - If we leave space+offset separate, we'll get ITLB misses to an - incomplete virtual address. This also means that we must separate - out current cpu privilege from the low bits of IAOQ_F. */ -#ifdef CONFIG_USER_ONLY - *pc = env->iaoq_f & -4; - *cs_base = env->iaoq_b & -4; - flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; -#else - /* ??? E, T, H, L, B bits need to be here, when implemented. */ - flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P); - flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; - - *pc = hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0), - env->iaoq_f & -4); - *cs_base = env->iasq_f; - - /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero - low 32-bits of CS_BASE. This will succeed for all direct branches, - which is the primary case we care about -- using goto_tb within a page. - Failure is indicated by a zero difference. */ - if (env->iasq_f == env->iasq_b) { - target_long diff = env->iaoq_b - env->iaoq_f; - if (diff == (int32_t)diff) { - *cs_base |= (uint32_t)diff; - } - } - if ((env->sr[4] == env->sr[5]) - & (env->sr[4] == env->sr[6]) - & (env->sr[4] == env->sr[7])) { - flags |= TB_FLAG_SR_SAME; - } -#endif - - *pflags = flags; -} - target_ulong cpu_hppa_get_psw(CPUHPPAState *env); void cpu_hppa_put_psw(CPUHPPAState *env, target_ulong); void cpu_hppa_loaded_fr0(CPUHPPAState *env); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 6a5b180ccb..4352d0d163 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2315,20 +2315,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *env) #include "hw/i386/apic.h" #endif -static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *flags = env->hflags | - (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); - if (env->hflags & HF_CS64_MASK) { - *cs_base = 0; - *pc = env->eip; - } else { - *cs_base = env->segs[R_CS].base; - *pc = (uint32_t)(*cs_base + env->eip); - } -} - void do_cpu_init(X86CPU *cpu); #define MCE_INJECT_BROADCAST 1 diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 64eac07a16..dd375d115f 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -443,18 +443,6 @@ static inline void set_pc(CPULoongArchState *env, uint64_t value) #define HW_FLAGS_VA32 0x20 #define HW_FLAGS_EUEN_ASXE 0x40 -static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc = env->pc; - *cs_base = 0; - *flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); - *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE; - *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE; - *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_ASXE; - *flags |= is_va32(env) * HW_FLAGS_VA32; -} - #include "exec/cpu-all.h" #define CPU_RESOLVING_TYPE TYPE_LOONGARCH_CPU diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index aca4aa610b..54dcfe1194 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -601,22 +601,6 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, #define TB_FLAGS_TRACE 16 #define TB_FLAGS_TRACE_BIT (1 << TB_FLAGS_TRACE) -static inline void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc = env->pc; - *cs_base = 0; - *flags = (env->macsr >> 4) & TB_FLAGS_MACSR; - if (env->sr & SR_S) { - *flags |= TB_FLAGS_MSR_S; - *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S; - *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S; - } - if (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS) { - *flags |= TB_FLAGS_TRACE; - } -} - void dump_mmu(CPUM68KState *env); #endif diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 446af5dd4c..27ccfc92b4 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -415,14 +415,6 @@ void mb_tcg_init(void); /* Ensure there is no overlap between the two masks. */ QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK); -static inline void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc = env->pc; - *flags = (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK); - *cs_base = (*flags & IMM_FLAG ? env->imm : 0); -} - #if !defined(CONFIG_USER_ONLY) bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 4c9dc09a66..05e9c902d1 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1359,15 +1359,6 @@ void cpu_mips_clock_init(MIPSCPU *cpu); /* helper.c */ target_ulong exception_resume_pc(CPUMIPSState *env); -static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc = env->active_tc.PC; - *cs_base = 0; - *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | - MIPS_HFLAG_HWRENA_ULR); -} - /** * mips_cpu_create_with_clock: * @typename: a MIPS CPU type. diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 4164a3432e..d0616723fe 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -286,16 +286,4 @@ FIELD(TBFLAGS, CRS0, 0, 1) /* Set if CRS == 0. */ FIELD(TBFLAGS, U, 1, 1) /* Overlaps CR_STATUS_U */ FIELD(TBFLAGS, R0_0, 2, 1) /* Set if R0 == 0. */ -static inline void cpu_get_tb_cpu_state(CPUNios2State *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - unsigned crs = FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, CRS); - - *pc = env->pc; - *cs_base = 0; - *flags = (env->ctrl[CR_STATUS] & CR_STATUS_U) - | (crs ? 0 : R_TBFLAGS_CRS0_MASK) - | (env->regs[0] ? 0 : R_TBFLAGS_R0_0_MASK); -} - #endif /* NIOS2_CPU_H */ diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index b1b7db5cbd..6997c7534e 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -351,16 +351,6 @@ static inline void cpu_set_gpr(CPUOpenRISCState *env, int i, uint32_t val) env->shadow_gpr[0][i] = val; } -static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc = env->pc; - *cs_base = 0; - *flags = (env->dflag ? TB_FLAGS_DFLAG : 0) - | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) - | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); -} - static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) { return (env->sr diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 59587a8aba..3bb10f0188 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2652,19 +2652,6 @@ void cpu_write_xer(CPUPPCState *env, target_ulong xer); */ #define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B)) -#ifdef CONFIG_DEBUG_TCG -void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags); -#else -static inline void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc = env->nip; - *cs_base = 0; - *flags = env->hflags; -} -#endif - G_NORETURN void raise_exception(CPUPPCState *env, uint32_t exception); G_NORETURN void raise_exception_ra(CPUPPCState *env, uint32_t exception, uintptr_t raddr); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bca27278ed..625ffc7622 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -688,9 +688,6 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) return cpu->cfg.vlen >> (sew + 3 - lmul); } -void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags); - void riscv_cpu_update_mask(CPURISCVState *env); bool riscv_cpu_is_32bit(RISCVCPU *cpu); diff --git a/target/rx/cpu.h b/target/rx/cpu.h index c53593d7aa..dcda762212 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -149,15 +149,6 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte); #define RX_CPU_IRQ 0 #define RX_CPU_FIR 1 -static inline void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc = env->pc; - *cs_base = 0; - *flags = FIELD_DP32(0, PSW, PM, env->psw_pm); - *flags = FIELD_DP32(*flags, PSW, U, env->psw_u); -} - static inline uint32_t rx_cpu_pack_psw(CPURXState *env) { uint32_t psw = 0; diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index 61c893b1b9..dd5b145539 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -382,31 +382,7 @@ extern const VMStateDescription vmstate_s390_cpu; #define MMU_REAL_IDX 3 #ifdef CONFIG_TCG - #include "tcg/tcg_s390x.h" - -static inline void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - if (env->psw.addr & 1) { - /* - * Instructions must be at even addresses. - * This needs to be checked before address translation. - */ - env->int_pgm_ilen = 2; /* see s390_cpu_tlb_fill() */ - tcg_s390_program_interrupt(env, PGM_SPECIFICATION, 0); - } - *pc = env->psw.addr; - *cs_base = env->ex_value; - *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; - if (env->cregs[0] & CR0_AFP) { - *flags |= FLAG_MASK_AFP; - } - if (env->cregs[0] & CR0_VECTOR) { - *flags |= FLAG_MASK_VECTOR; - } -} - #endif /* CONFIG_TCG */ /* PER bits from control register 9 */ diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 9211da6bde..36aff035cf 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -370,19 +370,4 @@ static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr) env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T)); } -static inline void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc = env->pc; - /* For a gUSA region, notice the end of the region. */ - *cs_base = env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0; - *flags = env->flags - | (env->fpscr & TB_FLAG_FPSCR_MASK) - | (env->sr & TB_FLAG_SR_MASK) - | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ -#ifdef CONFIG_USER_ONLY - *flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; -#endif -} - #endif /* SH4_CPU_H */ diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 51856152fa..60c72f06f5 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -749,39 +749,6 @@ trap_state* cpu_tsptr(CPUSPARCState* env); #define TB_FLAG_HYPER (1 << 7) #define TB_FLAG_ASI_SHIFT 24 -static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *pflags) -{ - uint32_t flags; - *pc = env->pc; - *cs_base = env->npc; - flags = cpu_mmu_index(env, false); -#ifndef CONFIG_USER_ONLY - if (cpu_supervisor_mode(env)) { - flags |= TB_FLAG_SUPER; - } -#endif -#ifdef TARGET_SPARC64 -#ifndef CONFIG_USER_ONLY - if (cpu_hypervisor_mode(env)) { - flags |= TB_FLAG_HYPER; - } -#endif - if (env->pstate & PS_AM) { - flags |= TB_FLAG_AM_ENABLED; - } - if ((env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) { - flags |= TB_FLAG_FPU_ENABLED; - } - flags |= env->asi << TB_FLAG_ASI_SHIFT; -#else - if (env->psref) { - flags |= TB_FLAG_FPU_ENABLED; - } -#endif - *pflags = flags; -} - static inline bool tb_fpu_enabled(int tb_flags) { #if defined(CONFIG_USER_ONLY) diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 220af69fc2..9537fef2b9 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -253,18 +253,6 @@ FIELD(TB_FLAGS, PRIV, 0, 2) void cpu_state_reset(CPUTriCoreState *s); void tricore_tcg_init(void); -static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - uint32_t new_flags = 0; - *pc = env->PC; - *cs_base = 0; - - new_flags |= FIELD_DP32(new_flags, TB_FLAGS, PRIV, - extract32(env->PSW, 10, 2)); - *flags = new_flags; -} - #define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU /* helpers.c */ diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 6b8d0636d2..2b6f2bdea7 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -734,74 +734,6 @@ static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env) #include "exec/cpu-all.h" -static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc, - uint64_t *cs_base, uint32_t *flags) -{ - *pc = env->pc; - *cs_base = 0; - *flags = 0; - *flags |= xtensa_get_ring(env); - if (env->sregs[PS] & PS_EXCM) { - *flags |= XTENSA_TBFLAG_EXCM; - } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) { - target_ulong lend_dist = - env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS)); - - /* - * 0 in the csbase_lend field means that there may not be a loopback - * for any instruction that starts inside this page. Any other value - * means that an instruction that ends at this offset from the page - * start may loop back and will need loopback code to be generated. - * - * lend_dist is 0 when LEND points to the start of the page, but - * no instruction that starts inside this page may end at offset 0, - * so it's still correct. - * - * When an instruction ends at a page boundary it may only start in - * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE - * for the TB that contains this instruction. - */ - if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size) { - target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG]; - - *cs_base = lend_dist; - if (lbeg_off < 256) { - *cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; - } - } - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && - (env->sregs[LITBASE] & 1)) { - *flags |= XTENSA_TBFLAG_LITBASE; - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { - if (xtensa_get_cintlevel(env) < env->config->debug_level) { - *flags |= XTENSA_TBFLAG_DEBUG; - } - if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { - *flags |= XTENSA_TBFLAG_ICOUNT; - } - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { - *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; - } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) && - (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) { - uint32_t windowstart = xtensa_replicate_windowstart(env) >> - (env->sregs[WINDOW_BASE] + 1); - uint32_t w = ctz32(windowstart | 0x8); - - *flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; - *flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT, - PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT; - } else { - *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT; - } - if (env->yield_needed) { - *flags |= XTENSA_TBFLAG_YIELD; - } -} - XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk); diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index ce18bedcca..ce20a56270 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -34,6 +34,17 @@ int cpu_mmu_index(CPUAlphaState *env, bool ifetch) return ret; } +void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + *pc = env->pc; + *cs_base = 0; + *pflags = env->flags & ENV_FLAG_TB_MASK; +#ifdef CONFIG_USER_ONLY + *pflags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif +} + static void alpha_cpu_set_pc(CPUState *cs, vaddr value) { AlphaCPU *cpu = ALPHA_CPU(cs); diff --git a/target/avr/cpu.c b/target/avr/cpu.c index ffb2234ecf..76dbe56284 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -32,6 +32,24 @@ int cpu_mmu_index(CPUAVRState *env, bool ifetch) return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX; } +void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + uint32_t flags = 0; + + *pc = env->pc_w * 2; + *cs_base = 0; + + if (env->fullacc) { + flags |= TB_FLAGS_FULL_ACCESS; + } + if (env->skip) { + flags |= TB_FLAGS_SKIP; + } + + *pflags = flags; +} + static void avr_cpu_set_pc(CPUState *cs, vaddr value) { AVRCPU *cpu = AVR_CPU(cs); diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 1a8a544e31..6512ef8ee2 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -32,6 +32,16 @@ int cpu_mmu_index(CPUCRISState *env, bool ifetch) return !!(env->pregs[PR_CCS] & U_FLAG); } +void cpu_get_tb_cpu_state(CPUCRISState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc = env->pc; + *cs_base = 0; + *flags = env->dslot | + (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG + | X_FLAG | PFIX_FLAG)); +} + static void cris_cpu_set_pc(CPUState *cs, vaddr value) { CRISCPU *cpu = CRIS_CPU(cs); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index fd8dafad31..b2bbb21b59 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -35,6 +35,18 @@ int cpu_mmu_index(CPUHexagonState *env, bool ifetch) #endif } +void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + uint32_t hex_flags = 0; + *pc = env->gpr[HEX_REG_PC]; + *cs_base = 0; + if (*pc == env->gpr[HEX_REG_SA0]) { + hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1); + } + *flags = hex_flags; +} + static void hexagon_v67_cpu_init(Object *obj) { } static void hexagon_v68_cpu_init(Object *obj) { } static void hexagon_v69_cpu_init(Object *obj) { } diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 04f0b927b6..2cc8e43b33 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -41,6 +41,48 @@ int cpu_mmu_index(CPUHPPAState *env, bool ifetch) #endif } +void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + uint32_t flags = env->psw_n * PSW_N; + + /* TB lookup assumes that PC contains the complete virtual address. + If we leave space+offset separate, we'll get ITLB misses to an + incomplete virtual address. This also means that we must separate + out current cpu privilege from the low bits of IAOQ_F. */ +#ifdef CONFIG_USER_ONLY + *pc = env->iaoq_f & -4; + *cs_base = env->iaoq_b & -4; + flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#else + /* ??? E, T, H, L, B bits need to be here, when implemented. */ + flags |= env->psw & (PSW_W | PSW_C | PSW_D | PSW_P); + flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; + + *pc = hppa_form_gva_psw(env->psw, (env->psw & PSW_C ? env->iasq_f : 0), + env->iaoq_f & -4); + *cs_base = env->iasq_f; + + /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero + low 32-bits of CS_BASE. This will succeed for all direct branches, + which is the primary case we care about -- using goto_tb within a page. + Failure is indicated by a zero difference. */ + if (env->iasq_f == env->iasq_b) { + target_long diff = env->iaoq_b - env->iaoq_f; + if (diff == (int32_t)diff) { + *cs_base |= (uint32_t)diff; + } + } + if ((env->sr[4] == env->sr[5]) + & (env->sr[4] == env->sr[6]) + & (env->sr[4] == env->sr[7])) { + flags |= TB_FLAG_SR_SAME; + } +#endif + + *pflags = flags; +} + static void hppa_cpu_set_pc(CPUState *cs, vaddr value) { HPPACPU *cpu = HPPA_CPU(cs); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index d0adfb381b..da32929558 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -53,6 +53,20 @@ int cpu_mmu_index(CPUX86State *env, bool ifetch) ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX; } +void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *flags = env->hflags | + (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK)); + if (env->hflags & HF_CS64_MASK) { + *cs_base = 0; + *pc = env->eip; + } else { + *cs_base = env->segs[R_CS].base; + *pc = (uint32_t)(*cs_base + env->eip); + } +} + static void x86_cpu_realizefn(DeviceState *dev, Error **errp); /* Helpers for building CPUID[2] descriptors: */ diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 316a85bacd..ea4281e177 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -43,6 +43,18 @@ int cpu_mmu_index(CPULoongArchState *env, bool ifetch) #endif } +void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc = env->pc; + *cs_base = 0; + *flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); + *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE; + *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE; + *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, ASXE) * HW_FLAGS_EUEN_ASXE; + *flags |= is_va32(env) * HW_FLAGS_VA32; +} + const char * const regnames[32] = { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 604cdd5faf..f9dc447897 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -29,6 +29,22 @@ int cpu_mmu_index(CPUM68KState *env, bool ifetch) return (env->sr & SR_S) == 0 ? 1 : 0; } +void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc = env->pc; + *cs_base = 0; + *flags = (env->macsr >> 4) & TB_FLAGS_MACSR; + if (env->sr & SR_S) { + *flags |= TB_FLAGS_MSR_S; + *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S; + *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S; + } + if (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS) { + *flags |= TB_FLAGS_TRACE; + } +} + static void m68k_cpu_set_pc(CPUState *cs, vaddr value) { M68kCPU *cpu = M68K_CPU(cs); diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index f8891de41e..4c270e941f 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -47,6 +47,13 @@ int cpu_mmu_index(CPUMBState *env, bool ifetch) return MMU_KERNEL_IDX; } +void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc = env->pc; + *flags = (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK); + *cs_base = (*flags & IMM_FLAG ? env->imm : 0); +} static const struct { const char *name; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 34c0e40d32..4c3e1ec2d9 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -40,6 +40,15 @@ int cpu_mmu_index(CPUMIPSState *env, bool ifetch) return hflags_mmu_index(env->hflags); } +void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc = env->active_tc.PC; + *cs_base = 0; + *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | + MIPS_HFLAG_HWRENA_ULR); +} + const char regnames[32][3] = { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 976b8c50ad..3e42889ce6 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -32,6 +32,18 @@ int cpu_mmu_index(CPUNios2State *env, bool ifetch) MMU_SUPERVISOR_IDX; } +void cpu_get_tb_cpu_state(CPUNios2State *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + unsigned crs = FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, CRS); + + *pc = env->pc; + *cs_base = 0; + *flags = (env->ctrl[CR_STATUS] & CR_STATUS_U) + | (crs ? 0 : R_TBFLAGS_CRS0_MASK) + | (env->regs[0] ? 0 : R_TBFLAGS_R0_0_MASK); +} + static void nios2_cpu_set_pc(CPUState *cs, vaddr value) { Nios2CPU *cpu = NIOS2_CPU(cs); diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index fedeba3a3f..fda0dc9470 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -37,6 +37,16 @@ int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) return ret; } +void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc = env->pc; + *cs_base = 0; + *flags = (env->dflag ? TB_FLAGS_DFLAG : 0) + | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) + | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); +} + static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) { OpenRISCCPU *cpu = OPENRISC_CPU(cs); diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c index e0b2dcd02e..a506f9823c 100644 --- a/target/ppc/helper_regs.c +++ b/target/ppc/helper_regs.c @@ -217,26 +217,27 @@ void hreg_update_pmu_hflags(CPUPPCState *env) env->hflags |= hreg_compute_pmu_hflags_value(env); } -#ifdef CONFIG_DEBUG_TCG void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) { +#ifdef CONFIG_DEBUG_TCG + uint32_t hflags_rebuilt = hreg_compute_hflags_value(env); uint32_t hflags_current = env->hflags; - uint32_t hflags_rebuilt; - *pc = env->nip; - *cs_base = 0; - *flags = hflags_current; - - hflags_rebuilt = hreg_compute_hflags_value(env); if (unlikely(hflags_current != hflags_rebuilt)) { cpu_abort(env_cpu(env), "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n", hflags_current, hflags_rebuilt); } -} + *flags = hflags_current; +#else + *flags = env->hflags; #endif + *pc = env->nip; + *cs_base = 0; +} + void cpu_interrupt_exittb(CPUState *cs) { /* diff --git a/target/rx/cpu.c b/target/rx/cpu.c index b9f2bff9ce..de1cc7a5e6 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -31,6 +31,15 @@ int cpu_mmu_index(CPURXState *env, bool ifetch) return 0; } +void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc = env->pc; + *cs_base = 0; + *flags = FIELD_DP32(0, PSW, PM, env->psw_pm); + *flags = FIELD_DP32(*flags, PSW, U, env->psw_u); +} + static void rx_cpu_set_pc(CPUState *cs, vaddr value) { RXCPU *cpu = RX_CPU(cs); diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index bbb0b65bee..db1590472e 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -74,6 +74,28 @@ int cpu_mmu_index(CPUS390XState *env, bool ifetch) #endif } +void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + if (env->psw.addr & 1) { + /* + * Instructions must be at even addresses. + * This needs to be checked before address translation. + */ + env->int_pgm_ilen = 2; /* see s390_cpu_tlb_fill() */ + tcg_s390_program_interrupt(env, PGM_SPECIFICATION, 0); + } + *pc = env->psw.addr; + *cs_base = env->ex_value; + *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; + if (env->cregs[0] & CR0_AFP) { + *flags |= FLAG_MASK_AFP; + } + if (env->cregs[0] & CR0_VECTOR) { + *flags |= FLAG_MASK_VECTOR; + } +} + #ifndef CONFIG_USER_ONLY static bool is_early_exception_psw(uint64_t mask, uint64_t addr) { diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index e99fba7778..eb7eb6f30a 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -41,6 +41,21 @@ int cpu_mmu_index(CPUSH4State *env, bool ifetch) } } +void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc = env->pc; + /* For a gUSA region, notice the end of the region. */ + *cs_base = env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0; + *flags = env->flags + | (env->fpscr & TB_FLAG_FPSCR_MASK) + | (env->sr & TB_FLAG_SR_MASK) + | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */ +#ifdef CONFIG_USER_ONLY + *flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus; +#endif +} + static void superh_cpu_set_pc(CPUState *cs, vaddr value) { SuperHCPU *cpu = SUPERH_CPU(cs); diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index e2b1feac2f..99d57cc209 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -57,6 +57,39 @@ int cpu_mmu_index(CPUSPARCState *env, bool ifetch) #endif } +void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *pflags) +{ + uint32_t flags; + *pc = env->pc; + *cs_base = env->npc; + flags = cpu_mmu_index(env, false); +#ifndef CONFIG_USER_ONLY + if (cpu_supervisor_mode(env)) { + flags |= TB_FLAG_SUPER; + } +#endif +#ifdef TARGET_SPARC64 +#ifndef CONFIG_USER_ONLY + if (cpu_hypervisor_mode(env)) { + flags |= TB_FLAG_HYPER; + } +#endif + if (env->pstate & PS_AM) { + flags |= TB_FLAG_AM_ENABLED; + } + if ((env->pstate & PS_PEF) && (env->fprs & FPRS_FEF)) { + flags |= TB_FLAG_FPU_ENABLED; + } + flags |= env->asi << TB_FLAG_ASI_SHIFT; +#else + if (env->psref) { + flags |= TB_FLAG_FPU_ENABLED; + } +#endif + *pflags = flags; +} + static void sparc_cpu_reset_hold(Object *obj) { CPUState *s = CPU(obj); diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index a2bb1038ff..dff88184c9 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -29,6 +29,18 @@ int cpu_mmu_index(CPUTriCoreState *env, bool ifetch) return 0; } +void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + uint32_t new_flags = 0; + *pc = env->PC; + *cs_base = 0; + + new_flags |= FIELD_DP32(new_flags, TB_FLAGS, PRIV, + extract32(env->PSW, 10, 2)); + *flags = new_flags; +} + static inline void set_feature(CPUTriCoreState *env, int feature) { env->features |= 1ULL << feature; diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 7d69cef8cc..dfe0ff5c98 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -44,6 +44,74 @@ int cpu_mmu_index(CPUXtensaState *env, bool ifetch) return xtensa_get_cring(env); } +void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc, + uint64_t *cs_base, uint32_t *flags) +{ + *pc = env->pc; + *cs_base = 0; + *flags = 0; + *flags |= xtensa_get_ring(env); + if (env->sregs[PS] & PS_EXCM) { + *flags |= XTENSA_TBFLAG_EXCM; + } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) { + target_ulong lend_dist = + env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS)); + + /* + * 0 in the csbase_lend field means that there may not be a loopback + * for any instruction that starts inside this page. Any other value + * means that an instruction that ends at this offset from the page + * start may loop back and will need loopback code to be generated. + * + * lend_dist is 0 when LEND points to the start of the page, but + * no instruction that starts inside this page may end at offset 0, + * so it's still correct. + * + * When an instruction ends at a page boundary it may only start in + * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE + * for the TB that contains this instruction. + */ + if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size) { + target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG]; + + *cs_base = lend_dist; + if (lbeg_off < 256) { + *cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT; + } + } + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) && + (env->sregs[LITBASE] & 1)) { + *flags |= XTENSA_TBFLAG_LITBASE; + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) { + if (xtensa_get_cintlevel(env) < env->config->debug_level) { + *flags |= XTENSA_TBFLAG_DEBUG; + } + if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { + *flags |= XTENSA_TBFLAG_ICOUNT; + } + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) { + *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT; + } + if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) && + (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) { + uint32_t windowstart = xtensa_replicate_windowstart(env) >> + (env->sregs[WINDOW_BASE] + 1); + uint32_t w = ctz32(windowstart | 0x8); + + *flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE; + *flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT, + PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT; + } else { + *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT; + } + if (env->yield_needed) { + *flags |= XTENSA_TBFLAG_YIELD; + } +} + static void xtensa_cpu_set_pc(CPUState *cs, vaddr value) { XtensaCPU *cpu = XTENSA_CPU(cs); From patchwork Sun Jan 28 04:41:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767234 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp348302wro; Sat, 27 Jan 2024 20:46:52 -0800 (PST) X-Google-Smtp-Source: AGHT+IF7fxsOju/UTevTAVdm2FCCs6bKuYOJfwSWS1Y0t6LOd0vzJSWtGYiWboUgRGurgdyhhhiO X-Received: by 2002:ae9:f713:0:b0:783:d709:54e3 with SMTP id s19-20020ae9f713000000b00783d70954e3mr2844334qkg.25.1706417212811; Sat, 27 Jan 2024 20:46:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706417212; cv=none; d=google.com; s=arc-20160816; b=CVFphaU1DUxrVHKD5VKcDrYMj31QNSpiaUuhBg5+gupPjLjW7myPa3dXaCLq3iawy4 wTEY/ZqpsBs28iQ3fpVvdZ+yPNI4JIwFeCTrP5VlEwIqKZ34LxqvmnFCuwyzjQVyzNHV hsM+Sp6QJ3HRZ6t9UxkFkxBeSa/i3Tytxo4jq8uJ3W0aA2MBZKuxLd1Ihx42GZObD8CM HVNGuZ0HEKVox3I0H03E7Ncz6hPXfTE63e4cTZc0J+qkdJGxpiTPR5TnZjCa/+f+Iotz E11HZt1/9Cjk/YEfcBC2R31mpc0LXct6zZ0GygHCyUnbeW7VCcohJLn2Cb/8eJoGznqQ 3c/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=b//53eqNBjSFpOfVle7vTtty4ZHIEf38Wv0KnQlUNkk=; fh=l3rThTWYtfg9kQ3pwkdseR7wGfUMT6wsJF5cqMswxYY=; b=sHYv48JGPqnnMoMsu1azg5/oJvQTc7vObeiwbmyZyLB+ngHzbwmDemlZrhSgaGulkv rWdVRaFv2IZL9rWfPBBWmRF0VclAQlUNPEEHaxuzceCuoNTAZNl+URu2F1AtsBEUysHA s2WKW5HJT+liHA8JhJCcul7EUwKZYdJb4c4KVUlBlEdVTfQ0U4BRmHXwlnW6fYUTkiqP BD/RBrSkZqff6vLFHHV2BhrX+kXCoEvTg5CMLKrEq3w4HfM0NQGETnrt9Lp3xiDaperp Evt19pAZkEhg5ITZTnAg7+AYmPcQtCoPrFuwikqfKzfrlJVEDZjP8hvojRVgcx16j5KC 1B9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MmtVTpvt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PATCH 09/33] include/exec: Move PAGE_* macros to common header Date: Sun, 28 Jan 2024 14:41:49 +1000 Message-Id: <20240128044213.316480-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Anton Johansson These don't vary across targets and are used in soon-to-be common code (cputlb.c). Signed-off-by: Anton Johansson Message-Id: <20240119144024.14289-15-anjo@rev.ng> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 24 ------------------------ include/exec/cpu-common.h | 30 ++++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+), 24 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 5340907cfd..edee87d3f4 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -171,34 +171,10 @@ extern const TargetPageBits target_page; #define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE) -/* same as PROT_xxx */ -#define PAGE_READ 0x0001 -#define PAGE_WRITE 0x0002 -#define PAGE_EXEC 0x0004 -#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) -#define PAGE_VALID 0x0008 -/* - * Original state of the write flag (used when tracking self-modifying code) - */ -#define PAGE_WRITE_ORG 0x0010 -/* - * Invalidate the TLB entry immediately, helpful for s390x - * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() - */ -#define PAGE_WRITE_INV 0x0020 -/* For use with page_set_flags: page is being replaced; target_data cleared. */ -#define PAGE_RESET 0x0040 -/* For linux-user, indicates that the page is MAP_ANON. */ -#define PAGE_ANON 0x0080 - #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) /* FIXME: Code that sets/uses this is broken and needs to go away. */ #define PAGE_RESERVED 0x0100 #endif -/* Target-specific bits that will be used via page_get_flags(). */ -#define PAGE_TARGET_1 0x0200 -#define PAGE_TARGET_2 0x0400 - /* * For linux-user, indicates that the page is mapped with the same semantics * in both guest and host. diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 1a8fad9222..ba10351576 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -219,4 +219,34 @@ G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc); G_NORETURN void cpu_loop_exit(CPUState *cpu); G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc); +/* same as PROT_xxx */ +#define PAGE_READ 0x0001 +#define PAGE_WRITE 0x0002 +#define PAGE_EXEC 0x0004 +#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) +#define PAGE_VALID 0x0008 +/* + * Original state of the write flag (used when tracking self-modifying code) + */ +#define PAGE_WRITE_ORG 0x0010 +/* + * Invalidate the TLB entry immediately, helpful for s390x + * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() + */ +#define PAGE_WRITE_INV 0x0020 +/* For use with page_set_flags: page is being replaced; target_data cleared. */ +#define PAGE_RESET 0x0040 +/* For linux-user, indicates that the page is MAP_ANON. */ +#define PAGE_ANON 0x0080 + +/* Target-specific bits that will be used via page_get_flags(). */ +#define PAGE_TARGET_1 0x0200 +#define PAGE_TARGET_2 0x0400 + +/* + * For linux-user, indicates that the page is mapped with the same semantics + * in both guest and host. + */ +#define PAGE_PASSTHROUGH 0x0800 + #endif /* CPU_COMMON_H */ From patchwork Sun Jan 28 04:41:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767217 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp347958wro; Sat, 27 Jan 2024 20:45:00 -0800 (PST) X-Google-Smtp-Source: AGHT+IEdw8+fiu6OwVoEdAXbQ/O8t0Pi+Y4n96KDYpxzntCIe9D8stWbIGF+vFS936gi3zxwkGjN X-Received: by 2002:a05:620a:480d:b0:783:f6c6:35d7 with SMTP id eb13-20020a05620a480d00b00783f6c635d7mr523542qkb.147.1706417100491; Sat, 27 Jan 2024 20:45:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706417100; cv=none; d=google.com; s=arc-20160816; b=jn4fiKQjzbFEMAGm4pBXvwSdjDyyQW9YlMjBL1i/HFIsqsxLlHcsWj6eNGhsN7wzdD YmS7jZmFpJZ6rCtG1C5ul9U0El8tilnNjvDPyI/A5xYpNVCcRZc+aZD4e7PjfpueLvXX uDKnu6fzSjBxDH7cWQvdngnvtpjZquAxAs3dMXsb9lxl5zAvQJwUGfp+2UqACZAeBtuc pznF2I8amRJf/tKHnk8AuyFTQKtyjDoxfd8q51IbNkz4Y4vp5P2zWOj6KI+I3oZZOa50 /hgBmg5dTyRAkri/HW7e0SSENviP1ehceBZ45Or+t/u5pxgMGW1MpLs9FW5xSC5L5y6f xMkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=XtUAEvtZlEFe6xSkMZOBhFgppz0gGYIST8afKDqnszc=; fh=l3rThTWYtfg9kQ3pwkdseR7wGfUMT6wsJF5cqMswxYY=; b=zbxagcTRJl4phjV15gVfRMl0jjZhOODJatTYNUdIBmtBqHCsSugltkGqwsdLcKNTDa B+EH1e+e1Dm0HiWEQUtIO+3KZi8cPrLCFub6t9qwHoIsPo5tnSwTMHUsfP5e9PEWlDFJ ySFrh0DniqgNpUG4gAVqE2hXoM0EWWjUkN944ocAfY1gL6JxkmRyCVgE62Jus6TzJQWd mbnZ8cKwOke2AwTzcBaXCWq0qMigiiK1uB08MAdrF9KL7b3iZuDV12TAymfP3kL2tR/a kRvkiLc2mQ30LWBcf8SzGZaSXFYWIB0CV3eUJ83mn/O28uK+IMfvhN0HnEVZ6GfLzz/8 4BHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=crpLBow+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PATCH 10/33] include/exec: Move cpu_*()/cpu_env() to common header Date: Sun, 28 Jan 2024 14:41:50 +1000 Message-Id: <20240128044213.316480-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Anton Johansson Functions are target independent. Signed-off-by: Anton Johansson Message-Id: <20240119144024.14289-17-anjo@rev.ng> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- include/exec/cpu-all.h | 25 ------------------------- include/exec/cpu-common.h | 26 ++++++++++++++++++++++++++ 2 files changed, 26 insertions(+), 25 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index edee87d3f4..8501a33dbf 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -384,33 +384,8 @@ static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr) #endif /* !CONFIG_USER_ONLY */ -/* accel/tcg/cpu-exec.c */ -int cpu_exec(CPUState *cpu); - /* Validate correct placement of CPUArchState. */ QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) != 0); QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) != sizeof(CPUState)); -/** - * env_archcpu(env) - * @env: The architecture environment - * - * Return the ArchCPU associated with the environment. - */ -static inline ArchCPU *env_archcpu(CPUArchState *env) -{ - return (void *)env - sizeof(CPUState); -} - -/** - * env_cpu(env) - * @env: The architecture environment - * - * Return the CPUState associated with the environment. - */ -static inline CPUState *env_cpu(CPUArchState *env) -{ - return (void *)env - sizeof(CPUState); -} - #endif /* CPU_ALL_H */ diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index ba10351576..7e1a4afad8 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -7,6 +7,7 @@ #ifndef CONFIG_USER_ONLY #include "exec/hwaddr.h" #endif +#include "hw/core/cpu.h" #define EXCP_INTERRUPT 0x10000 /* async interruption */ #define EXCP_HLT 0x10001 /* hlt instruction reached */ @@ -249,4 +250,29 @@ G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc); */ #define PAGE_PASSTHROUGH 0x0800 +/* accel/tcg/cpu-exec.c */ +int cpu_exec(CPUState *cpu); + +/** + * env_archcpu(env) + * @env: The architecture environment + * + * Return the ArchCPU associated with the environment. + */ +static inline ArchCPU *env_archcpu(CPUArchState *env) +{ + return (void *)env - sizeof(CPUState); +} + +/** + * env_cpu(env) + * @env: The architecture environment + * + * Return the CPUState associated with the environment. + */ +static inline CPUState *env_cpu(CPUArchState *env) +{ + return (void *)env - sizeof(CPUState); +} + #endif /* CPU_COMMON_H */ From patchwork Sun Jan 28 04:41:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767231 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp348261wro; Sat, 27 Jan 2024 20:46:31 -0800 (PST) X-Google-Smtp-Source: AGHT+IETkd11mj8md9zNKF6wTjnv2ewx6JGeCEzeTgOxeW6IR8MHYFoDFaINftk57T3gGUhyGw4F X-Received: by 2002:ac8:7d15:0:b0:42a:687c:6029 with SMTP id g21-20020ac87d15000000b0042a687c6029mr2834579qtb.71.1706417190933; Sat, 27 Jan 2024 20:46:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706417190; cv=none; d=google.com; s=arc-20160816; b=tOnAvptCRJ/sXO3+YTcU0cAwiFyNMcuqB9iUFDbvvWY0h6U6HMdES4kifbFGR9sKtL /lArcFS8kwoDq6neplflloYXuqi95BRW9xpcNarOADKXe4biZIoeVNty9IzzElBfcaxa 1Zepy44WNo9rDGqvXOuAJuh3mCpzZRve57kQbsEXaFR3EE5i3qisCDmOxCS2SwSFx/wR 6k/nzSJHAQSpN92QbUPqSbCqYj0pJdLgTBwaRmQ/2PAGempDHE8t84s0p1pgqbhyTv5d 57FEaZuuHR2+irjxg/IuAFqUY89kQN6VPd0T2gppDADtokd6ua79gvTMdkn5xmBUWjRG 34Ig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=0IsJCYKuWrursPA6kPyaSh6Iig/if/7dsXp1H2oDJMs=; fh=l3rThTWYtfg9kQ3pwkdseR7wGfUMT6wsJF5cqMswxYY=; b=0UryTSkMLO9IRAETOSpz8B37A8rm2aU1hpB0JDdO8CjDC/WSdfqV29N/YzBgaP3epO kz/oxRPV3CcSXam1lEpWJSppKeZtFKCMLYcBRtkLKs3uga6/ri5AcpDLQQca5HT9hoZB ypDGfti9gLDG+QHns4WSRZgauG/ZiZn4V9bE5y2/9IyNYpOPhS5mn83SHBb+/qOjuAPo RBKFRr+SmeOfFQ6hCi/gFQkrQ9gBdCLkBlihQ+xT244c/n8XHnPRj7JiXaxAadxp+Znl xOkJRdpyf/oWxxCCjq3rWrpMHQAf2lE50vbEJGJcgDlParpwsZTcFCicekckfZpkQ1U2 2I6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BaOPrRv9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PATCH 11/33] include/hw/core: Move do_interrupt in TCGCPUOps Date: Sun, 28 Jan 2024 14:41:51 +1000 Message-Id: <20240128044213.316480-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Anton Johansson The ifdef out of which it is moved is not quite right: do_interrupt is only needed for system mode. Move it to the top of a different ifdef block, which preserves its position within the structure for that case. Signed-off-by: Anton Johansson Message-Id: <20240119144024.14289-18-anjo@rev.ng> [rth: Split from a larger patch and simplified.] Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 479713a36e..d6fe55d471 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -58,11 +58,6 @@ struct TCGCPUOps { * cpu execution loop (hack for x86 user mode). */ void (*fake_user_interrupt)(CPUState *cpu); -#else - /** - * @do_interrupt: Callback for interrupt handling. - */ - void (*do_interrupt)(CPUState *cpu); #endif /* !CONFIG_USER_ONLY || !TARGET_I386 */ #ifdef CONFIG_USER_ONLY /** @@ -114,6 +109,8 @@ struct TCGCPUOps { void (*record_sigbus)(CPUState *cpu, vaddr addr, MMUAccessType access_type, uintptr_t ra); #else + /** @do_interrupt: Callback for interrupt handling. */ + void (*do_interrupt)(CPUState *cpu); /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); /** From patchwork Sun Jan 28 04:41:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767226 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp348144wro; Sat, 27 Jan 2024 20:45:53 -0800 (PST) X-Google-Smtp-Source: AGHT+IEQerEqGvhhx1IGTnd4SEMvxk09zuZ21TlQdKHR81ZMbitaPheiW7xoDm0VeM82zAO3FiGj X-Received: by 2002:a05:620a:4714:b0:783:c923:309c with SMTP id bs20-20020a05620a471400b00783c923309cmr3635047qkb.13.1706417153114; Sat, 27 Jan 2024 20:45:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706417153; cv=none; d=google.com; s=arc-20160816; b=AraGMevK6snEtn9d9kxHRTOdwdv86vKxJLCaX3jfcW5TvmDkd5wQ/qzy68yJLzD9Vu h33CfKEAx3hcnMFoZ2s5VVQEIIDSS32Bt6PQd3HPH9OZz/AvobcvwafWnUJrhXOnv2Nh HB6UGILd4qobCHg2YBGizXyqhMwNRPKzVuau2E7ZkAl/utFp4GzifU1n43r/FqKbOl1P 7ktucWzGKy8cl2WbovCsz7Gyg79xY4fwgY362BgxyLwjvEA0XRRzx4+QwKZGiTIX1O/g fLo36q5yETrW5PlPsWQ9Qt53zntzG1Cwtf8YjMVEecHBhXtUMSANK+aPn1WOiQ60ISEU OGgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=o1cRBtAgGqadhUih0VNs9If35/tfCXiaB3lrOMREblM=; fh=l3rThTWYtfg9kQ3pwkdseR7wGfUMT6wsJF5cqMswxYY=; b=FmK00IYKFZ1WT8bvGRB4OKizBi39Qqj9s4n4hBP1qpbualNN9OOmrCMNGg7N0dyxM2 U5npgsQik7g+K/WCXR2oRLCUyw4kYuRsTd+pk7SRupTgOQ1BBj14CoOjlieGb3FV7kcZ B7A/++w0OWvT0DVl7Om7hOXzEv0V4Y7nRFO9wKzCUU0woUzvJagX2Uo+6q0xmny+6Mra PiqS4iLEUs4aJzBt8CB+lkSFYEJ347q3ahmlHYia3SHenrJJOdfFUp4k6bCcz04KAjV7 MbS7k6zTe8zRWPSe17q0SQgl+durwmnE1micFDFAIVtv8mxxOlpXqwcVA55aJJSDHpl2 gaRA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kYnh0zd0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PATCH 12/33] include/hw/core: Remove i386 conditional on fake_user_interrupt Date: Sun, 28 Jan 2024 14:41:52 +1000 Message-Id: <20240128044213.316480-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Anton Johansson Always include fake_user_interrupt in user-only build, despite only being used for i386. This will enable cpu-exec.c to be compiled only once. Signed-off-by: Anton Johansson Message-ID: <20240119144024.14289-18-anjo@rev.ng> [rth: Split out of a larger patch; remove TARGET_I386 conditional.] Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index d6fe55d471..3ed279836f 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -50,7 +50,7 @@ struct TCGCPUOps { void (*debug_excp_handler)(CPUState *cpu); #ifdef NEED_CPU_H -#if defined(CONFIG_USER_ONLY) && defined(TARGET_I386) +#ifdef CONFIG_USER_ONLY /** * @fake_user_interrupt: Callback for 'fake exception' handling. * @@ -58,8 +58,7 @@ struct TCGCPUOps { * cpu execution loop (hack for x86 user mode). */ void (*fake_user_interrupt)(CPUState *cpu); -#endif /* !CONFIG_USER_ONLY || !TARGET_I386 */ -#ifdef CONFIG_USER_ONLY + /** * record_sigsegv: * @cpu: cpu context From patchwork Sun Jan 28 04:41:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767221 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp348093wro; Sat, 27 Jan 2024 20:45:35 -0800 (PST) X-Google-Smtp-Source: AGHT+IGLTxM8/SJgRjadYnTRnZegyti14aqkxLBQzJhgQBY6w9/+SPyefrdaG4VlTdObj9SWNRcu X-Received: by 2002:a05:6214:d02:b0:686:ad15:5123 with SMTP id 2-20020a0562140d0200b00686ad155123mr3577726qvh.49.1706417135382; Sat, 27 Jan 2024 20:45:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706417135; cv=none; d=google.com; s=arc-20160816; b=rE4txnQ3DddU5v7pi5Qfaz3xIyg6oaDWk3e1diJt4ScPhMWIVFrcz+Kkdch+vUbKja WQmIP/JwGd1ezzymE1AuAHFoIv+nK9wPfgMeM17dJ9XoV2mM80prafa3umaV4/6wQn0I mLo5z0fdu30KRCbGbZkcHIWqjqKCdySGqcHK3vkkbAMrMqnwZ/He732Le5k+H2Lk59cc TK//5fPqXIOwmUBmpzk3VfxPI9d5GV+q0A5I9WYSEDSE1h9MrXoSh5ks2NNxgwl8OL0w PYACtBE11LfPi7ue5426JUZqUwiKBYPMTrwjnGmiEsTKZACFZQDJF5gvceUBA1clUxsZ nSJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=50eKL1UP4eaaSsdfVAm5gMAL4OibGGuLebFEQUtStnM=; fh=o2XzhdKG+B45MJCghEfnYoypmHvLX2hd4SL6yXeiyXI=; b=1KAMkIGLmD1MlsI0sznEYmpYd22nL9JBS263+wt39ZrxIwgSdpkLDUcVYnuoqrbDp/ Cc2cJfuB66vd3Zddq6AmsXQYiHS/w7uvDrjTsaW1JRfKkbmCwLELjeBdYNdrBgzAWTAn Vj2UKkmfo8JF2/Yi4jFhXJ7vNdLq8hDIYxgROs3RyBFqIwPEebmmg8OG5eLuQAxr3IaV xvf3BlDEZ9QMGZlZn3vrsXFlEkPZM5VFa3xMRh8bguIDp8JpZXt9hnbq1iH44OEvogSw L4ah44KjexCpDernjqKXbjMabesYa4EPlx1mpv3ghi29pbPWgkXnuHFSlGayzyGtaQyv 1DFg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hg3VOZS1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich Subject: [PATCH 13/33] linux-user: Allow gdbstub to ignore page protection Date: Sun, 28 Jan 2024 14:41:53 +1000 Message-Id: <20240128044213.316480-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::82b; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x82b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Ilya Leoshkevich gdbserver ignores page protection by virtue of using /proc/$pid/mem. Teach qemu gdbstub to do this too. This will not work if /proc is not mounted; accept this limitation. One alternative is to temporarily grant the missing PROT_* bit, but this is inherently racy. Another alternative is self-debugging with ptrace(POKE), which will break if QEMU itself is being debugged - a much more severe limitation. Signed-off-by: Ilya Leoshkevich Reviewed-by: Richard Henderson Message-Id: <20240109230808.583012-2-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- cpu-target.c | 76 +++++++++++++++++++++++++++++++++++++++++----------- 1 file changed, 61 insertions(+), 15 deletions(-) diff --git a/cpu-target.c b/cpu-target.c index f6e07c3deb..c4e2169ab1 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -382,6 +382,9 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, vaddr l, page; void * p; uint8_t *buf = ptr; + ssize_t written; + int ret = -1; + int fd = -1; while (len > 0) { page = addr & TARGET_PAGE_MASK; @@ -389,30 +392,73 @@ int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, if (l > len) l = len; flags = page_get_flags(page); - if (!(flags & PAGE_VALID)) - return -1; + if (!(flags & PAGE_VALID)) { + goto out_close; + } if (is_write) { - if (!(flags & PAGE_WRITE)) - return -1; + if (flags & PAGE_WRITE) { + /* XXX: this code should not depend on lock_user */ + p = lock_user(VERIFY_WRITE, addr, l, 0); + if (!p) { + goto out_close; + } + memcpy(p, buf, l); + unlock_user(p, addr, l); + } else { + /* Bypass the host page protection using ptrace. */ + if (fd == -1) { + fd = open("/proc/self/mem", O_WRONLY); + if (fd == -1) { + goto out; + } + } + /* + * If there is a TranslationBlock and we weren't bypassing the + * host page protection, the memcpy() above would SEGV, + * ultimately leading to page_unprotect(). So invalidate the + * translations manually. Both invalidation and pwrite() must + * be under mmap_lock() in order to prevent the creation of + * another TranslationBlock in between. + */ + mmap_lock(); + tb_invalidate_phys_range(addr, addr + l - 1); + written = pwrite(fd, buf, l, (off_t)g2h_untagged(addr)); + mmap_unlock(); + if (written != l) { + goto out_close; + } + } + } else if (flags & PAGE_READ) { /* XXX: this code should not depend on lock_user */ - if (!(p = lock_user(VERIFY_WRITE, addr, l, 0))) - return -1; - memcpy(p, buf, l); - unlock_user(p, addr, l); - } else { - if (!(flags & PAGE_READ)) - return -1; - /* XXX: this code should not depend on lock_user */ - if (!(p = lock_user(VERIFY_READ, addr, l, 1))) - return -1; + p = lock_user(VERIFY_READ, addr, l, 1); + if (!p) { + goto out_close; + } memcpy(buf, p, l); unlock_user(p, addr, 0); + } else { + /* Bypass the host page protection using ptrace. */ + if (fd == -1) { + fd = open("/proc/self/mem", O_RDONLY); + if (fd == -1) { + goto out; + } + } + if (pread(fd, buf, l, (off_t)g2h_untagged(addr)) != l) { + goto out_close; + } } len -= l; buf += l; addr += l; } - return 0; + ret = 0; +out_close: + if (fd != -1) { + close(fd); + } +out: + return ret; } #endif From patchwork Sun Jan 28 04:41:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767214 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp347907wro; Sat, 27 Jan 2024 20:44:44 -0800 (PST) X-Google-Smtp-Source: AGHT+IH7wvVnmFQNJp0zWtJlPV2M9whMPlKHAxi2mdFYmVogCk95nrEy+zWeSR5vnw1RsdoPe8H3 X-Received: by 2002:a05:620a:c06:b0:783:320b:cbeb with SMTP id l6-20020a05620a0c0600b00783320bcbebmr2307603qki.120.1706417083801; Sat, 27 Jan 2024 20:44:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706417083; cv=none; d=google.com; s=arc-20160816; b=JX/nP1sFrvBVQoayAawh+ZJ2jZteAwp1MyzLk4DgNSxtcy4UsZuiKkmUI7oXC46ah5 Hot4FNrcXqgDpih86HRkHdmJUPMgX+YxH0y0ePR3iYbeCf/YtikKboFloolfLkYKmfMS VvQBXZHktOznAdzldPdYGicNE53n+dveKgWsPattLA2KFbAYLuU8wb3OA9PEl8NJcjjt oDdVBsXtcQVwlpcytGQRNTD8yNCE7E4XoTevkF4Ys3cPa8KZMgLAxFch+TecN50GL9lP 6syNNj4l0n2MvLBS2Nh7CMHU/1xdl5oCGtvbdOXjNJ5Fn/dN330Kg2Ctt+mBY8AuzqQt sq8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=n3i8WIPnfJe6OJ/KMGjZPX6qT+eI0MPf6OW8gP6VkEI=; fh=o2XzhdKG+B45MJCghEfnYoypmHvLX2hd4SL6yXeiyXI=; b=iNeHBFITNTbGpzvdQKKYKHz0LyglAGfiPVnxw6ZjQ6fGLzrtm/+a0Ay0qcO68dDcwR RuigwyH/qHAlFAPf17ugzJeG/UGBTB4ZXGlNhb/IqJnI99CvWeipeUpQ7hXnci6t3W1H rlHLIl/ZvT2IRalti9WdUrV36HiP0b7ejiUoNQkdwnZsiEK53On/8yeiElnwfohkqpYp jZxW18Re92Lw+GggnG64rEMifPVTdvBJDOzF+p9ce42E7vCq605cH3lGr4qW/q0x/ELu r5UMPeIbVAnq+DepMiR4opdlIVK4vG6AgTdHYdhPuTmgN9thpTkcPMoYD26kwld0Xln6 v3TA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Eac12R1P; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich Subject: [PATCH 14/33] tests/tcg: Factor out gdbstub test functions Date: Sun, 28 Jan 2024 14:41:54 +1000 Message-Id: <20240128044213.316480-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Ilya Leoshkevich Both the report() function as well as the initial gdbstub test sequence are copy-pasted into ~10 files with slight modifications. This indicates that they are indeed generic, so factor them out. While at it, add a few newlines to make the formatting closer to PEP-8. Signed-off-by: Ilya Leoshkevich Message-Id: <20240109230808.583012-3-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- tests/guest-debug/run-test.py | 7 ++- tests/guest-debug/test_gdbstub.py | 56 +++++++++++++++++++ tests/tcg/aarch64/gdbstub/test-sve-ioctl.py | 34 +---------- tests/tcg/aarch64/gdbstub/test-sve.py | 33 +---------- tests/tcg/multiarch/gdbstub/interrupt.py | 47 ++-------------- tests/tcg/multiarch/gdbstub/memory.py | 39 +------------ tests/tcg/multiarch/gdbstub/registers.py | 41 ++------------ tests/tcg/multiarch/gdbstub/sha1.py | 38 ++----------- .../multiarch/gdbstub/test-proc-mappings.py | 39 +------------ .../multiarch/gdbstub/test-qxfer-auxv-read.py | 37 +----------- .../gdbstub/test-thread-breakpoint.py | 37 +----------- tests/tcg/s390x/gdbstub/test-signals-s390x.py | 42 +------------- tests/tcg/s390x/gdbstub/test-svc.py | 39 +------------ 13 files changed, 94 insertions(+), 395 deletions(-) create mode 100644 tests/guest-debug/test_gdbstub.py diff --git a/tests/guest-debug/run-test.py b/tests/guest-debug/run-test.py index b13b27d4b1..368ff8a890 100755 --- a/tests/guest-debug/run-test.py +++ b/tests/guest-debug/run-test.py @@ -97,7 +97,12 @@ def log(output, msg): sleep(1) log(output, "GDB CMD: %s" % (gdb_cmd)) - result = subprocess.call(gdb_cmd, shell=True, stdout=output, stderr=stderr) + gdb_env = dict(os.environ) + gdb_pythonpath = gdb_env.get("PYTHONPATH", "").split(os.pathsep) + gdb_pythonpath.append(os.path.dirname(os.path.realpath(__file__))) + gdb_env["PYTHONPATH"] = os.pathsep.join(gdb_pythonpath) + result = subprocess.call(gdb_cmd, shell=True, stdout=output, stderr=stderr, + env=gdb_env) # A result of greater than 128 indicates a fatal signal (likely a # crash due to gdb internal failure). That's a problem for GDB and diff --git a/tests/guest-debug/test_gdbstub.py b/tests/guest-debug/test_gdbstub.py new file mode 100644 index 0000000000..1bc4ed131f --- /dev/null +++ b/tests/guest-debug/test_gdbstub.py @@ -0,0 +1,56 @@ +"""Helper functions for gdbstub testing + +""" +from __future__ import print_function +import gdb +import sys + +fail_count = 0 + + +def report(cond, msg): + """Report success/fail of a test""" + if cond: + print("PASS: {}".format(msg)) + else: + print("FAIL: {}".format(msg)) + global fail_count + fail_count += 1 + + +def main(test, expected_arch=None): + """Run a test function + + This runs as the script it sourced (via -x, via run-test.py).""" + try: + inferior = gdb.selected_inferior() + arch = inferior.architecture() + print("ATTACHED: {}".format(arch)) + if expected_arch is not None: + report(arch.name() == expected_arch, + "connected to {}".format(expected_arch)) + except (gdb.error, AttributeError): + print("SKIP: not connected") + exit(0) + + if gdb.parse_and_eval("$pc") == 0: + print("SKIP: PC not set") + exit(0) + + try: + test() + except: + print("GDB Exception: {}".format(sys.exc_info()[0])) + global fail_count + fail_count += 1 + import code + code.InteractiveConsole(locals=globals()).interact() + raise + + try: + gdb.execute("kill") + except gdb.error: + pass + + print("All tests complete: %d failures".format(fail_count)) + exit(fail_count) diff --git a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py index ee8d467e59..a78a3a2514 100644 --- a/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py +++ b/tests/tcg/aarch64/gdbstub/test-sve-ioctl.py @@ -8,19 +8,10 @@ # import gdb -import sys +from test_gdbstub import main, report initial_vlen = 0 -failcount = 0 -def report(cond, msg): - "Report success/fail of test" - if cond: - print ("PASS: %s" % (msg)) - else: - print ("FAIL: %s" % (msg)) - global failcount - failcount += 1 class TestBreakpoint(gdb.Breakpoint): def __init__(self, sym_name="__sve_ld_done"): @@ -64,26 +55,5 @@ def run_test(): gdb.execute("c") -# -# This runs as the script it sourced (via -x, via run-test.py) -# -try: - inferior = gdb.selected_inferior() - arch = inferior.architecture() - report(arch.name() == "aarch64", "connected to aarch64") -except (gdb.error, AttributeError): - print("SKIPPING (not connected)", file=sys.stderr) - exit(0) -try: - # Run the actual tests - run_test() -except: - print ("GDB Exception: %s" % (sys.exc_info()[0])) - failcount += 1 - import code - code.InteractiveConsole(locals=globals()).interact() - raise - -print("All tests complete: %d failures" % failcount) -exit(failcount) +main(run_test, expected_arch="aarch64") diff --git a/tests/tcg/aarch64/gdbstub/test-sve.py b/tests/tcg/aarch64/gdbstub/test-sve.py index afd8ece98d..84cdcd4a32 100644 --- a/tests/tcg/aarch64/gdbstub/test-sve.py +++ b/tests/tcg/aarch64/gdbstub/test-sve.py @@ -6,20 +6,10 @@ # import gdb -import sys +from test_gdbstub import main, report MAGIC = 0xDEADBEEF -failcount = 0 - -def report(cond, msg): - "Report success/fail of test" - if cond: - print ("PASS: %s" % (msg)) - else: - print ("FAIL: %s" % (msg)) - global failcount - failcount += 1 def run_test(): "Run through the tests one by one" @@ -54,24 +44,5 @@ def run_test(): report(str(v.type) == "uint64_t", "size of %s" % (reg)) report(int(v) == MAGIC, "%s is 0x%x" % (reg, MAGIC)) -# -# This runs as the script it sourced (via -x, via run-test.py) -# -try: - inferior = gdb.selected_inferior() - arch = inferior.architecture() - report(arch.name() == "aarch64", "connected to aarch64") -except (gdb.error, AttributeError): - print("SKIPPING (not connected)", file=sys.stderr) - exit(0) -try: - # Run the actual tests - run_test() -except: - print ("GDB Exception: %s" % (sys.exc_info()[0])) - failcount += 1 - -print("All tests complete: %d failures" % failcount) - -exit(failcount) +main(run_test, expected_arch="aarch64") diff --git a/tests/tcg/multiarch/gdbstub/interrupt.py b/tests/tcg/multiarch/gdbstub/interrupt.py index c016e7afbb..90a45b5140 100644 --- a/tests/tcg/multiarch/gdbstub/interrupt.py +++ b/tests/tcg/multiarch/gdbstub/interrupt.py @@ -8,19 +8,7 @@ # import gdb -import sys - -failcount = 0 - - -def report(cond, msg): - "Report success/fail of test" - if cond: - print("PASS: %s" % (msg)) - else: - print("FAIL: %s" % (msg)) - global failcount - failcount += 1 +from test_gdbstub import main, report def check_interrupt(thread): @@ -59,6 +47,9 @@ def run_test(): Test if interrupting the code always lands us on the same thread when running with scheduler-lock enabled. """ + if len(gdb.selected_inferior().threads()) == 1: + print("SKIP: set to run on a single thread") + exit(0) gdb.execute("set scheduler-locking on") for thread in gdb.selected_inferior().threads(): @@ -66,32 +57,4 @@ def run_test(): "thread %d resumes correctly on interrupt" % thread.num) -# -# This runs as the script it sourced (via -x, via run-test.py) -# -try: - inferior = gdb.selected_inferior() - arch = inferior.architecture() - print("ATTACHED: %s" % arch.name()) -except (gdb.error, AttributeError): - print("SKIPPING (not connected)", file=sys.stderr) - exit(0) - -if gdb.parse_and_eval('$pc') == 0: - print("SKIP: PC not set") - exit(0) -if len(gdb.selected_inferior().threads()) == 1: - print("SKIP: set to run on a single thread") - exit(0) - -try: - # Run the actual tests - run_test() -except (gdb.error): - print("GDB Exception: %s" % (sys.exc_info()[0])) - failcount += 1 - pass - -# Finally kill the inferior and exit gdb with a count of failures -gdb.execute("kill") -exit(failcount) +main(run_test) diff --git a/tests/tcg/multiarch/gdbstub/memory.py b/tests/tcg/multiarch/gdbstub/memory.py index fb1d06b7bb..532b92e7fb 100644 --- a/tests/tcg/multiarch/gdbstub/memory.py +++ b/tests/tcg/multiarch/gdbstub/memory.py @@ -9,18 +9,7 @@ import gdb import sys - -failcount = 0 - - -def report(cond, msg): - "Report success/fail of test" - if cond: - print("PASS: %s" % (msg)) - else: - print("FAIL: %s" % (msg)) - global failcount - failcount += 1 +from test_gdbstub import main, report def check_step(): @@ -99,29 +88,5 @@ def run_test(): report(cbp.hit_count == 0, "didn't reach backstop") -# -# This runs as the script it sourced (via -x, via run-test.py) -# -try: - inferior = gdb.selected_inferior() - arch = inferior.architecture() - print("ATTACHED: %s" % arch.name()) -except (gdb.error, AttributeError): - print("SKIPPING (not connected)", file=sys.stderr) - exit(0) -if gdb.parse_and_eval('$pc') == 0: - print("SKIP: PC not set") - exit(0) - -try: - # Run the actual tests - run_test() -except (gdb.error): - print("GDB Exception: %s" % (sys.exc_info()[0])) - failcount += 1 - pass - -# Finally kill the inferior and exit gdb with a count of failures -gdb.execute("kill") -exit(failcount) +main(run_test) diff --git a/tests/tcg/multiarch/gdbstub/registers.py b/tests/tcg/multiarch/gdbstub/registers.py index 688c061107..b3d13cb077 100644 --- a/tests/tcg/multiarch/gdbstub/registers.py +++ b/tests/tcg/multiarch/gdbstub/registers.py @@ -7,20 +7,11 @@ # SPDX-License-Identifier: GPL-2.0-or-later import gdb -import sys import xml.etree.ElementTree as ET +from test_gdbstub import main, report + initial_vlen = 0 -failcount = 0 - -def report(cond, msg): - "Report success/fail of test." - if cond: - print("PASS: %s" % (msg)) - else: - print("FAIL: %s" % (msg)) - global failcount - failcount += 1 def fetch_xml_regmap(): @@ -75,6 +66,7 @@ def fetch_xml_regmap(): return reg_map + def get_register_by_regnum(reg_map, regnum): """ Helper to find a register from the map via its XML regnum @@ -84,6 +76,7 @@ def get_register_by_regnum(reg_map, regnum): return entry return None + def crosscheck_remote_xml(reg_map): """ Cross-check the list of remote-registers with the XML info. @@ -144,6 +137,7 @@ def crosscheck_remote_xml(reg_map): elif "seen" not in x_reg: print(f"{x_reg} wasn't seen in remote-registers") + def initial_register_read(reg_map): """ Do an initial read of all registers that we know gdb cares about @@ -214,27 +208,4 @@ def run_test(): complete_and_diff(reg_map) -# -# This runs as the script it sourced (via -x, via run-test.py) -# -try: - inferior = gdb.selected_inferior() - arch = inferior.architecture() - print("ATTACHED: %s" % arch.name()) -except (gdb.error, AttributeError): - print("SKIPPING (not connected)", file=sys.stderr) - exit(0) - -if gdb.parse_and_eval('$pc') == 0: - print("SKIP: PC not set") - exit(0) - -try: - run_test() -except (gdb.error): - print ("GDB Exception: %s" % (sys.exc_info()[0])) - failcount += 1 - pass - -print("All tests complete: %d failures" % failcount) -exit(failcount) +main(run_test) diff --git a/tests/tcg/multiarch/gdbstub/sha1.py b/tests/tcg/multiarch/gdbstub/sha1.py index 416728415f..1ce711a402 100644 --- a/tests/tcg/multiarch/gdbstub/sha1.py +++ b/tests/tcg/multiarch/gdbstub/sha1.py @@ -7,19 +7,11 @@ # import gdb -import sys +from test_gdbstub import main, report + initial_vlen = 0 -failcount = 0 -def report(cond, msg): - "Report success/fail of test" - if cond: - print("PASS: %s" % (msg)) - else: - print("FAIL: %s" % (msg)) - global failcount - failcount += 1 def check_break(sym_name): "Setup breakpoint, continue and check we stopped." @@ -35,6 +27,7 @@ def check_break(sym_name): bp.delete() + def run_test(): "Run through the tests one by one" @@ -57,28 +50,5 @@ def run_test(): # finally check we don't barf inspecting registers gdb.execute("info registers") -# -# This runs as the script it sourced (via -x, via run-test.py) -# -try: - inferior = gdb.selected_inferior() - arch = inferior.architecture() - print("ATTACHED: %s" % arch.name()) -except (gdb.error, AttributeError): - print("SKIPPING (not connected)", file=sys.stderr) - exit(0) -if gdb.parse_and_eval('$pc') == 0: - print("SKIP: PC not set") - exit(0) - -try: - # Run the actual tests - run_test() -except (gdb.error): - print ("GDB Exception: %s" % (sys.exc_info()[0])) - failcount += 1 - pass - -print("All tests complete: %d failures" % failcount) -exit(failcount) +main(run_test) diff --git a/tests/tcg/multiarch/gdbstub/test-proc-mappings.py b/tests/tcg/multiarch/gdbstub/test-proc-mappings.py index 04ec61d219..564613fabf 100644 --- a/tests/tcg/multiarch/gdbstub/test-proc-mappings.py +++ b/tests/tcg/multiarch/gdbstub/test-proc-mappings.py @@ -3,20 +3,7 @@ This runs as a sourced script (via -x, via run-test.py).""" from __future__ import print_function import gdb -import sys - - -n_failures = 0 - - -def report(cond, msg): - """Report success/fail of a test""" - if cond: - print("PASS: {}".format(msg)) - else: - print("FAIL: {}".format(msg)) - global n_failures - n_failures += 1 +from test_gdbstub import main, report def run_test(): @@ -37,26 +24,4 @@ def run_test(): # report("/sha1" in mappings, "Found the test binary name in the mappings") -def main(): - """Prepare the environment and run through the tests""" - try: - inferior = gdb.selected_inferior() - print("ATTACHED: {}".format(inferior.architecture().name())) - except (gdb.error, AttributeError): - print("SKIPPING (not connected)") - exit(0) - - if gdb.parse_and_eval('$pc') == 0: - print("SKIP: PC not set") - exit(0) - - try: - # Run the actual tests - run_test() - except gdb.error: - report(False, "GDB Exception: {}".format(sys.exc_info()[0])) - print("All tests complete: %d failures" % n_failures) - exit(n_failures) - - -main() +main(run_test) diff --git a/tests/tcg/multiarch/gdbstub/test-qxfer-auxv-read.py b/tests/tcg/multiarch/gdbstub/test-qxfer-auxv-read.py index 926fa962b7..00c26ab4a9 100644 --- a/tests/tcg/multiarch/gdbstub/test-qxfer-auxv-read.py +++ b/tests/tcg/multiarch/gdbstub/test-qxfer-auxv-read.py @@ -6,18 +6,8 @@ # import gdb -import sys +from test_gdbstub import main, report -failcount = 0 - -def report(cond, msg): - "Report success/fail of test" - if cond: - print ("PASS: %s" % (msg)) - else: - print ("FAIL: %s" % (msg)) - global failcount - failcount += 1 def run_test(): "Run through the tests one by one" @@ -26,28 +16,5 @@ def run_test(): report(isinstance(auxv, str), "Fetched auxv from inferior") report(auxv.find("sha1"), "Found test binary name in auxv") -# -# This runs as the script it sourced (via -x, via run-test.py) -# -try: - inferior = gdb.selected_inferior() - arch = inferior.architecture() - print("ATTACHED: %s" % arch.name()) -except (gdb.error, AttributeError): - print("SKIPPING (not connected)", file=sys.stderr) - exit(0) -if gdb.parse_and_eval('$pc') == 0: - print("SKIP: PC not set") - exit(0) - -try: - # Run the actual tests - run_test() -except (gdb.error): - print ("GDB Exception: %s" % (sys.exc_info()[0])) - failcount += 1 - pass - -print("All tests complete: %d failures" % failcount) -exit(failcount) +main(run_test) diff --git a/tests/tcg/multiarch/gdbstub/test-thread-breakpoint.py b/tests/tcg/multiarch/gdbstub/test-thread-breakpoint.py index e57d2a8db8..4d6b6b9fbe 100644 --- a/tests/tcg/multiarch/gdbstub/test-thread-breakpoint.py +++ b/tests/tcg/multiarch/gdbstub/test-thread-breakpoint.py @@ -6,18 +6,8 @@ # import gdb -import sys +from test_gdbstub import main, report -failcount = 0 - -def report(cond, msg): - "Report success/fail of test" - if cond: - print ("PASS: %s" % (msg)) - else: - print ("FAIL: %s" % (msg)) - global failcount - failcount += 1 def run_test(): "Run through the tests one by one" @@ -29,28 +19,5 @@ def run_test(): frame = gdb.selected_frame() report(str(frame.function()) == "thread1_func", "break @ %s"%frame) -# -# This runs as the script it sourced (via -x, via run-test.py) -# -try: - inferior = gdb.selected_inferior() - arch = inferior.architecture() - print("ATTACHED: %s" % arch.name()) -except (gdb.error, AttributeError): - print("SKIPPING (not connected)", file=sys.stderr) - exit(0) -if gdb.parse_and_eval('$pc') == 0: - print("SKIP: PC not set") - exit(0) - -try: - # Run the actual tests - run_test() -except (gdb.error): - print ("GDB Exception: %s" % (sys.exc_info()[0])) - failcount += 1 - pass - -print("All tests complete: %d failures" % failcount) -exit(failcount) +main(run_test) diff --git a/tests/tcg/s390x/gdbstub/test-signals-s390x.py b/tests/tcg/s390x/gdbstub/test-signals-s390x.py index ca2bbc0b03..b6b7b39fc4 100644 --- a/tests/tcg/s390x/gdbstub/test-signals-s390x.py +++ b/tests/tcg/s390x/gdbstub/test-signals-s390x.py @@ -7,19 +7,7 @@ # import gdb -import sys - -failcount = 0 - - -def report(cond, msg): - """Report success/fail of test""" - if cond: - print("PASS: %s" % (msg)) - else: - print("FAIL: %s" % (msg)) - global failcount - failcount += 1 +from test_gdbstub import main, report def run_test(): @@ -42,31 +30,7 @@ def run_test(): gdb.Breakpoint("_exit") gdb.execute("c") status = int(gdb.parse_and_eval("$r2")) - report(status == 0, "status == 0"); + report(status == 0, "status == 0") -# -# This runs as the script it sourced (via -x, via run-test.py) -# -try: - inferior = gdb.selected_inferior() - arch = inferior.architecture() - print("ATTACHED: %s" % arch.name()) -except (gdb.error, AttributeError): - print("SKIPPING (not connected)", file=sys.stderr) - exit(0) - -if gdb.parse_and_eval("$pc") == 0: - print("SKIP: PC not set") - exit(0) - -try: - # Run the actual tests - run_test() -except (gdb.error): - print("GDB Exception: %s" % (sys.exc_info()[0])) - failcount += 1 - pass - -print("All tests complete: %d failures" % failcount) -exit(failcount) +main(run_test) diff --git a/tests/tcg/s390x/gdbstub/test-svc.py b/tests/tcg/s390x/gdbstub/test-svc.py index 804705fede..17210b4e02 100644 --- a/tests/tcg/s390x/gdbstub/test-svc.py +++ b/tests/tcg/s390x/gdbstub/test-svc.py @@ -3,20 +3,7 @@ This runs as a sourced script (via -x, via run-test.py).""" from __future__ import print_function import gdb -import sys - - -n_failures = 0 - - -def report(cond, msg): - """Report success/fail of a test""" - if cond: - print("PASS: {}".format(msg)) - else: - print("FAIL: {}".format(msg)) - global n_failures - n_failures += 1 +from test_gdbstub import main, report def run_test(): @@ -35,26 +22,4 @@ def run_test(): gdb.execute("si") -def main(): - """Prepare the environment and run through the tests""" - try: - inferior = gdb.selected_inferior() - print("ATTACHED: {}".format(inferior.architecture().name())) - except (gdb.error, AttributeError): - print("SKIPPING (not connected)") - exit(0) - - if gdb.parse_and_eval('$pc') == 0: - print("SKIP: PC not set") - exit(0) - - try: - # Run the actual tests - run_test() - except gdb.error: - report(False, "GDB Exception: {}".format(sys.exc_info()[0])) - print("All tests complete: %d failures" % n_failures) - exit(n_failures) - - -main() +main(run_test) From patchwork Sun Jan 28 04:41:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767232 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp348270wro; Sat, 27 Jan 2024 20:46:34 -0800 (PST) X-Google-Smtp-Source: AGHT+IHdZDo4tkMxWelH3o86C8wROt5vGO/3aI+r1iiU8N2/WkLMD3+z17fZbafceWL4NzYUhphN X-Received: by 2002:ad4:5761:0:b0:685:2971:cf39 with SMTP id r1-20020ad45761000000b006852971cf39mr3261908qvx.30.1706417194273; Sat, 27 Jan 2024 20:46:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706417194; cv=none; d=google.com; s=arc-20160816; b=mw1lx/9JvEt4KHFzL5bqL/rMFWPzk1+91orBGwq6ago9hqujqR4yvWO28wJqX86RRk zCT8MnDPrUuSK2fkhMZgh9imM1I+4JCAu4No72pvxxGicJw1nUWCMOYtOEKZmjqLPByW g7eTsfX9V22Qo9pP5ZKbFa0KVJGMJo9LfZgjF4blfiGpGxrGkygNOvG/MmdrrUb+Lic/ qh+OJoLRSUb67WwMPZzpxDyxQapce264CcJZa1Q7GLCjKUEkuECMX8UrJ0YTQFlaTlCm mShdEJ14Gbs3qPMKT2QLNAeHHtyRol4nk3kw0+xUyCylpj6v40Vmafiq+g6pLl1SakBt atRg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=s84QwsvJ4FUEfSYgoD2xLjKpOUhTXQHsXWR0Okjxs+g=; fh=o2XzhdKG+B45MJCghEfnYoypmHvLX2hd4SL6yXeiyXI=; b=qsqj5ihxwN1IP2/nQt8f3A/1Od7KrAWIKryudpNlpPOxg2DIgcfY5c7k9KwBd7WnVV 5VrK5SiEfs1gROmcVlpSV5Bpr4PpZj/cOwwNWN1p0toKiDYq9P89o8lvjudGASEZPCrK BhxDqOcs933mzztjtSS00RM832c9fTNskKnf4mzayMwj1KgGwkV+3HNmuG9gb7pDBCJT kq6Pua043xTZdq2L8FEXNF/nrfk6+/T8t1YhYkf1lLiFJg1yXMGk9xByYL8g07xLrHmq bQPGXBA7t6xxdSfFpgKVSOnS4X6EaUy5ROPcMs+C02MaMYqossiGBwnR2TGDVBwwvgBi gp2g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="esJ/DG5Q"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich Subject: [PATCH 15/33] tests/tcg: Add the PROT_NONE gdbstub test Date: Sun, 28 Jan 2024 14:41:55 +1000 Message-Id: <20240128044213.316480-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::333; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Ilya Leoshkevich Make sure that qemu gdbstub, like gdbserver, allows reading from and writing to PROT_NONE pages. Signed-off-by: Ilya Leoshkevich Message-Id: <20240109230808.583012-4-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- tests/tcg/multiarch/prot-none.c | 40 ++++++++++++++++++++++++ tests/tcg/multiarch/Makefile.target | 9 +++++- tests/tcg/multiarch/gdbstub/prot-none.py | 22 +++++++++++++ 3 files changed, 70 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/multiarch/prot-none.c create mode 100644 tests/tcg/multiarch/gdbstub/prot-none.py diff --git a/tests/tcg/multiarch/prot-none.c b/tests/tcg/multiarch/prot-none.c new file mode 100644 index 0000000000..dc56aadb3c --- /dev/null +++ b/tests/tcg/multiarch/prot-none.c @@ -0,0 +1,40 @@ +/* + * Test that GDB can access PROT_NONE pages. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include +#include +#include +#include +#include + +void break_here(void *q) +{ +} + +int main(void) +{ + long pagesize = sysconf(_SC_PAGESIZE); + void *p, *q; + int err; + + p = mmap(NULL, pagesize * 2, PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + assert(p != MAP_FAILED); + q = p + pagesize - 1; + strcpy(q, "42"); + + err = mprotect(p, pagesize * 2, PROT_NONE); + assert(err == 0); + + break_here(q); + + err = mprotect(p, pagesize * 2, PROT_READ); + assert(err == 0); + if (getenv("PROT_NONE_PY")) { + assert(strcmp(q, "24") == 0); + } + + return EXIT_SUCCESS; +} diff --git a/tests/tcg/multiarch/Makefile.target b/tests/tcg/multiarch/Makefile.target index d31ba8d6ae..315a2e1358 100644 --- a/tests/tcg/multiarch/Makefile.target +++ b/tests/tcg/multiarch/Makefile.target @@ -101,13 +101,20 @@ run-gdbstub-registers: sha512 --bin $< --test $(MULTIARCH_SRC)/gdbstub/registers.py, \ checking register enumeration) +run-gdbstub-prot-none: prot-none + $(call run-test, $@, env PROT_NONE_PY=1 $(GDB_SCRIPT) \ + --gdb $(GDB) \ + --qemu $(QEMU) --qargs "$(QEMU_OPTS)" \ + --bin $< --test $(MULTIARCH_SRC)/gdbstub/prot-none.py, \ + accessing PROT_NONE memory) + else run-gdbstub-%: $(call skip-test, "gdbstub test $*", "need working gdb with $(patsubst -%,,$(TARGET_NAME)) support") endif EXTRA_RUNS += run-gdbstub-sha1 run-gdbstub-qxfer-auxv-read \ run-gdbstub-proc-mappings run-gdbstub-thread-breakpoint \ - run-gdbstub-registers + run-gdbstub-registers run-gdbstub-prot-none # ARM Compatible Semi Hosting Tests # diff --git a/tests/tcg/multiarch/gdbstub/prot-none.py b/tests/tcg/multiarch/gdbstub/prot-none.py new file mode 100644 index 0000000000..f1f1dd82cb --- /dev/null +++ b/tests/tcg/multiarch/gdbstub/prot-none.py @@ -0,0 +1,22 @@ +"""Test that GDB can access PROT_NONE pages. + +This runs as a sourced script (via -x, via run-test.py). + +SPDX-License-Identifier: GPL-2.0-or-later +""" +from test_gdbstub import main, report + + +def run_test(): + """Run through the tests one by one""" + gdb.Breakpoint("break_here") + gdb.execute("continue") + val = gdb.parse_and_eval("*(char[2] *)q").string() + report(val == "42", "{} == 42".format(val)) + gdb.execute("set *(char[3] *)q = \"24\"") + gdb.execute("continue") + exitcode = int(gdb.parse_and_eval("$_exitcode")) + report(exitcode == 0, "{} == 0".format(exitcode)) + + +main(run_test) From patchwork Sun Jan 28 04:41:56 2024 Content-Type: text/plain; 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 16/33] accel/tcg/cpu-exec: Use RCU_READ_LOCK_GUARD Date: Sun, 28 Jan 2024 14:41:56 +1000 Message-Id: <20240128044213.316480-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Replace the manual rcu_read_(un)lock calls in cpu_exec(). Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20240124074201.8239-2-philmd@linaro.org> [rth: Use RCU_READ_LOCK_GUARD not WITH_RCU_READ_LOCK_GUARD] Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- accel/tcg/cpu-exec.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 40c268bfa1..950dad63cb 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -1050,7 +1050,7 @@ int cpu_exec(CPUState *cpu) return EXCP_HALTED; } - rcu_read_lock(); + RCU_READ_LOCK_GUARD(); cpu_exec_enter(cpu); /* @@ -1064,8 +1064,6 @@ int cpu_exec(CPUState *cpu) ret = cpu_exec_setjmp(cpu, &sc); cpu_exec_exit(cpu); - rcu_read_unlock(); - return ret; } From patchwork Sun Jan 28 04:41:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767238 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp348415wro; Sat, 27 Jan 2024 20:47:29 -0800 (PST) X-Google-Smtp-Source: AGHT+IHNuzNhgkMXIMjBi7yKjcm7syIonUC2WHp4YWtT0m+8YulqcC9yQLSIL+j7oE2LFNlo8Ygp X-Received: by 2002:a05:622a:1906:b0:42a:7092:c19b with SMTP id w6-20020a05622a190600b0042a7092c19bmr3871900qtc.83.1706417249062; Sat, 27 Jan 2024 20:47:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706417249; cv=none; d=google.com; s=arc-20160816; b=p23PuK/OrtGSO1pHB5TOnQg8EUstEvmEoxCwDj123tYiZBhexv8DxpcfFgsL6q4gPm Y2MEmGebH7YUq4SuLdoEpKenf7pd0P/zPLIHV9Nznb1Adn/HKbe5PzD3/739twAnphTJ mWVfZSf5H0le3SUwDMztQlyoKxIbi41dIudELRLf2TUGwuvg1Bb/xRTUqywVgKwc3s/I kuTwGeiVgy6p1sumVwRtREcXsq9R6j3W9b3BkFni0ftu0XGURBkzK/ChKDRE3VEl2Jqz HiWo/dnuACYhnO+71kCFcKnRyIox2bChxXMWEMg9gjP2/2YoOnehpSxj2ShQAnuz9jBR 29ow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=5Gt1CNQckx8yO7WR3bedyoAfBxjm8E850nOtIhoFZIA=; fh=ZlbSsaokz6j5XPQU+IhUbFpcK1AM7Y5orhlncwoVMh8=; b=ifU4cfL3RLi2dkuIOHo+pQpsEvDekC8lQYa/SLhpc1URYZZpymC/Oz1nJye3hh02oI SmJj5CVMfFJAsuqyxFSHTm9Osdyebq69hPQQG7hlHM6IUapl9smvIaaCs4IlSbgbNN7m GSriEbo9pNY2rjZGM7yNdJBRuEa0F4H0oofczCMAl0lAsOg4vKXFw+m+KInub8LV+DEt yTpl2k6GDKs9sN0uaE3LW43KPx51iyfev2QKgxjE9X70F3yE4WEGUUGwG69QQ+njtZmY c00VvQOLSDTxEqdFJtelLeaE5cNeC+pniFNUpEO9s6gwqS4TQonxgA8o6Mh27gM92sPH rvBw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WJdnCzuc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.42.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:42:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 17/33] target: Make qemu_target_page_mask() available for *-user Date: Sun, 28 Jan 2024 14:41:57 +1000 Message-Id: <20240128044213.316480-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c2f; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Ilya Leoshkevich Currently qemu_target_page_mask() is usable only from the softmmu code. Make it possible to use it from the *-user code as well. Signed-off-by: Ilya Leoshkevich Message-ID: <20231208003754.3688038-2-iii@linux.ibm.com> Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20240124075609.14756-2-philmd@linaro.org> Reviewed-by: Richard Henderson [rth: Split out change to accel/tcg/perf.c] Signed-off-by: Richard Henderson --- system/physmem.c | 5 ----- target/target-common.c | 10 ++++++++++ target/meson.build | 2 ++ 3 files changed, 12 insertions(+), 5 deletions(-) create mode 100644 target/target-common.c diff --git a/system/physmem.c b/system/physmem.c index cc68a79763..5e66d9ae36 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -3431,11 +3431,6 @@ size_t qemu_target_page_size(void) return TARGET_PAGE_SIZE; } -int qemu_target_page_mask(void) -{ - return TARGET_PAGE_MASK; -} - int qemu_target_page_bits(void) { return TARGET_PAGE_BITS; diff --git a/target/target-common.c b/target/target-common.c new file mode 100644 index 0000000000..903b10cfe4 --- /dev/null +++ b/target/target-common.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#include "qemu/osdep.h" + +#include "cpu.h" +#include "exec/target_page.h" + +int qemu_target_page_mask(void) +{ + return TARGET_PAGE_MASK; +} diff --git a/target/meson.build b/target/meson.build index a53a60486f..dee2ac47e0 100644 --- a/target/meson.build +++ b/target/meson.build @@ -19,3 +19,5 @@ subdir('sh4') subdir('sparc') subdir('tricore') subdir('xtensa') + +specific_ss.add(files('target-common.c')) From patchwork Sun Jan 28 04:41:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767222 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp348102wro; Sat, 27 Jan 2024 20:45:38 -0800 (PST) X-Google-Smtp-Source: AGHT+IEVtCMLe6zQBf8MrGtpoj9TJX/lt5NgoNo8L6YOtvhtQ2c+BpSgmpECi+5kofvFhrq/sRVQ X-Received: by 2002:a05:622a:45:b0:42a:839e:ea35 with SMTP id y5-20020a05622a004500b0042a839eea35mr3343165qtw.13.1706417138112; Sat, 27 Jan 2024 20:45:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706417138; cv=none; d=google.com; s=arc-20160816; b=phbq9UHCeB+Q3dWb1fUtlO+/kewHw0WYGAjyKnRL59UO5GShlzSKfdoe5nIRzeKF7P y3D7/u5wm/qFT5KffHzIDl3MWjiL7fqtbe0lIv+u0vQT6rG3yxP7QTd/ndh1s9ndfyin WIDO/N4phJWct+xMDLHSfVGklM3keSETPZIirau2OYVaKWg+liy8CjIoaKm+nH4/ZBlk hMLe84v6lSOGLUP1aGwdO9uf9+A13vWKpIVQ/7mbbVPpRq+bOIfNsIAOiDbbW6Se9SXz SD++9d48IPPWjTUnyEXMPuQvaFeLiDvcEOqupEgU7qRQpE1dZQHEBVLsLGVhmLk5XT0Z NQKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=qYcGKO9y7L+9nQKGBMKS98rrLGXyxY/fBFTDvtgcJC4=; fh=U8v/Dtss/m4oPeJtZ17DHKEvZGyePY/+mu3CqtBX2ks=; b=B+aflfBzRNsMkd0BeAo5kBuhp05gLyplvu3a1Wms8SlNlZACfWXaDKYuDSfmXe/jl4 FO1YLCLHie50O1+jluJTXIPtUSj8fEoVebcZWtBfF3i/nfT2x5PRhzX/ZkhxxcBHb9qf gzj03ilefhXgqXN/fGf8N0ilvgM+wPRPSbt3LsPPIQqA+XfmSyq4XsimsBqZS3mvYLMS +mwNwdGa8qCtghxL6P9xm3kwaRYPgCMWGf80cYn5yryb0MM8iwN3TVCPibRRlVzVscUE 0GOzw9Q23YDYO41tNykn1sp/QL7QDp7RFcOcf7BSzx48OEhDLoOrFqgDwJjnM/7Ml9jT OUEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cQu9qzDO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , =?utf-8?q?Alex_Benn=C3=A9e?= , =?utf-8?q?Philippe_M?= =?utf-8?q?athieu-Daud=C3=A9?= Subject: [PATCH 18/33] accel/tcg: Make use of qemu_target_page_mask() in perf.c Date: Sun, 28 Jan 2024 14:41:58 +1000 Message-Id: <20240128044213.316480-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c2b; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Ilya Leoshkevich Stop using TARGET_PAGE_MASK in order to make perf.c more target-agnostic. Signed-off-by: Ilya Leoshkevich Reviewed-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20231212003837.64090-2-iii@linux.ibm.com> Reviewed-by: Richard Henderson Message-Id: <20240125054631.78867-2-philmd@linaro.org> Signed-off-by: Richard Henderson --- accel/tcg/perf.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/accel/tcg/perf.c b/accel/tcg/perf.c index cd1aa99a7e..ba75c1bbe4 100644 --- a/accel/tcg/perf.c +++ b/accel/tcg/perf.c @@ -10,6 +10,7 @@ #include "qemu/osdep.h" #include "elf.h" +#include "exec/target_page.h" #include "exec/exec-all.h" #include "qemu/timer.h" #include "tcg/tcg.h" @@ -335,7 +336,7 @@ void perf_report_code(uint64_t guest_pc, TranslationBlock *tb, /* FIXME: This replicates the restore_state_to_opc() logic. */ q[insn].address = gen_insn_data[insn * start_words + 0]; if (tb_cflags(tb) & CF_PCREL) { - q[insn].address |= (guest_pc & TARGET_PAGE_MASK); + q[insn].address |= (guest_pc & qemu_target_page_mask()); } else { #if defined(TARGET_I386) q[insn].address -= tb->cs_base; From patchwork Sun Jan 28 04:41:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767213 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp347898wro; Sat, 27 Jan 2024 20:44:42 -0800 (PST) X-Google-Smtp-Source: AGHT+IFTAXH/J2ZRXctoIqqI93LpWmP6P+qGK0IQg3vhuhpkWZTOFnfFxpmrk8kk8VTb6/YoQj1Y X-Received: by 2002:a05:620a:4917:b0:783:b4ea:8632 with SMTP id vy23-20020a05620a491700b00783b4ea8632mr2438285qkn.8.1706417081782; Sat, 27 Jan 2024 20:44:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706417081; cv=none; d=google.com; s=arc-20160816; b=vKlhnaLOj8mlVINHLD4B8QfOOB9dNv2FODdEpbx8E3x769UPcC5zuFzr034pImifn6 Tikew1KRfT255CLxNFnXe4NEoa2tBfBJt+AMQNUSVeqe3aAyr1bh2M6qrhbTV/t//noc jZcsDgFSqWHddD7toTB6vQbpqo5vwGs3/xrhADojP8GKvAs+c0Q8rsZ/OsnD6r9RkAj3 jarKFLHwnet7lEeKJcNymZdV1NEdN4rjQJ4COsj3WcSZTcVhDfwLVHJWDI/Po2mk2Gdx JOx5dGzYRWklSNvMO2+4zBTGjqoxe3YebQXvPVE2HqDy/0QkR77jMlAI+95fuga8X04v GXyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=4bfmq9Mg4HxfU53OW0oPle9hQIH8zXg09YsWAHRVD1c=; fh=ZlbSsaokz6j5XPQU+IhUbFpcK1AM7Y5orhlncwoVMh8=; b=a11WIc387z0ytYlNadbHNCcHuuPEnZuWdrhBirBr4N2hz7uOAa0tyBZuMCNHuzoRup faACeSUXvdoCQetenb+cwUPiWVetYDb4xthGbXn8kc0JZ1YWR6evzljzFRTe+GjJDQrY IZlmHBDU8zk9cLHjYdyZtmhkUiVq2aZ7C8+kRuQtopoeBIil4z4bLGTmuu641SpZKk6q R5R5+INvEYu5SF1oDvguJwyx3X87+7uQUAiwkbm3m1vJpt2O61UkLH4UqrjaVlmxvqJP coo8QZqUbn77vqnZji2N0nL5J4fEtyVJFphVn3nAcVVysuoerhh8ibwCqtoB25tCIYuY 8ZJQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oMOjDl1Y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 19/33] tcg: Make tb_cflags() usable from target-agnostic code Date: Sun, 28 Jan 2024 14:41:59 +1000 Message-Id: <20240128044213.316480-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Ilya Leoshkevich Currently tb_cflags() is defined in exec-all.h, which is not usable from target-agnostic code. Move it to translation-block.h, which is. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Ilya Leoshkevich Reviewed-by: Richard Henderson Message-ID: <20231212003837.64090-3-iii@linux.ibm.com> Message-Id: <20240125054631.78867-3-philmd@linaro.org> Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 6 ------ include/exec/translation-block.h | 6 ++++++ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index df3d93a2e2..ce36bb10d4 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -459,12 +459,6 @@ int probe_access_full_mmu(CPUArchState *env, vaddr addr, int size, #endif -/* Hide the qatomic_read to make code a little easier on the eyes */ -static inline uint32_t tb_cflags(const TranslationBlock *tb) -{ - return qatomic_read(&tb->cflags); -} - static inline tb_page_addr_t tb_page_addr0(const TranslationBlock *tb) { #ifdef CONFIG_USER_ONLY diff --git a/include/exec/translation-block.h b/include/exec/translation-block.h index e2b26e16da..48211c890a 100644 --- a/include/exec/translation-block.h +++ b/include/exec/translation-block.h @@ -145,4 +145,10 @@ struct TranslationBlock { /* The alignment given to TranslationBlock during allocation. */ #define CODE_GEN_ALIGN 16 +/* Hide the qatomic_read to make code a little easier on the eyes */ +static inline uint32_t tb_cflags(const TranslationBlock *tb) +{ + return qatomic_read(&tb->cflags); +} + #endif /* EXEC_TRANSLATION_BLOCK_H */ From patchwork Sun Jan 28 04:42:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767233 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp348277wro; Sat, 27 Jan 2024 20:46:38 -0800 (PST) X-Google-Smtp-Source: AGHT+IElVHsVPCEPGwaLITBJ6G0MuEERjD6nt50yh6p/iQyYsEgiZbRqdJbeDe+Yz7gfnXSAVYw7 X-Received: by 2002:a05:622a:1887:b0:42a:8b5e:873b with SMTP id v7-20020a05622a188700b0042a8b5e873bmr2755508qtc.113.1706417198356; Sat, 27 Jan 2024 20:46:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706417198; cv=none; d=google.com; s=arc-20160816; b=NaeLFWXnMeAJytGhQGBucQQuPD7ga6IYQ89bBc57NbF4VxVor4452SV4qNhtzX6lg3 aXUjHtbgVu/b9yBBSR4sKvGXx/ua5RrtdJ1vYSWYv2zkS9iWk5La0izDQ50cYBq/D57W XdGYdxPl8xZ939SXcVPyJ/SH5O4hUNIsaIsz1NnIbUZp4ryjX2P/kyLHszJVXkMtwJiu CL4KndB9pl4pDHlL7OB58oufdS6by5Wie5JWx3iFNCkQ6zcHhknBY872lj1m8Camn+N+ B5d19sHvXQ9R65umXtntQnPKLdHGp6ATKKKNHrglLEViisb388DsD0oi/5zgBhcQj//3 vINA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=TByYFDCUWCaxnnHjASz8MJMk4paFqdDSnL+kqN7t/Zk=; fh=m3bIYSMZqCABEJVkIKLKf3tNf8TH8EKhZ9yqNwsZqDo=; b=MYvRe990Awdpq1xAkn8H/R4j9qMJJ1nNID2rcAMqNjcc+GZNMH9nfqj7IfVBqlXjti f7o2YfTQVVNpckf729IW7U1U/ImokLRdno4uLvn7bUfzA+WbgGdlNkqzdSwLpRbwDvVJ N33Q2YISR/RgdJnWawJpb2j//ihk6ydcYMDkWuTqyONMHeAa8mmdalvaZZGqLY3fwK2D pobgmlcuYs2u6Wg7rtV93uC9CGyxlJI8k2SZYpF+N4U1oMw+zLZW+pPpRV2/qzA2qN5E pvdqOIeBcEmsIS8zfGmbSqIzxreD+EtCt05JQpxEQCMR6WtJ2fx5lOZ0yM9ppo1koLRt rrFg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eXVbQFpA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PATCH 20/33] accel/tcg: Remove #ifdef TARGET_I386 from perf.c Date: Sun, 28 Jan 2024 14:42:00 +1000 Message-Id: <20240128044213.316480-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c35; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Ilya Leoshkevich Preparation for moving perf.c to tcg/. This affects only profiling guest code, which has code in a non-0 based segment, e.g., 16-bit code, which is not particularly important. Suggested-by: Richard Henderson Signed-off-by: Ilya Leoshkevich Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson Message-ID: <20231212003837.64090-4-iii@linux.ibm.com> Message-Id: <20240125054631.78867-4-philmd@linaro.org> Signed-off-by: Richard Henderson --- accel/tcg/perf.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/accel/tcg/perf.c b/accel/tcg/perf.c index ba75c1bbe4..68a46b1b52 100644 --- a/accel/tcg/perf.c +++ b/accel/tcg/perf.c @@ -337,10 +337,6 @@ void perf_report_code(uint64_t guest_pc, TranslationBlock *tb, q[insn].address = gen_insn_data[insn * start_words + 0]; if (tb_cflags(tb) & CF_PCREL) { q[insn].address |= (guest_pc & qemu_target_page_mask()); - } else { -#if defined(TARGET_I386) - q[insn].address -= tb->cs_base; -#endif } q[insn].flags = DEBUGINFO_SYMBOL | (jitdump ? DEBUGINFO_LINE : 0); } From patchwork Sun Jan 28 04:42:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767210 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp347789wro; Sat, 27 Jan 2024 20:44:10 -0800 (PST) X-Google-Smtp-Source: AGHT+IH5amco9vWpdF9gPS/pmnDflsG58ArFCDCkvWPtaObDwaQXcahXHPmt+xlFh3vL2Mkjy54I X-Received: by 2002:ae9:e645:0:b0:783:aebc:35f3 with SMTP id x5-20020ae9e645000000b00783aebc35f3mr2905882qkl.80.1706417049919; Sat, 27 Jan 2024 20:44:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706417049; cv=none; d=google.com; s=arc-20160816; b=DphvDXtu6SiIsheZWcYv65H1Q9LaVvZVmIGT9A6rMtGlwvHvJZuEh500FqfL9AfpC9 AMgretu1fgUY8Xu5pU6CYL6Snnz0Uy9SdcDOWH5+o/vPcBorg5QjHTQgsoMzakPP9ieP qiFPaLWTA0PleIQrTbOxaAEtqrGwgcl8oICi7zRnHoxYTS46+MT4TVPOzGbQTOVbKxaW SkfTL/PzfCoebdLbCgmgvURCmYcFA3DmMsvmGbKQliT4eep4cIbxjueEVQqYPHyTBwjy HmiehBj2hWrHOHz63+kkmcONPfhFEzISOMH8IBdn3vxWOsydwasonqCiPaQNkH9jFhfS V2wQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=MmzrBNQK2eDwb+/K0EzCDtsTU1SD4iiHNXZIgeBMj8o=; fh=ZlbSsaokz6j5XPQU+IhUbFpcK1AM7Y5orhlncwoVMh8=; b=LCYbRWEqjG2a+zx7oKE/nCpAOUfkUNu8+S/xQZAgrJKTqRE58OoZF0x1b//Z35bvfX wUcfMKB3BYjSe/vQbAm+4G2IvQI3fMt+ts8viFgvyE0ACT1ZOqDwSL2C6imU27DG6Aho S96Ysg9y6QZEvB8PQQswaDrpcx1ELx0zrwPpOFey/vkKJE8Xsl6dC0lOpf2Pyt5XcyTe b3SP5AlSjvtuRUcnrD2D52Ks6OWSxmrbkoLZJ2ZSxThdilLYbBvuYmP2cvzYKQp3VIlf +DdoVRrGoAFHF0gix63hVFQoWM9EQFGROKmzqynlBpo1lphvrAeIxS3QxJfExZJL6QnD J4tA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vRjIfXPx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 21/33] accel/tcg: Move perf and debuginfo support to tcg/ Date: Sun, 28 Jan 2024 14:42:01 +1000 Message-Id: <20240128044213.316480-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c30; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Ilya Leoshkevich tcg/ should not depend on accel/tcg/, but perf and debuginfo support provided by the latter are being used by tcg/tcg.c. Since that's the only user, move both to tcg/. Suggested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Ilya Leoshkevich Reviewed-by: Richard Henderson Message-ID: <20231212003837.64090-5-iii@linux.ibm.com> Message-Id: <20240125054631.78867-5-philmd@linaro.org> Signed-off-by: Richard Henderson --- {accel => include}/tcg/debuginfo.h | 4 ++-- {accel => include}/tcg/perf.h | 4 ++-- accel/tcg/translate-all.c | 2 +- hw/core/loader.c | 2 +- linux-user/elfload.c | 2 +- linux-user/exit.c | 2 +- linux-user/main.c | 2 +- system/vl.c | 2 +- {accel/tcg => tcg}/debuginfo.c | 3 +-- {accel/tcg => tcg}/perf.c | 7 +++---- tcg/tcg.c | 2 +- accel/tcg/meson.build | 4 ---- tcg/meson.build | 5 +++++ 13 files changed, 20 insertions(+), 21 deletions(-) rename {accel => include}/tcg/debuginfo.h (96%) rename {accel => include}/tcg/perf.h (95%) rename {accel/tcg => tcg}/debuginfo.c (98%) rename {accel/tcg => tcg}/perf.c (99%) diff --git a/accel/tcg/debuginfo.h b/include/tcg/debuginfo.h similarity index 96% rename from accel/tcg/debuginfo.h rename to include/tcg/debuginfo.h index f064e1c144..858535b5da 100644 --- a/accel/tcg/debuginfo.h +++ b/include/tcg/debuginfo.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef ACCEL_TCG_DEBUGINFO_H -#define ACCEL_TCG_DEBUGINFO_H +#ifndef TCG_DEBUGINFO_H +#define TCG_DEBUGINFO_H #include "qemu/bitops.h" diff --git a/accel/tcg/perf.h b/include/tcg/perf.h similarity index 95% rename from accel/tcg/perf.h rename to include/tcg/perf.h index f92dd52c69..c96b5920a3 100644 --- a/accel/tcg/perf.h +++ b/include/tcg/perf.h @@ -4,8 +4,8 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef ACCEL_TCG_PERF_H -#define ACCEL_TCG_PERF_H +#ifndef TCG_PERF_H +#define TCG_PERF_H #if defined(CONFIG_TCG) && defined(CONFIG_LINUX) /* Start writing perf-.map. */ diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 1737bb3da5..1c695efe02 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -63,7 +63,7 @@ #include "tb-context.h" #include "internal-common.h" #include "internal-target.h" -#include "perf.h" +#include "tcg/perf.h" #include "tcg/insn-start-words.h" TBContext tb_ctx; diff --git a/hw/core/loader.c b/hw/core/loader.c index e7a9b3775b..b8e52f3fb0 100644 --- a/hw/core/loader.c +++ b/hw/core/loader.c @@ -62,7 +62,7 @@ #include "hw/boards.h" #include "qemu/cutils.h" #include "sysemu/runstate.h" -#include "accel/tcg/debuginfo.h" +#include "tcg/debuginfo.h" #include diff --git a/linux-user/elfload.c b/linux-user/elfload.c index daf7ef8435..b8eef893d0 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -22,7 +22,7 @@ #include "qapi/error.h" #include "qemu/error-report.h" #include "target_signal.h" -#include "accel/tcg/debuginfo.h" +#include "tcg/debuginfo.h" #ifdef TARGET_ARM #include "target/arm/cpu-features.h" diff --git a/linux-user/exit.c b/linux-user/exit.c index 50266314e0..1ff8fe4f07 100644 --- a/linux-user/exit.c +++ b/linux-user/exit.c @@ -17,7 +17,7 @@ * along with this program; if not, see . */ #include "qemu/osdep.h" -#include "accel/tcg/perf.h" +#include "tcg/perf.h" #include "gdbstub/syscalls.h" #include "qemu.h" #include "user-internals.h" diff --git a/linux-user/main.c b/linux-user/main.c index c9470eeccf..74b2fbb393 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -54,7 +54,7 @@ #include "signal-common.h" #include "loader.h" #include "user-mmap.h" -#include "accel/tcg/perf.h" +#include "tcg/perf.h" #ifdef CONFIG_SEMIHOSTING #include "semihosting/semihost.h" diff --git a/system/vl.c b/system/vl.c index 788d88ea03..60fd1e56b6 100644 --- a/system/vl.c +++ b/system/vl.c @@ -96,7 +96,7 @@ #endif #include "sysemu/qtest.h" #ifdef CONFIG_TCG -#include "accel/tcg/perf.h" +#include "tcg/perf.h" #endif #include "disas/disas.h" diff --git a/accel/tcg/debuginfo.c b/tcg/debuginfo.c similarity index 98% rename from accel/tcg/debuginfo.c rename to tcg/debuginfo.c index 71c66d04d1..3753f7ef67 100644 --- a/accel/tcg/debuginfo.c +++ b/tcg/debuginfo.c @@ -6,11 +6,10 @@ #include "qemu/osdep.h" #include "qemu/lockable.h" +#include "tcg/debuginfo.h" #include -#include "debuginfo.h" - static QemuMutex lock; static Dwfl *dwfl; static const Dwfl_Callbacks dwfl_callbacks = { diff --git a/accel/tcg/perf.c b/tcg/perf.c similarity index 99% rename from accel/tcg/perf.c rename to tcg/perf.c index 68a46b1b52..412a987d95 100644 --- a/accel/tcg/perf.c +++ b/tcg/perf.c @@ -11,13 +11,12 @@ #include "qemu/osdep.h" #include "elf.h" #include "exec/target_page.h" -#include "exec/exec-all.h" +#include "exec/translation-block.h" #include "qemu/timer.h" +#include "tcg/debuginfo.h" +#include "tcg/perf.h" #include "tcg/tcg.h" -#include "debuginfo.h" -#include "perf.h" - static FILE *safe_fopen_w(const char *path) { int saved_errno; diff --git a/tcg/tcg.c b/tcg/tcg.c index e2c38f6d11..eeff4c1d51 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -55,7 +55,7 @@ #include "tcg/tcg-ldst.h" #include "tcg/tcg-temp-internal.h" #include "tcg-internal.h" -#include "accel/tcg/perf.h" +#include "tcg/perf.h" #ifdef CONFIG_USER_ONLY #include "exec/user/guest-base.h" #endif diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index c15ac9ac8f..46f7d53eeb 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -16,10 +16,6 @@ tcg_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_false: files('user-exec-stub.c')) if get_option('plugins') tcg_ss.add(files('plugin-gen.c')) endif -tcg_ss.add(when: libdw, if_true: files('debuginfo.c')) -if host_os == 'linux' - tcg_ss.add(files('perf.c')) -endif specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss) specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( diff --git a/tcg/meson.build b/tcg/meson.build index 5afdec1e1a..8251589fd4 100644 --- a/tcg/meson.build +++ b/tcg/meson.build @@ -22,6 +22,11 @@ if get_option('tcg_interpreter') tcg_ss.add(files('tci.c')) endif +tcg_ss.add(when: libdw, if_true: files('debuginfo.c')) +if host_os == 'linux' + tcg_ss.add(files('perf.c')) +endif + tcg_ss = tcg_ss.apply({}) libtcg_user = static_library('tcg_user', From patchwork Sun Jan 28 04:42:02 2024 Content-Type: text/plain; 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Anton Johansson Subject: [PATCH 22/33] accel/tcg: Rename tcg_ss[] -> tcg_specific_ss[] in meson Date: Sun, 28 Jan 2024 14:42:02 +1000 Message-Id: <20240128044213.316480-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::835; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x835.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé tcg_ss[] source set contains target-specific units. Rename it as 'tcg_specific_ss[]' for clarity. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Anton Johansson Message-Id: <20240124101639.30056-2-philmd@linaro.org> Signed-off-by: Richard Henderson --- accel/tcg/meson.build | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index 46f7d53eeb..aef80de967 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -1,8 +1,8 @@ -tcg_ss = ss.source_set() common_ss.add(when: 'CONFIG_TCG', if_true: files( 'cpu-exec-common.c', )) -tcg_ss.add(files( +tcg_specific_ss = ss.source_set() +tcg_specific_ss.add(files( 'tcg-all.c', 'cpu-exec.c', 'tb-maint.c', @@ -11,12 +11,12 @@ tcg_ss.add(files( 'translate-all.c', 'translator.c', )) -tcg_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user-exec.c')) -tcg_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_false: files('user-exec-stub.c')) +tcg_specific_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user-exec.c')) +tcg_specific_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_false: files('user-exec-stub.c')) if get_option('plugins') - tcg_ss.add(files('plugin-gen.c')) + tcg_specific_ss.add(files('plugin-gen.c')) endif -specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss) +specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss) specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( 'cputlb.c', From patchwork Sun Jan 28 04:42:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767230 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp348246wro; Sat, 27 Jan 2024 20:46:25 -0800 (PST) X-Google-Smtp-Source: AGHT+IEu1y8iDD7i8GhfWmHs6jPsHd2YQgNvHm+sAy+ZeNci4U8oeXughanS0errEtHBB/eoDumo X-Received: by 2002:a05:620a:15aa:b0:783:b637:1543 with SMTP id f10-20020a05620a15aa00b00783b6371543mr2525036qkk.126.1706417185747; Sat, 27 Jan 2024 20:46:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706417185; cv=none; d=google.com; s=arc-20160816; b=KBdg8x0cjipG94/UFosBt2dZW6C04lYvL6UpcZn+JFpGVcWcCvjET1xJo7W4VQxTwI 6WXR19c+8/Jme1VA+Gv5XB4QgTN3NCAatkRk3wTFFYP6QQhM7myKAxzTPcQYRhoygaD+ X86/MWbgitKMNautgs2dXaMui+8el+iFD/B36iCCEq3bnw0JLsv1E9B8X5YFPXJpIbb8 mfYixoLqSINK9zzZkwoVpPCUZL3u7mr0FpJfm2BnKJo6nm8gfUWcz3dJNOCoUe0+Ol7W 3BhbeBGsx/Z9B4qkkJcR2SSHnC3Au1CmdY01rpplimZAXrex1bxBLk8PCN7QhGL+5HMq sZcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=IeBfHlDAifxu4F1/UNQzzGCEUArq4HbYf2mScaRZKZ4=; fh=HGG5jZNhe8Q+zQJ9+mddel2c/xsqW3vEoqbd78QYiOw=; b=q26oRwVe2J2Mt1nBcgh7Yg7+UqCCg5F0sB7VJYFk9VTshiB0ic3U3JVMUWl1HwZSZj bpn6FU7srCoAfo+YIjCCuOAas1xyTUIt3Lbu8oH11UK7ZdZ2tn3xbO5t0KXUMwyC2MWW 3KOD91BK/ejlMcQ6rUXejYU28/tyAtpPsT1jm/XHJO9kyYH3YNM7P8VXKYu/2A8YJCsn BSpwbhGrD045TNtzMNnKQR2SRJd41GkpLf+j9Gorkk74/ThOGEZo/pXJiVInYGA4h/XH korWTDhxfn8QFDzeUZfA5oVBe6yeQ2LEQYCG2GcYSnna2s5v5VjlNQwfiQ5zjNiqOoOz 4O/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=f7FzQJha; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Anton Johansson Subject: [PATCH 23/33] accel/tcg: Rename tcg_cpus_destroy() -> tcg_cpu_destroy() Date: Sun, 28 Jan 2024 14:42:03 +1000 Message-Id: <20240128044213.316480-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c2a; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé tcg_cpus_destroy() operates on a single vCPU, rename it as 'tcg_cpu_destroy'. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Message-Id: <20240124101639.30056-3-philmd@linaro.org> Signed-off-by: Richard Henderson --- accel/tcg/tcg-accel-ops.h | 2 +- accel/tcg/tcg-accel-ops-mttcg.c | 2 +- accel/tcg/tcg-accel-ops-rr.c | 2 +- accel/tcg/tcg-accel-ops.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/accel/tcg/tcg-accel-ops.h b/accel/tcg/tcg-accel-ops.h index f9bc6330e2..17c7ed00eb 100644 --- a/accel/tcg/tcg-accel-ops.h +++ b/accel/tcg/tcg-accel-ops.h @@ -14,7 +14,7 @@ #include "sysemu/cpus.h" -void tcg_cpus_destroy(CPUState *cpu); +void tcg_cpu_destroy(CPUState *cpu); int tcg_cpus_exec(CPUState *cpu); void tcg_handle_interrupt(CPUState *cpu, int mask); void tcg_cpu_init_cflags(CPUState *cpu, bool parallel); diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttcg.c index af7307013a..bcba314a65 100644 --- a/accel/tcg/tcg-accel-ops-mttcg.c +++ b/accel/tcg/tcg-accel-ops-mttcg.c @@ -118,7 +118,7 @@ static void *mttcg_cpu_thread_fn(void *arg) qemu_wait_io_event(cpu); } while (!cpu->unplug || cpu_can_run(cpu)); - tcg_cpus_destroy(cpu); + tcg_cpu_destroy(cpu); bql_unlock(); rcu_remove_force_rcu_notifier(&force_rcu.notifier); rcu_unregister_thread(); diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c index 3208035d85..0617f66b5b 100644 --- a/accel/tcg/tcg-accel-ops-rr.c +++ b/accel/tcg/tcg-accel-ops-rr.c @@ -131,7 +131,7 @@ static void rr_deal_with_unplugged_cpus(void) CPU_FOREACH(cpu) { if (cpu->unplug && !cpu_can_run(cpu)) { - tcg_cpus_destroy(cpu); + tcg_cpu_destroy(cpu); break; } } diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 813065c0ec..9b84b84218 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -63,7 +63,7 @@ void tcg_cpu_init_cflags(CPUState *cpu, bool parallel) cpu->tcg_cflags |= cflags; } -void tcg_cpus_destroy(CPUState *cpu) +void tcg_cpu_destroy(CPUState *cpu) { cpu_thread_signal_destroyed(cpu); } From patchwork Sun Jan 28 04:42:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767211 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp347856wro; Sat, 27 Jan 2024 20:44:31 -0800 (PST) X-Google-Smtp-Source: AGHT+IHpFLGdMk3E5EHB47RhPKpvvflnUGzwA09cptI09yKhhp8Kww5IpYvyJbm4nQbbU2sQBfrT X-Received: by 2002:ac8:5747:0:b0:42a:46e5:599b with SMTP id 7-20020ac85747000000b0042a46e5599bmr3417749qtx.77.1706417071201; Sat, 27 Jan 2024 20:44:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706417071; cv=none; d=google.com; s=arc-20160816; b=c/1NxPvrFh1WaBD/UHFIii+at5dG72YMZ1DD/BKAnGgidoJ1RPqBobVsj4+dYVVaEa ZAjcRz+JKE38WuOAgTntWIuOoNqOkcOBw7EC+t7YNHCtMj8fxkqmCfhknKuE4fe/tVyk Nuvx/osTOMLLQ4EI1xwizHvxzjwOIsaN238ixVrQThn4Y1WQe/sEPc+O6/9LfN1mGj+E 54IrjteaJuDDqS6+RKKFfUBywNg4YtC+5FOI+3X0kVUoA1pi8MTQhqS/cyKLVrKK8LfA 82rEuLXg1oyhOOHiBslmZJ19R6tdtrUB4b/Opn1YgCbo1ZbIn74p7Ww7THWIDCL0R6vb bHSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=h0D5wvbqCBKDS3PIRJ2u8mID+Ysdp5Zl/usWtkQWmMI=; fh=HGG5jZNhe8Q+zQJ9+mddel2c/xsqW3vEoqbd78QYiOw=; b=Kbe2BMybL1O+XFIi1/SXPLRW5tzLvgAh0t8xlKXyorNZPQhYDdn+KpdDmG/+nsFyZ1 TZn8aQi8kPUdpeI/u8m5sNI2ga2ek20DLqm10gRd9EL2I/ME3AyL4FNoQGv/4dtggzac PYRam95RNR89c+2JdaB+RMdxm8sMfYZ1hSWqv1CvzDmWb7QmiBHWFgYP2uTLXJZgIijV ThHx5FrPKClQTxyxADohH2sORNLZA8PfSoY/AO2UZjQ41y8DG7+YVGOdKhmyneIdmY4C I1xgm4mHlq4U5JKAVKj9yYjD56OZ9R/xTsEYBOgU9ofBsRKgUo7yHD9OMaPzNwzW2F+P 3Qxg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XVvQXq9b; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Anton Johansson Subject: [PATCH 24/33] accel/tcg: Rename tcg_cpus_exec() -> tcg_cpu_exec() Date: Sun, 28 Jan 2024 14:42:04 +1000 Message-Id: <20240128044213.316480-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c2c; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé tcg_cpus_exec() operates on a single vCPU, rename it as 'tcg_cpu_exec'. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Anton Johansson Message-Id: <20240124101639.30056-4-philmd@linaro.org> Signed-off-by: Richard Henderson --- accel/tcg/tcg-accel-ops.h | 2 +- accel/tcg/tcg-accel-ops-mttcg.c | 2 +- accel/tcg/tcg-accel-ops-rr.c | 2 +- accel/tcg/tcg-accel-ops.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/accel/tcg/tcg-accel-ops.h b/accel/tcg/tcg-accel-ops.h index 17c7ed00eb..44c4079972 100644 --- a/accel/tcg/tcg-accel-ops.h +++ b/accel/tcg/tcg-accel-ops.h @@ -15,7 +15,7 @@ #include "sysemu/cpus.h" void tcg_cpu_destroy(CPUState *cpu); -int tcg_cpus_exec(CPUState *cpu); +int tcg_cpu_exec(CPUState *cpu); void tcg_handle_interrupt(CPUState *cpu, int mask); void tcg_cpu_init_cflags(CPUState *cpu, bool parallel); diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttcg.c index bcba314a65..c552b45b8e 100644 --- a/accel/tcg/tcg-accel-ops-mttcg.c +++ b/accel/tcg/tcg-accel-ops-mttcg.c @@ -92,7 +92,7 @@ static void *mttcg_cpu_thread_fn(void *arg) if (cpu_can_run(cpu)) { int r; bql_unlock(); - r = tcg_cpus_exec(cpu); + r = tcg_cpu_exec(cpu); bql_lock(); switch (r) { case EXCP_DEBUG: diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c index 0617f66b5b..894e73e52c 100644 --- a/accel/tcg/tcg-accel-ops-rr.c +++ b/accel/tcg/tcg-accel-ops-rr.c @@ -258,7 +258,7 @@ static void *rr_cpu_thread_fn(void *arg) if (icount_enabled()) { icount_prepare_for_run(cpu, cpu_budget); } - r = tcg_cpus_exec(cpu); + r = tcg_cpu_exec(cpu); if (icount_enabled()) { icount_process_data(cpu); } diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 9b84b84218..9c957f421c 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -68,7 +68,7 @@ void tcg_cpu_destroy(CPUState *cpu) cpu_thread_signal_destroyed(cpu); } -int tcg_cpus_exec(CPUState *cpu) +int tcg_cpu_exec(CPUState *cpu) { int ret; assert(tcg_enabled()); From patchwork Sun Jan 28 04:42:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767218 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp347997wro; Sat, 27 Jan 2024 20:45:08 -0800 (PST) X-Google-Smtp-Source: AGHT+IHy0Bhc3CiKBDtBWgkN5txzUMEuck2kkpNNB52BrazgzckyVttvhkiUNHbFYffpjxqJB4Ii X-Received: by 2002:a05:6214:cab:b0:681:86c:ac4 with SMTP id s11-20020a0562140cab00b00681086c0ac4mr4116442qvs.74.1706417107986; Sat, 27 Jan 2024 20:45:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706417107; cv=none; d=google.com; s=arc-20160816; b=fOpMdTdB5uGIsYY5GXZInuhFzMVHHitmir4Jp/bQvliMhZ0y/vl16hW74rNeU3buvA /otMNxGZbBVGH1BzEh1/BTCrD1X+XUew7asndyYpZZEzw9sKQbFzadU9n3fBOSIEmbvi twRWoJhmPtm4yUJv0ubtmA2lVHqwTpq47raLbcdnzPyM3FtcWT0heLg/9jf02RnamTRa svghrj/P9OsRzhD4eiWllFyg0DhVcJUUraOUL+/zWARaEtsvSHM/6uKkUGKe/PO/1poz pnIKxrnMBWWJM0KTyEmDKVxZGXQLgxgdpT1LG28de4Dn4rgMA2mUQfoytuXCK8TapxnG zJzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=zfMhTQxwxgwjYRWhH0P+ZcfoxncjyISGzQ2K+4rTjEw=; fh=HGG5jZNhe8Q+zQJ9+mddel2c/xsqW3vEoqbd78QYiOw=; b=PI4VWmVNrjsE+4Ao+ZD7exmE5uSm1jiqfprqJJaTmyyshAxgZmA8juTgombSAUEamv oauRxuAL03lf5I9Vvxiw3qrac6lqRDxVPamHtnjX2rs8FIS1VI9ZTu8+i3Lgq7xWJOJw VmsRMI3mkLr8X0Q04Xz2VX05cBs+E3pTl2HvZZXYtvkcogfuhfCToFvzeezPFL0Ix9xu RcUp9x2Zhx9+paJYpwAYYhXBi8G2KxxQB1/Uu5gFoQzn/lfZT5WcBzFWrsPopcXN89Cv 7zm5SwqfgnvQ6LXEGPO/nevtMQjk+4DNLyuvaSv/hpGDv3y6GNW65WAD332CwxHOqPK3 x3bw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=T7y1ebxa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Anton Johansson Subject: [PATCH 25/33] accel/tcg: Un-inline icount_exit_request() for clarity Date: Sun, 28 Jan 2024 14:42:05 +1000 Message-Id: <20240128044213.316480-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Convert packed logic to dumb icount_exit_request() helper. No functional change intended. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Anton Johansson Message-Id: <20240124101639.30056-5-philmd@linaro.org> Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 950dad63cb..f2535a2991 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -777,6 +777,17 @@ static inline bool need_replay_interrupt(int interrupt_request) } #endif /* !CONFIG_USER_ONLY */ +static inline bool icount_exit_request(CPUState *cpu) +{ + if (!icount_enabled()) { + return false; + } + if (cpu->cflags_next_tb != -1 && !(cpu->cflags_next_tb & CF_USE_ICOUNT)) { + return false; + } + return cpu->neg.icount_decr.u16.low + cpu->icount_extra == 0; +} + static inline bool cpu_handle_interrupt(CPUState *cpu, TranslationBlock **last_tb) { @@ -882,10 +893,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, } /* Finally, check if we need to exit to the main loop. */ - if (unlikely(qatomic_read(&cpu->exit_request)) - || (icount_enabled() - && (cpu->cflags_next_tb == -1 || cpu->cflags_next_tb & CF_USE_ICOUNT) - && cpu->neg.icount_decr.u16.low + cpu->icount_extra == 0)) { + if (unlikely(qatomic_read(&cpu->exit_request)) || icount_exit_request(cpu)) { qatomic_set(&cpu->exit_request, 0); if (cpu->exception_index == -1) { cpu->exception_index = EXCP_INTERRUPT; From patchwork Sun Jan 28 04:42:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767229 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp348194wro; Sat, 27 Jan 2024 20:46:11 -0800 (PST) X-Google-Smtp-Source: AGHT+IEa3ZRnaNt+ToQzogs0cTv6vqSa0RSYbL+aQY/796RnGQsU7rnX2oYLN/sme3y8Vnx6wS7N X-Received: by 2002:a05:6214:2021:b0:686:ae75:dad7 with SMTP id 1-20020a056214202100b00686ae75dad7mr3385256qvf.77.1706417171527; Sat, 27 Jan 2024 20:46:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706417171; cv=none; d=google.com; s=arc-20160816; b=aRQ7rnJLdOyta9xgO8ieOYMkCgQVO1HQD8o4gkgtchQvCL+grwqvczMuhw3ZxuNhb9 ZFCkisrW+icmvdy4yKz+KlrxLVbGElTwduhqdd9BFuMK5rJek34VHQnKKdWQG+gCkKkx jNvoSP7viUv7Trv7dOXerpPshKMTHAtCnXDn8Nn8svUgKNSqDlEfaOn+6RD4aReFkE2Y 9rSl442lwzXL0r+M2pBLjvgdo1VwJoE5bxi++C4ACHNj3qNRHjffOiny/DKy+KKXVcYD AdOFUu/si5dd3DfuoSQFn0lwBGzCehUznXwiJq2CvUM81xVYCFc82bWGIkyxyZ9L+ExV LA9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=fDrlqZJJ0WFNjsqbAt49Vqu9oOvOnIDnuEZmci/Hrlo=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=wDJjDnndpmDVx5hpD1QQIjb86tJxIQO1i/C9YtlObfUwBdHzgvgV3AJ7eWfn1uP61l xeMfwHLpnHm14b4NDUa7Ieu0gI5YnlEJwgLVuGuNwJs6qoUS76BWKf2h7syiNuFpR9NN LbJ4avUn4Rksscf1CBOAPbeZA4BTJIH6v3BvzWbl7H1OM8fZj6h8nQzyAXLvd3TaoOca WvwlTM5i0PCKZI/VorVM1e7PEpjkM6TUYdhrwTvGTKrfDiyj470O3KutHaERj2Yjl+Ru Y9j0RTECMm0zjGXCI0T5kFGPyfXfI9i6fO0zSwx9ZwFnLnJM2PI7oIfFjF/3gIMUmPYH I7JA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=G3thYD7H; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 26/33] include/qemu: Add TCGCPUOps typedef to typedefs.h Date: Sun, 28 Jan 2024 14:42:06 +1000 Message-Id: <20240128044213.316480-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org QEMU coding style recommends using structure typedefs. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 5 +---- include/qemu/typedefs.h | 1 + bsd-user/signal.c | 4 ++-- linux-user/signal.c | 4 ++-- target/alpha/cpu.c | 2 +- target/arm/cpu.c | 2 +- target/arm/tcg/cpu32.c | 2 +- target/avr/cpu.c | 2 +- target/cris/cpu.c | 4 ++-- target/hexagon/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/tcg/tcg-cpu.c | 2 +- target/loongarch/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 2 +- target/nios2/cpu.c | 2 +- target/openrisc/cpu.c | 2 +- target/ppc/cpu_init.c | 2 +- target/riscv/tcg/tcg-cpu.c | 2 +- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 2 +- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 2 +- target/xtensa/cpu.c | 2 +- 26 files changed, 29 insertions(+), 31 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index db58f12233..2c284d6397 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -90,9 +90,6 @@ typedef enum MMUAccessType { typedef struct CPUWatchpoint CPUWatchpoint; -/* see tcg-cpu-ops.h */ -struct TCGCPUOps; - /* see accel-cpu.h */ struct AccelCPUClass; @@ -177,7 +174,7 @@ struct CPUClass { const struct SysemuCPUOps *sysemu_ops; /* when TCG is not available, this pointer is NULL */ - const struct TCGCPUOps *tcg_ops; + const TCGCPUOps *tcg_ops; /* * if not NULL, this is called in order for the CPUClass to initialize diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 5abdbc3874..d7c703b4ae 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -131,6 +131,7 @@ typedef struct Range Range; typedef struct ReservedRegion ReservedRegion; typedef struct SHPCDevice SHPCDevice; typedef struct SSIBus SSIBus; +typedef struct TCGCPUOps TCGCPUOps; typedef struct TCGHelperInfo TCGHelperInfo; typedef struct TranslationBlock TranslationBlock; typedef struct VirtIODevice VirtIODevice; diff --git a/bsd-user/signal.c b/bsd-user/signal.c index ca31470772..f4352e4530 100644 --- a/bsd-user/signal.c +++ b/bsd-user/signal.c @@ -1022,7 +1022,7 @@ void process_pending_signals(CPUArchState *env) void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, MMUAccessType access_type, bool maperr, uintptr_t ra) { - const struct TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops; + const TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops; if (tcg_ops->record_sigsegv) { tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra); @@ -1038,7 +1038,7 @@ void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr, MMUAccessType access_type, uintptr_t ra) { - const struct TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops; + const TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops; if (tcg_ops->record_sigbus) { tcg_ops->record_sigbus(cpu, addr, access_type, ra); diff --git a/linux-user/signal.c b/linux-user/signal.c index c9527adfa3..d3e62ab030 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -671,7 +671,7 @@ void force_sigsegv(int oldsig) void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, MMUAccessType access_type, bool maperr, uintptr_t ra) { - const struct TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops; + const TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops; if (tcg_ops->record_sigsegv) { tcg_ops->record_sigsegv(cpu, addr, access_type, maperr, ra); @@ -687,7 +687,7 @@ void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr, MMUAccessType access_type, uintptr_t ra) { - const struct TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops; + const TCGCPUOps *tcg_ops = CPU_GET_CLASS(cpu)->tcg_ops; if (tcg_ops->record_sigbus) { tcg_ops->record_sigbus(cpu, addr, access_type, ra); diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index ce20a56270..80760be0f3 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -222,7 +222,7 @@ static const struct SysemuCPUOps alpha_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps alpha_tcg_ops = { +static const TCGCPUOps alpha_tcg_ops = { .initialize = alpha_translate_init, .restore_state_to_opc = alpha_restore_state_to_opc, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0ee9a879f0..e050928598 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2456,7 +2456,7 @@ static const struct SysemuCPUOps arm_sysemu_ops = { #endif #ifdef CONFIG_TCG -static const struct TCGCPUOps arm_tcg_ops = { +static const TCGCPUOps arm_tcg_ops = { .initialize = arm_translate_init, .synchronize_from_tb = arm_cpu_synchronize_from_tb, .debug_excp_handler = arm_debug_excp_handler, diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index d9e0e2a4dd..1125305115 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -1018,7 +1018,7 @@ static void pxa270c5_initfn(Object *obj) cpu->reset_sctlr = 0x00000078; } -static const struct TCGCPUOps arm_v7m_tcg_ops = { +static const TCGCPUOps arm_v7m_tcg_ops = { .initialize = arm_translate_init, .synchronize_from_tb = arm_cpu_synchronize_from_tb, .debug_excp_handler = arm_debug_excp_handler, diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 76dbe56284..41ff121d20 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -233,7 +233,7 @@ static const struct SysemuCPUOps avr_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps avr_tcg_ops = { +static const TCGCPUOps avr_tcg_ops = { .initialize = avr_cpu_tcg_init, .synchronize_from_tb = avr_cpu_synchronize_from_tb, .restore_state_to_opc = avr_restore_state_to_opc, diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 6512ef8ee2..93f26542d8 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -192,7 +192,7 @@ static const struct SysemuCPUOps cris_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps crisv10_tcg_ops = { +static const TCGCPUOps crisv10_tcg_ops = { .initialize = cris_initialize_crisv10_tcg, .restore_state_to_opc = cris_restore_state_to_opc, @@ -203,7 +203,7 @@ static const struct TCGCPUOps crisv10_tcg_ops = { #endif /* !CONFIG_USER_ONLY */ }; -static const struct TCGCPUOps crisv32_tcg_ops = { +static const TCGCPUOps crisv32_tcg_ops = { .initialize = cris_initialize_tcg, .restore_state_to_opc = cris_restore_state_to_opc, diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index b2bbb21b59..49f05eae99 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -358,7 +358,7 @@ static void hexagon_cpu_init(Object *obj) #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps hexagon_tcg_ops = { +static const TCGCPUOps hexagon_tcg_ops = { .initialize = hexagon_translate_init, .synchronize_from_tb = hexagon_cpu_synchronize_from_tb, .restore_state_to_opc = hexagon_restore_state_to_opc, diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 2cc8e43b33..2d98082306 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -225,7 +225,7 @@ static const struct SysemuCPUOps hppa_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps hppa_tcg_ops = { +static const TCGCPUOps hppa_tcg_ops = { .initialize = hppa_translate_init, .synchronize_from_tb = hppa_cpu_synchronize_from_tb, .restore_state_to_opc = hppa_restore_state_to_opc, diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index e1405b7be9..8e148e9bc4 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -106,7 +106,7 @@ static bool x86_debug_check_breakpoint(CPUState *cs) #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps x86_tcg_ops = { +static const TCGCPUOps x86_tcg_ops = { .initialize = tcg_x86_init, .synchronize_from_tb = x86_cpu_synchronize_from_tb, .restore_state_to_opc = x86_restore_state_to_opc, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index ea4281e177..d9ddab5b9a 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -758,7 +758,7 @@ void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" -static struct TCGCPUOps loongarch_tcg_ops = { +static TCGCPUOps loongarch_tcg_ops = { .initialize = loongarch_translate_init, .synchronize_from_tb = loongarch_cpu_synchronize_from_tb, .restore_state_to_opc = loongarch_restore_state_to_opc, diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index f9dc447897..288140c986 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -546,7 +546,7 @@ static const struct SysemuCPUOps m68k_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps m68k_tcg_ops = { +static const TCGCPUOps m68k_tcg_ops = { .initialize = m68k_tcg_init, .restore_state_to_opc = m68k_restore_state_to_opc, diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 4c270e941f..171937564d 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -410,7 +410,7 @@ static const struct SysemuCPUOps mb_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps mb_tcg_ops = { +static const TCGCPUOps mb_tcg_ops = { .initialize = mb_tcg_init, .synchronize_from_tb = mb_cpu_synchronize_from_tb, .restore_state_to_opc = mb_restore_state_to_opc, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 4c3e1ec2d9..dfe82f93ef 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -563,7 +563,7 @@ static const struct SysemuCPUOps mips_sysemu_ops = { * NB: cannot be const, as some elements are changed for specific * mips hardware (see hw/mips/jazz.c). */ -static const struct TCGCPUOps mips_tcg_ops = { +static const TCGCPUOps mips_tcg_ops = { .initialize = mips_tcg_init, .synchronize_from_tb = mips_cpu_synchronize_from_tb, .restore_state_to_opc = mips_restore_state_to_opc, diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 3e42889ce6..bff35f835a 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -372,7 +372,7 @@ static const struct SysemuCPUOps nios2_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps nios2_tcg_ops = { +static const TCGCPUOps nios2_tcg_ops = { .initialize = nios2_tcg_init, .restore_state_to_opc = nios2_restore_state_to_opc, diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index fda0dc9470..bc54e7ccd0 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -235,7 +235,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps openrisc_tcg_ops = { +static const TCGCPUOps openrisc_tcg_ops = { .initialize = openrisc_translate_init, .synchronize_from_tb = openrisc_cpu_synchronize_from_tb, .restore_state_to_opc = openrisc_restore_state_to_opc, diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 344196a8ce..23eb5522b6 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7332,7 +7332,7 @@ static const struct SysemuCPUOps ppc_sysemu_ops = { #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps ppc_tcg_ops = { +static const TCGCPUOps ppc_tcg_ops = { .initialize = ppc_translate_init, .restore_state_to_opc = ppc_restore_state_to_opc, diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 994ca1cdf9..b7da92783b 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -129,7 +129,7 @@ static void riscv_restore_state_to_opc(CPUState *cs, env->bins = data[1]; } -static const struct TCGCPUOps riscv_tcg_ops = { +static const TCGCPUOps riscv_tcg_ops = { .initialize = riscv_translate_init, .synchronize_from_tb = riscv_cpu_synchronize_from_tb, .restore_state_to_opc = riscv_restore_state_to_opc, diff --git a/target/rx/cpu.c b/target/rx/cpu.c index de1cc7a5e6..cfc97d06e7 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -192,7 +192,7 @@ static const struct SysemuCPUOps rx_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps rx_tcg_ops = { +static const TCGCPUOps rx_tcg_ops = { .initialize = rx_translate_init, .synchronize_from_tb = rx_cpu_synchronize_from_tb, .restore_state_to_opc = rx_restore_state_to_opc, diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index db1590472e..b783e1e2e6 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -372,7 +372,7 @@ static void s390_cpu_reset_full(DeviceState *dev) #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps s390_tcg_ops = { +static const TCGCPUOps s390_tcg_ops = { .initialize = s390x_translate_init, .restore_state_to_opc = s390x_restore_state_to_opc, diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index eb7eb6f30a..89a42e0e22 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -265,7 +265,7 @@ static const struct SysemuCPUOps sh4_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps superh_tcg_ops = { +static const TCGCPUOps superh_tcg_ops = { .initialize = sh4_translate_init, .synchronize_from_tb = superh_cpu_synchronize_from_tb, .restore_state_to_opc = superh_restore_state_to_opc, diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 99d57cc209..8385c8a2b0 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -935,7 +935,7 @@ static const struct SysemuCPUOps sparc_sysemu_ops = { #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps sparc_tcg_ops = { +static const TCGCPUOps sparc_tcg_ops = { .initialize = sparc_tcg_init, .synchronize_from_tb = sparc_cpu_synchronize_from_tb, .restore_state_to_opc = sparc_restore_state_to_opc, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index dff88184c9..2f07fdbfab 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -190,7 +190,7 @@ static const struct SysemuCPUOps tricore_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps tricore_tcg_ops = { +static const TCGCPUOps tricore_tcg_ops = { .initialize = tricore_tcg_init, .synchronize_from_tb = tricore_cpu_synchronize_from_tb, .restore_state_to_opc = tricore_restore_state_to_opc, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index dfe0ff5c98..0da5409742 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -294,7 +294,7 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = { #include "hw/core/tcg-cpu-ops.h" -static const struct TCGCPUOps xtensa_tcg_ops = { +static const TCGCPUOps xtensa_tcg_ops = { .initialize = xtensa_translate_init, .debug_excp_handler = xtensa_breakpoint_handler, .restore_state_to_opc = xtensa_restore_state_to_opc, From patchwork Sun Jan 28 04:42:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767212 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp347888wro; Sat, 27 Jan 2024 20:44:38 -0800 (PST) X-Google-Smtp-Source: AGHT+IG6Iawk8bv28M26w658TOp0RGTW4IQx7zQ8AU7Diu3ZaRnE2fzbDhO2hcYvxie/IhxcRUf2 X-Received: by 2002:a05:620a:2099:b0:783:8c8a:fe4d with SMTP id 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 27/33] target/loongarch: Constify loongarch_tcg_ops Date: Sun, 28 Jan 2024 14:42:07 +1000 Message-Id: <20240128044213.316480-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::835; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x835.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/loongarch/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index d9ddab5b9a..d663d46b00 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -758,7 +758,7 @@ void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags) #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" -static TCGCPUOps loongarch_tcg_ops = { +static const TCGCPUOps loongarch_tcg_ops = { .initialize = loongarch_translate_init, .synchronize_from_tb = loongarch_cpu_synchronize_from_tb, .restore_state_to_opc = loongarch_restore_state_to_opc, From patchwork Sun Jan 28 04:42:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767209 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp347753wro; Sat, 27 Jan 2024 20:43:58 -0800 (PST) X-Google-Smtp-Source: AGHT+IHCMhkON7NMMW7yRiQyd15qwL0+yYjOiDT3x6A99zjcw5UxLMbgzT/5frzJsh1Vlc7vVwCK X-Received: by 2002:a05:6214:1711:b0:68c:3cbc:f4fa with SMTP id db17-20020a056214171100b0068c3cbcf4famr2169900qvb.12.1706417037811; Sat, 27 Jan 2024 20:43:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706417037; cv=none; d=google.com; s=arc-20160816; b=GaBp3ejWqvydUe3QxJZJ9SKL40qlmw+SnB+na4+OdUAePXabAZwOHMu5Kip+k1zHe9 swbMSQtcmkaoxeXqkkl1wQmxJd8q/2VqQhcCBpRUmQcOfTInhoZuPoOCqS3WZ6Dq/Eos 2nkjKuoJPFPUtadERVtzrqEilWt7dhru6Bqj2iBXedv6uPR2I7lTr1U+OdEDbj57wiQB RJdoeM+BWhcn21OVdccDdnIRxeJY4/a+71/EwVSbrx/3bGZHnnJiAUkFhtyBjyzoq73i dX44gL++2zwMetziocS4ex+W2BUJHM8/UcVE0cj8dUziGaqN3D0WKKH51XrjB/NxPTsd IDPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=7BY3FC/8lb12NjJs4/taRcBSMiYCFRNyNU57iKW6Ebg=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=HQ69L2spzryPidf1Odm4rGNB317h89chDI1sgV8852j95//0VE9QwVy/vz+BgofRnV sMd5ntj3ZtkkXhZsQQY2M3dVfY4fA4VQpmSHLgrACf+C6lYPEFuQArm36F3f81QuKCnV ZER8uBP0ViJxBoFYAWnQJEKqeQT8Jbz5C3Lipii1gjT6uspRR6T+OgRS+fZqUeCriZ39 KhhDph4bLH1g6k6qpWXte+RP4ll9kqXMHZs6W9L+K58nUlVPnXjYkTYwEZEibYKEDiIm 2wAXwqfpgg4EcXBmBtQ1+KH57xtCCW7+32GFVKalVSfpkAvucZPfR2TdZ7+IusTRi67T a52g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Rk6V89Na; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 28/33] accel/tcg: Use CPUState.cc instead of CPU_GET_CLASS in cpu-exec.c Date: Sun, 28 Jan 2024 14:42:08 +1000 Message-Id: <20240128044213.316480-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::832; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x832.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org CPU_GET_CLASS does runtime type checking; use the cached copy of the class instead. Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 109 ++++++++++++++++++++++--------------------- 1 file changed, 56 insertions(+), 53 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index f2535a2991..3aebf46849 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -343,9 +343,9 @@ static bool check_for_breakpoints_slow(CPUState *cpu, vaddr pc, #ifdef CONFIG_USER_ONLY g_assert_not_reached(); #else - CPUClass *cc = CPU_GET_CLASS(cpu); - assert(cc->tcg_ops->debug_check_breakpoint); - match_bp = cc->tcg_ops->debug_check_breakpoint(cpu); + const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; + assert(tcg_ops->debug_check_breakpoint); + match_bp = tcg_ops->debug_check_breakpoint(cpu); #endif } @@ -462,10 +462,11 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit) * counter hit zero); we must restore the guest PC to the address * of the start of the TB. */ - CPUClass *cc = CPU_GET_CLASS(cpu); + CPUClass *cc = cpu->cc; + const TCGCPUOps *tcg_ops = cc->tcg_ops; - if (cc->tcg_ops->synchronize_from_tb) { - cc->tcg_ops->synchronize_from_tb(cpu, last_tb); + if (tcg_ops->synchronize_from_tb) { + tcg_ops->synchronize_from_tb(cpu, last_tb); } else { tcg_debug_assert(!(tb_cflags(last_tb) & CF_PCREL)); assert(cc->set_pc); @@ -497,19 +498,19 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit) static void cpu_exec_enter(CPUState *cpu) { - CPUClass *cc = CPU_GET_CLASS(cpu); + const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; - if (cc->tcg_ops->cpu_exec_enter) { - cc->tcg_ops->cpu_exec_enter(cpu); + if (tcg_ops->cpu_exec_enter) { + tcg_ops->cpu_exec_enter(cpu); } } static void cpu_exec_exit(CPUState *cpu) { - CPUClass *cc = CPU_GET_CLASS(cpu); + const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; - if (cc->tcg_ops->cpu_exec_exit) { - cc->tcg_ops->cpu_exec_exit(cpu); + if (tcg_ops->cpu_exec_exit) { + tcg_ops->cpu_exec_exit(cpu); } } @@ -685,7 +686,7 @@ static inline bool cpu_handle_halt(CPUState *cpu) static inline void cpu_handle_debug_exception(CPUState *cpu) { - CPUClass *cc = CPU_GET_CLASS(cpu); + const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; CPUWatchpoint *wp; if (!cpu->watchpoint_hit) { @@ -694,8 +695,8 @@ static inline void cpu_handle_debug_exception(CPUState *cpu) } } - if (cc->tcg_ops->debug_excp_handler) { - cc->tcg_ops->debug_excp_handler(cpu); + if (tcg_ops->debug_excp_handler) { + tcg_ops->debug_excp_handler(cpu); } } @@ -712,6 +713,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret) #endif return false; } + if (cpu->exception_index >= EXCP_INTERRUPT) { /* exit request from the cpu execution loop */ *ret = cpu->exception_index; @@ -720,43 +722,45 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret) } cpu->exception_index = -1; return true; - } else { -#if defined(CONFIG_USER_ONLY) - /* if user mode only, we simulate a fake exception - which will be handled outside the cpu execution - loop */ -#if defined(TARGET_I386) - CPUClass *cc = CPU_GET_CLASS(cpu); - cc->tcg_ops->fake_user_interrupt(cpu); -#endif /* TARGET_I386 */ - *ret = cpu->exception_index; - cpu->exception_index = -1; - return true; -#else - if (replay_exception()) { - CPUClass *cc = CPU_GET_CLASS(cpu); - bql_lock(); - cc->tcg_ops->do_interrupt(cpu); - bql_unlock(); - cpu->exception_index = -1; + } - if (unlikely(cpu->singlestep_enabled)) { - /* - * After processing the exception, ensure an EXCP_DEBUG is - * raised when single-stepping so that GDB doesn't miss the - * next instruction. - */ - *ret = EXCP_DEBUG; - cpu_handle_debug_exception(cpu); - return true; - } - } else if (!replay_has_interrupt()) { - /* give a chance to iothread in replay mode */ - *ret = EXCP_INTERRUPT; +#if defined(CONFIG_USER_ONLY) + /* + * If user mode only, we simulate a fake exception which will be + * handled outside the cpu execution loop. + */ +#if defined(TARGET_I386) + const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; + tcg_ops->fake_user_interrupt(cpu); +#endif /* TARGET_I386 */ + *ret = cpu->exception_index; + cpu->exception_index = -1; + return true; +#else + if (replay_exception()) { + const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; + + bql_lock(); + tcg_ops->do_interrupt(cpu); + bql_unlock(); + cpu->exception_index = -1; + + if (unlikely(cpu->singlestep_enabled)) { + /* + * After processing the exception, ensure an EXCP_DEBUG is + * raised when single-stepping so that GDB doesn't miss the + * next instruction. + */ + *ret = EXCP_DEBUG; + cpu_handle_debug_exception(cpu); return true; } -#endif + } else if (!replay_has_interrupt()) { + /* give a chance to iothread in replay mode */ + *ret = EXCP_INTERRUPT; + return true; } +#endif return false; } @@ -856,10 +860,10 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, True when it is, and we should restart on a new TB, and via longjmp via cpu_loop_exit. */ else { - CPUClass *cc = CPU_GET_CLASS(cpu); + const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; - if (cc->tcg_ops->cpu_exec_interrupt && - cc->tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) { + if (tcg_ops->cpu_exec_interrupt && + tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) { if (need_replay_interrupt(interrupt_request)) { replay_interrupt(); } @@ -1078,10 +1082,9 @@ int cpu_exec(CPUState *cpu) bool tcg_exec_realizefn(CPUState *cpu, Error **errp) { static bool tcg_target_initialized; - CPUClass *cc = CPU_GET_CLASS(cpu); if (!tcg_target_initialized) { - cc->tcg_ops->initialize(); + cpu->cc->tcg_ops->initialize(); tcg_target_initialized = true; } From patchwork Sun Jan 28 04:42:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767216 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp347955wro; Sat, 27 Jan 2024 20:45:00 -0800 (PST) X-Google-Smtp-Source: AGHT+IFs5xWtwO/39mNFaI3Nvu21TT9AYbneqCgfCTRgQBdW8Wun9DeYNi0Bk5xJ54TBPnfiJq6l X-Received: by 2002:ac8:57c9:0:b0:42a:4246:3b32 with SMTP id w9-20020ac857c9000000b0042a42463b32mr3492100qta.45.1706417100171; Sat, 27 Jan 2024 20:45:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706417100; cv=none; d=google.com; s=arc-20160816; b=EOMq4hxzUSo+PS9Jrnfq4s1qV8FeR1WodTH4awN2TKpfqmR2nLggkYn0EMcajYjMRL STmlOmpJ+8Mts6X5lyRefj44MToE+1cRAXyWHXHWfhUrMYatDRfMxrLueLB6jcRwTdjq SL+ifq3qDcxV5C8kvSzda5rct/ZpAhALOUDM+o8mOfVhipMq76ja/Bmy88y9iXiCsH1A Z9wNorjuiQoF02uZobOo5iBktCWgtYZzwRW7Qjlo5b4Fu+7W5r5axpGpWif2wzCoD8QT 8DFla15pu+WgiELMMXQQGcPgRtMONzOD75c1F4u7GX8zfRwcWazJhfgU8Co1kA+vPQC5 LApg== ARC-Message-Signature: i=1; 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Anton Johansson , Pavel Dovgalyuk Subject: [PATCH 29/33] accel/tcg: Introduce TCGCPUOps::need_replay_interrupt() handler Date: Sun, 28 Jan 2024 14:42:09 +1000 Message-Id: <20240128044213.316480-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c29; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé In order to make accel/tcg/ target agnostic, introduce the need_replay_interrupt() handler. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Anton Johansson Reviewed-by: Pavel Dovgalyuk Message-Id: <20240124101639.30056-7-philmd@linaro.org> Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 5 +++++ accel/tcg/cpu-exec.c | 8 +++++--- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 3ed279836f..013867b890 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -166,6 +166,11 @@ struct TCGCPUOps { */ bool (*io_recompile_replay_branch)(CPUState *cpu, const TranslationBlock *tb); + /** + * @need_replay_interrupt: Return %true if @interrupt_request + * needs to be recorded for replay purposes. + */ + bool (*need_replay_interrupt)(int interrupt_request); #endif /* !CONFIG_USER_ONLY */ #endif /* NEED_CPU_H */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 3aebf46849..34d10eb173 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -771,12 +771,14 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret) * "real" interrupt event later. It does not need to be recorded for * replay purposes. */ -static inline bool need_replay_interrupt(int interrupt_request) +static inline bool need_replay_interrupt(CPUState *cpu, int interrupt_request) { #if defined(TARGET_I386) return !(interrupt_request & CPU_INTERRUPT_POLL); #else - return true; + const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; + return !tcg_ops->need_replay_interrupt + || tcg_ops->need_replay_interrupt(interrupt_request); #endif } #endif /* !CONFIG_USER_ONLY */ @@ -864,7 +866,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, if (tcg_ops->cpu_exec_interrupt && tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) { - if (need_replay_interrupt(interrupt_request)) { + if (need_replay_interrupt(cpu, interrupt_request)) { replay_interrupt(); } /* From patchwork Sun Jan 28 04:42:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767220 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp348064wro; Sat, 27 Jan 2024 20:45:26 -0800 (PST) X-Google-Smtp-Source: AGHT+IFkAb0wGCGx0hqh0UnTudZVBJUnE6c0EbNlnwh/0JuijofqkjkqTXrTTS/sGNVCHh63e/wc X-Received: by 2002:ad4:4eaf:0:b0:68c:3df8:735e with SMTP id ed15-20020ad44eaf000000b0068c3df8735emr3119078qvb.63.1706417126045; Sat, 27 Jan 2024 20:45:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706417126; cv=none; d=google.com; s=arc-20160816; b=BZ023so5DZdV7FY20f//vqkNZcRTy/8cocxFAqx3EGS3GhKfPkxr8fHi5KmLMpT/tN BZuGQyQCEbxbgNdseOzONf2m4kDgwt1pab8tXI+tlPSuKdqTFHbxsi/TGIon2dVZuDIv kpTQVuvGN0hjQMixBgxj2wXd8f9lpJBiRJPj15Sc0PBFKELo8dc5WA3nHg+BdGgsQaJh HDRlKPuQ8BH9Djpr9yQpTGiwM3pGLPSsmbuk15xHmqQ6m5daYWk12a9VgfW5FIvh00h/ TGrdwfgHp6tUuyUANkUkHc26l86isAhkeTTvHqMG4T0HXyyT+zjHuR/QUeMlYNM5eQcK Rl2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=4tMFQE97q4aUbL8LMPU5R9Llk18uVwdymUNm4iTykmc=; fh=HPaGXKsmKghdmujZ6SN7T9DPluDP/5SUmo+zFc4N+Vk=; b=WsymPMnvyeFGPEXpXJFrqkkYSAoL+S2G2/2U4aKieFbpMqZW3LnppgkzjrRWAvZP/9 eicqD1RSk5ZJz9Mvvk5i+BtxBvVXI3Tc8rML5dG46IRmyX2TuJMpq0+ddkSkzWT9dC3w t6Q4TZNLABIU2fP7NAIPKSVfdzcyvmIE6ykK5/LyDKRdLMeReX2VFc2X0sP4M0chMi8g cfzytWUeb/IYGoGwplYgZ80TG9XkQNJyOMSDPsHPYA+fiveoG0u959lmZ2z6uuzaf9tA HODknb+PpGbe51xDZ9i0zCdhD/MC3AXWU5ic0N4WrsorSpmhbH0niXY9omdCxO5tvnX8 sYtQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WsWMU4Ae; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Anton Johansson , Pavel Dovgalyuk Subject: [PATCH 30/33] target/i386: Extract x86_need_replay_interrupt() from accel/tcg/ Date: Sun, 28 Jan 2024 14:42:10 +1000 Message-Id: <20240128044213.316480-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Move this x86-specific code out of the generic accel/tcg/. Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Reviewed-by: Pavel Dovgalyuk Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20240124101639.30056-8-philmd@linaro.org> Signed-off-by: Richard Henderson --- target/i386/tcg/helper-tcg.h | 1 + accel/tcg/cpu-exec.c | 4 ---- target/i386/tcg/sysemu/seg_helper.c | 10 ++++++++++ target/i386/tcg/tcg-cpu.c | 1 + 4 files changed, 12 insertions(+), 4 deletions(-) diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index ce34b737bb..253b1f561e 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -39,6 +39,7 @@ QEMU_BUILD_BUG_ON(TCG_PHYS_ADDR_BITS > TARGET_PHYS_ADDR_SPACE_BITS); */ void x86_cpu_do_interrupt(CPUState *cpu); #ifndef CONFIG_USER_ONLY +bool x86_need_replay_interrupt(int interrupt_request); bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); #endif diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 34d10eb173..2eacd694ea 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -773,13 +773,9 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret) */ static inline bool need_replay_interrupt(CPUState *cpu, int interrupt_request) { -#if defined(TARGET_I386) - return !(interrupt_request & CPU_INTERRUPT_POLL); -#else const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; return !tcg_ops->need_replay_interrupt || tcg_ops->need_replay_interrupt(interrupt_request); -#endif } #endif /* !CONFIG_USER_ONLY */ diff --git a/target/i386/tcg/sysemu/seg_helper.c b/target/i386/tcg/sysemu/seg_helper.c index 1cb5a0db45..e6f42282bb 100644 --- a/target/i386/tcg/sysemu/seg_helper.c +++ b/target/i386/tcg/sysemu/seg_helper.c @@ -127,6 +127,16 @@ void x86_cpu_do_interrupt(CPUState *cs) } } +bool x86_need_replay_interrupt(int interrupt_request) +{ + /* + * CPU_INTERRUPT_POLL is a virtual event which gets converted into a + * "real" interrupt event later. It does not need to be recorded for + * replay purposes. + */ + return !(interrupt_request & CPU_INTERRUPT_POLL); +} + bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { X86CPU *cpu = X86_CPU(cs); diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 8e148e9bc4..5bdcf45199 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -123,6 +123,7 @@ static const TCGCPUOps x86_tcg_ops = { .do_unaligned_access = x86_cpu_do_unaligned_access, .debug_excp_handler = breakpoint_handler, .debug_check_breakpoint = x86_debug_check_breakpoint, + .need_replay_interrupt = x86_need_replay_interrupt, #endif /* !CONFIG_USER_ONLY */ }; From patchwork Sun Jan 28 04:42:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767237 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp348395wro; Sat, 27 Jan 2024 20:47:23 -0800 (PST) X-Google-Smtp-Source: AGHT+IH8TV30vTWMr42rwrMAcxm0+dFKT0mpukbLlng4ohOHuDV1Gtkp76VsvXz+t/Vhx9lRJcNP X-Received: by 2002:a05:620a:21c9:b0:783:6e9a:6597 with SMTP id h9-20020a05620a21c900b007836e9a6597mr3056464qka.141.1706417243209; Sat, 27 Jan 2024 20:47:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706417243; cv=none; d=google.com; s=arc-20160816; b=oeg628kEKsWMK83Uxi2En0ID50s7TPwLN8K+MsP7Wk2o8GnQBkgFLlARtiOqDU2OYd Ya73w4FpsQ1DmYfF3vDj/CnGkYb9LkW8zCR/+Aq9VotygZCW8+dD/L6rOqOL7JDecbmx LRrnm7YBrZk8m2ucHVvxMiqAXBaBUAphK7b/ptV5Za3IkHc+/loRqC8rHe8YTnLLZ54S rO5r5H/o7g8DChhPB/t0Jp8Ys5CVFQt05CPpcPLdvMmlOQttg7kcyqMMBX5f6i4LGlBa iK+dHbliSBvgxE3SXV1lKvhPYbpBejkBolPFl2/RrvMASC+p08eHXvIcXCTAL2NDUGIm 1aQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=2hwCZNX7r6WcP/DB6F59Yv2bYfXzcZik2wXoCrV2EBg=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=lNW/Sehurc7WbZKah+aI15wl16WuGfZRC2x6Z0H1YvRe6pRpO1V/pcfCWtfgkay20q ZTI2i7bmI8dV74FtrJGbsOYv5vFyK1r57acR/eNa/6QwBMu3z9vsFGqIQkB8lgXfOusc w9XBnF/jtlnoADsr9W9ZyGRWAChGPr+gQlu1O00NbK70BZERw3VgbfQZOKlHg9Cd6Ng8 PAwaU7eazO2wN6Ha0AzaWDkyxcVSJC/Ggc14KyuN2mqHew1CU0ajXiWVmAoxRq/orz9H d2aku5OuOsQqZsYItRdZCfvx9FlWPhPYq3QdSS9FE1y8jhrbNgbKuSnAVTIO1qPXOi0c M5dg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ygmUA1MP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 31/33] accel/tcg: Inline need_replay_interrupt Date: Sun, 28 Jan 2024 14:42:11 +1000 Message-Id: <20240128044213.316480-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c33; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc33.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The function is now trivial, and with inlining we can re-use the calling function's tcg_ops variable. Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 17 ++--------------- 1 file changed, 2 insertions(+), 15 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 2eacd694ea..75f7ba7bed 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -765,20 +765,6 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret) return false; } -#ifndef CONFIG_USER_ONLY -/* - * CPU_INTERRUPT_POLL is a virtual event which gets converted into a - * "real" interrupt event later. It does not need to be recorded for - * replay purposes. - */ -static inline bool need_replay_interrupt(CPUState *cpu, int interrupt_request) -{ - const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; - return !tcg_ops->need_replay_interrupt - || tcg_ops->need_replay_interrupt(interrupt_request); -} -#endif /* !CONFIG_USER_ONLY */ - static inline bool icount_exit_request(CPUState *cpu) { if (!icount_enabled()) { @@ -862,7 +848,8 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, if (tcg_ops->cpu_exec_interrupt && tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) { - if (need_replay_interrupt(cpu, interrupt_request)) { + if (!tcg_ops->need_replay_interrupt || + tcg_ops->need_replay_interrupt(interrupt_request)) { replay_interrupt(); } /* From patchwork Sun Jan 28 04:42:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767236 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp348351wro; Sat, 27 Jan 2024 20:47:07 -0800 (PST) X-Google-Smtp-Source: AGHT+IFLvzSWF5YFvDkN1wCQs+jcwh81iiiqiXlgcr590ZMhxO9HW2bwYDva4Rwn6H4+/CCL/Wuc X-Received: by 2002:a05:6214:d84:b0:685:28b6:4e55 with SMTP id e4-20020a0562140d8400b0068528b64e55mr3021711qve.79.1706417227649; Sat, 27 Jan 2024 20:47:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706417227; cv=none; d=google.com; s=arc-20160816; b=zx4FjkxJryZKRBNCeFdhkY/1dmKDMiolmXSap8FJnOD+TDhkTaor6cEXHj7xbi7gWG Hc2QI3HBuktxGnT/PEWIID6wIrp3rknKhCheLp1dk3EQLwp15hv5E27WlQftuIELDRxM LHleB4JwdkghHaTx6Uu5X7vlGEy0UjeHqFwSWmW5+vDispAqIB1gThZvnUPzj0tFUAlQ vhJ+Vsweqbr70jw2EIGccQ4UcyvzkAPBRKFwjTeyVYPKYAh62KzrTxtZZgvL+N3qwxQe 64vnCpcBsTn4CRcSc7/W48m0No6NW6vQ+RLG6AWOzFAKpiEYekY465rrzr+zNUIVf0H2 9RBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=LMqE9xBix0QLmyhH8Xqft/09pdbioiePfeACz0Kfp3o=; fh=HGG5jZNhe8Q+zQJ9+mddel2c/xsqW3vEoqbd78QYiOw=; b=ChHy2ZIPohhFIayHw/ku2d63wIo2qNA4VYBTUOvLzfMaUzYzZhf6tVWbRV4QhJeEoa wtp3QGdmyXgqgD3WlGQF/YA6KazJphZt0/i3Z+UkQ93mFH2MdnW7BhWPeh3uuLqfSisK e6jZuY/d7AprnrKu3kopxgcaw64Vjy+2CuHhHheAOd3z67pCBxvucAVvxnjaPs8c/Z0U 1vR6uwuAAoujV4GN6Qe5319qaE1vS0cAGmI56ba/32S5yNezdYvalugmmbb3XhJecoFN zJ9J9Sfh/t30PBnOjzynDrMI5PArGDpIzSvBHOp5H8MJSfwHSKrQaLz7P5cqjwQqK6d7 k1MQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yWyFvs5G; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Anton Johansson Subject: [PATCH 32/33] accel/tcg: Introduce TCGCPUOps::cpu_exec_halt() handler Date: Sun, 28 Jan 2024 14:42:12 +1000 Message-Id: <20240128044213.316480-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé In order to make accel/tcg/ target agnostic, introduce the cpu_exec_halt() handler. Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20240124101639.30056-9-philmd@linaro.org> Signed-off-by: Richard Henderson --- include/hw/core/tcg-cpu-ops.h | 2 ++ accel/tcg/cpu-exec.c | 5 +++++ 2 files changed, 7 insertions(+) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 013867b890..bf8ff8e3ee 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -112,6 +112,8 @@ struct TCGCPUOps { void (*do_interrupt)(CPUState *cpu); /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); + /** @cpu_exec_halt: Callback for handling halt in cpu_exec */ + void (*cpu_exec_halt)(CPUState *cpu); /** * @tlb_fill: Handle a softmmu tlb miss * diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 75f7ba7bed..82627b12b8 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -664,6 +664,8 @@ static inline bool cpu_handle_halt(CPUState *cpu) { #ifndef CONFIG_USER_ONLY if (cpu->halted) { + const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; + #if defined(TARGET_I386) if (cpu->interrupt_request & CPU_INTERRUPT_POLL) { X86CPU *x86_cpu = X86_CPU(cpu); @@ -673,6 +675,9 @@ static inline bool cpu_handle_halt(CPUState *cpu) bql_unlock(); } #endif /* TARGET_I386 */ + if (tcg_ops->cpu_exec_halt) { + tcg_ops->cpu_exec_halt(cpu); + } if (!cpu_has_work(cpu)) { return true; } From patchwork Sun Jan 28 04:42:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 767227 Delivered-To: patch@linaro.org Received: by 2002:adf:ee41:0:b0:33a:e5bd:fedd with SMTP id w1csp348170wro; Sat, 27 Jan 2024 20:46:06 -0800 (PST) X-Google-Smtp-Source: AGHT+IEza0ns8Ef/JEZSDVEsQRoo82yZ6UIT4yyUGRKhHTG+yyEAc1344+crCL3pRydaxI1xHaIu X-Received: by 2002:a05:622a:199e:b0:42a:898c:16fa with SMTP id u30-20020a05622a199e00b0042a898c16famr2770473qtc.63.1706417165759; Sat, 27 Jan 2024 20:46:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706417165; cv=none; d=google.com; s=arc-20160816; b=rqKYu1B/CvtqULotbVPMc5nZ4ajE2XpZlRD1eJjB+iJxIMqRjolvnwyTuBZzDMgspY h+pbBA3cSEuLoTKhfxlQ2l/hhR8GOPkE2nuEf3XwZrad6c+gM3uoCgkz/2f0w+1k2nPh S6aBQnVV72COUFKyB7Ih8RTqDGvXxQoD0E7LrOMC4aKnjRIveqMngDHd+xLW5ehmPGkQ g10Gat7Te9kjHHB8Xv8XqxGwL8bTXdY0+Mvpeep7FS2OTEb9C2o0p7p8spn+xzZNtu/d rL/1q5TWNPnYU5wZvUiH95kYHX/WJ8IycH2dV/smtTSMpd7eG6pv2Iep+gH8EoY24ecz 7mtg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=T/uaC3GU2r5ag1NYLRtG0R3ws3tDO6FtLPMPWrHI/7I=; fh=HGG5jZNhe8Q+zQJ9+mddel2c/xsqW3vEoqbd78QYiOw=; b=y0DOxSMOkUlYfJsS03/dlqPyPaRdFRRUORNYpOBXEEJdanAcVb8N+Yl+SKTVcqwIX9 GpE5fwHXTbMALat6fqId76DYi4l8TE4gW5rkzBWNkYah/X8zBCifASEh1UtsGzEy37UL Ea5yTs649KcVnqJOqHWPrUAybuCu9ZU/ALcnkgZmVl2pfmz8kPWKvFVAU2rNdluCd7lP rNrbceOOI1VLfpF/R2FToC6vfjsBqq0AU4Rn3RsNHGeNcUnZuZt8tM9PjK5LUjO7pk1G qjmP7GxFd7/qWzCgeJlDd4LU7PJqNXs8gWJ+19aBeVjUP4s0mhklta8b4tNg0IDKOydi KdYg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CNxCRIli; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[121.45.131.89]) by smtp.gmail.com with ESMTPSA id w24-20020a17090aaf9800b002906e09e1d1sm5631873pjq.18.2024.01.27.20.43.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 20:43:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Anton Johansson Subject: [PATCH 33/33] target/i386: Extract x86_cpu_exec_halt() from accel/tcg/ Date: Sun, 28 Jan 2024 14:42:13 +1000 Message-Id: <20240128044213.316480-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240128044213.316480-1-richard.henderson@linaro.org> References: <20240128044213.316480-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Move this x86-specific code out of the generic accel/tcg/. Reported-by: Anton Johansson Reviewed-by: Anton Johansson Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20240124101639.30056-10-philmd@linaro.org> Signed-off-by: Richard Henderson --- target/i386/tcg/helper-tcg.h | 1 + accel/tcg/cpu-exec.c | 12 ------------ target/i386/tcg/sysemu/seg_helper.c | 13 +++++++++++++ target/i386/tcg/tcg-cpu.c | 1 + 4 files changed, 15 insertions(+), 12 deletions(-) diff --git a/target/i386/tcg/helper-tcg.h b/target/i386/tcg/helper-tcg.h index 253b1f561e..effc2c1c98 100644 --- a/target/i386/tcg/helper-tcg.h +++ b/target/i386/tcg/helper-tcg.h @@ -39,6 +39,7 @@ QEMU_BUILD_BUG_ON(TCG_PHYS_ADDR_BITS > TARGET_PHYS_ADDR_SPACE_BITS); */ void x86_cpu_do_interrupt(CPUState *cpu); #ifndef CONFIG_USER_ONLY +void x86_cpu_exec_halt(CPUState *cpu); bool x86_need_replay_interrupt(int interrupt_request); bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); #endif diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 82627b12b8..977576ca14 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -30,9 +30,6 @@ #include "qemu/rcu.h" #include "exec/log.h" #include "qemu/main-loop.h" -#if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY) -#include "hw/i386/apic.h" -#endif #include "sysemu/cpus.h" #include "exec/cpu-all.h" #include "sysemu/cpu-timers.h" @@ -666,15 +663,6 @@ static inline bool cpu_handle_halt(CPUState *cpu) if (cpu->halted) { const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops; -#if defined(TARGET_I386) - if (cpu->interrupt_request & CPU_INTERRUPT_POLL) { - X86CPU *x86_cpu = X86_CPU(cpu); - bql_lock(); - apic_poll_irq(x86_cpu->apic_state); - cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL); - bql_unlock(); - } -#endif /* TARGET_I386 */ if (tcg_ops->cpu_exec_halt) { tcg_ops->cpu_exec_halt(cpu); } diff --git a/target/i386/tcg/sysemu/seg_helper.c b/target/i386/tcg/sysemu/seg_helper.c index e6f42282bb..2db8083748 100644 --- a/target/i386/tcg/sysemu/seg_helper.c +++ b/target/i386/tcg/sysemu/seg_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" +#include "qemu/main-loop.h" #include "cpu.h" #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" @@ -127,6 +128,18 @@ void x86_cpu_do_interrupt(CPUState *cs) } } +void x86_cpu_exec_halt(CPUState *cpu) +{ + if (cpu->interrupt_request & CPU_INTERRUPT_POLL) { + X86CPU *x86_cpu = X86_CPU(cpu); + + bql_lock(); + apic_poll_irq(x86_cpu->apic_state); + cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL); + bql_unlock(); + } +} + bool x86_need_replay_interrupt(int interrupt_request) { /* diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 5bdcf45199..cca19cd40e 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -119,6 +119,7 @@ static const TCGCPUOps x86_tcg_ops = { #else .tlb_fill = x86_cpu_tlb_fill, .do_interrupt = x86_cpu_do_interrupt, + .cpu_exec_halt = x86_cpu_exec_halt, .cpu_exec_interrupt = x86_cpu_exec_interrupt, .do_unaligned_access = x86_cpu_do_unaligned_access, .debug_excp_handler = breakpoint_handler,