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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:42 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/36] target/xtensa: fix OOB TLB entry access Date: Fri, 26 Jan 2024 14:33:06 +0000 Message-Id: <20240126143341.2101237-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Max Filippov r[id]tlb[01], [iw][id]tlb opcodes use TLB way index passed in a register by the guest. The host uses 3 bits of the index for ITLB indexing and 4 bits for DTLB, but there's only 7 entries in the ITLB array and 10 in the DTLB array, so a malicious guest may trigger out-of-bound access to these arrays. Change split_tlb_entry_spec return type to bool to indicate whether TLB way passed to it is valid. Change get_tlb_entry to return NULL in case invalid TLB way is requested. Add assertion to xtensa_tlb_get_entry that requested TLB way and entry indices are valid. Add checks to the [rwi]tlb helpers that requested TLB way is valid and return 0 or do nothing when it's not. Cc: qemu-stable@nongnu.org Fixes: b67ea0cd7441 ("target-xtensa: implement memory protection options") Signed-off-by: Max Filippov Reviewed-by: Peter Maydell Message-id: 20231215120307.545381-1-jcmvbkbc@gmail.com Signed-off-by: Peter Maydell --- target/xtensa/mmu_helper.c | 47 ++++++++++++++++++++++++++++---------- 1 file changed, 35 insertions(+), 12 deletions(-) diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index 12552a33470..2fda4e887cc 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -224,22 +224,31 @@ static void split_tlb_entry_spec_way(const CPUXtensaState *env, uint32_t v, * Split TLB address into TLB way, entry index and VPN (with index). * See ISA, 4.6.5.5 - 4.6.5.8 for the TLB addressing format */ -static void split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb, - uint32_t *vpn, uint32_t *wi, uint32_t *ei) +static bool split_tlb_entry_spec(CPUXtensaState *env, uint32_t v, bool dtlb, + uint32_t *vpn, uint32_t *wi, uint32_t *ei) { if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { *wi = v & (dtlb ? 0xf : 0x7); - split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei); + if (*wi < (dtlb ? env->config->dtlb.nways : env->config->itlb.nways)) { + split_tlb_entry_spec_way(env, v, dtlb, vpn, *wi, ei); + return true; + } else { + return false; + } } else { *vpn = v & REGION_PAGE_MASK; *wi = 0; *ei = (v >> 29) & 0x7; + return true; } } static xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env, bool dtlb, unsigned wi, unsigned ei) { + const xtensa_tlb *tlb = dtlb ? &env->config->dtlb : &env->config->itlb; + + assert(wi < tlb->nways && ei < tlb->way_size[wi]); return dtlb ? env->dtlb[wi] + ei : env->itlb[wi] + ei; @@ -252,11 +261,14 @@ static xtensa_tlb_entry *get_tlb_entry(CPUXtensaState *env, uint32_t wi; uint32_t ei; - split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei); - if (pwi) { - *pwi = wi; + if (split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei)) { + if (pwi) { + *pwi = wi; + } + return xtensa_tlb_get_entry(env, dtlb, wi, ei); + } else { + return NULL; } - return xtensa_tlb_get_entry(env, dtlb, wi, ei); } static void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env, @@ -482,7 +494,12 @@ uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { uint32_t wi; const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi); - return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid; + + if (entry) { + return (entry->vaddr & get_vpn_mask(env, dtlb, wi)) | entry->asid; + } else { + return 0; + } } else { return v & REGION_PAGE_MASK; } @@ -491,7 +508,12 @@ uint32_t HELPER(rtlb0)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) uint32_t HELPER(rtlb1)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) { const xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, NULL); - return entry->paddr | entry->attr; + + if (entry) { + return entry->paddr | entry->attr; + } else { + return 0; + } } void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) @@ -499,7 +521,7 @@ void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb) if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) { uint32_t wi; xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi); - if (entry->variable && entry->asid) { + if (entry && entry->variable && entry->asid) { tlb_flush_page(env_cpu(env), entry->vaddr); entry->asid = 0; } @@ -537,8 +559,9 @@ void HELPER(wtlb)(CPUXtensaState *env, uint32_t p, uint32_t v, uint32_t dtlb) uint32_t vpn; uint32_t wi; uint32_t ei; - split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei); - xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p); + if (split_tlb_entry_spec(env, v, dtlb, &vpn, &wi, &ei)) { + xtensa_tlb_set_entry(env, dtlb, wi, ei, vpn, p); + } } /*! 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/36] target/arm: Fix VNCR fault detection logic Date: Fri, 26 Jan 2024 14:33:07 +0000 Message-Id: <20240126143341.2101237-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In arm_deliver_fault() we check for whether the fault is caused by a data abort due to an access to a FEAT_NV2 sysreg in the memory pointed to by the VNCR. Unfortunately part of the condition checks the wrong argument to the function, meaning that it would spuriously trigger, resulting in some instruction aborts being taken to the wrong EL and reported incorrectly. Use the right variable in the condition. Fixes: 674e5345275d425 ("target/arm: Report VNCR_EL2 based faults correctly") Reported-by: Jonathan Cameron Signed-off-by: Peter Maydell Tested-by: Jonathan Cameron Reviewed-by: Jonathan Cameron Message-id: 20240116165605.2523055-1-peter.maydell@linaro.org --- target/arm/tcg/tlb_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index dd5de74ffb7..5477c7fb7dc 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -184,7 +184,7 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, * (and indeed syndrome does not have the EC field in it, * because we masked that out in disas_set_insn_syndrome()) */ - bool is_vncr = (mmu_idx != MMU_INST_FETCH) && + bool is_vncr = (access_type != MMU_INST_FETCH) && (env->exception.syndrome & ARM_EL_VNCR); if (is_vncr) { From patchwork Fri Jan 26 14:33:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766345 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp266688wrb; Fri, 26 Jan 2024 06:34:55 -0800 (PST) X-Google-Smtp-Source: AGHT+IHskFCF5/SsSsGPRdNPg4wgq4HsVQlcwnvc+PAteKc5Dfn+mPAB7oz/W5HSwypkbx8BiM3T X-Received: by 2002:a05:620a:1448:b0:783:c881:679f with SMTP id i8-20020a05620a144800b00783c881679fmr1474984qkl.52.1706279695101; Fri, 26 Jan 2024 06:34:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706279695; cv=none; d=google.com; s=arc-20160816; b=BMAbQzQwQ35MKSxhgrQ9D6+NGSjlUyKu327Bc31nCvzqCQCUReotI+h4mq3FUbq0at uWUAiFOIZ3OrrHKg7/ekwXIiPhHn/KkwTgWN8RzDNqdFAWacz+XsJGgveWX+MU7yTKfg BK/ezH2SR4/m5dtF90fr/8sh7S0/JNvj9PPWcGovHBtfk8UKO0RlMlbAtPpMHOUsspoM 9AE6w+6nUTpFRx8yVNJg0UzKDfEUNF4F3zdUgeziU3qOlbKzKWZi2UvUOHukql4JDS+r 0jGvTTCLeHVTvpHIz2kTn7DWqJP0BlyRPeatE28EOXQa5xqzuwb22A4EReRdrkrAXWYP Cdww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=M6SHCWbrZ+mqpOFqOLQgsC9xtK67Vc6rtoI9yN+xnY0=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=FxPQ4z1GHMNxKNnwUCiYPDzYskwZimZhIAaS3DCt0IaNxSBaBFIZq9Xeq59uv6ppGr /+ye44DLtRH+SQ7EJ8a6CE09i4TfuOUq7cw4/E2G3SJFhSC6Z3EuBPqvJElpoHgDJSDs BV9tpiTN1FDAV/cbsRg5J9n0QC2VUVRAar1SDQzplskxAivNfM6qtdbLa9NKA+ehiR8s 4Y67GciwGlqfG717vvujMSllAeAGopjAmf80YKFh8HfK4lFrqd0aodPG2nwZ6+o2F7jU JQqdNSx2Ri2+P3Q51zoSu7LlBFFetTCmnixbIs5mT4iSs393Gi0V5qGGm0EJM3ktWYWz bL0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HRR83KHa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/36] hw/arm/virt.c: Remove newline from error_report() string Date: Fri, 26 Jan 2024 14:33:08 +0000 Message-Id: <20240126143341.2101237-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org error_report() strings should not include trailing newlines; remove the newline from the error we print when devices won't fit into the address space of the CPU. This commit also fixes the accidental hardcoded tabs that were in this line, since we have to touch the line anyway. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Message-id: 20240118131649.2726375-1-peter.maydell@linaro.org --- hw/arm/virt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 5cbc69dff83..ed4ed9f4142 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1771,8 +1771,8 @@ static void virt_set_memmap(VirtMachineState *vms, int pa_bits) /* Base address of the high IO region */ memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB); if (memtop > BIT_ULL(pa_bits)) { - error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes\n", - pa_bits, memtop - BIT_ULL(pa_bits)); + error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes", + pa_bits, memtop - BIT_ULL(pa_bits)); exit(EXIT_FAILURE); } if (base < device_memory_base) { From patchwork Fri Jan 26 14:33:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766368 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp268111wrb; Fri, 26 Jan 2024 06:38:17 -0800 (PST) X-Google-Smtp-Source: AGHT+IHZfcJ325Fw8skVmEeJQdpdiYxfQ31kGpYN8v/VfnHEqS80n4xRi7rYVECa6zLQvPW89WOu X-Received: by 2002:a05:6122:1817:b0:4bd:6323:fd16 with SMTP id ay23-20020a056122181700b004bd6323fd16mr689885vkb.22.1706279896851; Fri, 26 Jan 2024 06:38:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706279896; cv=none; d=google.com; s=arc-20160816; b=CbiFDt3ljnTdb/NWbBmPftDhjuBw+fL4KHZx4uQdohEQNc/ronTmmqK1Ij3qKn0k8M v5L4Z4P8HXNFCpmjcDRdOpEzvl7SrKvD6Xl7u7PZj4bBHiaGvAxM69GPV5jUUxFq6z8J tvWQbwYg+HPLJGKl6hYwTp0O0UdFfra/TW+TpWooGhwGCVV2K9RsHHub4Fp1N+cB1/Eq w/eu7pxs4qgO6IfkInP3XRk9WuSOfbrgmkQJPj9pQRXb9ycGgMJwK1TYeKtvn3Grd9rB CtOM4qp2MJ65M4AjmOXnvP+XOrJteu4y4EmkDMsVxlvv0jqRTAUkrtyy6laczMmzbpp2 qZ2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=FgvQRpsiH5zpwPcK6Oo54VoqD9iaIo5i9dZssiG51CE=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=z84CiHqXCqZ0PL8pwvz6FibRIGqh6+A4CfJklIdpW+lHRW4Zv/s/zaBz1XHUEChrho t94Gm1XpokIbNbouK2kI8U2FSXsUkuPEk1UYTs52HAdl3RjxbgBTmmYkIB1k5ew045u2 NxEg1AyOgkopO4xvIZIYWY9F2Mk5/X8de2yEM9p6vWASQv24sxGlcv1Q3XHmyim5INIx jYFS00a0SLk0WWaW4hYw8SLQ+P5gmMd9PjJYZmpyZp7ZvXQSOqiwZxSRD5B1a9kVhXwX XsLvY5XhbnXTDTz4cC66yXTLo/l4OHComJ0L2Niyk0AOQ29lwkaIZdcQbaP4gW18g4N3 cVPw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SBT0neLZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/36] hw/arm/musicpal: Convert to qemu_add_kbd_event_handler() Date: Fri, 26 Jan 2024 14:33:09 +0000 Message-Id: <20240126143341.2101237-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Convert the musicpal key input device to use qemu_add_kbd_event_handler(). This lets us simplify it because we no longer need to track whether we're in the middle of a PS/2 multibyte key sequence. In the conversion we move the keyboard handler registration from init to realize, because devices shouldn't disturb the state of the simulation by doing things like registering input handlers until they're realized, so that device objects can be introspected safely. The behaviour where key-repeat is permitted for the arrow-keys only is intentional (added in commit 7c6ce4baedfcd0c), so we retain it, and add a comment to that effect. This is a migration compatibility break for musicpal. Signed-off-by: Peter Maydell Tested-by: Alex Bennée Reviewed-by: Alex Bennée Message-id: 20231103182750.855577-1-peter.maydell@linaro.org --- hw/arm/musicpal.c | 131 +++++++++++++++++++++------------------------- 1 file changed, 61 insertions(+), 70 deletions(-) diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index 3200c9f68ac..6987472871e 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -1043,20 +1043,6 @@ static const TypeInfo musicpal_gpio_info = { }; /* Keyboard codes & masks */ -#define KEY_RELEASED 0x80 -#define KEY_CODE 0x7f - -#define KEYCODE_TAB 0x0f -#define KEYCODE_ENTER 0x1c -#define KEYCODE_F 0x21 -#define KEYCODE_M 0x32 - -#define KEYCODE_EXTENDED 0xe0 -#define KEYCODE_UP 0x48 -#define KEYCODE_DOWN 0x50 -#define KEYCODE_LEFT 0x4b -#define KEYCODE_RIGHT 0x4d - #define MP_KEY_WHEEL_VOL (1 << 0) #define MP_KEY_WHEEL_VOL_INV (1 << 1) #define MP_KEY_WHEEL_NAV (1 << 2) @@ -1074,67 +1060,66 @@ struct musicpal_key_state { SysBusDevice parent_obj; /*< public >*/ - uint32_t kbd_extended; uint32_t pressed_keys; qemu_irq out[8]; }; -static void musicpal_key_event(void *opaque, int keycode) +static void musicpal_key_event(DeviceState *dev, QemuConsole *src, + InputEvent *evt) { - musicpal_key_state *s = opaque; + musicpal_key_state *s = MUSICPAL_KEY(dev); + InputKeyEvent *key = evt->u.key.data; + int qcode = qemu_input_key_value_to_qcode(key->key); uint32_t event = 0; int i; - if (keycode == KEYCODE_EXTENDED) { - s->kbd_extended = 1; - return; + switch (qcode) { + case Q_KEY_CODE_UP: + event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV; + break; + + case Q_KEY_CODE_DOWN: + event = MP_KEY_WHEEL_NAV; + break; + + case Q_KEY_CODE_LEFT: + event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV; + break; + + case Q_KEY_CODE_RIGHT: + event = MP_KEY_WHEEL_VOL; + break; + + case Q_KEY_CODE_F: + event = MP_KEY_BTN_FAVORITS; + break; + + case Q_KEY_CODE_TAB: + event = MP_KEY_BTN_VOLUME; + break; + + case Q_KEY_CODE_RET: + event = MP_KEY_BTN_NAVIGATION; + break; + + case Q_KEY_CODE_M: + event = MP_KEY_BTN_MENU; + break; } - if (s->kbd_extended) { - switch (keycode & KEY_CODE) { - case KEYCODE_UP: - event = MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_NAV_INV; - break; - - case KEYCODE_DOWN: - event = MP_KEY_WHEEL_NAV; - break; - - case KEYCODE_LEFT: - event = MP_KEY_WHEEL_VOL | MP_KEY_WHEEL_VOL_INV; - break; - - case KEYCODE_RIGHT: - event = MP_KEY_WHEEL_VOL; - break; - } - } else { - switch (keycode & KEY_CODE) { - case KEYCODE_F: - event = MP_KEY_BTN_FAVORITS; - break; - - case KEYCODE_TAB: - event = MP_KEY_BTN_VOLUME; - break; - - case KEYCODE_ENTER: - event = MP_KEY_BTN_NAVIGATION; - break; - - case KEYCODE_M: - event = MP_KEY_BTN_MENU; - break; - } - /* Do not repeat already pressed buttons */ - if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) { + /* + * We allow repeated wheel-events when the arrow keys are held down, + * but do not repeat already-pressed buttons for the other key inputs. + */ + if (!(event & (MP_KEY_WHEEL_NAV | MP_KEY_WHEEL_VOL))) { + if (key->down && (s->pressed_keys & event)) { event = 0; } } if (event) { /* Raise GPIO pin first if repeating a key */ - if (!(keycode & KEY_RELEASED) && (s->pressed_keys & event)) { + if (key->down && (s->pressed_keys & event)) { for (i = 0; i <= 7; i++) { if (event & (1 << i)) { qemu_set_irq(s->out[i], 1); @@ -1143,17 +1128,15 @@ static void musicpal_key_event(void *opaque, int keycode) } for (i = 0; i <= 7; i++) { if (event & (1 << i)) { - qemu_set_irq(s->out[i], !!(keycode & KEY_RELEASED)); + qemu_set_irq(s->out[i], !key->down); } } - if (keycode & KEY_RELEASED) { - s->pressed_keys &= ~event; - } else { + if (key->down) { s->pressed_keys |= event; + } else { + s->pressed_keys &= ~event; } } - - s->kbd_extended = 0; } static void musicpal_key_init(Object *obj) @@ -1162,20 +1145,27 @@ static void musicpal_key_init(Object *obj) DeviceState *dev = DEVICE(sbd); musicpal_key_state *s = MUSICPAL_KEY(dev); - s->kbd_extended = 0; s->pressed_keys = 0; qdev_init_gpio_out(dev, s->out, ARRAY_SIZE(s->out)); +} - qemu_add_kbd_event_handler(musicpal_key_event, s); +static const QemuInputHandler musicpal_key_handler = { + .name = "musicpal_key", + .mask = INPUT_EVENT_MASK_KEY, + .event = musicpal_key_event, +}; + +static void musicpal_key_realize(DeviceState *dev, Error **errp) +{ + qemu_input_handler_register(dev, &musicpal_key_handler); } static const VMStateDescription musicpal_key_vmsd = { .name = "musicpal_key", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (const VMStateField[]) { - VMSTATE_UINT32(kbd_extended, musicpal_key_state), VMSTATE_UINT32(pressed_keys, musicpal_key_state), VMSTATE_END_OF_LIST() } @@ -1186,6 +1176,7 @@ static void musicpal_key_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); dc->vmsd = &musicpal_key_vmsd; + dc->realize = musicpal_key_realize; } static const TypeInfo musicpal_key_info = { From patchwork Fri Jan 26 14:33:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766351 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp266848wrb; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/36] hw/arm/allwinner-a10: Unconditionally map the USB Host controllers Date: Fri, 26 Jan 2024 14:33:10 +0000 Message-Id: <20240126143341.2101237-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé The USB Controllers are part of the chipset, thus are always present and mapped in memory. This is a migration compatibility break for the cubieboard machine started with the '-usb none' option. Reported-by: Guenter Roeck Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Guenter Roeck Tested-by: Guenter Roeck Message-id: 20240119215106.45776-2-philmd@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/allwinner-a10.c | 49 +++++++++++++++++------------------------- 1 file changed, 20 insertions(+), 29 deletions(-) diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c index b0ea3f7f662..0135632996c 100644 --- a/hw/arm/allwinner-a10.c +++ b/hw/arm/allwinner-a10.c @@ -79,15 +79,10 @@ static void aw_a10_init(Object *obj) object_initialize_child(obj, "i2c0", &s->i2c0, TYPE_AW_I2C); - if (machine_usb(current_machine)) { - int i; - - for (i = 0; i < AW_A10_NUM_USB; i++) { - object_initialize_child(obj, "ehci[*]", &s->ehci[i], - TYPE_PLATFORM_EHCI); - object_initialize_child(obj, "ohci[*]", &s->ohci[i], - TYPE_SYSBUS_OHCI); - } + for (size_t i = 0; i < AW_A10_NUM_USB; i++) { + object_initialize_child(obj, "ehci[*]", &s->ehci[i], + TYPE_PLATFORM_EHCI); + object_initialize_child(obj, "ohci[*]", &s->ohci[i], TYPE_SYSBUS_OHCI); } object_initialize_child(obj, "mmc0", &s->mmc0, TYPE_AW_SDHOST_SUN4I); @@ -165,28 +160,24 @@ static void aw_a10_realize(DeviceState *dev, Error **errp) qdev_get_gpio_in(dev, 1), 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); - if (machine_usb(current_machine)) { - int i; + for (size_t i = 0; i < AW_A10_NUM_USB; i++) { + g_autofree char *bus = g_strdup_printf("usb-bus.%zu", i); - for (i = 0; i < AW_A10_NUM_USB; i++) { - g_autofree char *bus = g_strdup_printf("usb-bus.%d", i); + object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable", + true, &error_fatal); + sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, + AW_A10_EHCI_BASE + i * 0x8000); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, + qdev_get_gpio_in(dev, 39 + i)); - object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable", - true, &error_fatal); - sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, - AW_A10_EHCI_BASE + i * 0x8000); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, - qdev_get_gpio_in(dev, 39 + i)); - - object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", bus, - &error_fatal); - sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_fatal); - sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0, - AW_A10_OHCI_BASE + i * 0x8000); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0, - qdev_get_gpio_in(dev, 64 + i)); - } + object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", bus, + &error_fatal); + sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0, + AW_A10_OHCI_BASE + i * 0x8000); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0, + qdev_get_gpio_in(dev, 64 + i)); } /* SD/MMC */ From patchwork Fri Jan 26 14:33:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766363 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp267697wrb; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/36] hw/arm/nseries: Unconditionally map the TUSB6010 USB Host controller Date: Fri, 26 Jan 2024 14:33:11 +0000 Message-Id: <20240126143341.2101237-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé The TUSB6010 USB controller is soldered on the N800 and N810 tablets, thus is always present. This is a migration compatibility break for the n800/n810 machines started with the '-usb none' option. Signed-off-by: Philippe Mathieu-Daudé Message-id: 20240119215106.45776-3-philmd@linaro.org [PMM: fixed commit message typo] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/nseries.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c index 35aff46b4b4..35deb74f655 100644 --- a/hw/arm/nseries.c +++ b/hw/arm/nseries.c @@ -1353,9 +1353,7 @@ static void n8x0_init(MachineState *machine, n8x0_spi_setup(s); n8x0_dss_setup(s); n8x0_cbus_setup(s); - if (machine_usb(machine)) { - n8x0_usb_setup(s); - } + n8x0_usb_setup(s); if (machine->kernel_filename) { /* Or at the linux loader. */ From patchwork Fri Jan 26 14:33:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766358 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp267238wrb; Fri, 26 Jan 2024 06:36:09 -0800 (PST) X-Google-Smtp-Source: AGHT+IHxEOgjNveNnvrSnns2x1W8dV2NdhL+nrcs72AwnVwKmqoMtJ7FHUhmnb70A8R1qrqvoLse X-Received: by 2002:a05:620a:1486:b0:781:407b:9ae0 with SMTP id w6-20020a05620a148600b00781407b9ae0mr1797116qkj.48.1706279769459; Fri, 26 Jan 2024 06:36:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706279769; cv=none; d=google.com; s=arc-20160816; b=jWwLf7a86FmVCQfLwX9qDqmkfxmApIyDga8Yj1fElnQMcxI/uTmT6iERIViB77af6I ztFaXO012S+2hWwDBGi8KbGFRqieyKkoppNBQeUEAQBGg5I2WKA0Oe4FDBu5L4QFa5wD SaH5okgw4KNL+1+kTBxyE3y50lhxgZrfdrPrYk9vOh9MUTYkrJirPrT5NIJbSRnWy6RV NS9+dke1JGouRu1u+V+mbY+0sXOjCe7+2VU2gICe+8wTrBkfe1HAuoVy6ZHoECEqKXLC OrccQB4Kv6zFeXkd+P/7lcOzn4SWF3uHKWGms76dFsnaTccIWM+1fh2LZj8AV1Sw99WA oBKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=lK9uzbOPuqI5nBpCiVJSQd+IeQXNzZSi8eQru0HuK+4=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=K1BJFm5WXnn/wmhSZCB53GULTrQRVkredkx3SsqBMfYXpaR8teg/1BRj54Nl12HDak oURD0h991QldgIffuFkG1dicKiKu0uifBjttCpXGur14Cor1B9sB3kJuRQj+eNQKRme9 /Rep4ZmaEZuIOCVskGYPwtzZCcLbAjrIO6JWnPmIgfMeoUh/Y8qBhcynXF5rqWlgdS+w KWxYB0d/C8lKuqo98yhjSOWJiaREotgXI8jXfQS3sBcv/yJVtsz2QOzl9rwqWRs8JyMh bp8O9jI0tN9C0pVCGJtLMXp7mtye4/qEKzKKWC5aOiTSNKhx9hSndccbYP3c5+PP63MG e5jw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jF+FcIz1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/36] hw/arm: Add EHCI/OHCI controllers to Allwinner R40 and Bananapi board Date: Fri, 26 Jan 2024 14:33:12 +0000 Message-Id: <20240126143341.2101237-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, WEIRD_QUOTING=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Guenter Roeck Allwinner R40 supports two USB host ports shared between a USB 2.0 EHCI host controller and a USB 1.1 OHCI host controller. Add support for both of them. If machine USB support is not enabled, create unimplemented devices for the USB memory ranges to avoid crashes when booting Linux. Signed-off-by: Guenter Roeck Reviewed-by: Philippe Mathieu-Daudé Message-id: 20240115182757.1095012-2-linux@roeck-us.net Signed-off-by: Peter Maydell --- docs/system/arm/bananapi_m2u.rst | 2 +- include/hw/arm/allwinner-r40.h | 9 ++++++ hw/arm/allwinner-r40.c | 47 ++++++++++++++++++++++++++++++-- hw/arm/Kconfig | 2 ++ 4 files changed, 57 insertions(+), 3 deletions(-) diff --git a/docs/system/arm/bananapi_m2u.rst b/docs/system/arm/bananapi_m2u.rst index b09ba5c5486..e77c425e2cb 100644 --- a/docs/system/arm/bananapi_m2u.rst +++ b/docs/system/arm/bananapi_m2u.rst @@ -23,6 +23,7 @@ The Banana Pi M2U machine supports the following devices: * GMAC ethernet * Clock Control Unit * TWI (I2C) + * USB 2.0 Limitations """"""""""" @@ -33,7 +34,6 @@ Currently, Banana Pi M2U does *not* support the following features: - Audio output - Hardware Watchdog - Real Time Clock -- USB 2.0 interfaces Also see the 'unimplemented' array in the Allwinner R40 SoC module for a complete list of unimplemented I/O devices: ``./hw/arm/allwinner-r40.c`` diff --git a/include/hw/arm/allwinner-r40.h b/include/hw/arm/allwinner-r40.h index 6e1ac9d4c13..ae82822d424 100644 --- a/include/hw/arm/allwinner-r40.h +++ b/include/hw/arm/allwinner-r40.h @@ -30,6 +30,8 @@ #include "hw/i2c/allwinner-i2c.h" #include "hw/net/allwinner_emac.h" #include "hw/net/allwinner-sun8i-emac.h" +#include "hw/usb/hcd-ohci.h" +#include "hw/usb/hcd-ehci.h" #include "target/arm/cpu.h" #include "sysemu/block-backend.h" @@ -44,6 +46,10 @@ enum { AW_R40_DEV_MMC1, AW_R40_DEV_MMC2, AW_R40_DEV_MMC3, + AW_R40_DEV_EHCI1, + AW_R40_DEV_OHCI1, + AW_R40_DEV_EHCI2, + AW_R40_DEV_OHCI2, AW_R40_DEV_CCU, AW_R40_DEV_PIT, AW_R40_DEV_UART0, @@ -88,6 +94,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(AwR40State, AW_R40) * which are currently emulated by the R40 SoC code. */ #define AW_R40_NUM_MMCS 4 +#define AW_R40_NUM_USB 2 #define AW_R40_NUM_UARTS 8 struct AwR40State { @@ -106,6 +113,8 @@ struct AwR40State { AwSRAMCState sramc; AwA10PITState timer; AwSdHostState mmc[AW_R40_NUM_MMCS]; + EHCISysBusState ehci[AW_R40_NUM_USB]; + OHCISysBusState ohci[AW_R40_NUM_USB]; AwR40ClockCtlState ccu; AwR40DramCtlState dramc; AWI2CState i2c0; diff --git a/hw/arm/allwinner-r40.c b/hw/arm/allwinner-r40.c index a0d367c60d1..2e8943eff74 100644 --- a/hw/arm/allwinner-r40.c +++ b/hw/arm/allwinner-r40.c @@ -23,6 +23,7 @@ #include "qemu/bswap.h" #include "qemu/module.h" #include "qemu/units.h" +#include "hw/boards.h" #include "hw/qdev-core.h" #include "hw/sysbus.h" #include "hw/char/serial.h" @@ -45,6 +46,10 @@ const hwaddr allwinner_r40_memmap[] = { [AW_R40_DEV_MMC1] = 0x01c10000, [AW_R40_DEV_MMC2] = 0x01c11000, [AW_R40_DEV_MMC3] = 0x01c12000, + [AW_R40_DEV_EHCI1] = 0x01c19000, + [AW_R40_DEV_OHCI1] = 0x01c19400, + [AW_R40_DEV_EHCI2] = 0x01c1c000, + [AW_R40_DEV_OHCI2] = 0x01c1c400, [AW_R40_DEV_CCU] = 0x01c20000, [AW_R40_DEV_PIT] = 0x01c20c00, [AW_R40_DEV_UART0] = 0x01c28000, @@ -89,9 +94,9 @@ static struct AwR40Unimplemented r40_unimplemented[] = { { "crypto", 0x01c15000, 4 * KiB }, { "spi2", 0x01c17000, 4 * KiB }, { "sata", 0x01c18000, 4 * KiB }, - { "usb1-host", 0x01c19000, 4 * KiB }, + { "usb1-phy", 0x01c19800, 2 * KiB }, { "sid", 0x01c1b000, 4 * KiB }, - { "usb2-host", 0x01c1c000, 4 * KiB }, + { "usb2-phy", 0x01c1c800, 2 * KiB }, { "cs1", 0x01c1d000, 4 * KiB }, { "spi3", 0x01c1f000, 4 * KiB }, { "rtc", 0x01c20400, 1 * KiB }, @@ -181,6 +186,10 @@ enum { AW_R40_GIC_SPI_MMC2 = 34, AW_R40_GIC_SPI_MMC3 = 35, AW_R40_GIC_SPI_EMAC = 55, + AW_R40_GIC_SPI_OHCI1 = 64, + AW_R40_GIC_SPI_OHCI2 = 65, + AW_R40_GIC_SPI_EHCI1 = 76, + AW_R40_GIC_SPI_EHCI2 = 78, AW_R40_GIC_SPI_GMAC = 85, }; @@ -276,6 +285,13 @@ static void allwinner_r40_init(Object *obj) TYPE_AW_SDHOST_SUN50I_A64); } + for (size_t i = 0; i < AW_R40_NUM_USB; i++) { + object_initialize_child(obj, "ehci[*]", &s->ehci[i], + TYPE_PLATFORM_EHCI); + object_initialize_child(obj, "ohci[*]", &s->ohci[i], + TYPE_SYSBUS_OHCI); + } + object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C_SUN6I); object_initialize_child(obj, "emac", &s->emac, TYPE_AW_EMAC); @@ -407,6 +423,33 @@ static void allwinner_r40_realize(DeviceState *dev, Error **errp) sysbus_realize(SYS_BUS_DEVICE(&s->ccu), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_R40_DEV_CCU]); + /* USB */ + for (size_t i = 0; i < AW_R40_NUM_USB; i++) { + g_autofree char *bus = g_strdup_printf("usb-bus.%zu", i); + + object_property_set_bool(OBJECT(&s->ehci[i]), "companion-enable", true, + &error_fatal); + sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, + allwinner_r40_memmap[i ? AW_R40_DEV_EHCI2 + : AW_R40_DEV_EHCI1]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, + qdev_get_gpio_in(DEVICE(&s->gic), + i ? AW_R40_GIC_SPI_EHCI2 + : AW_R40_GIC_SPI_EHCI1)); + + object_property_set_str(OBJECT(&s->ohci[i]), "masterbus", bus, + &error_fatal); + sysbus_realize(SYS_BUS_DEVICE(&s->ohci[i]), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0, + allwinner_r40_memmap[i ? AW_R40_DEV_OHCI2 + : AW_R40_DEV_OHCI1]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0, + qdev_get_gpio_in(DEVICE(&s->gic), + i ? AW_R40_GIC_SPI_OHCI2 + : AW_R40_GIC_SPI_OHCI1)); + } + /* SD/MMC */ for (int i = 0; i < AW_R40_NUM_MMCS; i++) { qemu_irq irq = qdev_get_gpio_in(DEVICE(&s->gic), diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 218b454e97f..4a2a5fca974 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -415,6 +415,8 @@ config ALLWINNER_R40 select ARM_TIMER select ARM_GIC select UNIMP + select USB_OHCI + select USB_EHCI_SYSBUS select SD config RASPI From patchwork Fri Jan 26 14:33:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766354 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp266997wrb; Fri, 26 Jan 2024 06:35:37 -0800 (PST) X-Google-Smtp-Source: AGHT+IFtuIHK9YIYvXC0jwwDD+SDF+2PsP7wXOhwRoMr57atVjrt1yYnCINcaUaGeC+2XbUzMhkg X-Received: by 2002:a05:620a:1451:b0:783:3900:335b with SMTP id i17-20020a05620a145100b007833900335bmr1446311qkl.38.1706279737289; Fri, 26 Jan 2024 06:35:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706279737; cv=none; d=google.com; s=arc-20160816; b=Y5oQlDaJ1l9hJgw2IKAvmb0Y/1plKRfOT2m56VdNj9Phq5Yz4Cfpn8jeK4j9rVZlXa aDUSDuc39/ph4RDTsWfNgnazwe7qTrErG6ncL2/qDeP1mZq2+NkocV/fsAoyNUov16f5 b8/CZ1PwtqCAf+FvtwiYMTHeo2Se5RBCxc+aLqVylnpYeuemyo1P4uCbgw70x68KtnuH bo0vbZTKWa3ly9ZUkAX4gbdOwsUqh+p9fE4xhVaW0Ci28sOTTAIuyxT4qgIAdry5NoTt Gc/dvG+8hFpCGba2ugDXJuPswK+UJOsT+EBSF+DUGTJGC1aGrXnVFRJy7gWkd/TJAQUy ET5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=HEc7i4Xgpnf10j5Y5ryc8bAt0O15wFZx7gUBthUTBOc=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=xPluzUg/i9dOgD58nkQozbnjy4O0cSkTZ9qEVjbtIuX19enwpiPYK0ah+T7P+2WBtd p7poa7C4K3M6gPPEUMIrWmCAJHB3KHsHkvVhN6uDly181+TK5bvjMuTr/eL5UzUd+7DH h5mzWBiDzE1WP3UKw52A5GbiZ5at2aEAEaF6aVwkQjp/XjJqYQ1hmXY/VA8c5uP3tioP 7HHZJ+cX6W7NQ8Kqu6hK/fR5xGO2Zp3F31NGMnIot4V5W7b4k6bh7oFWtcAAKPq+wr4n iaJItdaND8oCcxdn7lU8NYkKTGkIZKGsZDUiWQGl8D25Fg3/Dw93so7DSh9Pi+ND+ql7 /SIw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LXA1JhHa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/36] hw/arm: Add AHCI/SATA controller to Allwinner R40 and Bananapi board Date: Fri, 26 Jan 2024 14:33:13 +0000 Message-Id: <20240126143341.2101237-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Guenter Roeck Allwinner R40 supports an AHCI compliant SATA controller. Add support for it. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Guenter Roeck Message-id: 20240115182757.1095012-3-linux@roeck-us.net Signed-off-by: Peter Maydell --- docs/system/arm/bananapi_m2u.rst | 1 + include/hw/arm/allwinner-r40.h | 3 +++ hw/arm/allwinner-r40.c | 12 +++++++++++- hw/arm/Kconfig | 1 + 4 files changed, 16 insertions(+), 1 deletion(-) diff --git a/docs/system/arm/bananapi_m2u.rst b/docs/system/arm/bananapi_m2u.rst index e77c425e2cb..542310591d6 100644 --- a/docs/system/arm/bananapi_m2u.rst +++ b/docs/system/arm/bananapi_m2u.rst @@ -22,6 +22,7 @@ The Banana Pi M2U machine supports the following devices: * EMAC ethernet * GMAC ethernet * Clock Control Unit + * SATA * TWI (I2C) * USB 2.0 diff --git a/include/hw/arm/allwinner-r40.h b/include/hw/arm/allwinner-r40.h index ae82822d424..c589fcc1c15 100644 --- a/include/hw/arm/allwinner-r40.h +++ b/include/hw/arm/allwinner-r40.h @@ -22,6 +22,7 @@ #include "qom/object.h" #include "hw/timer/allwinner-a10-pit.h" +#include "hw/ide/ahci.h" #include "hw/intc/arm_gic.h" #include "hw/sd/allwinner-sdhost.h" #include "hw/misc/allwinner-r40-ccu.h" @@ -46,6 +47,7 @@ enum { AW_R40_DEV_MMC1, AW_R40_DEV_MMC2, AW_R40_DEV_MMC3, + AW_R40_DEV_AHCI, AW_R40_DEV_EHCI1, AW_R40_DEV_OHCI1, AW_R40_DEV_EHCI2, @@ -112,6 +114,7 @@ struct AwR40State { const hwaddr *memmap; AwSRAMCState sramc; AwA10PITState timer; + AllwinnerAHCIState sata; AwSdHostState mmc[AW_R40_NUM_MMCS]; EHCISysBusState ehci[AW_R40_NUM_USB]; OHCISysBusState ohci[AW_R40_NUM_USB]; diff --git a/hw/arm/allwinner-r40.c b/hw/arm/allwinner-r40.c index 2e8943eff74..534be4a735d 100644 --- a/hw/arm/allwinner-r40.c +++ b/hw/arm/allwinner-r40.c @@ -46,6 +46,7 @@ const hwaddr allwinner_r40_memmap[] = { [AW_R40_DEV_MMC1] = 0x01c10000, [AW_R40_DEV_MMC2] = 0x01c11000, [AW_R40_DEV_MMC3] = 0x01c12000, + [AW_R40_DEV_AHCI] = 0x01c18000, [AW_R40_DEV_EHCI1] = 0x01c19000, [AW_R40_DEV_OHCI1] = 0x01c19400, [AW_R40_DEV_EHCI2] = 0x01c1c000, @@ -93,7 +94,6 @@ static struct AwR40Unimplemented r40_unimplemented[] = { { "usb0-host", 0x01c14000, 4 * KiB }, { "crypto", 0x01c15000, 4 * KiB }, { "spi2", 0x01c17000, 4 * KiB }, - { "sata", 0x01c18000, 4 * KiB }, { "usb1-phy", 0x01c19800, 2 * KiB }, { "sid", 0x01c1b000, 4 * KiB }, { "usb2-phy", 0x01c1c800, 2 * KiB }, @@ -186,6 +186,7 @@ enum { AW_R40_GIC_SPI_MMC2 = 34, AW_R40_GIC_SPI_MMC3 = 35, AW_R40_GIC_SPI_EMAC = 55, + AW_R40_GIC_SPI_AHCI = 56, AW_R40_GIC_SPI_OHCI1 = 64, AW_R40_GIC_SPI_OHCI2 = 65, AW_R40_GIC_SPI_EHCI1 = 76, @@ -285,6 +286,8 @@ static void allwinner_r40_init(Object *obj) TYPE_AW_SDHOST_SUN50I_A64); } + object_initialize_child(obj, "sata", &s->sata, TYPE_ALLWINNER_AHCI); + for (size_t i = 0; i < AW_R40_NUM_USB; i++) { object_initialize_child(obj, "ehci[*]", &s->ehci[i], TYPE_PLATFORM_EHCI); @@ -423,6 +426,13 @@ static void allwinner_r40_realize(DeviceState *dev, Error **errp) sysbus_realize(SYS_BUS_DEVICE(&s->ccu), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_R40_DEV_CCU]); + /* SATA / AHCI */ + sysbus_realize(SYS_BUS_DEVICE(&s->sata), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, + allwinner_r40_memmap[AW_R40_DEV_AHCI]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, + qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_AHCI)); + /* USB */ for (size_t i = 0; i < AW_R40_NUM_USB; i++) { g_autofree char *bus = g_strdup_printf("usb-bus.%zu", i); diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 4a2a5fca974..704517edd4f 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -408,6 +408,7 @@ config ALLWINNER_H3 config ALLWINNER_R40 bool default y if TCG && ARM + select AHCI select ALLWINNER_SRAMC select ALLWINNER_A10_PIT select AXP2XX_PMU From patchwork Fri Jan 26 14:33:14 2024 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:46 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/36] hw/arm: Add watchdog timer to Allwinner H40 and Bananapi board Date: Fri, 26 Jan 2024 14:33:14 +0000 Message-Id: <20240126143341.2101237-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, WEIRD_QUOTING=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Guenter Roeck Add watchdog timer support to Allwinner-H40 and Bananapi. The watchdog timer is added as an overlay to the Timer module memory map. Signed-off-by: Guenter Roeck Reviewed-by: Strahinja Jankovic Message-id: 20240115182757.1095012-4-linux@roeck-us.net Signed-off-by: Peter Maydell --- docs/system/arm/bananapi_m2u.rst | 2 +- include/hw/arm/allwinner-r40.h | 3 +++ hw/arm/allwinner-r40.c | 8 ++++++++ hw/arm/Kconfig | 1 + 4 files changed, 13 insertions(+), 1 deletion(-) diff --git a/docs/system/arm/bananapi_m2u.rst b/docs/system/arm/bananapi_m2u.rst index 542310591d6..587b4886553 100644 --- a/docs/system/arm/bananapi_m2u.rst +++ b/docs/system/arm/bananapi_m2u.rst @@ -25,6 +25,7 @@ The Banana Pi M2U machine supports the following devices: * SATA * TWI (I2C) * USB 2.0 + * Hardware Watchdog Limitations """"""""""" @@ -33,7 +34,6 @@ Currently, Banana Pi M2U does *not* support the following features: - Graphical output via HDMI, GPU and/or the Display Engine - Audio output -- Hardware Watchdog - Real Time Clock Also see the 'unimplemented' array in the Allwinner R40 SoC module diff --git a/include/hw/arm/allwinner-r40.h b/include/hw/arm/allwinner-r40.h index c589fcc1c15..66c38e7d907 100644 --- a/include/hw/arm/allwinner-r40.h +++ b/include/hw/arm/allwinner-r40.h @@ -33,6 +33,7 @@ #include "hw/net/allwinner-sun8i-emac.h" #include "hw/usb/hcd-ohci.h" #include "hw/usb/hcd-ehci.h" +#include "hw/watchdog/allwinner-wdt.h" #include "target/arm/cpu.h" #include "sysemu/block-backend.h" @@ -54,6 +55,7 @@ enum { AW_R40_DEV_OHCI2, AW_R40_DEV_CCU, AW_R40_DEV_PIT, + AW_R40_DEV_WDT, AW_R40_DEV_UART0, AW_R40_DEV_UART1, AW_R40_DEV_UART2, @@ -114,6 +116,7 @@ struct AwR40State { const hwaddr *memmap; AwSRAMCState sramc; AwA10PITState timer; + AwWdtState wdt; AllwinnerAHCIState sata; AwSdHostState mmc[AW_R40_NUM_MMCS]; EHCISysBusState ehci[AW_R40_NUM_USB]; diff --git a/hw/arm/allwinner-r40.c b/hw/arm/allwinner-r40.c index 534be4a735d..a28e5b3886a 100644 --- a/hw/arm/allwinner-r40.c +++ b/hw/arm/allwinner-r40.c @@ -53,6 +53,7 @@ const hwaddr allwinner_r40_memmap[] = { [AW_R40_DEV_OHCI2] = 0x01c1c400, [AW_R40_DEV_CCU] = 0x01c20000, [AW_R40_DEV_PIT] = 0x01c20c00, + [AW_R40_DEV_WDT] = 0x01c20c90, [AW_R40_DEV_UART0] = 0x01c28000, [AW_R40_DEV_UART1] = 0x01c28400, [AW_R40_DEV_UART2] = 0x01c28800, @@ -279,6 +280,8 @@ static void allwinner_r40_init(Object *obj) object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer), "clk1-freq"); + object_initialize_child(obj, "wdt", &s->wdt, TYPE_AW_WDT_SUN4I); + object_initialize_child(obj, "ccu", &s->ccu, TYPE_AW_R40_CCU); for (int i = 0; i < AW_R40_NUM_MMCS; i++) { @@ -545,6 +548,11 @@ static void allwinner_r40_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0, qdev_get_gpio_in(DEVICE(&s->gic), AW_R40_GIC_SPI_EMAC)); + /* WDT */ + sysbus_realize(SYS_BUS_DEVICE(&s->wdt), &error_fatal); + sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->wdt), 0, + allwinner_r40_memmap[AW_R40_DEV_WDT], 1); + /* Unimplemented devices */ for (unsigned i = 0; i < ARRAY_SIZE(r40_unimplemented); i++) { create_unimplemented_device(r40_unimplemented[i].device_name, diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 704517edd4f..2bc3ea3425e 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -411,6 +411,7 @@ config ALLWINNER_R40 select AHCI select ALLWINNER_SRAMC select ALLWINNER_A10_PIT + select ALLWINNER_WDT select AXP2XX_PMU select SERIAL select ARM_TIMER From patchwork Fri Jan 26 14:33:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766376 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp268492wrb; Fri, 26 Jan 2024 06:39:09 -0800 (PST) X-Google-Smtp-Source: AGHT+IGkBzU8WeyKS6CGaNuGM9X3Zt/CcRLnorbK0C1GChpKHDR/caxm1s3wpPZtoO2h4u3pFtI0 X-Received: by 2002:a05:622a:4c7:b0:42a:4de9:4a94 with SMTP id q7-20020a05622a04c700b0042a4de94a94mr1543708qtx.52.1706279949627; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:46 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/36] hw/arm/exynos4210: Include missing 'exec/tswap.h' header Date: Fri, 26 Jan 2024 14:33:15 +0000 Message-Id: <20240126143341.2101237-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé hw/arm/exynos4210.c calls tswap32() which is declared in "exec/tswap.h". Include it in order to avoid when refactoring unrelated headers: hw/arm/exynos4210.c:499:22: error: call to undeclared function 'tswap32'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] smpboot[n] = tswap32(smpboot[n]); ^ Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20240118200643.29037-2-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/arm/exynos4210.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index de39fb0ece8..af511a153dd 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -23,6 +23,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" +#include "exec/tswap.h" #include "cpu.h" #include "hw/cpu/a9mpcore.h" #include "hw/irq.h" From patchwork Fri Jan 26 14:33:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766346 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp266706wrb; Fri, 26 Jan 2024 06:34:57 -0800 (PST) X-Google-Smtp-Source: AGHT+IEUbYUvPnnO/dhZMIWYJIIaoptGZOFvKZBWag7m3QdOiY2DyqveS56aoXXzXnNwAY9I3jeA X-Received: by 2002:ad4:5b8b:0:b0:680:5f85:f81c with SMTP id 11-20020ad45b8b000000b006805f85f81cmr1542047qvp.40.1706279697072; Fri, 26 Jan 2024 06:34:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706279697; cv=none; d=google.com; s=arc-20160816; b=dBxzOX0bBRAqpw4q8mRmEbFVXpqyXBJn37DukmygrlFAU1ObZhMCtU2USm3mFq2q2A XgIOpnEK9LaXmJNKo97g2P+qq3t+DM74/IfvfAesYnWjlkAevhO8KjMnVUdrwKYjE1pG wSVn4fsyMDC28W0XpMNoOG93Wct/VL8imzUzN9e9ZE3ZVYwRBRz9oUhc/AZsyYCG5RKI DNSYJDTZ+eHD3/RCq9fhIHNI/58UrbaEP5dsJtIZZlsnI8TN5lFZpNiTCpemPl93cZWf mN/7dRPdeojpvLEA713RQXQCXjQNMLDtucxMqL7z8OeIsZ+7wtwY6OnO0tn0xxKgbNnv LIYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=PQlpwttdu93pWOUx8f8ZpRO+tP7SjE8rg5GEXBoZTSo=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=OY4Pdu6YSfW19c+vqeAvdVLM1rG0Xb5M5LtmFP1fAFaU7j9SVOcG1P0i65MQtZpe0L 55c1LM8pYd65P2DukxltJkATK+ijTWRBqFVA5Mn7G46HdaxtGyjyXCEeAH7FEAxYLzC3 c4oVMA3O2gE8XqT5MTd3+bycQdv/Gkf8ZIJUNNo7aC7fy07IHPz/6xH9op1V9BVEr0TD pQ2TRZ4mRTYLSoy4G7vzZEcCWGDybgx8vvPN6A7BuJ1jqoZUaHcfxDo2Vc+WBLqSS4Bx 2RHtcQimBTsX6tteut7gdeW8gNBe6lPPfxC+SF6UjP7YU9MJu8PkK/19p4b7fPm5WrZS ajBA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=seGSi7Nn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:47 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/36] hw/arm/xilinx_zynq: Include missing 'exec/tswap.h' header Date: Fri, 26 Jan 2024 14:33:16 +0000 Message-Id: <20240126143341.2101237-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé hw/arm/xilinx_zynq.c calls tswap32() which is declared in "exec/tswap.h". Include it in order to avoid when refactoring unrelated headers: hw/arm/xilinx_zynq.c:103:31: error: call to undeclared function 'tswap32'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] board_setup_blob[n] = tswap32(board_setup_blob[n]); ^ Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20240118200643.29037-3-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/arm/xilinx_zynq.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index dbb9793aa13..d4c817ecdc0 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -37,6 +37,7 @@ #include "hw/qdev-clock.h" #include "sysemu/reset.h" #include "qom/object.h" +#include "exec/tswap.h" #define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9") OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE) From patchwork Fri Jan 26 14:33:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766369 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp268123wrb; Fri, 26 Jan 2024 06:38:18 -0800 (PST) X-Google-Smtp-Source: AGHT+IFjxfow8ZNPf8BqnOjeCkLh6LPy6nC9TY6qhi9FJGpEYAFOlA0jOo7Ki7WmJmoXZa0vztjP X-Received: by 2002:a05:6214:40b:b0:67f:8b8f:6fd5 with SMTP id z11-20020a056214040b00b0067f8b8f6fd5mr1493320qvx.94.1706279898174; Fri, 26 Jan 2024 06:38:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706279898; cv=none; d=google.com; s=arc-20160816; b=TZiHIEa29qypS6CqMJv8O0ohwUgh5vFbtW9s+YUwVbMNzVfqm5NVMGuF7NKC5+TFCb MK+Ybfq5KgoY63pEzKdZ1ye5OVCunBtlf3O/DJULlFo85Szsshmajm05LmEfRN1f5fnO B0ggu9AZo1r9GmQddU3+AK3/ho0N+pbI03N4UGwN2pQ3yHegG7i7vKBIHzPblYZOnHQv KcGbPJIqD0OjIiPv7v61HWc7ixI9FMyuPmalzXDJIN1cNkOYN8cFiGASaI7EkWIOFbiX CmwOD13ZzYqtlUqaqjWIk1HUOLWaxZOUPTFuJPeC1v2Wp6MHJdz3ZRrC3C6CF6gQsBgB WyPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=fI0vqBKhfwteSfpqeytU8U01fv4ToN4htezLoldNdvs=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=p2aSsHCP6mbB7UnGELrkw6KO0ggydGkH8H8CYBJq96bnuajlkC8dKc0M3lWdT2y3yO xO4reLTnnynB2ndD1r+epckv7puxcvWaKfNhuVvv8tHA2n2omK5QnYiFEOM5DLUCKa1F uFzIwVbL/D5Apf/Ixo22Rj+LqC6Oeg60z9ZSFDKzuYHeBdor8OcsdqLpwMJvDb7K8K7/ Sy2hPiH+I4fuT+K/2alrhGzaQ/98YQqQ5SQ+xOvWkrpBTMJMWiw4vMC8Cmnb0f9h2sgS 2gyJmO0cWUiuNIwIkC6G4C3aJhB10bu53mA/RBQR6Da67uYz7rlSiqjZ/hjG0/jaHGsk eANA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sNl3UFpT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:47 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/36] hw/arm/smmuv3: Include missing 'hw/registerfields.h' header Date: Fri, 26 Jan 2024 14:33:17 +0000 Message-Id: <20240126143341.2101237-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé hw/arm/smmuv3-internal.h uses the REG32() and FIELD() macros defined in "hw/registerfields.h". Include it in order to avoid when refactoring unrelated headers: In file included from ../../hw/arm/smmuv3.c:34: hw/arm/smmuv3-internal.h:36:28: error: expected identifier REG32(IDR0, 0x0) ^ hw/arm/smmuv3-internal.h:37:5: error: expected function body after function declarator FIELD(IDR0, S2P, 0 , 1) ^ Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20240118200643.29037-4-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/arm/smmuv3-internal.h | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index 6076025ad6a..e987bc4686b 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -21,6 +21,7 @@ #ifndef HW_ARM_SMMUV3_INTERNAL_H #define HW_ARM_SMMUV3_INTERNAL_H +#include "hw/registerfields.h" #include "hw/arm/smmu-common.h" typedef enum SMMUTranslationStatus { From patchwork Fri Jan 26 14:33:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766355 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp267024wrb; Fri, 26 Jan 2024 06:35:41 -0800 (PST) X-Google-Smtp-Source: AGHT+IEC1NK0JD1NrAfESkDQrFfTukR/8TC+GgKGjC8hP2aa8omo/6ctbe5QHEgf8QIz1RSL1A0/ X-Received: by 2002:a05:6808:2384:b0:3bd:e3b3:6c2a with SMTP id bp4-20020a056808238400b003bde3b36c2amr1366096oib.33.1706279740785; Fri, 26 Jan 2024 06:35:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706279740; cv=none; d=google.com; s=arc-20160816; b=qnypR3yMObroNXER438VwU0NqQIeeYYrYxyB5iXS5F6W4AYOfRYp8kGKVuyaUEwqM/ J4xEtoZzlgteFVt3s/PoueD+GDglhWWPPEjn4w1+Ims7Bj5PqdwXuaZsJP5XTT/pFZmt 7js2z8dtS+egBcxg5wPhm8LoSLe9z3Q9GAWASlTVTKNc5LUZ5l2hdXnqvntJZ99FxrpE QaJGtgOn5k22XRfHzf4RXEMCd917Hx+8X4HTGYAObG8vxi9tlLxiCetEaBKHOUaiEBhH eYszRqNACJtEaxOfVBFBhMqut4WnwV3Cf6ljFih8+trhh9c6OHUxz099ojcM1CQFmi2S J4+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=SayjVZreUIIZvwgWfW2preOvFMoE7PMcRfYHzIZ+5wg=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=QbWPwVNGI2SV2Bg1mvh86afpg8Uf7KpcNSBn3fU2tcZnXDevrk5sDL2oKeTr/pe6Ft 13vyXfnviP0YQpZO8YCQ/Y5oZ8+JoMLm+umE0lfRZ8ZXO8Qo539pXJ3VHdG1JI6OL2n+ 8pbwLO95lkKKyTKYu8Aij5/Ry4BYsGL6Tw9YrX5XPwv0xdQ/1sbh1ge8MohF8e5NikuR /u5RYQBGToeWxm5VMTuSxIEx5AyfnoYiAYzrUGzmEXoeP5kkOphMxeQdQNnmsRSSOwEy WAP+5H/CAPGIfKTI0Ftvq6YC3tYgghW6M9WZT8+zbkK0fEdAbFa9ZhnTMCg8suD+d70J Cqgg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AJ4+1TzM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:47 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/36] hw/arm/xlnx-versal: Include missing 'cpu.h' header Date: Fri, 26 Jan 2024 14:33:18 +0000 Message-Id: <20240126143341.2101237-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé include/hw/arm/xlnx-versal.h uses the ARMCPU structure which is defined in the "target/arm/cpu.h" header. Include it in order to avoid when refactoring unrelated headers: In file included from hw/arm/xlnx-versal-virt.c:20: include/hw/arm/xlnx-versal.h:62:23: error: array has incomplete element type 'ARMCPU' (aka 'struct ArchCPU') ARMCPU cpu[XLNX_VERSAL_NR_ACPUS]; ^ Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20240118200643.29037-5-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/arm/xlnx-versal.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index b24fa64557f..025beb5532d 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -34,6 +34,7 @@ #include "hw/net/xlnx-versal-canfd.h" #include "hw/misc/xlnx-versal-cfu.h" #include "hw/misc/xlnx-versal-cframe-reg.h" +#include "target/arm/cpu.h" #define TYPE_XLNX_VERSAL "xlnx-versal" OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) From patchwork Fri Jan 26 14:33:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766364 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp267838wrb; Fri, 26 Jan 2024 06:37:36 -0800 (PST) X-Google-Smtp-Source: AGHT+IH2nRGyrzQIhOfGe+bPzGnfRlQ5vAqaREtqX8W0GAkfTulNI5fF5Z1iG5F0pq0rEdjx5a/G X-Received: by 2002:ad4:5dec:0:b0:686:1f2:4c00 with SMTP id jn12-20020ad45dec000000b0068601f24c00mr1397843qvb.117.1706279856016; Fri, 26 Jan 2024 06:37:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706279856; cv=none; d=google.com; s=arc-20160816; b=I36ZbCk9wvcxsV0IKZ2iRogkEA/8lDwvmiwZkF6wDpx8e+8X8ig+3aBoTRf/zLTZG1 apEKFnvto+mjV0XYEWXUkOG76+kgj5OPejJIO6dB07XkQVzYuhZmF5R1BtdGHtBe4dJx XeONYu1H8ORzY9KUTCOUySXQexly1VuH4+o9AKc2G0De5jMzHx+8vf7/lxn/CDs0GTCq b5B8qbOpe9gC/qhsYsfV4qL546BFg7LDO6eXmzZ5DcfGVbZHqCdYX4oT0jXjrypbNS8y F5C8JL1FiDiJRyACunxB/+vwdKr5QhYKa1jX/O4CKSl2+asPhKuB+GMMtBPtfRXGcfe7 YIxw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=qOAj+xgESAfIYVFV2UzsvAbHui7mgq2G92H1X0CLzHk=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=uANDIod68RJRktG4n+BgSqgYnudNDf4aQq27oD1dpaWI53pn7UTNGoAZlZHuCeQ8n6 HBrjFbiZYkP1PmLJF5eU5/GeDyA42LLKSvAkj3L/fHP66/ay/N1/LK3C4I+rRCPZeBv/ /0jzIRmMkvk7Yho0ewuNWKKt1LBM7NA65PVpEtFTYa9OFePJQ/T5TMHBkm0+3CgkxUzy kJXn6nRxqvAEr+En/3E8sWTA4bKMLNAaEGXwYbvRFUs2XGmElLgSK+oX2eCu2w51Cw9v AEvh5DNK1oGVwtywklY8u7BOwUDyWGOG1/H4FWYDY+E7LUtFLVHI9Z8R0/H9r9qoTFZr 8HVQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zmYoonAc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:48 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/36] target/arm/cpu-features: Include missing 'hw/registerfields.h' header Date: Fri, 26 Jan 2024 14:33:19 +0000 Message-Id: <20240126143341.2101237-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé target/arm/cpu-features.h uses the FIELD_EX32() macro defined in "hw/registerfields.h". Include it in order to avoid when refactoring unrelated headers: target/arm/cpu-features.h:44:12: error: call to undeclared function 'FIELD_EX32'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; ^ Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20240118200643.29037-6-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu-features.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 7a590c824cf..028795ff23f 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -20,6 +20,8 @@ #ifndef TARGET_ARM_FEATURES_H #define TARGET_ARM_FEATURES_H +#include "hw/registerfields.h" + /* * Naming convention for isar_feature functions: * Functions which test 32-bit ID registers should have _aa32_ in From patchwork Fri Jan 26 14:33:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766377 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp268511wrb; Fri, 26 Jan 2024 06:39:13 -0800 (PST) X-Google-Smtp-Source: AGHT+IHg30mbQk21s+oRLgSvRUC5alZUBujUPyHMER3gswQ5C1pAHHwwR9DGVJojkFYKDRlMdAMX X-Received: by 2002:a05:620a:172a:b0:783:9b9d:43f with SMTP id az42-20020a05620a172a00b007839b9d043fmr1979468qkb.92.1706279953741; Fri, 26 Jan 2024 06:39:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706279953; cv=none; d=google.com; s=arc-20160816; b=g1ZqTmPXO7fF1Gs+VdRjfbb11zytN9tmtlF8nraLHT+uO6CsSxi4bdUEZzSfOzhzaC Mgb9nKK7lOqUWkgKDJBx4RHw+Bz0Nub2wZCZi4R+/YniUJPkl6355PyLpoe63i5hHzo3 sMSLltLir0sotk3sC/zCdODcqFc6pmGpfADjn++limbH9reMXyvcCsVB4fjZHtQrTW9i gnHvxR5UKYYDYDJFNXxgVpj64C9Tsf9HLvhBDzXkXeISqxxXsMIW9+CT11RMQbInJAwn XBc/CedSznDOOxTAX2nRnvW9KzohMk3/idOnf7XfwDeZcD0Y9gjZSh+xHIaUHtPTHOnE Zikw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=JzJ/7eGoWRxiuO78ttkuN8WfwtChGDxYPbjZXcNs7S0=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=lzIr3hb/UowbyJ20s7TiqfmT8mfbT5/GKuNiBGQlpzj9FKdh8p3gEmxi7q9Uprn1R1 5OyV/nLA+aDcCiHY61CL97nAThNnJPUwvKTCpJhbQLp8FHSkaqwBSvuitYyxisrmZztd JJq+foa41Hjuhavw6+o46+wW6aTip6fjd2+WoDiYyWZQaQ3haLiGfjvjsfg4XhvmNfOF Du2L4pkehxKSVw2ROLFkSKpkFxQpi6S8UQVf8L0zFtuht+Gcjvl34HqUFFoGfNrnGKpg d7rO6TTmL7N7ReWCmkXF+S816ZM5KdJBdbyrOQPh+CQyusa9/HgmHvv1i9VrHF7E9wyu 8FzQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=B0ACAv7f; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:48 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/36] target/arm/cpregs: Include missing 'hw/registerfields.h' header Date: Fri, 26 Jan 2024 14:33:20 +0000 Message-Id: <20240126143341.2101237-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé target/arm/cpregs.h uses the FIELD() macro defined in "hw/registerfields.h". Include it in order to avoid when refactoring unrelated headers: target/arm/cpregs.h:347:30: error: expected identifier FIELD(HFGRTR_EL2, AFSR0_EL1, 0, 1) ^ Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20240118200643.29037-7-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index b6fdd0f3eb4..ca2d6006ceb 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -21,6 +21,8 @@ #ifndef TARGET_ARM_CPREGS_H #define TARGET_ARM_CPREGS_H +#include "hw/registerfields.h" + /* * ARMCPRegInfo type field bits: */ From patchwork Fri Jan 26 14:33:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766366 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp268013wrb; Fri, 26 Jan 2024 06:38:01 -0800 (PST) X-Google-Smtp-Source: AGHT+IFq5reaqZnN+55qwXwOdVzlGcL/5XRF0ycQywlFbGMQLAp45JLdJJuVShqfkDSImJXOUP7B X-Received: by 2002:ac8:57d6:0:b0:42a:4662:48c8 with SMTP id w22-20020ac857d6000000b0042a466248c8mr1641483qta.63.1706279881489; Fri, 26 Jan 2024 06:38:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706279881; cv=none; d=google.com; s=arc-20160816; b=X8gfc/0nVLlDFd8ak6VLkoCHptiywF9hLgYVxUKaXcv9nmGtIn/NS/AF55Ij8eoL5i KvGM6/R9/1q37Z2NfrzLIaeEagP29ElBkSe8f31mm3PCGKABvhzVx5dGdcCgr66xQAcO YlOsBXtxIocYQnMFkvIjBIHRS15jtKjYB79fELL+VegdSE6Eu49RjbZfa0YxV9ClyUTg q/PFQEq8Q9ywnckHr05yg6qLruDwY/C143F5Bc3EsytMZ+ZsORY/xQdRrTjxl03/7WHi YX9s6LMbDuvmFdpbNGdvfWSb84BfmwM2EJ4RDt/yO/XdpE7N5zNQ1tx8nnc1T7DBRKhM CTFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ELkpfpUcCpMmE/EyjZLsfEZZ/g6NmNI21NxV4ntMPM8=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=NA5YZP8PQ9CLrjZRnr4qN4uB4iVTKpRkgLv4xlpoVEEqGbnjgRIGO0R2xHg46JLD7Y Jiu0oLkU6BYJck5ULQIPTnlETcKbSq4pCsu1ECeVEmfj8miAwL+C/ZzF/jyq9bzIOSIt rF84/RUu11DJ6IrS04yjMmnE646uQT8nSVyEH+5PlAlisYt/ICpDfxdnK4CrN+l0ojm1 LQvgiSn7MWczMcpAvtHqo1/Cl4B0OmtQ3KcDkorPw52V1GWpJpIhMUsqp52FJvdmxeqq N2ktwokkoOPEat/41UjE6ZMK2X2nxTJfbiPIArG5YWdqoSj3OaeTUqeDp5ZQHz4blTBz CK7g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dsn1n0rj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:48 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/36] target/arm/cpregs: Include missing 'kvm-consts.h' header Date: Fri, 26 Jan 2024 14:33:21 +0000 Message-Id: <20240126143341.2101237-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé target/arm/cpregs.h uses the CP_REG_ARCH_* definitions from "target/arm/kvm-consts.h". Include it in order to avoid when refactoring unrelated headers: target/arm/cpregs.h:191:18: error: use of undeclared identifier 'CP_REG_ARCH_MASK' if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { ^ Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20240118200643.29037-8-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index ca2d6006ceb..cc7c54378f4 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -22,6 +22,7 @@ #define TARGET_ARM_CPREGS_H #include "hw/registerfields.h" +#include "target/arm/kvm-consts.h" /* * ARMCPRegInfo type field bits: From patchwork Fri Jan 26 14:33:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766356 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp267156wrb; Fri, 26 Jan 2024 06:36:00 -0800 (PST) X-Google-Smtp-Source: AGHT+IGOLehkD00iAZzk4r7DnC9VQZNE6ojJEa3EUmbp/XsVArGs7vGPQSZVY+SzSQ6/Htst4kY0 X-Received: by 2002:a05:6808:6490:b0:3bd:a5ac:9d77 with SMTP id fh16-20020a056808649000b003bda5ac9d77mr1797230oib.97.1706279760107; Fri, 26 Jan 2024 06:36:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706279760; cv=none; d=google.com; s=arc-20160816; b=jT12TkkGL5ooIc+Ro9NimjgY2y1m4hUgW0A0QzxkfUxtMr4y4ycsWlaPoRmUIkKgdk agRnM4p24jOet+aS8CKFFxyff+sCy3RF3DrQr1FKZa3astyrgf0Eksm/GjU/Ke8HYq/d zCd6iv6gS2Yh44cLHYy/uYcba8zhae6kb4CB/tMfTzmTr7caAvCimb3WNiSAzqXq1X25 kjqaUkp+N9kPjkXw7/3HWGFziFELY6l+nyC1mbT39cevZT/M/Cjc5IlICGu3otE0oOlJ jWBU1RkDtTGIBjJOsGN289XzkOXQMLu1+ONJHcsVfj5Lht9YadvJ45EORdc0ibJh4jHu sxuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=WClEbAYEMyFm8PZOzcgu+oaG2+JFImSPU42hTK0ft1A=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=04tX45tKXWF3lMlIt6NXdiQTPwZAO/wOKCtj8ywADRPZfEcqFxnl2PmGB5BPX6zRPg YTcFYTvc52nNYUrqS7aPvzaSz8RKdjZUftt7grQ6+WUdAFCnqrb994qbTg0vhaoQGYdm WYca0/u/lpmdqlIUeRTUNHrxcSD8TEG3oBdDWeGTsM/T8hGzUW+5Qgo3dt6+qVvdZxRb imhghaRRUueVtxaeBlFkNQ2M4AZtoQmanoMSzElhuhqsDZCUNhJBYWBVH5DifGsiwzkE MQ/Txhzw13omtEo7QLrd744yqvzqB6snuAQrFVM9RNRbQe0oe83+WmhpqhwqwZRS3FIf 1/nw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=J8ACLJhT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:49 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/36] target/arm: Rename arm_cpu_mp_affinity Date: Fri, 26 Jan 2024 14:33:22 +0000 Message-Id: <20240126143341.2101237-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Rename to arm_build_mp_affinity. This frees up the name for other usage, and emphasizes that the cpu object is not involved. Signed-off-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20240118200643.29037-9-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 +- hw/arm/npcm7xx.c | 2 +- hw/arm/sbsa-ref.c | 2 +- hw/arm/virt.c | 2 +- target/arm/cpu.c | 6 +++--- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ec276fcd57c..55a19e8539e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1171,7 +1171,7 @@ void arm_cpu_post_init(Object *obj); (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK) #define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) -uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); +uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz); #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_arm_cpu; diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index 15ff21d0472..7fb0a233b2d 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -474,7 +474,7 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) /* CPUs */ for (i = 0; i < nc->num_cpus; i++) { object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", - arm_cpu_mp_affinity(i, NPCM7XX_MAX_NUM_CPUS), + arm_build_mp_affinity(i, NPCM7XX_MAX_NUM_CPUS), &error_abort); object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", NPCM7XX_GIC_CPU_IF_ADDR, &error_abort); diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 477dca06373..b8857d1e9e4 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -148,7 +148,7 @@ static const int sbsa_ref_irqmap[] = { static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) { uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; - return arm_cpu_mp_affinity(idx, clustersz); + return arm_build_mp_affinity(idx, clustersz); } static void sbsa_fdt_add_gic_node(SBSAMachineState *sms) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ed4ed9f4142..eecde04fc77 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1676,7 +1676,7 @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) clustersz = GICV3_TARGETLIST_BITS; } } - return arm_cpu_mp_affinity(idx, clustersz); + return arm_build_mp_affinity(idx, clustersz); } static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 593695b4247..5b5af7d4e1e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1307,7 +1307,7 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) } } -uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) +uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz) { uint32_t Aff1 = idx / clustersz; uint32_t Aff0 = idx % clustersz; @@ -2113,8 +2113,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) * so these bits always RAZ. */ if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { - cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, - ARM_DEFAULT_CPUS_PER_CLUSTER); + cpu->mp_affinity = arm_build_mp_affinity(cs->cpu_index, + ARM_DEFAULT_CPUS_PER_CLUSTER); } if (cpu->reset_hivecs) { From patchwork Fri Jan 26 14:33:23 2024 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:50 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/36] target/arm: Create arm_cpu_mp_affinity Date: Fri, 26 Jan 2024 14:33:23 +0000 Message-Id: <20240126143341.2101237-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Wrapper to return the mp affinity bits from the cpu. Signed-off-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20240118200643.29037-10-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 5 +++++ hw/arm/virt-acpi-build.c | 2 +- hw/arm/virt.c | 6 +++--- hw/arm/xlnx-versal-virt.c | 3 ++- hw/misc/xlnx-versal-crl.c | 4 ++-- target/arm/arm-powerctl.c | 2 +- target/arm/hvf/hvf.c | 4 ++-- target/arm/tcg/psci.c | 2 +- 8 files changed, 17 insertions(+), 11 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 55a19e8539e..d1584bdb3b5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1173,6 +1173,11 @@ void arm_cpu_post_init(Object *obj); uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz); +static inline uint64_t arm_cpu_mp_affinity(ARMCPU *cpu) +{ + return cpu->mp_affinity; +} + #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_arm_cpu; diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index a22a2f43a56..2127778c1ea 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -720,7 +720,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) build_append_int_noprefix(table_data, vgic_interrupt, 4); build_append_int_noprefix(table_data, 0, 8); /* GICR Base Address*/ /* MPIDR */ - build_append_int_noprefix(table_data, armcpu->mp_affinity, 8); + build_append_int_noprefix(table_data, arm_cpu_mp_affinity(armcpu), 8); /* Processor Power Efficiency Class */ build_append_int_noprefix(table_data, 0, 1); /* Reserved */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index eecde04fc77..b3592798ea9 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -370,7 +370,7 @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms) for (cpu = 0; cpu < smp_cpus; cpu++) { ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); - if (armcpu->mp_affinity & ARM_AFF3_MASK) { + if (arm_cpu_mp_affinity(armcpu) & ARM_AFF3_MASK) { addr_cells = 2; break; } @@ -397,10 +397,10 @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms) if (addr_cells == 2) { qemu_fdt_setprop_u64(ms->fdt, nodename, "reg", - armcpu->mp_affinity); + arm_cpu_mp_affinity(armcpu)); } else { qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", - armcpu->mp_affinity); + arm_cpu_mp_affinity(armcpu)); } if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index 537118224fb..841ef69df66 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -107,7 +107,8 @@ static void fdt_add_cpu_nodes(VersalVirt *s, uint32_t psci_conduit) ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); qemu_fdt_add_subnode(s->fdt, name); - qemu_fdt_setprop_cell(s->fdt, name, "reg", armcpu->mp_affinity); + qemu_fdt_setprop_cell(s->fdt, name, "reg", + arm_cpu_mp_affinity(armcpu)); if (psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { qemu_fdt_setprop_string(s->fdt, name, "enable-method", "psci"); } diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c index ac6889fcf26..9bfa9baa157 100644 --- a/hw/misc/xlnx-versal-crl.c +++ b/hw/misc/xlnx-versal-crl.c @@ -67,9 +67,9 @@ static void crl_reset_cpu(XlnxVersalCRL *s, ARMCPU *armcpu, bool rst_old, bool rst_new) { if (rst_new) { - arm_set_cpu_off(armcpu->mp_affinity); + arm_set_cpu_off(arm_cpu_mp_affinity(armcpu)); } else { - arm_set_cpu_on_and_reset(armcpu->mp_affinity); + arm_set_cpu_on_and_reset(arm_cpu_mp_affinity(armcpu)); } } diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index 88503815659..6c86e901028 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -37,7 +37,7 @@ CPUState *arm_get_cpu_by_id(uint64_t id) CPU_FOREACH(cpu) { ARMCPU *armcpu = ARM_CPU(cpu); - if (armcpu->mp_affinity == id) { + if (arm_cpu_mp_affinity(armcpu) == id) { return cpu; } } diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index a537a5bc94c..659401e12c7 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1016,7 +1016,7 @@ static void hvf_raise_exception(CPUState *cpu, uint32_t excp, static void hvf_psci_cpu_off(ARMCPU *arm_cpu) { - int32_t ret = arm_set_cpu_off(arm_cpu->mp_affinity); + int32_t ret = arm_set_cpu_off(arm_cpu_mp_affinity(arm_cpu)); assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS); } @@ -1045,7 +1045,7 @@ static bool hvf_handle_psci_call(CPUState *cpu) int32_t ret = 0; trace_hvf_psci_call(param[0], param[1], param[2], param[3], - arm_cpu->mp_affinity); + arm_cpu_mp_affinity(arm_cpu)); switch (param[0]) { case QEMU_PSCI_0_2_FN_PSCI_VERSION: diff --git a/target/arm/tcg/psci.c b/target/arm/tcg/psci.c index 9080a91d9c6..50d4b23d26b 100644 --- a/target/arm/tcg/psci.c +++ b/target/arm/tcg/psci.c @@ -215,7 +215,7 @@ err: return; cpu_off: - ret = arm_set_cpu_off(cpu->mp_affinity); + ret = arm_set_cpu_off(arm_cpu_mp_affinity(cpu)); /* notreached */ /* sanity check in case something failed */ assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS); From patchwork Fri Jan 26 14:33:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766352 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp266856wrb; Fri, 26 Jan 2024 06:35:16 -0800 (PST) X-Google-Smtp-Source: AGHT+IGfcQU2ADdC0ViTDjcBxklwnxYrZ4buO6LYJ1/mZgy008mKLXcK8hikv7JRdtrwzJcS059A X-Received: by 2002:a05:6122:729:b0:4b6:d7ad:ac1f with SMTP id 41-20020a056122072900b004b6d7adac1fmr744668vki.21.1706279716097; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:50 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/36] target/arm: Expose arm_cpu_mp_affinity() in 'multiprocessing.h' header Date: Fri, 26 Jan 2024 14:33:24 +0000 Message-Id: <20240126143341.2101237-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Declare arm_cpu_mp_affinity() prototype in the new "target/arm/multiprocessing.h" header so units in hw/arm/ can use it without having to include the huge target-specific "cpu.h". File list to include the new header generated using: $ git grep -lw arm_cpu_mp_affinity Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20240118200643.29037-11-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 6 +----- target/arm/multiprocessing.h | 16 ++++++++++++++++ hw/arm/virt-acpi-build.c | 1 + hw/arm/virt.c | 1 + hw/arm/xlnx-versal-virt.c | 1 + hw/misc/xlnx-versal-crl.c | 1 + target/arm/arm-powerctl.c | 1 + target/arm/cpu.c | 5 +++++ target/arm/hvf/hvf.c | 1 + target/arm/tcg/psci.c | 1 + 10 files changed, 29 insertions(+), 5 deletions(-) create mode 100644 target/arm/multiprocessing.h diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d1584bdb3b5..cecac4c0a12 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -26,6 +26,7 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" #include "qapi/qapi-types-common.h" +#include "target/arm/multiprocessing.h" /* ARM processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) @@ -1173,11 +1174,6 @@ void arm_cpu_post_init(Object *obj); uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz); -static inline uint64_t arm_cpu_mp_affinity(ARMCPU *cpu) -{ - return cpu->mp_affinity; -} - #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_arm_cpu; diff --git a/target/arm/multiprocessing.h b/target/arm/multiprocessing.h new file mode 100644 index 00000000000..81715d345c2 --- /dev/null +++ b/target/arm/multiprocessing.h @@ -0,0 +1,16 @@ +/* + * ARM multiprocessor CPU helpers + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef TARGET_ARM_MULTIPROCESSING_H +#define TARGET_ARM_MULTIPROCESSING_H + +#include "target/arm/cpu-qom.h" + +uint64_t arm_cpu_mp_affinity(ARMCPU *cpu); + +#endif diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 2127778c1ea..43ccc60f43c 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -59,6 +59,7 @@ #include "hw/acpi/ghes.h" #include "hw/acpi/viot.h" #include "hw/virtio/virtio-acpi.h" +#include "target/arm/multiprocessing.h" #define ARM_SPI_BASE 32 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index b3592798ea9..1e0df6ea3ad 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -74,6 +74,7 @@ #include "hw/arm/smmuv3.h" #include "hw/acpi/acpi.h" #include "target/arm/internals.h" +#include "target/arm/multiprocessing.h" #include "hw/mem/pc-dimm.h" #include "hw/mem/nvdimm.h" #include "hw/acpi/generic_event_device.h" diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index 841ef69df66..29f4d2c2dce 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -20,6 +20,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/xlnx-versal.h" #include "hw/arm/boot.h" +#include "target/arm/multiprocessing.h" #include "qom/object.h" #define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt") diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c index 9bfa9baa157..1f1762ef163 100644 --- a/hw/misc/xlnx-versal-crl.c +++ b/hw/misc/xlnx-versal-crl.c @@ -19,6 +19,7 @@ #include "hw/resettable.h" #include "target/arm/arm-powerctl.h" +#include "target/arm/multiprocessing.h" #include "hw/misc/xlnx-versal-crl.h" #ifndef XLNX_VERSAL_CRL_ERR_DEBUG diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index 6c86e901028..2b2055c6acc 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -16,6 +16,7 @@ #include "qemu/log.h" #include "qemu/main-loop.h" #include "sysemu/tcg.h" +#include "target/arm/multiprocessing.h" #ifndef DEBUG_ARM_POWERCTL #define DEBUG_ARM_POWERCTL 0 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5b5af7d4e1e..04296f2928f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1314,6 +1314,11 @@ uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz) return (Aff1 << ARM_AFF1_SHIFT) | Aff0; } +uint64_t arm_cpu_mp_affinity(ARMCPU *cpu) +{ + return cpu->mp_affinity; +} + static void arm_cpu_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 659401e12c7..71a26db1886 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -28,6 +28,7 @@ #include "arm-powerctl.h" #include "target/arm/cpu.h" #include "target/arm/internals.h" +#include "target/arm/multiprocessing.h" #include "trace/trace-target_arm_hvf.h" #include "migration/vmstate.h" diff --git a/target/arm/tcg/psci.c b/target/arm/tcg/psci.c index 50d4b23d26b..51d2ca3d30d 100644 --- a/target/arm/tcg/psci.c +++ b/target/arm/tcg/psci.c @@ -24,6 +24,7 @@ #include "sysemu/runstate.h" #include "internals.h" #include "arm-powerctl.h" +#include "target/arm/multiprocessing.h" bool arm_is_psci_call(ARMCPU *cpu, int excp_type) { From patchwork Fri Jan 26 14:33:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766362 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp267615wrb; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:50 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/36] target/arm: Declare ARM_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h' Date: Fri, 26 Jan 2024 14:33:25 +0000 Message-Id: <20240126143341.2101237-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Missed in commit 2d56be5a29 ("target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'"). See it for more details. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20240118200643.29037-12-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu-qom.h | 3 +++ target/arm/cpu.h | 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 02b914c8767..f795994135f 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -33,4 +33,7 @@ typedef struct AArch64CPUClass AArch64CPUClass; DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, TYPE_AARCH64_CPU) +#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU +#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) + #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cecac4c0a12..41659d0ef15 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2837,8 +2837,6 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); #define ARM_CPUID_TI915T 0x54029152 #define ARM_CPUID_TI925T 0x54029252 -#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU -#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_ARM_CPU #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU From patchwork Fri Jan 26 14:33:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766347 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp266709wrb; Fri, 26 Jan 2024 06:34:57 -0800 (PST) X-Google-Smtp-Source: AGHT+IFCF6fR2bF3ZyOXITybeR+rhpPmu5BH6aJadsALLGnR5xXWF1dDDrhzVOjFGsEpZGW6q3B4 X-Received: by 2002:a05:620a:22e8:b0:783:a2e6:be95 with SMTP id p8-20020a05620a22e800b00783a2e6be95mr1498281qki.153.1706279696956; Fri, 26 Jan 2024 06:34:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706279696; cv=none; d=google.com; s=arc-20160816; b=JX9EH+8LBhS/zak3UDToUJmVLkjEiJ88JupzYCpHuR4wLHPwLwhG4zJl/4jThuA21X 6qoVRdwMTmYJYPA6BM7krTsQ2HLgvCYv2Werw7HdgNgaxiaVGPBlTJk1WvwkNqq2jVeK Jm+ObKJn2sLIhBFxPgqcxxQfMGkfPKcpGxoj0TwhoIxODie9HlKjP4pXdbG+9tvibvej dYMQqKvr4tD4Hnh6E4x8Fwxev/Bnkh/9k83yWsvhChQNgOmOBVT5zx2RIzrDYSVg/XGE 2VJWzMQoK6S68vmeSMO1A2eCZ0D+3dQwKZKEsIuNCjO1+JQwTmRSUHeOWKqMgakKXyC0 StYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=8W6Dmg/Z15G38A2ANLX0PCG/NULptGOn1F3YALWfvag=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=DwvvOMgzkOsG2CKWl6p8qxQJYMa/4ICpF9Zonn8+aP6TLl5WVdTqvNLm5jclBYhBCQ qXbipgGiU2nhO2+xLIM9g+hqTmMkflsyKq+aQTYnsViAaCPItmfAoxBap5L9gujI7pdH 23TReZn1fPvpgVKRww/Ua6kEvhyLpQHcWJYI9S5wG+BcjXBGhaJ1/jJzerW/DKn3iNyn Q7amh1rkhB+fJa3HFeEj1PP9O82FCCNhlW2NQmipHbQ0xyg49ebDKor2HBQAZGLI57S/ 4nQbV9pK1BUaw1RdYyAS8fkThvPk8hudABi5EHUArm2O055OEzYvw2texDGLJZxxkIOO mYHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fkEx0Ejj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:51 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/36] hw/cpu/a9mpcore: Build it only once Date: Fri, 26 Jan 2024 14:33:26 +0000 Message-Id: <20240126143341.2101237-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé hw/cpu/a9mpcore.c doesn't require "cpu.h" anymore. By removing it, the unit become target agnostic: we can build it once. Update meson. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20240118200643.29037-13-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/cpu/a9mpcore.c | 2 +- hw/cpu/meson.build | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index d03f57e579b..c30ef72c669 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -15,7 +15,7 @@ #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/core/cpu.h" -#include "cpu.h" +#include "target/arm/cpu-qom.h" #define A9_GIC_NUM_PRIORITY_BITS 5 diff --git a/hw/cpu/meson.build b/hw/cpu/meson.build index 6d319947ca0..38cdcfbe572 100644 --- a/hw/cpu/meson.build +++ b/hw/cpu/meson.build @@ -2,5 +2,5 @@ system_ss.add(files('core.c', 'cluster.c')) system_ss.add(when: 'CONFIG_ARM11MPCORE', if_true: files('arm11mpcore.c')) system_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview_mpcore.c')) -specific_ss.add(when: 'CONFIG_A9MPCORE', if_true: files('a9mpcore.c')) +system_ss.add(when: 'CONFIG_A9MPCORE', if_true: files('a9mpcore.c')) specific_ss.add(when: 'CONFIG_A15MPCORE', if_true: files('a15mpcore.c')) From patchwork Fri Jan 26 14:33:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766379 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp268517wrb; Fri, 26 Jan 2024 06:39:14 -0800 (PST) X-Google-Smtp-Source: AGHT+IHmbFeM55kctEX4+k2z/XSN7+D0YmT1sXX9am9Yn/+6Oc7t4wFPa1ZbFk4pK3/AAdzijym2 X-Received: by 2002:a9d:64d7:0:b0:6e0:b604:ca9a with SMTP id n23-20020a9d64d7000000b006e0b604ca9amr1604065otl.40.1706279954429; Fri, 26 Jan 2024 06:39:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706279954; cv=none; d=google.com; s=arc-20160816; b=tvYOHLFIOfUXzJHAMJXlKdARUjG6F2wx+UC324IFDayQunlvuP0xhFc8VqHcSY9lxd IZyvvpeXCRLbmTeapEMPscPHh5gT4RqmFi+J12MvAN/8y41GVvzKmCW9SJhYsZsu3J5C kdav5oDBI8zEUDEIdUbJv2DoKKGsmktoHC0PcKCqxwXkRuolP1TxH/Ici8d9xjoEfnym kG7IgJLSZNhxwl/m2fjunSW/4rtcSekfIZmTVGDWACv8yzjjE6I1v7lpM4F0vFuOd+F6 zyzfYWEZEKKk6rKfhnhMCBZfzdrKEdjI+LnBAdixkXjyf6WgNFsD9geSJWPrt4bpHJYd OrnQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=STnpdxdBqg+D7O0t/DW+hSCI5CBTAErw95dM/Zpjin0=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=blJ9FT1MNoDREIIQtrqanK056u/Yy3DtcLwLlebjXb99p6/PbUrkYc1U4Q3STw7OLS UpprZkD9Xa3k5QagmH6RUlGKHNkhXIGA2cB+6TDIaX8SokZFnCcmtZlFdYDXeB2VeFqR NJbMYTdxaXDJBCl9vTcETgYahLyzOOoliZqeII2djW5L08V2akk77Ihajr6Dj/joCf10 KwlUUg/UAKDdegco/oCh/Wu+2S/ltCuATP6tl44PE1gwX1XAaS1BvvMDMUiobmogdg0f i/hF0duahtnapmABlZweKa680U4f5QZLq001RbFTZzuDYMtBDMWXXUv8eqQaukfJgb4v hhKg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=A4CZHqLJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:51 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/36] hw/misc/xlnx-versal-crl: Include generic 'cpu-qom.h' instead of 'cpu.h' Date: Fri, 26 Jan 2024 14:33:27 +0000 Message-Id: <20240126143341.2101237-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé "target/arm/cpu.h" is target specific, any file including it becomes target specific too, thus this is the same for any file including "hw/misc/xlnx-versal-crl.h". "hw/misc/xlnx-versal-crl.h" doesn't require any target specific definition however, only the target-agnostic QOM definitions from "target/arm/cpu-qom.h". Include the latter header to avoid tainting unnecessary objects as target-specific. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20240118200643.29037-14-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/misc/xlnx-versal-crl.h | 2 +- hw/misc/xlnx-versal-crl.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/include/hw/misc/xlnx-versal-crl.h b/include/hw/misc/xlnx-versal-crl.h index dfb8dff197d..dba6d3585d1 100644 --- a/include/hw/misc/xlnx-versal-crl.h +++ b/include/hw/misc/xlnx-versal-crl.h @@ -11,7 +11,7 @@ #include "hw/sysbus.h" #include "hw/register.h" -#include "target/arm/cpu.h" +#include "target/arm/cpu-qom.h" #define TYPE_XLNX_VERSAL_CRL "xlnx-versal-crl" OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCRL, XLNX_VERSAL_CRL) diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c index 1f1762ef163..1a596f1cf57 100644 --- a/hw/misc/xlnx-versal-crl.c +++ b/hw/misc/xlnx-versal-crl.c @@ -18,6 +18,7 @@ #include "hw/register.h" #include "hw/resettable.h" +#include "target/arm/cpu.h" #include "target/arm/arm-powerctl.h" #include "target/arm/multiprocessing.h" #include "hw/misc/xlnx-versal-crl.h" From patchwork Fri Jan 26 14:33:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766370 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp268140wrb; Fri, 26 Jan 2024 06:38:19 -0800 (PST) X-Google-Smtp-Source: AGHT+IF10svnXoPmiDtEz9e/QywG9lfpOdpEvTYoL0YDOkd1/rAqRhtLtgagiqBEeF79yJYxZxJq X-Received: by 2002:a05:6808:6501:b0:3bd:c15c:23c9 with SMTP id fm1-20020a056808650100b003bdc15c23c9mr1648753oib.55.1706279899375; Fri, 26 Jan 2024 06:38:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706279899; cv=none; d=google.com; s=arc-20160816; b=gtKleICqSWqkQJpLumbv9M4gSqOXg3lq+WulVWAZz/CZMXqYJcxn86jRQ+lYfTpTD6 lDGOkHjzUEx4puxZvcJbsnU0W8wAUBCGf+A6r935ALSu2iRB7n8F816kX8nRb3RXTY62 pYG1XhV7VoxBRIuV3WRESFlnyaPQf5ERGDNn4qESAJYj4R/Mu7qAvtZkXsKuZ5+A8TIT Rg0mBnmS57La4uKE5ZEeJoguto3P2UGcDsuqCxMp2kqitb2Czs3SkIGM91mpKFv5NGsI vPyyeyR/w0QA5L9Bay4K6FBeMh0njkMhXpmZS6b+s++vKHPA3NFy7TXZjD+MCBB/cr+3 1DUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=LouzfqvK2IHKPiiDEvjrZzysBnMRC0GfKDnWQD9WZEU=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=zHfEsoNMApuFReEdoxAZ9HH6TEysdOVsRNR9b9QbZqzrlrjgyQV+s/o+2m7uawgp+2 LEwXrjnX1aNGTWWNGTG//usH4cQ8uffjR/9F9Djj5rGVsfZ9ovldWa/j5Qu33HEYePeg LmaVZByRp7shE1lEJPbhbIXGCcIJbLnw4qWN2Ex4V3mFoslVdcH5KCd/tAJdWGSr/F0B lVjY2Wujg9yvWvH/X5uPvJwkmrji/XIe1i5OKR8GiW18cCm8uBFvy1ksoSssoHoQBzCp LwB8bQyCFMb8WzZpDVLXkqx6jWERgsta9bxd+kuR/z/jrQT2HvWAvP1PXLRWC2XrFrPQ U2oA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MBs5J5Xt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:52 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/36] hw/misc/xlnx-versal-crl: Build it only once Date: Fri, 26 Jan 2024 14:33:28 +0000 Message-Id: <20240126143341.2101237-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé hw/misc/xlnx-versal-crl.c doesn't require "cpu.h" anymore. By removing it, the unit become target agnostic: we can build it once. Update meson. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20240118200643.29037-15-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/misc/xlnx-versal-crl.c | 1 - hw/misc/meson.build | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c index 1a596f1cf57..1f1762ef163 100644 --- a/hw/misc/xlnx-versal-crl.c +++ b/hw/misc/xlnx-versal-crl.c @@ -18,7 +18,6 @@ #include "hw/register.h" #include "hw/resettable.h" -#include "target/arm/cpu.h" #include "target/arm/arm-powerctl.h" #include "target/arm/multiprocessing.h" #include "hw/misc/xlnx-versal-crl.h" diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 2ca2ce4b62e..e4ef1da5a53 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -96,8 +96,8 @@ system_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c')) system_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c')) system_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c')) system_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c')) -specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-crl.c')) system_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files( + 'xlnx-versal-crl.c', 'xlnx-versal-xramc.c', 'xlnx-versal-pmc-iou-slcr.c', 'xlnx-versal-cfu.c', From patchwork Fri Jan 26 14:33:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766375 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp268402wrb; Fri, 26 Jan 2024 06:38:54 -0800 (PST) X-Google-Smtp-Source: AGHT+IGW4SveFO5LgYlEMNmcOMga2obbX0AW+/RCS8hXDzribMxlF2u6P4MXiWjZ9K4fiBUEC6af X-Received: by 2002:a05:620a:8404:b0:783:912b:3778 with SMTP id pc4-20020a05620a840400b00783912b3778mr2239487qkn.39.1706279933865; Fri, 26 Jan 2024 06:38:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706279933; cv=none; d=google.com; s=arc-20160816; b=SN02fZgUWneThqymJUO4al/ZfCGAal/KedHFGr7kVt6rXkzCQJAOv2hm4jn7SGpMcs aibTRK98rMjKao3YhlUejLTV8rvM+n+6FjWPzyFLGfeBpnz7rhbNkWL85HhGE2PdB35A maxZw8UCxQ4/s/VE3Oi7Kt6wat+FMWSgpqC0hQMoug2OFhxRN0is1UWyU4Tg5QLOES+t yftwhZA1jfqzORSLt4yo+7LbSN+1yXE9/ATkZZj0VtknCGlV6SUaLbqXjX2cdGTauGBp qLgvaWjQuWKcpYvjDdZrh1VoI064QDuVYJiosRuse5k8p9NyE2vbEEFXaLLMm81oCs5v UjQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=KENK9Mpj18OXyJdvgmdqz6uWTQ8A1jTnhGCoNoZ/oAs=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=YJsrtrbLuGxvH+4h3M29XPBd4GB6To4MMPHw/3uw4DxD4BI9pArObagJ4ijptY7BNT YmBARY40oHJmIB/AyuHf8uwWAtVZqyFFP1XW5yK39pirs2BxO+uNUxiyy3cWjiCyOEWW WwCgpBIrL4Q/ueO+I1sY7o0QbBoUGTCmFQPEYiK9usMNkvCChex58AwidXD4hk3um4Ye ILvztN7maiBG+OQtilBjIODiM59dXRAgQs1m6SYv5zFj8//fSnMW4zNGCNuh2vgmv4Yh aNgUSQL1HYRGDAWFmxCFfuLVYmEl6MZ1FEyEj8UieeT+KOzdSXCQB5wA7zWaee2L87fP /Lqg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XbPhYnoP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:52 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/36] target/arm: Expose M-profile register bank index definitions Date: Fri, 26 Jan 2024 14:33:29 +0000 Message-Id: <20240126143341.2101237-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé The ARMv7M QDev container accesses the QDev SysTickState by its secure/non-secure bank index. In order to make the "hw/intc/armv7m_nvic.h" header target-agnostic in the next commit, first move the M-profile bank index definitions to "target/arm/cpu-qom.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20240118200643.29037-16-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu-qom.h | 15 +++++++++++++++ target/arm/cpu.h | 15 --------------- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index f795994135f..77bbc1f13c9 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -36,4 +36,19 @@ DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) +/* For M profile, some registers are banked secure vs non-secure; + * these are represented as a 2-element array where the first element + * is the non-secure copy and the second is the secure copy. + * When the CPU does not have implement the security extension then + * only the first element is used. + * This means that the copy for the current security state can be + * accessed via env->registerfield[env->v7m.secure] (whether the security + * extension is implemented or not). + */ +enum { + M_REG_NS = 0, + M_REG_S = 1, + M_REG_NUM_BANKS = 2, +}; + #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 41659d0ef15..d6a79482adb 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -73,21 +73,6 @@ #define ARMV7M_EXCP_PENDSV 14 #define ARMV7M_EXCP_SYSTICK 15 -/* For M profile, some registers are banked secure vs non-secure; - * these are represented as a 2-element array where the first element - * is the non-secure copy and the second is the secure copy. - * When the CPU does not have implement the security extension then - * only the first element is used. - * This means that the copy for the current security state can be - * accessed via env->registerfield[env->v7m.secure] (whether the security - * extension is implemented or not). - */ -enum { - M_REG_NS = 0, - M_REG_S = 1, - M_REG_NUM_BANKS = 2, -}; - /* ARM-specific interrupt pending bits. */ #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 From patchwork Fri Jan 26 14:33:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766371 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp268146wrb; Fri, 26 Jan 2024 06:38:20 -0800 (PST) X-Google-Smtp-Source: AGHT+IFgw0+E5Q+ymD7bJXIgM0jbKGPra4vc0HjtRU3iuel1KprSwedmwbM2UK3SxCUX1NN0SUN7 X-Received: by 2002:a05:620a:e0a:b0:783:2146:86f6 with SMTP id y10-20020a05620a0e0a00b00783214686f6mr1731476qkm.33.1706279899771; Fri, 26 Jan 2024 06:38:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706279899; cv=none; d=google.com; s=arc-20160816; b=MsXlNA0jCvTQdG/OeEQNpkzKMUv58lo6DCFQsJ0rqA8gjlifZ+jhud/SSgxzK+FAYQ dIZayWsLHl584vADdP8APzOgo8OqjocQbjkBv+zZ4mnwVgpd7G79BRbnX8IIHKdGiN9l xO6fMmUpRyt6Yp8jk4p67hTrLW3Jlm48IVFsxTbMHTnw5Tn1ik8pNNoaJkJcZBsO92Yj iAAKHQdhihwL1PVhSz1aEUIqWuNOQaMg+Kft8kuFX4owqfs62USJMzAwOwRgV/wbLJGG MHk4sNhX1DnlZLXK+zlPWRdfN9HBTsT47aY/z4SCWSBnXp5oHaLnZDi0g58u/aiROBt/ 5h5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=VXXpoqeWUrMcxrn/dztG+5/UTCdvQjyp/SkalnZboFI=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=p5BYPaDvMLTd/Nn+whjJaq2/C39rXz/FYVyNDX8yWjOjYcnYWtm41YfhsRfOqrgRpU sr4sLvEGiLvZ4E/wIdpUU1jJJtLmdeTPE1BXsFFlxkgPlac7VMcAPxaRwBRxV9OzNrV6 DNj5yf0PBvyWJd6Za/054CxFy0TQqCtu2dw9GCs0W9dg4a1ZZ8Ls2D+0BuXVkFyxUBeg xRJG0TFCU0HgEjRxHR7pHegJ37ThHMFcj+eiAJRHU6A+mKuTnGl8rvzdcIC5EfvMKW8y NkomvLJtOBT+jWfIyfjjJdtZHrAl/5iVkNdeFOh+6mpGUGfCBupJYn+cUrntkYmGV7vl 4WXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aMprNKQv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:53 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/36] hw/arm/armv7m: Make 'hw/intc/armv7m_nvic.h' a target agnostic header Date: Fri, 26 Jan 2024 14:33:30 +0000 Message-Id: <20240126143341.2101237-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Now than we can access the M-profile bank index definitions from the target-agnostic "cpu-qom.h" header, we don't need the huge "cpu.h" anymore (except in hw/arm/armv7m.c). Reduce its inclusion to the source unit. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20240118200643.29037-17-philmd@linaro.org Signed-off-by: Peter Maydell --- include/hw/intc/armv7m_nvic.h | 2 +- hw/arm/armv7m.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index 6b4ae566c9a..89fe8aedaa9 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -10,7 +10,7 @@ #ifndef HW_ARM_ARMV7M_NVIC_H #define HW_ARM_ARMV7M_NVIC_H -#include "target/arm/cpu.h" +#include "target/arm/cpu-qom.h" #include "hw/sysbus.h" #include "hw/timer/armv7m_systick.h" #include "qom/object.h" diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 1f218277734..edcd8adc748 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -21,6 +21,7 @@ #include "qemu/module.h" #include "qemu/log.h" #include "target/arm/idau.h" +#include "target/arm/cpu.h" #include "target/arm/cpu-features.h" #include "migration/vmstate.h" From patchwork Fri Jan 26 14:33:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766350 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp266799wrb; Fri, 26 Jan 2024 06:35:10 -0800 (PST) X-Google-Smtp-Source: AGHT+IHL7AVpOQ1W7HI90yQgdkgbYta4mt+z3cUsHAD8uk9v5WfYCM9qrcciByiqFgNUPTsCls5B X-Received: by 2002:ac8:7dc9:0:b0:42a:7f80:6e57 with SMTP id c9-20020ac87dc9000000b0042a7f806e57mr995084qte.40.1706279710436; Fri, 26 Jan 2024 06:35:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706279710; cv=none; d=google.com; s=arc-20160816; b=r4TU4CvXdoXVbWUykEvDgREu62ip/qLaoXvGZjt8IC0aV65S/9e2fl2ovH9v4tnjIU PZVg34oZqCsA6mH8MM03ozucPQsQvyUFP357BDrKJ2rkgGbl1VM+3R88PThfcX70aQX/ daW0PX9j+OrJ2onS7DTo+opnFnMVyCNcENt1L5W3VgQzmPKHET1h1S6XYlxEUQopH+CX AOcbBIG0dNPT3jxELP3JunXrpSkytypbNS01rJmMtCAvqrADkwha0j6RS0lT4bgAfonh BpbBgDeEHT7pdLOSccwRbZ4LNIb0Af+A6oRw37cRSjEdFaf/Mt2ZKRM5oxrk+8VQNiEJ 5N7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kT4FU7BdZDSw/ALIzrvXiPFzXH+nnZjgGXux5dvXWzU=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=ye2bVSSnkmj/ARGHLTREaD/s7e9IHAgU9F1qJJMVl0kn93kqtGN4ee3KNHkw7pQHmc CwiOQtTyn10k+m+qz63vqg/qEwMDoHzZ6F36+L+wfnQydLXwO9VgLWki9FwefPFY2fOd H07PcX40x9mJ2v8nbLwVW4ibtMBkYVX68VgLxW5NgkJ/28d4lyHyH7x7L/+7GCjzvqM+ GQuOUE40KxRlUmhaNJNCQK1EgYlaHXG/7nuKVAdx55YbHxeT184e9Dp8w3f8FnsxwrfF 19zonFbSPPM2nb5N37sIsHCxb9AH0/cNuj0FVKRwFMIRLoT4ZSfX+sg8U14zDz19lcf5 Y7zw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="c7Xl2/sN"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:53 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/36] target/arm: Move ARM_CPU_IRQ/FIQ definitions to 'cpu-qom.h' header Date: Fri, 26 Jan 2024 14:33:31 +0000 Message-Id: <20240126143341.2101237-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé The ARM_CPU_IRQ/FIQ definitions are used to index the GPIO IRQ created calling qdev_init_gpio_in() in ARMCPU instance_init() handler. To allow non-ARM code to raise interrupt on ARM cores, move they to 'target/arm/cpu-qom.h' which is non-ARM specific and can be included by any hw/ file. File list to include the new header generated using: $ git grep -wEl 'ARM_CPU_(\w*IRQ|FIQ)' Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20240118200643.29037-18-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu-qom.h | 6 ++++++ target/arm/cpu.h | 6 ------ hw/arm/allwinner-a10.c | 1 + hw/arm/allwinner-h3.c | 1 + hw/arm/allwinner-r40.c | 1 + hw/arm/armv7m.c | 1 + hw/arm/aspeed_ast2400.c | 1 + hw/arm/aspeed_ast2600.c | 1 + hw/arm/bcm2836.c | 1 + hw/arm/exynos4210.c | 1 + hw/arm/fsl-imx25.c | 1 + hw/arm/fsl-imx31.c | 1 + hw/arm/fsl-imx6.c | 1 + hw/arm/fsl-imx6ul.c | 1 + hw/arm/fsl-imx7.c | 1 + hw/arm/highbank.c | 1 + hw/arm/integratorcp.c | 1 + hw/arm/musicpal.c | 1 + hw/arm/npcm7xx.c | 1 + hw/arm/omap1.c | 1 + hw/arm/omap2.c | 1 + hw/arm/realview.c | 1 + hw/arm/sbsa-ref.c | 1 + hw/arm/strongarm.c | 1 + hw/arm/versatilepb.c | 1 + hw/arm/vexpress.c | 1 + hw/arm/virt.c | 1 + hw/arm/xilinx_zynq.c | 1 + hw/arm/xlnx-versal.c | 1 + hw/arm/xlnx-zynqmp.c | 1 + target/arm/cpu.c | 1 + 31 files changed, 35 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 77bbc1f13c9..8e032691dbf 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -36,6 +36,12 @@ DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) +/* Meanings of the ARMCPU object's four inbound GPIO lines */ +#define ARM_CPU_IRQ 0 +#define ARM_CPU_FIQ 1 +#define ARM_CPU_VIRQ 2 +#define ARM_CPU_VFIQ 3 + /* For M profile, some registers are banked secure vs non-secure; * these are represented as a 2-element array where the first element * is the non-secure copy and the second is the secure copy. diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d6a79482adb..e8df41d642e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -93,12 +93,6 @@ #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) #endif -/* Meanings of the ARMCPU object's four inbound GPIO lines */ -#define ARM_CPU_IRQ 0 -#define ARM_CPU_FIQ 1 -#define ARM_CPU_VIRQ 2 -#define ARM_CPU_VFIQ 3 - /* ARM-specific extra insn start words: * 1: Conditional execution bits * 2: Partial exception syndrome for data aborts diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c index 0135632996c..581dd45edf0 100644 --- a/hw/arm/allwinner-a10.c +++ b/hw/arm/allwinner-a10.c @@ -26,6 +26,7 @@ #include "hw/boards.h" #include "hw/usb/hcd-ohci.h" #include "hw/loader.h" +#include "target/arm/cpu-qom.h" #define AW_A10_SRAM_A_BASE 0x00000000 #define AW_A10_DRAMC_BASE 0x01c01000 diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index f05afddf7e0..2d684b5287b 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -30,6 +30,7 @@ #include "hw/loader.h" #include "sysemu/sysemu.h" #include "hw/arm/allwinner-h3.h" +#include "target/arm/cpu-qom.h" /* Memory map */ const hwaddr allwinner_h3_memmap[] = { diff --git a/hw/arm/allwinner-r40.c b/hw/arm/allwinner-r40.c index a28e5b3886a..79976b0b54d 100644 --- a/hw/arm/allwinner-r40.c +++ b/hw/arm/allwinner-r40.c @@ -33,6 +33,7 @@ #include "sysemu/sysemu.h" #include "hw/arm/allwinner-r40.h" #include "hw/misc/allwinner-r40-dramc.h" +#include "target/arm/cpu-qom.h" /* Memory map */ const hwaddr allwinner_r40_memmap[] = { diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index edcd8adc748..7c68525a9e6 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -23,6 +23,7 @@ #include "target/arm/idau.h" #include "target/arm/cpu.h" #include "target/arm/cpu-features.h" +#include "target/arm/cpu-qom.h" #include "migration/vmstate.h" /* Bitbanded IO. Each word corresponds to a single bit. */ diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c index 0baa2ff96e4..ad76035528f 100644 --- a/hw/arm/aspeed_ast2400.c +++ b/hw/arm/aspeed_ast2400.c @@ -21,6 +21,7 @@ #include "hw/i2c/aspeed_i2c.h" #include "net/net.h" #include "sysemu/sysemu.h" +#include "target/arm/cpu-qom.h" #define ASPEED_SOC_IOMEM_SIZE 0x00200000 diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 3a9a303ab8b..386a88d4e0f 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -16,6 +16,7 @@ #include "hw/i2c/aspeed_i2c.h" #include "net/net.h" #include "sysemu/sysemu.h" +#include "target/arm/cpu-qom.h" #define ASPEED_SOC_IOMEM_SIZE 0x00200000 #define ASPEED_SOC_DPMCU_SIZE 0x00040000 diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index b0674a22a6c..58a78780d2b 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -15,6 +15,7 @@ #include "hw/arm/bcm2836.h" #include "hw/arm/raspi_platform.h" #include "hw/sysbus.h" +#include "target/arm/cpu-qom.h" struct BCM283XClass { /*< private >*/ diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index af511a153dd..6c428d8eeb4 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -36,6 +36,7 @@ #include "hw/arm/exynos4210.h" #include "hw/sd/sdhci.h" #include "hw/usb/hcd-ehci.h" +#include "target/arm/cpu-qom.h" #define EXYNOS4210_CHIPID_ADDR 0x10000000 diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c index 9d2fb75a689..4a49507ef19 100644 --- a/hw/arm/fsl-imx25.c +++ b/hw/arm/fsl-imx25.c @@ -28,6 +28,7 @@ #include "sysemu/sysemu.h" #include "hw/qdev-properties.h" #include "chardev/char.h" +#include "target/arm/cpu-qom.h" #define IMX25_ESDHC_CAPABILITIES 0x07e20000 diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c index c0584e4dfcd..4b8d9b8e4fe 100644 --- a/hw/arm/fsl-imx31.c +++ b/hw/arm/fsl-imx31.c @@ -26,6 +26,7 @@ #include "exec/address-spaces.h" #include "hw/qdev-properties.h" #include "chardev/char.h" +#include "target/arm/cpu-qom.h" static void fsl_imx31_init(Object *obj) { diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index af2e982b052..42f90588251 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -29,6 +29,7 @@ #include "chardev/char.h" #include "qemu/error-report.h" #include "qemu/module.h" +#include "target/arm/cpu-qom.h" #define IMX6_ESDHC_CAPABILITIES 0x057834b4 diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index e37b69a5e16..486a009deb8 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -25,6 +25,7 @@ #include "sysemu/sysemu.h" #include "qemu/error-report.h" #include "qemu/module.h" +#include "target/arm/cpu-qom.h" #define NAME_SIZE 20 diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index 474cfdc87c6..57281094918 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -26,6 +26,7 @@ #include "sysemu/sysemu.h" #include "qemu/error-report.h" #include "qemu/module.h" +#include "target/arm/cpu-qom.h" #define NAME_SIZE 20 diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index c21e18d08fd..e6e27d69af5 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -36,6 +36,7 @@ #include "qemu/log.h" #include "qom/object.h" #include "cpu.h" +#include "target/arm/cpu-qom.h" #define SMP_BOOT_ADDR 0x100 #define SMP_BOOT_REG 0x40 diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c index 1830e1d7850..5600616a4dd 100644 --- a/hw/arm/integratorcp.c +++ b/hw/arm/integratorcp.c @@ -28,6 +28,7 @@ #include "hw/sd/sd.h" #include "qom/object.h" #include "audio/audio.h" +#include "target/arm/cpu-qom.h" #define TYPE_INTEGRATOR_CM "integrator_core" OBJECT_DECLARE_SIMPLE_TYPE(IntegratorCMState, INTEGRATOR_CM) diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index 6987472871e..a2d25139e20 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -39,6 +39,7 @@ #include "hw/net/mv88w8618_eth.h" #include "audio/audio.h" #include "qemu/error-report.h" +#include "target/arm/cpu-qom.h" #define MP_MISC_BASE 0x80002000 #define MP_MISC_SIZE 0x00001000 diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index 7fb0a233b2d..e3243a520d8 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -26,6 +26,7 @@ #include "qapi/error.h" #include "qemu/units.h" #include "sysemu/sysemu.h" +#include "target/arm/cpu-qom.h" /* * This covers the whole MMIO space. We'll use this to catch any MMIO accesses diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c index d5438156ee9..86ee336e599 100644 --- a/hw/arm/omap1.c +++ b/hw/arm/omap1.c @@ -40,6 +40,7 @@ #include "hw/sysbus.h" #include "qemu/cutils.h" #include "qemu/bcd.h" +#include "target/arm/cpu-qom.h" static inline void omap_log_badwidth(const char *funcname, hwaddr addr, int sz) { diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c index f170728e7ec..f159fb73ea9 100644 --- a/hw/arm/omap2.c +++ b/hw/arm/omap2.c @@ -39,6 +39,7 @@ #include "hw/sysbus.h" #include "hw/boards.h" #include "audio/audio.h" +#include "target/arm/cpu-qom.h" /* Enhanced Audio Controller (CODEC only) */ struct omap_eac_s { diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 132217b2edd..566deff9ced 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -30,6 +30,7 @@ #include "hw/i2c/arm_sbcon_i2c.h" #include "hw/sd/sd.h" #include "audio/audio.h" +#include "target/arm/cpu-qom.h" #define SMP_BOOT_ADDR 0xe0000000 #define SMP_BOOTREG_ADDR 0x10000030 diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index b8857d1e9e4..d6081bfc41f 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -50,6 +50,7 @@ #include "net/net.h" #include "qapi/qmp/qlist.h" #include "qom/object.h" +#include "target/arm/cpu-qom.h" #define RAMLIMIT_GB 8192 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c index fef3638acaa..75637869cba 100644 --- a/hw/arm/strongarm.c +++ b/hw/arm/strongarm.c @@ -46,6 +46,7 @@ #include "qemu/cutils.h" #include "qemu/log.h" #include "qom/object.h" +#include "target/arm/cpu-qom.h" //#define DEBUG diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index 4b2257787b2..15b5ed0cedc 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -27,6 +27,7 @@ #include "hw/sd/sd.h" #include "qom/object.h" #include "audio/audio.h" +#include "target/arm/cpu-qom.h" #define VERSATILE_FLASH_ADDR 0x34000000 #define VERSATILE_FLASH_SIZE (64 * 1024 * 1024) diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index fd981f4c33e..49dbcdcbf0c 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -46,6 +46,7 @@ #include "qapi/qmp/qlist.h" #include "qom/object.h" #include "audio/audio.h" +#include "target/arm/cpu-qom.h" #define VEXPRESS_BOARD_ID 0x8e0 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 1e0df6ea3ad..64802446cb1 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -73,6 +73,7 @@ #include "standard-headers/linux/input.h" #include "hw/arm/smmuv3.h" #include "hw/acpi/acpi.h" +#include "target/arm/cpu-qom.h" #include "target/arm/internals.h" #include "target/arm/multiprocessing.h" #include "hw/mem/pc-dimm.h" diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index d4c817ecdc0..5809fc32af9 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -38,6 +38,7 @@ #include "sysemu/reset.h" #include "qom/object.h" #include "exec/tswap.h" +#include "target/arm/cpu-qom.h" #define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9") OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE) diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 9600551c442..87fdb39d430 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -23,6 +23,7 @@ #include "hw/misc/unimp.h" #include "hw/arm/xlnx-versal.h" #include "qemu/log.h" +#include "target/arm/cpu-qom.h" #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f") diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 5905a330151..38cb34942f8 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -25,6 +25,7 @@ #include "sysemu/kvm.h" #include "sysemu/sysemu.h" #include "kvm_arm.h" +#include "target/arm/cpu-qom.h" #define GIC_NUM_SPI_INTR 160 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 04296f2928f..4807a4fea0d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -48,6 +48,7 @@ #include "disas/capstone.h" #include "fpu/softfloat.h" #include "cpregs.h" +#include "target/arm/cpu-qom.h" static void arm_cpu_set_pc(CPUState *cs, vaddr value) { From patchwork Fri Jan 26 14:33:32 2024 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:54 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/36] target/arm: Move e2h_access() helper around Date: Fri, 26 Jan 2024 14:33:32 +0000 Message-Id: <20240126143341.2101237-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé e2h_access() was added in commit bb5972e439 ("target/arm: Add VHE timer register redirection and aliasing") close to the generic_timer_cp_reginfo[] array, but isn't used until vhe_reginfo[] definition. Move it closer to the other e2h helpers. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20240118200643.29037-19-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e068d353831..e07b2af8a3d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3345,20 +3345,6 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { }, }; -static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) -{ - if (arm_current_el(env) == 1) { - /* This must be a FEAT_NV access */ - /* TODO: FEAT_ECV will need to check CNTHCTL_EL2 here */ - return CP_ACCESS_OK; - } - if (!(arm_hcr_el2_eff(env) & HCR_E2H)) { - return CP_ACCESS_TRAP; - } - return CP_ACCESS_OK; -} - #else /* @@ -6546,6 +6532,21 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { }; #ifndef CONFIG_USER_ONLY + +static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) == 1) { + /* This must be a FEAT_NV access */ + /* TODO: FEAT_ECV will need to check CNTHCTL_EL2 here */ + return CP_ACCESS_OK; + } + if (!(arm_hcr_el2_eff(env) & HCR_E2H)) { + return CP_ACCESS_TRAP; + } + return CP_ACCESS_OK; +} + /* Test if system register redirection is to occur in the current state. */ static bool redirect_for_e2h(CPUARMState *env) { From patchwork Fri Jan 26 14:33:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766374 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp268387wrb; Fri, 26 Jan 2024 06:38:52 -0800 (PST) X-Google-Smtp-Source: AGHT+IGcv1PzD9DCdZX7adlmvHKf06fl6O49eeHZ0ypUUUymw806jiuZggsBHgl673t+kEB7TjuI X-Received: by 2002:a0c:b219:0:b0:686:abae:b8a1 with SMTP id x25-20020a0cb219000000b00686abaeb8a1mr1480616qvd.57.1706279932419; Fri, 26 Jan 2024 06:38:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706279932; cv=none; d=google.com; s=arc-20160816; b=YzTYIecst9gEpkaVfGel6Tjto3YDRWwKkCnE5eV1M3Vtfln56pBMSjQSDzX1RuzqnT 2ey9bAYztlKD59Cv0OF97jGsNiYW66Zkr2w7kyLt21IN84I1Bb2DiIxV6v9/Dhb/xxIi Do+eBRd0XfYqAEudVdYDQFuYoqZWz/tKaNGy+zAwSpipa7HChfMFWodm/D4X/Bu6CJhq XTnZxm/CPixDeH3cqQXSjcvlF7RiLgER0j7OZn3ZZU8OG8jOe537IH+DRdwXu7GNtawP y0jeRYXO9AmcQEJF+Dy9VbAoi1D4nYLKsUufHtZy9CxOObP7JVlNv6snpnR0j0qjktjP 8eew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=2Ij/Lp2rwQRGvyHfQ52tPmKqtKK6wJgy1701b00v8tA=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=LxgeAaapJPidRXEngHxlI3oFjLzx/ragtstktyzS/4rm1X2Eh3pnPUKbihpZLxgHJM 3RVRu1ZPgxsgM9TSErgJ8dd95In9+CK7zX4uBE7X1yEt6JSanUDXSvmjG4oQzZBdhgG5 9Tya0JyHv/atWUpm715vYx77eko1h6TYioEUXANePenu0sEOsKi5s6rtWoDi2//tx47e RdjiGp2SXxf1i1YwFtGxi/ZX2sC0V3KcbGSTJSVDbLcdE2/caQXB3RX3ct+uhDQ+ken3 PDQbm3l/Sz5Fxhd/Xp7KZTZFKadD3dRMQkqsTI4sEEGL8+1PHkGZFX2OiM0fPnvC8NzV UF+w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=I1AEzOtk; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:54 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/36] target/arm: Move GTimer definitions to new 'gtimer.h' header Date: Fri, 26 Jan 2024 14:33:33 +0000 Message-Id: <20240126143341.2101237-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12f; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x12f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Move Arm A-class Generic Timer definitions to the new "target/arm/gtimer.h" header so units in hw/ which don't need access to ARMCPU internals can use them without having to include the huge "cpu.h". Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20240118200643.29037-20-philmd@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 8 +------- target/arm/gtimer.h | 21 +++++++++++++++++++++ hw/arm/allwinner-h3.c | 1 + hw/arm/allwinner-r40.c | 1 + hw/arm/bcm2836.c | 1 + hw/arm/sbsa-ref.c | 1 + hw/arm/virt.c | 1 + hw/arm/xlnx-versal.c | 1 + hw/arm/xlnx-zynqmp.c | 1 + hw/cpu/a15mpcore.c | 1 + target/arm/cpu.c | 1 + target/arm/helper.c | 1 + target/arm/hvf/hvf.c | 1 + target/arm/kvm.c | 1 + target/arm/machine.c | 1 + 15 files changed, 35 insertions(+), 7 deletions(-) create mode 100644 target/arm/gtimer.h diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e8df41d642e..d3477b16018 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -27,6 +27,7 @@ #include "exec/cpu-defs.h" #include "qapi/qapi-types-common.h" #include "target/arm/multiprocessing.h" +#include "target/arm/gtimer.h" /* ARM processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) @@ -140,13 +141,6 @@ typedef struct ARMGenericTimer { uint64_t ctl; /* Timer Control register */ } ARMGenericTimer; -#define GTIMER_PHYS 0 -#define GTIMER_VIRT 1 -#define GTIMER_HYP 2 -#define GTIMER_SEC 3 -#define GTIMER_HYPVIRT 4 -#define NUM_GTIMERS 5 - #define VTCR_NSW (1u << 29) #define VTCR_NSA (1u << 30) #define VSTCR_SW VTCR_NSW diff --git a/target/arm/gtimer.h b/target/arm/gtimer.h new file mode 100644 index 00000000000..b992941bef1 --- /dev/null +++ b/target/arm/gtimer.h @@ -0,0 +1,21 @@ +/* + * ARM generic timer definitions for Arm A-class CPU + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef TARGET_ARM_GTIMER_H +#define TARGET_ARM_GTIMER_H + +enum { + GTIMER_PHYS = 0, + GTIMER_VIRT = 1, + GTIMER_HYP = 2, + GTIMER_SEC = 3, + GTIMER_HYPVIRT = 4, +#define NUM_GTIMERS 5 +}; + +#endif diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index 2d684b5287b..380e0ec11d6 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -31,6 +31,7 @@ #include "sysemu/sysemu.h" #include "hw/arm/allwinner-h3.h" #include "target/arm/cpu-qom.h" +#include "target/arm/gtimer.h" /* Memory map */ const hwaddr allwinner_h3_memmap[] = { diff --git a/hw/arm/allwinner-r40.c b/hw/arm/allwinner-r40.c index 79976b0b54d..eef1fc196e5 100644 --- a/hw/arm/allwinner-r40.c +++ b/hw/arm/allwinner-r40.c @@ -34,6 +34,7 @@ #include "hw/arm/allwinner-r40.h" #include "hw/misc/allwinner-r40-dramc.h" #include "target/arm/cpu-qom.h" +#include "target/arm/gtimer.h" /* Memory map */ const hwaddr allwinner_r40_memmap[] = { diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 58a78780d2b..e3ba18a8ec1 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -16,6 +16,7 @@ #include "hw/arm/raspi_platform.h" #include "hw/sysbus.h" #include "target/arm/cpu-qom.h" +#include "target/arm/gtimer.h" struct BCM283XClass { /*< private >*/ diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index d6081bfc41f..85cb68d5463 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -51,6 +51,7 @@ #include "qapi/qmp/qlist.h" #include "qom/object.h" #include "target/arm/cpu-qom.h" +#include "target/arm/gtimer.h" #define RAMLIMIT_GB 8192 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 64802446cb1..e6ead2c5c89 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -76,6 +76,7 @@ #include "target/arm/cpu-qom.h" #include "target/arm/internals.h" #include "target/arm/multiprocessing.h" +#include "target/arm/gtimer.h" #include "hw/mem/pc-dimm.h" #include "hw/mem/nvdimm.h" #include "hw/acpi/generic_event_device.h" diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 87fdb39d430..2798df3730d 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -24,6 +24,7 @@ #include "hw/arm/xlnx-versal.h" #include "qemu/log.h" #include "target/arm/cpu-qom.h" +#include "target/arm/gtimer.h" #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f") diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 38cb34942f8..65901c6e74b 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -26,6 +26,7 @@ #include "sysemu/sysemu.h" #include "kvm_arm.h" #include "target/arm/cpu-qom.h" +#include "target/arm/gtimer.h" #define GIC_NUM_SPI_INTR 160 diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index bfd8aa56448..967d8d3dd50 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -26,6 +26,7 @@ #include "hw/qdev-properties.h" #include "sysemu/kvm.h" #include "kvm_arm.h" +#include "target/arm/gtimer.h" static void a15mp_priv_set_irq(void *opaque, int irq, int level) { diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4807a4fea0d..b60e1030469 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -49,6 +49,7 @@ #include "fpu/softfloat.h" #include "cpregs.h" #include "target/arm/cpu-qom.h" +#include "target/arm/gtimer.h" static void arm_cpu_set_pc(CPUState *cs, vaddr value) { diff --git a/target/arm/helper.c b/target/arm/helper.c index e07b2af8a3d..945d8571a61 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -30,6 +30,7 @@ #include "semihosting/common-semi.h" #endif #include "cpregs.h" +#include "target/arm/gtimer.h" #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 71a26db1886..e5f0f60093e 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -29,6 +29,7 @@ #include "target/arm/cpu.h" #include "target/arm/internals.h" #include "target/arm/multiprocessing.h" +#include "target/arm/gtimer.h" #include "trace/trace-target_arm_hvf.h" #include "migration/vmstate.h" diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 8f52b211f9a..81813030a5a 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -38,6 +38,7 @@ #include "qemu/log.h" #include "hw/acpi/acpi.h" #include "hw/acpi/ghes.h" +#include "target/arm/gtimer.h" const KVMCapabilityInfo kvm_arch_required_capabilities[] = { KVM_CAP_LAST_INFO diff --git a/target/arm/machine.c b/target/arm/machine.c index 542be14bec2..9d7dbaea54c 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -7,6 +7,7 @@ #include "internals.h" #include "cpu-features.h" #include "migration/cpu.h" +#include "target/arm/gtimer.h" static bool vfp_needed(void *opaque) { From patchwork Fri Jan 26 14:33:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766367 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp268039wrb; Fri, 26 Jan 2024 06:38:06 -0800 (PST) X-Google-Smtp-Source: AGHT+IErcRa7IdX3X1VCz6Q3GNsK5++VDJMqEH0eTv2PkS4HTrcKmX7qoHJifIFtKuyNYhapjMVP X-Received: by 2002:a05:6830:19ec:b0:6dd:e810:3ab9 with SMTP id p44-20020a05683019ec00b006dde8103ab9mr2563666otp.4.1706279886205; Fri, 26 Jan 2024 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:54 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/36] hw/arm: Build various units only once Date: Fri, 26 Jan 2024 14:33:34 +0000 Message-Id: <20240126143341.2101237-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Various files in hw/arm/ don't require "cpu.h" anymore. Except virt-acpi-build.c, all of them don't require any ARM specific knowledge anymore and can be build once as target agnostic units. Update meson accordingly. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20240118200643.29037-21-philmd@linaro.org Signed-off-by: Peter Maydell --- hw/arm/collie.c | 1 - hw/arm/gumstix.c | 1 - hw/arm/integratorcp.c | 1 - hw/arm/mainstone.c | 1 - hw/arm/musicpal.c | 1 - hw/arm/omap2.c | 1 - hw/arm/omap_sx1.c | 1 - hw/arm/palm.c | 1 - hw/arm/spitz.c | 1 - hw/arm/strongarm.c | 1 - hw/arm/versatilepb.c | 1 - hw/arm/vexpress.c | 1 - hw/arm/virt-acpi-build.c | 1 - hw/arm/xilinx_zynq.c | 1 - hw/arm/xlnx-versal-virt.c | 1 - hw/arm/z2.c | 1 - hw/arm/meson.build | 23 ++++++++++++----------- 17 files changed, 12 insertions(+), 27 deletions(-) diff --git a/hw/arm/collie.c b/hw/arm/collie.c index a0ad1b8dc7e..eaa5c52d45a 100644 --- a/hw/arm/collie.c +++ b/hw/arm/collie.c @@ -17,7 +17,6 @@ #include "hw/arm/boot.h" #include "hw/block/flash.h" #include "exec/address-spaces.h" -#include "cpu.h" #include "qom/object.h" #include "qemu/error-report.h" diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c index 2ca4140c9fc..3f2bcaa24e4 100644 --- a/hw/arm/gumstix.c +++ b/hw/arm/gumstix.c @@ -44,7 +44,6 @@ #include "hw/boards.h" #include "exec/address-spaces.h" #include "sysemu/qtest.h" -#include "cpu.h" #define CONNEX_FLASH_SIZE (16 * MiB) #define CONNEX_RAM_SIZE (64 * MiB) diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c index 5600616a4dd..793262eca8c 100644 --- a/hw/arm/integratorcp.c +++ b/hw/arm/integratorcp.c @@ -9,7 +9,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/sysbus.h" #include "migration/vmstate.h" #include "hw/boards.h" diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c index 68329c46178..fc14e050608 100644 --- a/hw/arm/mainstone.c +++ b/hw/arm/mainstone.c @@ -23,7 +23,6 @@ #include "hw/block/flash.h" #include "hw/sysbus.h" #include "exec/address-spaces.h" -#include "cpu.h" /* Device addresses */ #define MST_FPGA_PHYS 0x08000000 diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index a2d25139e20..0fe0160b48b 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -12,7 +12,6 @@ #include "qemu/osdep.h" #include "qemu/units.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/sysbus.h" #include "migration/vmstate.h" #include "hw/arm/boot.h" diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c index f159fb73ea9..d9683276c68 100644 --- a/hw/arm/omap2.c +++ b/hw/arm/omap2.c @@ -21,7 +21,6 @@ #include "qemu/osdep.h" #include "qemu/error-report.h" #include "qapi/error.h" -#include "cpu.h" #include "exec/address-spaces.h" #include "sysemu/blockdev.h" #include "sysemu/qtest.h" diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c index 4bf1579f8c1..62d7915fb8f 100644 --- a/hw/arm/omap_sx1.c +++ b/hw/arm/omap_sx1.c @@ -35,7 +35,6 @@ #include "hw/block/flash.h" #include "sysemu/qtest.h" #include "exec/address-spaces.h" -#include "cpu.h" #include "qemu/cutils.h" #include "qemu/error-report.h" diff --git a/hw/arm/palm.c b/hw/arm/palm.c index b86f2c331bb..8c4c8316140 100644 --- a/hw/arm/palm.c +++ b/hw/arm/palm.c @@ -29,7 +29,6 @@ #include "hw/input/tsc2xxx.h" #include "hw/irq.h" #include "hw/loader.h" -#include "cpu.h" #include "qemu/cutils.h" #include "qom/object.h" #include "qemu/error-report.h" diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index 1d680b61e24..643a02b1807 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -33,7 +33,6 @@ #include "hw/adc/max111x.h" #include "migration/vmstate.h" #include "exec/address-spaces.h" -#include "cpu.h" #include "qom/object.h" #include "audio/audio.h" diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c index 75637869cba..7fd99a0f144 100644 --- a/hw/arm/strongarm.c +++ b/hw/arm/strongarm.c @@ -28,7 +28,6 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/qdev-properties-system.h" diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index 15b5ed0cedc..1d813aa23b5 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -9,7 +9,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/sysbus.h" #include "migration/vmstate.h" #include "hw/arm/boot.h" diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 49dbcdcbf0c..f1b45245d5d 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -24,7 +24,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/datadir.h" -#include "cpu.h" #include "hw/sysbus.h" #include "hw/arm/boot.h" #include "hw/arm/primecell.h" diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 43ccc60f43c..17aeec7a6f5 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -32,7 +32,6 @@ #include "qemu/error-report.h" #include "trace.h" #include "hw/core/cpu.h" -#include "target/arm/cpu.h" #include "hw/acpi/acpi-defs.h" #include "hw/acpi/acpi.h" #include "hw/nvram/fw_cfg_acpi.h" diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 5809fc32af9..66d0de139f2 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -18,7 +18,6 @@ #include "qemu/osdep.h" #include "qemu/units.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/sysbus.h" #include "hw/arm/boot.h" #include "net/net.h" diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index 29f4d2c2dce..94942c55dff 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -16,7 +16,6 @@ #include "hw/boards.h" #include "hw/sysbus.h" #include "hw/arm/fdt.h" -#include "cpu.h" #include "hw/qdev-properties.h" #include "hw/arm/xlnx-versal.h" #include "hw/arm/boot.h" diff --git a/hw/arm/z2.c b/hw/arm/z2.c index 83741a49092..a67fba2cfd2 100644 --- a/hw/arm/z2.c +++ b/hw/arm/z2.c @@ -25,7 +25,6 @@ #include "hw/audio/wm8750.h" #include "audio/audio.h" #include "exec/address-spaces.h" -#include "cpu.h" #include "qom/object.h" #include "qapi/error.h" diff --git a/hw/arm/meson.build b/hw/arm/meson.build index bb92b27db3e..c4017790670 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -9,23 +9,14 @@ arm_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c')) arm_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mainstone.c')) arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c')) arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c')) -arm_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c')) arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c')) arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-h405.c')) arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_boards.c')) arm_ss.add(when: 'CONFIG_NSERIES', if_true: files('nseries.c')) -arm_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c')) -arm_ss.add(when: 'CONFIG_CHEETAH', if_true: files('palm.c')) -arm_ss.add(when: 'CONFIG_GUMSTIX', if_true: files('gumstix.c')) -arm_ss.add(when: 'CONFIG_SPITZ', if_true: files('spitz.c')) -arm_ss.add(when: 'CONFIG_Z2', if_true: files('z2.c')) arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c')) arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c')) arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c')) arm_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vldiscovery.c')) -arm_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c')) -arm_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c')) -arm_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c')) arm_ss.add(when: 'CONFIG_ZYNQ', if_true: files('xilinx_zynq.c')) arm_ss.add(when: 'CONFIG_SABRELITE', if_true: files('sabrelite.c')) @@ -33,8 +24,7 @@ arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m.c')) arm_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210.c')) arm_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx.c', 'pxa2xx_gpio.c', 'pxa2xx_pic.c')) arm_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic.c')) -arm_ss.add(when: 'CONFIG_OMAP', if_true: files('omap1.c', 'omap2.c')) -arm_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c')) +arm_ss.add(when: 'CONFIG_OMAP', if_true: files('omap1.c')) arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c')) arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c')) arm_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true: files('allwinner-r40.c', 'bananapi_m2u.c')) @@ -69,8 +59,19 @@ arm_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c')) arm_ss.add(when: 'CONFIG_XEN', if_true: files('xen_arm.c')) system_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmu-common.c')) +system_ss.add(when: 'CONFIG_CHEETAH', if_true: files('palm.c')) +system_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c')) system_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c')) +system_ss.add(when: 'CONFIG_GUMSTIX', if_true: files('gumstix.c')) +system_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c')) +system_ss.add(when: 'CONFIG_OMAP', if_true: files('omap2.c')) system_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c')) +system_ss.add(when: 'CONFIG_SPITZ', if_true: files('spitz.c')) +system_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c')) +system_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c')) system_ss.add(when: 'CONFIG_TOSA', if_true: files('tosa.c')) +system_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c')) +system_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c')) +system_ss.add(when: 'CONFIG_Z2', if_true: files('z2.c')) hw_arch += {'arm': arm_ss} From patchwork Fri Jan 26 14:33:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766378 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp268513wrb; Fri, 26 Jan 2024 06:39:14 -0800 (PST) X-Google-Smtp-Source: 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:55 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/36] fsl-imx6ul: Add various missing unimplemented devices Date: Fri, 26 Jan 2024 14:33:35 +0000 Message-Id: <20240126143341.2101237-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Guenter Roeck Add MMDC, OCOTP, SQPI, CAAM, and USBMISC as unimplemented devices. This allows operating systems such as Linux to run emulations such as mcimx6ul-evk. Before commit 0cd4926b85 ("Refactor i.MX6UL processor code"), the affected memory ranges were covered by the unimplemented DAP device. The commit reduced the DAP address range from 0x100000 to 4kB, and the emulation thus no longer covered the various unimplemented devices in the affected address range. Fixes: 0cd4926b85 ("Refactor i.MX6UL processor code") Cc: Jean-Christophe Dubois Signed-off-by: Guenter Roeck Reviewed-by: Philippe Mathieu-Daudé Message-id: 20240120005356.2599547-1-linux@roeck-us.net Signed-off-by: Peter Maydell --- include/hw/arm/fsl-imx6ul.h | 2 ++ hw/arm/fsl-imx6ul.c | 30 ++++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h index 14390f60144..8277b0e8b2c 100644 --- a/include/hw/arm/fsl-imx6ul.h +++ b/include/hw/arm/fsl-imx6ul.h @@ -182,6 +182,8 @@ enum FslIMX6ULMemoryMap { FSL_IMX6UL_ENET1_ADDR = 0x02188000, FSL_IMX6UL_USBO2_USBMISC_ADDR = 0x02184800, + FSL_IMX6UL_USBO2_USBMISC_SIZE = 0x200, + FSL_IMX6UL_USBO2_USB1_ADDR = 0x02184000, FSL_IMX6UL_USBO2_USB2_ADDR = 0x02184200, diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index 486a009deb8..343bd65d1b2 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -193,6 +193,36 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp) create_unimplemented_device("a7mpcore-dap", FSL_IMX6UL_A7MPCORE_DAP_ADDR, FSL_IMX6UL_A7MPCORE_DAP_SIZE); + /* + * MMDC + */ + create_unimplemented_device("a7mpcore-mmdc", FSL_IMX6UL_MMDC_CFG_ADDR, + FSL_IMX6UL_MMDC_CFG_SIZE); + + /* + * OCOTP + */ + create_unimplemented_device("a7mpcore-ocotp", FSL_IMX6UL_OCOTP_CTRL_ADDR, + FSL_IMX6UL_OCOTP_CTRL_SIZE); + + /* + * QSPI + */ + create_unimplemented_device("a7mpcore-qspi", FSL_IMX6UL_QSPI_ADDR, + FSL_IMX6UL_QSPI_SIZE); + + /* + * CAAM + */ + create_unimplemented_device("a7mpcore-qspi", FSL_IMX6UL_CAAM_ADDR, + FSL_IMX6UL_CAAM_SIZE); + + /* + * USBMISC + */ + create_unimplemented_device("a7mpcore-usbmisc", FSL_IMX6UL_USBO2_USBMISC_ADDR, + FSL_IMX6UL_USBO2_USBMISC_SIZE); + /* * GPTs */ From patchwork Fri Jan 26 14:33:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766372 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp268200wrb; Fri, 26 Jan 2024 06:38:25 -0800 (PST) X-Google-Smtp-Source: AGHT+IE71TewMaWuXSzUtDAg/UFw6O9lqGwSbkPFsrmOZmo0OBZmVroK9B8nxw/VoXh3LzhM9Q8R X-Received: by 2002:ac8:1408:0:b0:42a:73ae:6e60 with SMTP id k8-20020ac81408000000b0042a73ae6e60mr1573427qtj.113.1706279905613; Fri, 26 Jan 2024 06:38:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706279905; cv=none; d=google.com; s=arc-20160816; b=SPyJH9G+y9voLZwn8CU7Wil74uj+RltbYFhaXhYDQsjJVyOL/LynKRdPtqeux1caNq 4JezXiy4YDPU0FKWth63eUu2d+t21XfpvciLsIRwiZJMlIA7aK5mz+xg28+JANe6kpe2 KbtOaGrmUXB4aNs9LTTTcNO7r7nRI94WLpm7dyguqJw2mFHjGM28cwqQQWyjz2L4cGSi HsEbB/8qrvpxKOjbVYkq/Tru3kC8+1cNxAn1hbI64fKDBfAPPiwv/C6EEFMvaVlhFDl0 rIocn1g5hlNUCM3WW1rycmisyXKJJyMOeReyskZ5kh83SHKaQzs0Ws77BCsEZ4htXJ02 9LUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=CbytbZE5r6VKI1aTBZEBghdNkVDSmRfkbInRbv2Plj8=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=FRcHvu5MWhSu243V3PLpOjz9+afq8JJ9bsXva6npEGrmhaA7e4+wAcnH2PhvrDA1T8 OcrqukSHojBB7wR6+Sfg/1+ryl3RYiBnfeHnzHCLGYTbashR19CYs4Y2CbGQ3OSl7g06 wi1IOiY0fLWnQgf+pE+QE6WO0wvkC+eOt4Mw2l9gBoBRXka+/TEN5wl77F3OwpSsFHC8 z11FIs6RmTlu5mNia9fzOl0O16QhWOmlc2y6GqvoTz+UFZKGOlvXzsAdAEmOulB6rjAE 5YFDpSCcJWWWc2p7ptYedKLc5o5dSHUpWuKiJ35q8e5epX//HZnppu4MnKfqR7xE+jmp K1pA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZqeJ10ta; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:55 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/36] docs/system/arm/virt.rst: Add note on CPU features off by default Date: Fri, 26 Jan 2024 14:33:36 +0000 Message-Id: <20240126143341.2101237-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12f; envelope-from=peter.maydell@linaro.org; helo=mail-lf1-x12f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Gustavo Romero Add a note on CPU features that are off by default in `virt` machines. Some CPU features will remain off even if a CPU-capable CPU (e.g., `-cpu max`) is selected because they require support in both the CPU itself and in the wider system. Therefore, the user, besides selecting a CPU that supports such features, must also turn on the feature using a machine option. Signed-off-by: Gustavo Romero Message-id: 20240122211215.95073-1-gustavo.romero@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- docs/system/arm/virt.rst | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index c245c52b7ac..26fcba00b76 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -69,6 +69,19 @@ Supported guest CPU types: Note that the default is ``cortex-a15``, so for an AArch64 guest you must specify a CPU type. +Also, please note that passing ``max`` CPU (i.e. ``-cpu max``) won't +enable all the CPU features for a given ``virt`` machine. Where a CPU +architectural feature requires support in both the CPU itself and in the +wider system (e.g. the MTE feature), it may not be enabled by default, +but instead requires a machine option to enable it. + +For example, MTE support must be enabled with ``-machine virt,mte=on``, +as well as by selecting an MTE-capable CPU (e.g., ``max``) with the +``-cpu`` option. + +See the machine-specific options below, or check them for a given machine +by passing the ``help`` suboption, like: ``-machine virt-9.0,help``. + Graphics output is available, but unlike the x86 PC machine types there is no default display device enabled: you should select one from the Display devices section of "-device help". The recommended option From patchwork Fri Jan 26 14:33:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766361 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp267570wrb; Fri, 26 Jan 2024 06:36:57 -0800 (PST) X-Google-Smtp-Source: AGHT+IHlk27uWkD1zam9KCvRErK0q+deFnoLvNw5587h8BayZO0gmmwc7Yz/Pv4/IiYQZjOSwyDz X-Received: by 2002:a05:620a:611a:b0:783:29d2:da95 with SMTP id oq26-20020a05620a611a00b0078329d2da95mr1418109qkn.121.1706279817618; Fri, 26 Jan 2024 06:36:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706279817; cv=none; d=google.com; s=arc-20160816; b=ShzMep/F7IK0WMjYMIaT24zQ0nXMGcZViZwBgAU8RTy092pTJVbcf8kZdnU10KLHYr OGb99yepN4mCm/H8AkoZfs+vkGBQsi3nCUyCB8AEFozjobIMatTqAQdgzBZyTM2tegbt P73qgyW95Gpr6Ie8T2jhWdp+oz32AFS/5QATyR7btqoMpig6V/aqZiOGhAuMQ5kuOUUS eUha2xeGAK9MmFIE6Jxr1hUBMyf5HKNNaRWoQARtVOZzzn/o3HlzgOPVIMloo+cT/HGD sROL/W2hsO9yY6kKdwW+j6OO+TsZ2LgPp+lJ9vwn6W5U2OmfH8vKog8+nX3tiCSag5Oo rINA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6GdiHkmihi3/CT5xTxzMMWZkQ0ZumRMBWRBDkHYF3cM=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=I+IMQOev49dIwCKwXCWwF33tD1xemVc7vsuKg4/UbB2loiPjv5JCVwVwjh2yjy28Lj NUR1Kyiigz/2VCUJWzTS6IJTei5uPvfNlMtzXiSD81v1qMy3l1375mBgh2Z6hHCHAdIV pRCeBrwek/ulakHl5qeXhIO5jTe2J1DCiniV/Yih6iQChAIWF2ANDQEsgx9kyewuRKdO 7Yh/OCJIzOK6DYoXP2cNNEwplyt/KVMxV7BKeUYbgbYOAu8s3++CGk/HpSvBLAqnAxFI hV6FS28aMNZ9wMkEZO0QyQ8Aq4InzUcgzv7E1DIqln4yLsEnsY25AUZXn8H2ahiPAo5P Qlcg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HS4FzEvb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:56 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/36] hw/char/imx_serial: Implement receive FIFO and ageing timer Date: Fri, 26 Jan 2024 14:33:37 +0000 Message-Id: <20240126143341.2101237-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Rayhan Faizel This patch implements a 32 half word FIFO as per imx serial device specifications. If a non empty FIFO is below the trigger level, an ageing timer will tick for a duration of 8 characters. On expiry, AGTIM will be set triggering an interrupt. AGTIM timer resets when there is activity in the receive FIFO. Otherwise, RRDY is set when trigger level is exceeded. The receive trigger level is 8 in newer kernel versions and 1 in older ones. This change will break migration compatibility for the imx boards. Signed-off-by: Rayhan Faizel Message-id: 20240125151931.83494-1-rayhan.faizel@gmail.com Reviewed-by: Peter Maydell [PMM: commit message tidyups] Signed-off-by: Peter Maydell --- include/hw/char/imx_serial.h | 20 ++++++- hw/char/imx_serial.c | 102 ++++++++++++++++++++++++++++++----- 2 files changed, 108 insertions(+), 14 deletions(-) diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h index b823f945195..65f0e97c76b 100644 --- a/include/hw/char/imx_serial.h +++ b/include/hw/char/imx_serial.h @@ -21,12 +21,16 @@ #include "hw/sysbus.h" #include "chardev/char-fe.h" #include "qom/object.h" +#include "qemu/fifo32.h" #define TYPE_IMX_SERIAL "imx.serial" OBJECT_DECLARE_SIMPLE_TYPE(IMXSerialState, IMX_SERIAL) +#define FIFO_SIZE 32 + #define URXD_CHARRDY (1<<15) /* character read is valid */ #define URXD_ERR (1<<14) /* Character has error */ +#define URXD_OVRRUN (1<<13) /* 32nd character in RX FIFO */ #define URXD_FRMERR (1<<12) /* Character has frame error */ #define URXD_BRK (1<<11) /* Break received */ @@ -65,11 +69,13 @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXSerialState, IMX_SERIAL) #define UCR1_TXMPTYEN (1<<6) /* Tx Empty Interrupt Enable */ #define UCR1_UARTEN (1<<0) /* UART Enable */ +#define UCR2_ATEN (1<<3) /* Ageing Timer Enable */ #define UCR2_TXEN (1<<2) /* Transmitter enable */ #define UCR2_RXEN (1<<1) /* Receiver enable */ #define UCR2_SRST (1<<0) /* Reset complete */ #define UCR4_DREN BIT(0) /* Receive Data Ready interrupt enable */ +#define UCR4_OREN BIT(1) /* Overrun interrupt enable */ #define UCR4_TCEN BIT(3) /* TX complete interrupt enable */ #define UCR4_WKEN BIT(7) /* WAKE interrupt enable */ @@ -78,13 +84,25 @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXSerialState, IMX_SERIAL) #define UTS1_TXFULL (1<<4) #define UTS1_RXFULL (1<<3) +#define TL_MASK 0x3f + + /* Bit time in nanoseconds assuming maximum baud rate of 115200 */ +#define BIT_TIME_NS 8681 + +/* Assume 8 bits per character */ +#define NUM_BITS 8 + +/* Ageing timer triggers after 8 characters */ +#define AGE_DURATION_NS (8 * NUM_BITS * BIT_TIME_NS) + struct IMXSerialState { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ MemoryRegion iomem; - int32_t readbuff; + QEMUTimer ageing_timer; + Fifo32 rx_fifo; uint32_t usr1; uint32_t usr2; diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c index 1df862eb7ff..ba37be6faab 100644 --- a/hw/char/imx_serial.c +++ b/hw/char/imx_serial.c @@ -26,6 +26,7 @@ #include "migration/vmstate.h" #include "qemu/log.h" #include "qemu/module.h" +#include "qemu/fifo32.h" #ifndef DEBUG_IMX_UART #define DEBUG_IMX_UART 0 @@ -41,10 +42,11 @@ static const VMStateDescription vmstate_imx_serial = { .name = TYPE_IMX_SERIAL, - .version_id = 2, - .minimum_version_id = 2, + .version_id = 3, + .minimum_version_id = 3, .fields = (const VMStateField[]) { - VMSTATE_INT32(readbuff, IMXSerialState), + VMSTATE_FIFO32(rx_fifo, IMXSerialState), + VMSTATE_TIMER(ageing_timer, IMXSerialState), VMSTATE_UINT32(usr1, IMXSerialState), VMSTATE_UINT32(usr2, IMXSerialState), VMSTATE_UINT32(ucr1, IMXSerialState), @@ -71,6 +73,10 @@ static void imx_update(IMXSerialState *s) * following: */ usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY); + /* + * Interrupt if AGTIM is set (ageing timer interrupt in RxFIFO) + */ + usr1 |= (s->ucr2 & UCR2_ATEN) ? (s->usr1 & USR1_AGTIM) : 0; /* * Bits that we want in USR2 are not as conveniently laid out, * unfortunately. @@ -78,15 +84,66 @@ static void imx_update(IMXSerialState *s) mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0; /* * TCEN and TXDC are both bit 3 + * ORE and OREN are both bit 1 * RDR and DREN are both bit 0 */ - mask |= s->ucr4 & (UCR4_WKEN | UCR4_TCEN | UCR4_DREN); + mask |= s->ucr4 & (UCR4_WKEN | UCR4_TCEN | UCR4_DREN | UCR4_OREN); usr2 = s->usr2 & mask; qemu_set_irq(s->irq, usr1 || usr2); } +static void imx_serial_rx_fifo_push(IMXSerialState *s, uint32_t value) +{ + uint32_t pushed_value = value; + if (fifo32_is_full(&s->rx_fifo)) { + /* Set ORE if FIFO is already full */ + s->usr2 |= USR2_ORE; + } else { + if (fifo32_num_used(&s->rx_fifo) == FIFO_SIZE - 1) { + /* Set OVRRUN on 32nd character in FIFO */ + pushed_value |= URXD_ERR | URXD_OVRRUN; + } + fifo32_push(&s->rx_fifo, pushed_value); + } +} + +static uint32_t imx_serial_rx_fifo_pop(IMXSerialState *s) +{ + if (fifo32_is_empty(&s->rx_fifo)) { + return 0; + } + return fifo32_pop(&s->rx_fifo); +} + +static void imx_serial_rx_fifo_ageing_timer_int(void *opaque) +{ + IMXSerialState *s = (IMXSerialState *) opaque; + s->usr1 |= USR1_AGTIM; + imx_update(s); +} + +static void imx_serial_rx_fifo_ageing_timer_restart(void *opaque) +{ + /* + * Ageing timer starts ticking when + * RX FIFO is non empty and below trigger level. + * Timer is reset if new character is received or + * a FIFO read occurs. + * Timer triggers an interrupt when duration of + * 8 characters has passed (assuming 115200 baudrate). + */ + IMXSerialState *s = (IMXSerialState *) opaque; + + if (!(s->usr1 & USR1_RRDY) && !(s->uts1 & UTS1_RXEMPTY)) { + timer_mod_ns(&s->ageing_timer, + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + AGE_DURATION_NS); + } else { + timer_del(&s->ageing_timer); + } +} + static void imx_serial_reset(IMXSerialState *s) { @@ -102,7 +159,9 @@ static void imx_serial_reset(IMXSerialState *s) s->ucr3 = 0x700; s->ubmr = 0; s->ubrc = 4; - s->readbuff = URXD_ERR; + + fifo32_reset(&s->rx_fifo); + timer_del(&s->ageing_timer); } static void imx_serial_reset_at_boot(DeviceState *dev) @@ -125,20 +184,28 @@ static uint64_t imx_serial_read(void *opaque, hwaddr offset, unsigned size) { IMXSerialState *s = (IMXSerialState *)opaque; - uint32_t c; + uint32_t c, rx_used; + uint8_t rxtl = s->ufcr & TL_MASK; DPRINTF("read(offset=0x%" HWADDR_PRIx ")\n", offset); switch (offset >> 2) { case 0x0: /* URXD */ - c = s->readbuff; + c = imx_serial_rx_fifo_pop(s); if (!(s->uts1 & UTS1_RXEMPTY)) { /* Character is valid */ c |= URXD_CHARRDY; - s->usr1 &= ~USR1_RRDY; - s->usr2 &= ~USR2_RDR; - s->uts1 |= UTS1_RXEMPTY; + rx_used = fifo32_num_used(&s->rx_fifo); + /* Clear RRDY if below threshold */ + if (rx_used < rxtl) { + s->usr1 &= ~USR1_RRDY; + } + if (rx_used == 0) { + s->usr2 &= ~USR2_RDR; + s->uts1 |= UTS1_RXEMPTY; + } imx_update(s); + imx_serial_rx_fifo_ageing_timer_restart(s); qemu_chr_fe_accept_input(&s->chr); } return c; @@ -300,19 +367,24 @@ static void imx_serial_write(void *opaque, hwaddr offset, static int imx_can_receive(void *opaque) { IMXSerialState *s = (IMXSerialState *)opaque; - return !(s->usr1 & USR1_RRDY); + return s->ucr2 & UCR2_RXEN && fifo32_num_used(&s->rx_fifo) < FIFO_SIZE; } static void imx_put_data(void *opaque, uint32_t value) { IMXSerialState *s = (IMXSerialState *)opaque; + uint8_t rxtl = s->ufcr & TL_MASK; DPRINTF("received char\n"); + imx_serial_rx_fifo_push(s, value); + if (fifo32_num_used(&s->rx_fifo) >= rxtl) { + s->usr1 |= USR1_RRDY; + } + + imx_serial_rx_fifo_ageing_timer_restart(s); - s->usr1 |= USR1_RRDY; s->usr2 |= USR2_RDR; s->uts1 &= ~UTS1_RXEMPTY; - s->readbuff = value; if (value & URXD_BRK) { s->usr2 |= USR2_BRCD; } @@ -345,6 +417,10 @@ static void imx_serial_realize(DeviceState *dev, Error **errp) { IMXSerialState *s = IMX_SERIAL(dev); + fifo32_create(&s->rx_fifo, FIFO_SIZE); + timer_init_ns(&s->ageing_timer, QEMU_CLOCK_VIRTUAL, + imx_serial_rx_fifo_ageing_timer_int, s); + DPRINTF("char dev for uart: %p\n", qemu_chr_fe_get_driver(&s->chr)); qemu_chr_fe_set_handlers(&s->chr, imx_can_receive, imx_receive, From patchwork Fri Jan 26 14:33:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766360 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp267540wrb; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:57 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/36] target/arm: Fix A64 scalar SQSHRN and SQRSHRN Date: Fri, 26 Jan 2024 14:33:38 +0000 Message-Id: <20240126143341.2101237-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In commit 1b7bc9b5c8bf374dd we changed handle_vec_simd_sqshrn() so that instead of starting with a 0 value and depositing in each new element from the narrowing operation, it instead started with the raw result of the narrowing operation of the first element. This is fine in the vector case, because the deposit operations for the second and subsequent elements will always overwrite any higher bits that might have been in the first element's result value in tcg_rd. However in the scalar case we only go through this loop once. The effect is that for a signed narrowing operation, if the result is negative then we will now return a value where the bits above the first element are incorrectly 1 (because the narrowfn returns a sign-extended result, not one that is truncated to the element size). Fix this by using an extract operation to get exactly the correct bits of the output of the narrowfn for element 1, instead of a plain move. Cc: qemu-stable@nongnu.org Fixes: 1b7bc9b5c8bf374dd3 ("target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2089 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20240123153416.877308-1-peter.maydell@linaro.org --- target/arm/tcg/translate-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 27335e85407..340265beb05 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -8343,7 +8343,7 @@ static void handle_vec_simd_sqshrn(DisasContext *s, bool is_scalar, bool is_q, narrowfn(tcg_rd_narrowed, tcg_env, tcg_rd); tcg_gen_extu_i32_i64(tcg_rd, tcg_rd_narrowed); if (i == 0) { - tcg_gen_mov_i64(tcg_final, tcg_rd); + tcg_gen_extract_i64(tcg_final, tcg_rd, 0, esize); } else { tcg_gen_deposit_i64(tcg_final, tcg_final, tcg_rd, esize * i, esize); } From patchwork Fri Jan 26 14:33:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766357 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp267227wrb; Fri, 26 Jan 2024 06:36:08 -0800 (PST) X-Google-Smtp-Source: AGHT+IFl3ywOysHuDm9h6ePC5K1NA7iUkqfYnPOWwiXHUImSaWcMcIT+raaePSsCpcS2m+n2G7Bb X-Received: by 2002:a05:6214:1c4e:b0:685:9014:93f8 with SMTP id if14-20020a0562141c4e00b00685901493f8mr2061285qvb.38.1706279768030; Fri, 26 Jan 2024 06:36:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706279768; cv=none; d=google.com; s=arc-20160816; b=W2PU7PXJ+6TyZPSOnZ4yYuvTjsCYYB5t0a+hoWtXpcUMRx2YRk0shdo4DVD3dVlJfq v/v4tVvVshpRoJAN0KFmfp96gkdJXqLl0cm3TFSreS4xBtuEdCdxacdu/e7PuHn5ZTnx n8GVysk9IErRteF0evttJqYeyEVttyozQi3Cao5usSNQtI1JlOXjGPdHkT0LN3YHXFWq 7HcXACKfK/j5tUquOMYcECK3DpalmqlN8TaZI0ivaLtctkvDAxmcXoBEr2R5mEJxLToT plQBpCwRjBUOGjtwKni/p21EAjGrcOgN74kf514lrn6kRKzF3COvwx7gsZ57PKknGljx 9GcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=28nbiWFQ3dXc2wMfXx4/3I1JNB6kABMI1o1Dd2Ej4Ok=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=plbJxezNJZ/zfrKgi9UnvMQ6zm2tZ7tBW9pH+AbJnMksNI0vm3WOMB8ZdFLJhX3yTz B3Vig0wVV5dkNKfo/MdlNndwqxj/xsF+NinDL7U9YQlILTnjenbCP6zcJoAtsLSbpQJI jbbRvJ7zplwjY/xuu4UtufyFKXEKvlfQpAR5+IH9l48gARrkVS13MGdn8Tqw2ECj6i6l ziN6TWvzfgsrKfrCSne7Q7jx2H0ONVHiEaYs9R1BBjqlLv889P7pcvKLL3E4j4dKr/4v WRdXjEy9YJHRgxAzpSctoNxpkb4Gjrh1AvIbi7egAzZ9lLJIHxvfF6L5vwJ0nY44P79P Q0jw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YXVVmRfM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:57 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/36] bswap.h: Fix const_le64() macro Date: Fri, 26 Jan 2024 14:33:39 +0000 Message-Id: <20240126143341.2101237-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The const_le64() macro introduced in commit 845d80a8c7b187 turns out to have a bug which means that on big-endian systems the compiler complains if the argument isn't already a 64-bit type. This hasn't caused a problem yet, because there are no in-tree uses, but it means it's not possible for anybody to add one without it failing CI. This example is from an attempted use of it with the argument '0', from the s390 CI runner's gcc: ../block/blklogwrites.c: In function ‘blk_log_writes_co_do_log’: ../include/qemu/bswap.h:148:36: error: left shift count >= width of type [-Werror=shift-count-overflow] 148 | ((((_x) & 0x00000000000000ffU) << 56) | \ | ^~ ../block/blklogwrites.c:409:27: note: in expansion of macro ‘const_le64’ 409 | .nr_entries = const_le64(0), | ^~~~~~~~~~ ../include/qemu/bswap.h:149:36: error: left shift count >= width of type [-Werror=shift-count-overflow] 149 | (((_x) & 0x000000000000ff00U) << 40) | \ | ^~ ../block/blklogwrites.c:409:27: note: in expansion of macro ‘const_le64’ 409 | .nr_entries = const_le64(0), | ^~~~~~~~~~ cc1: all warnings being treated as errors Fix this by making all the constants in the macro have the ULL suffix. This will cause them all to be 64-bit integers, which means the result of the logical & will also be an unsigned 64-bit type, even if the input to the macro is a smaller type, and so the shifts will be in range. Fixes: 845d80a8c7b187 ("qemu/bswap: Add const_le64()") Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Kevin Wolf Reviewed-by: Ira Weiny Message-id: 20240122173735.472951-1-peter.maydell@linaro.org --- include/qemu/bswap.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h index 933a66ee87e..bd67468e5e4 100644 --- a/include/qemu/bswap.h +++ b/include/qemu/bswap.h @@ -145,14 +145,14 @@ CPU_CONVERT(le, 64, uint64_t) */ #if HOST_BIG_ENDIAN # define const_le64(_x) \ - ((((_x) & 0x00000000000000ffU) << 56) | \ - (((_x) & 0x000000000000ff00U) << 40) | \ - (((_x) & 0x0000000000ff0000U) << 24) | \ - (((_x) & 0x00000000ff000000U) << 8) | \ - (((_x) & 0x000000ff00000000U) >> 8) | \ - (((_x) & 0x0000ff0000000000U) >> 24) | \ - (((_x) & 0x00ff000000000000U) >> 40) | \ - (((_x) & 0xff00000000000000U) >> 56)) + ((((_x) & 0x00000000000000ffULL) << 56) | \ + (((_x) & 0x000000000000ff00ULL) << 40) | \ + (((_x) & 0x0000000000ff0000ULL) << 24) | \ + (((_x) & 0x00000000ff000000ULL) << 8) | \ + (((_x) & 0x000000ff00000000ULL) >> 8) | \ + (((_x) & 0x0000ff0000000000ULL) >> 24) | \ + (((_x) & 0x00ff000000000000ULL) >> 40) | \ + (((_x) & 0xff00000000000000ULL) >> 56)) # define const_le32(_x) \ ((((_x) & 0x000000ffU) << 24) | \ (((_x) & 0x0000ff00U) << 8) | \ From patchwork Fri Jan 26 14:33:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766353 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp266999wrb; Fri, 26 Jan 2024 06:35:37 -0800 (PST) X-Google-Smtp-Source: AGHT+IE2Ir72gbAsMha8nCtQuuNpYK54UoQfMYuzHaoRoqxUuqhnevG0Uvf3n6leqniqCmbSsJz2 X-Received: by 2002:ad4:5181:0:b0:686:aa86:9530 with SMTP id b1-20020ad45181000000b00686aa869530mr1514628qvp.41.1706279737651; Fri, 26 Jan 2024 06:35:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706279737; cv=none; d=google.com; s=arc-20160816; b=A5MdXF/2Z0WuGVGIdb4DQuufo7Gt5/h0LBIvgAg20wn9UeB4wGGUHBq6p3VqyQg2RV YrmeNoHucxImrIeltrOXEPTLocY+kQjkJIupVqjgU7FhQgqw6OrveaMIRtMmf2oK8AhO 8IxQ/I0R8Y8Ubr8ml6q7ebi2WwIJjpIikaU8HgkFYoC8qwMisxEUCuLyPtN2nQwqNfdg xbzjOlbEudyREluEZUqOJ+d/gcyBF/pTnLS9eo5MqOUdudsIuJ603P9gKSEZdHw3rshv km4uo/8NrJ7+QBzwMGy83FAUOLxAJgmgLdssyY4ILXmR+9WK+NAhHCZh1cQDMYJiIqkC 9x1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=C5S28rdH5ZOgcnO36OWOW5DPAS8PCmcDgoLOzpGvQH0=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=aF5aRCHmAUEEnWkuFMWbSbvKwBTTxnTd4v8NPUu5dLI++3GNY9v//6Ro9fPypuxbGQ wGlsROEu6pBRMjbrwkMduDJLzWkcNrZV9FRl4V9r30oXQvi98oTsR9FDRWxDNAr2NzY2 MwSLsRwqiNl1FHMeC+SYVJJBds7mzE/Wzlcj/+594H3sNH2EiBECJII/Z43wmVg4pKJc c40buWXobgVbcgE2TqCUetFIp28KK8zcb1AAbrfP8uzRQhigBtOpjM6isWfnIkwwiCZF m+o2pBwwgE3OrUnjTBQ4xQcp8hDfTW5mBaAd0QnTGtADfEOAKdBmKGg7LTgjB9BMaRIK e5ag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="VM6/jWRY"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:58 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 35/36] target/arm: Fix incorrect aa64_tidcp1 feature check Date: Fri, 26 Jan 2024 14:33:40 +0000 Message-Id: <20240126143341.2101237-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org A typo in the implementation of isar_feature_aa64_tidcp1() means we were checking the field in the wrong ID register, so we might have provided the feature on CPUs that don't have it and not provided it on CPUs that should have it. Correct this bug. Cc: qemu-stable@nongnu.org Fixes: 9cd0c0dec97be9 "target/arm: Implement FEAT_TIDCP1" Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2120 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20240123160333.958841-1-peter.maydell@linaro.org --- target/arm/cpu-features.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 028795ff23f..7567854db63 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -773,7 +773,7 @@ static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id) static inline bool isar_feature_aa64_tidcp1(const ARMISARegisters *id) { - return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR1, TIDCP1) != 0; + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, TIDCP1) != 0; } static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id) From patchwork Fri Jan 26 14:33:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 766349 Delivered-To: patch@linaro.org Received: by 2002:adf:a314:0:b0:337:62d3:c6d5 with SMTP id c20csp266758wrb; Fri, 26 Jan 2024 06:35:04 -0800 (PST) X-Google-Smtp-Source: AGHT+IFThukRc/xtrV5jZkPpw/9K7e5TmeFXdbejIQy4PoozH+B0mwD+QZSrMRGz47D99g1iVYva X-Received: by 2002:a05:6214:21c3:b0:681:9ae1:94f3 with SMTP id d3-20020a05621421c300b006819ae194f3mr1997417qvh.115.1706279703883; Fri, 26 Jan 2024 06:35:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706279703; cv=none; d=google.com; s=arc-20160816; b=RFDpcjlLv/tc91Is6ad9P7Jq3RsPQhCgUhTtNzAVd+D/JOZ9ooZUYXGc1Z/Lzz5sZ/ bb4zHzdjT6Wd/HiA7iQVnJ90A4t78b3xe6NDRdS/n4C5B5nZ6I9MdaNIK0168zMB7hQq AIwistmbN7gip1qTBlhvkRqZ2qxK5H3vf1a1Db3/LyAZ/9X6FTI2DwKl5PMGoCkAZqxc vIqKQzaGArwiSzSS1UnJw2Y18+XisxAJYNSZesivAMYYkekvxyEbO//OKaETUa/NyHH2 WVaWWu92TmI+Yz0rM6VlVheqMHaIoUsx4q9P6QTEw//9/4U7oeLK3M3MvadVDVPJl1CW eg2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=cnb5Te5JjfcRGo6jPAixA7Wqdmj5tk2fqhvny4CjP+g=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=c5BC/pcavv3zLUzvDXBCV6glGfo9mLW1CL1ek3Va09RFv7EPVrDy7shHF4mGwKpigi i8K58wAIX3qBpkB+Ij1GoZwVzH0JWhLQ3oKnf0DbQpwbE13YLQgSZsMaDSG7QciUPeQW nUKb5xdicANhC5siXVgGGOIy2YbkdWDrePUeC6Ptz7zfDvTpC6ab7EffmhFuQaET7mmB LvcfytAefmD3SIN8t9KNmdw2jx8Mpun3Ydq3szZEe8Suxv0KWYk9yvqIyvLJGI8OUlPi 3FhRPpafDqUe+k3y717Gmb58AD8xbSR4SMmFnN9zK63aJlDcc+xtXjqAHTHqqs4atoAA Q7rQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=T4azvJks; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id n5-20020a5d4845000000b00337f722e5ccsm1396207wrs.65.2024.01.26.06.33.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Jan 2024 06:33:58 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/36] hw/arm: add PCIe to Freescale i.MX6 Date: Fri, 26 Jan 2024 14:33:41 +0000 Message-Id: <20240126143341.2101237-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240126143341.2101237-1-peter.maydell@linaro.org> References: <20240126143341.2101237-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Nikita Ostrenkov Signed-off-by: Nikita Ostrenkov Message-id: 20240108140325.1291-1-n.ostrenkov@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/arm/fsl-imx6.h | 44 ++++++++++++++++++++------------------- hw/arm/fsl-imx6.c | 25 ++++++++++++++++++++++ hw/arm/Kconfig | 2 ++ 3 files changed, 50 insertions(+), 21 deletions(-) diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h index 519b871014a..61c593ffd24 100644 --- a/include/hw/arm/fsl-imx6.h +++ b/include/hw/arm/fsl-imx6.h @@ -32,6 +32,7 @@ #include "hw/net/imx_fec.h" #include "hw/usb/chipidea.h" #include "hw/usb/imx-usb-phy.h" +#include "hw/pci-host/designware.h" #include "exec/memory.h" #include "cpu.h" #include "qom/object.h" @@ -55,27 +56,28 @@ struct FslIMX6State { DeviceState parent_obj; /*< public >*/ - ARMCPU cpu[FSL_IMX6_NUM_CPUS]; - A9MPPrivState a9mpcore; - IMX6CCMState ccm; - IMX6SRCState src; - IMX7SNVSState snvs; - IMXSerialState uart[FSL_IMX6_NUM_UARTS]; - IMXGPTState gpt; - IMXEPITState epit[FSL_IMX6_NUM_EPITS]; - IMXI2CState i2c[FSL_IMX6_NUM_I2CS]; - IMXGPIOState gpio[FSL_IMX6_NUM_GPIOS]; - SDHCIState esdhc[FSL_IMX6_NUM_ESDHCS]; - IMXSPIState spi[FSL_IMX6_NUM_ECSPIS]; - IMX2WdtState wdt[FSL_IMX6_NUM_WDTS]; - IMXUSBPHYState usbphy[FSL_IMX6_NUM_USB_PHYS]; - ChipideaState usb[FSL_IMX6_NUM_USBS]; - IMXFECState eth; - MemoryRegion rom; - MemoryRegion caam; - MemoryRegion ocram; - MemoryRegion ocram_alias; - uint32_t phy_num; + ARMCPU cpu[FSL_IMX6_NUM_CPUS]; + A9MPPrivState a9mpcore; + IMX6CCMState ccm; + IMX6SRCState src; + IMX7SNVSState snvs; + IMXSerialState uart[FSL_IMX6_NUM_UARTS]; + IMXGPTState gpt; + IMXEPITState epit[FSL_IMX6_NUM_EPITS]; + IMXI2CState i2c[FSL_IMX6_NUM_I2CS]; + IMXGPIOState gpio[FSL_IMX6_NUM_GPIOS]; + SDHCIState esdhc[FSL_IMX6_NUM_ESDHCS]; + IMXSPIState spi[FSL_IMX6_NUM_ECSPIS]; + IMX2WdtState wdt[FSL_IMX6_NUM_WDTS]; + IMXUSBPHYState usbphy[FSL_IMX6_NUM_USB_PHYS]; + ChipideaState usb[FSL_IMX6_NUM_USBS]; + IMXFECState eth; + DesignwarePCIEHost pcie; + MemoryRegion rom; + MemoryRegion caam; + MemoryRegion ocram; + MemoryRegion ocram_alias; + uint32_t phy_num; }; diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index 42f90588251..b7f93d8d9ce 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -22,6 +22,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/arm/fsl-imx6.h" +#include "hw/misc/unimp.h" #include "hw/usb/imx-usb-phy.h" #include "hw/boards.h" #include "hw/qdev-properties.h" @@ -103,6 +104,8 @@ static void fsl_imx6_init(Object *obj) object_initialize_child(obj, "eth", &s->eth, TYPE_IMX_ENET); + + object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HOST); } static void fsl_imx6_realize(DeviceState *dev, Error **errp) @@ -110,6 +113,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) MachineState *ms = MACHINE(qdev_get_machine()); FslIMX6State *s = FSL_IMX6(dev); uint16_t i; + qemu_irq irq; unsigned int smp_cpus = ms->smp.cpus; if (smp_cpus > FSL_IMX6_NUM_CPUS) { @@ -425,6 +429,27 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) FSL_IMX6_WDOGn_IRQ[i])); } + /* + * PCIe + */ + sysbus_realize(SYS_BUS_DEVICE(&s->pcie), &error_abort); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX6_PCIe_REG_ADDR); + + irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE1_IRQ); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq); + irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE2_IRQ); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq); + irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE3_IRQ); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq); + irq = qdev_get_gpio_in(DEVICE(&s->a9mpcore), FSL_IMX6_PCIE4_IRQ); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq); + + /* + * PCIe PHY + */ + create_unimplemented_device("pcie-phy", FSL_IMX6_PCIe_ADDR, + FSL_IMX6_PCIe_SIZE); + /* ROM memory */ if (!memory_region_init_rom(&s->rom, OBJECT(dev), "imx6.rom", FSL_IMX6_ROM_SIZE, errp)) { diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 2bc3ea3425e..f927878152a 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -547,6 +547,7 @@ config FSL_IMX31 config FSL_IMX6 bool + imply PCIE_DEVICES imply I2C_DEVICES select A9MPCORE select IMX @@ -555,6 +556,7 @@ config FSL_IMX6 select IMX_USBPHY select WDT_IMX2 select PL310 # cache controller + select PCI_EXPRESS_DESIGNWARE select SDHCI config ASPEED_SOC