From patchwork Tue Jan 23 08:02:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devyn Liu X-Patchwork-Id: 766188 Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB9A85675F for ; Tue, 23 Jan 2024 08:06:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.191 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705997187; cv=none; b=JPtVIHegYAn8EFyK9cbJv/hKL37xrBfRRE7uyLMGZsfv8eQajZ7mmuuoKYOcb2cheRj5nDvrGxUdoH8nq8iFXwAVYmLwh5wyL1p08WyEvnVEDcdGYm8kN5jstTSdAC4V7wrXAgLZniiaMcJsiqA8pwSdYJVpKvwqaDStYNSSRlw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705997187; c=relaxed/simple; bh=E8ClC+xI68iVUZ3u5HFzj9otJkACKMdU2+GNl4rHwlU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=pbVpKlyGvSKTsOELLgHBi3dGQYR8aHbzYWMMQMZsYIA1LLGF9zs8xSxwY9/70N4e6U4p/IMFZE6ERei+VEOca/QySpLHd6WIaI06fOvLG96YD6wyimny33PJtm/pD/k6xiWon98lxQONcYawH3rWF41prsh/AK2BH6j03IOvkCI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.191 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.163]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4TK0474P6Nz1gxwh; Tue, 23 Jan 2024 16:04:39 +0800 (CST) Received: from kwepemm600002.china.huawei.com (unknown [7.193.23.29]) by mail.maildlp.com (Postfix) with ESMTPS id B4A4A180030; Tue, 23 Jan 2024 16:06:22 +0800 (CST) Received: from localhost.localdomain (10.67.165.2) by kwepemm600002.china.huawei.com (7.193.23.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 23 Jan 2024 16:06:22 +0800 From: Devyn Liu To: CC: , , , , Subject: [PATCH 1/2] i2c: hisi: Optimized the value setting of maxwrite limit to fifo depth - 1 Date: Tue, 23 Jan 2024 16:02:21 +0800 Message-ID: <20240123080222.1512009-2-liudingyuan@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20240123080222.1512009-1-liudingyuan@huawei.com> References: <20240123080222.1512009-1-liudingyuan@huawei.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To kwepemm600002.china.huawei.com (7.193.23.29) The driver finishs a write cycle by read the fifo tx full status or write limit decrease to 0. The driver starts to write data to the FIFO after the I2C FIFO almost empty interrupt is reported. The threshold for FIFO empty interrupt is that the amount of data in the FIFO is less than or equal to 1. Reduce write maxwrite to the fifo depth - 1. Limiting the number of data to be written at a time to remaining fifo capacity. Signed-off-by: Devyn Liu Reviewed-by: Yicong Yang --- drivers/i2c/busses/i2c-hisi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-hisi.c b/drivers/i2c/busses/i2c-hisi.c index dfad5bad5075..82a0c739aae4 100644 --- a/drivers/i2c/busses/i2c-hisi.c +++ b/drivers/i2c/busses/i2c-hisi.c @@ -266,7 +266,7 @@ static int hisi_i2c_read_rx_fifo(struct hisi_i2c_controller *ctlr) static void hisi_i2c_xfer_msg(struct hisi_i2c_controller *ctlr) { - int max_write = HISI_I2C_TX_FIFO_DEPTH; + int max_write = HISI_I2C_TX_FIFO_DEPTH - 1; bool need_restart = false, last_msg; struct i2c_msg *cur_msg; u32 cmd, fifo_state; From patchwork Tue Jan 23 08:02:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Devyn Liu X-Patchwork-Id: 766187 Received: from szxga08-in.huawei.com (szxga08-in.huawei.com [45.249.212.255]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B146F57316 for ; Tue, 23 Jan 2024 08:06:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.255 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705997192; cv=none; b=OYRygFKJprIeK2zQteh1gpSbAyLjiA0GaS870sTMLJodRCjKm0rMnodu5FxbW4DSLuDcas3js6/2u7zfMl8jnTTJgxn6PpHsSRJ5/hdDvPezZ+lvu9qLzr44SnBZ20i0HcPmAfGaXnT4in1Wxxf7hMtQd5Mql88nMQIj8Nsfm7o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705997192; c=relaxed/simple; bh=1TVbFpb2qzCl2NEaUM5NvTtzbQL4H6HFaoyz8fyLNc8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=kbgY7NqG16jeW5JH1pcfYp61NvWlEoAuN4l4fy6H+EcldQeQop8D+NvNljqswaPiyXnbzDHWBBVldbWBHU3hGEvmwT4GYSnVTp5mFMx8kzJXeaXMOtTfxssIQPCAxQVGNOShgHNRuckRBwILzE51qJ0xqoThL6Vtms2LiWWUS60= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.255 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.48]) by szxga08-in.huawei.com (SkyGuard) with ESMTP id 4TK04x6Dkcz1Q87p; Tue, 23 Jan 2024 16:05:21 +0800 (CST) Received: from kwepemm600002.china.huawei.com (unknown [7.193.23.29]) by mail.maildlp.com (Postfix) with ESMTPS id 1A68118005E; Tue, 23 Jan 2024 16:06:23 +0800 (CST) Received: from localhost.localdomain (10.67.165.2) by kwepemm600002.china.huawei.com (7.193.23.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 23 Jan 2024 16:06:22 +0800 From: Devyn Liu To: CC: , , , , Subject: [PATCH 2/2] i2c: hisi: Add clearing tx aempty interrupt operation Date: Tue, 23 Jan 2024 16:02:22 +0800 Message-ID: <20240123080222.1512009-3-liudingyuan@huawei.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20240123080222.1512009-1-liudingyuan@huawei.com> References: <20240123080222.1512009-1-liudingyuan@huawei.com> Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To kwepemm600002.china.huawei.com (7.193.23.29) The driver receives the tx fifo almost empty(aempty) interrupt and reads the tx_aempty_int_mstat to start a round of data transfer. The operation of clearing the TX aempty interrupt after completing a write cycle is added to ensure that the FIFO is truly at almost empty status when an aempty interrupt is received. The threshold for fifo almost empty interrupt is defined as 1. Signed-off-by: Devyn Liu Reviewed-by: Yicong Yang --- drivers/i2c/busses/i2c-hisi.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/i2c/busses/i2c-hisi.c b/drivers/i2c/busses/i2c-hisi.c index 82a0c739aae4..08f6f97722a8 100644 --- a/drivers/i2c/busses/i2c-hisi.c +++ b/drivers/i2c/busses/i2c-hisi.c @@ -57,6 +57,8 @@ #define HISI_I2C_FS_SPK_LEN_CNT GENMASK(7, 0) #define HISI_I2C_HS_SPK_LEN 0x003c #define HISI_I2C_HS_SPK_LEN_CNT GENMASK(7, 0) +#define HISI_I2C_TX_INT_CLR 0x0040 +#define HISI_I2C_TX_AEMPTY_INT BIT(0) #define HISI_I2C_INT_MSTAT 0x0044 #define HISI_I2C_INT_CLR 0x0048 #define HISI_I2C_INT_MASK 0x004C @@ -124,6 +126,11 @@ static void hisi_i2c_clear_int(struct hisi_i2c_controller *ctlr, u32 mask) writel_relaxed(mask, ctlr->iobase + HISI_I2C_INT_CLR); } +static void hisi_i2c_clear_tx_int(struct hisi_i2c_controller *ctlr, u32 mask) +{ + writel_relaxed(mask, ctlr->iobase + HISI_I2C_TX_INT_CLR); +} + static void hisi_i2c_handle_errors(struct hisi_i2c_controller *ctlr) { u32 int_err = ctlr->xfer_err, reg; @@ -168,6 +175,7 @@ static int hisi_i2c_start_xfer(struct hisi_i2c_controller *ctlr) writel(reg, ctlr->iobase + HISI_I2C_FIFO_CTRL); hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL); + hisi_i2c_clear_tx_int(ctlr, HISI_I2C_TX_AEMPTY_INT); hisi_i2c_enable_int(ctlr, HISI_I2C_INT_ALL); return 0; @@ -323,6 +331,8 @@ static void hisi_i2c_xfer_msg(struct hisi_i2c_controller *ctlr) */ if (ctlr->msg_tx_idx == ctlr->msg_num) hisi_i2c_disable_int(ctlr, HISI_I2C_INT_TX_EMPTY); + + hisi_i2c_clear_tx_int(ctlr, HISI_I2C_TX_AEMPTY_INT); } static irqreturn_t hisi_i2c_irq(int irq, void *context) @@ -363,6 +373,7 @@ static irqreturn_t hisi_i2c_irq(int irq, void *context) if (int_stat & HISI_I2C_INT_TRANS_CPLT) { hisi_i2c_disable_int(ctlr, HISI_I2C_INT_ALL); hisi_i2c_clear_int(ctlr, HISI_I2C_INT_ALL); + hisi_i2c_clear_tx_int(ctlr, HISI_I2C_TX_AEMPTY_INT); complete(ctlr->completion); }