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[209.51.188.17]) by mx.google.com with ESMTPS id f1si15873887qtm.155.2019.09.11.09.50.49 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 11 Sep 2019 09:50:49 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=SthgXHrE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53814 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i85pQ-0006tG-0c for patch@linaro.org; Wed, 11 Sep 2019 12:50:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43480) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i85oi-0006Ua-Qn for qemu-devel@nongnu.org; Wed, 11 Sep 2019 12:50:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i85oh-000481-6U for qemu-devel@nongnu.org; Wed, 11 Sep 2019 12:50:04 -0400 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:53734) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i85og-00047L-VS for qemu-devel@nongnu.org; Wed, 11 Sep 2019 12:50:03 -0400 Received: by mail-wm1-x344.google.com with SMTP id q18so4306081wmq.3 for ; Wed, 11 Sep 2019 09:50:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LdShYhT6EQrLVHl+0PZ3U9EB4Wx5zUovoSRv7pyVvlc=; b=SthgXHrElek+o9gIx9oiI/fmC4N5MLFMdcGZoWUrBpH48/6i54wz+Tctgtt8zTp1r0 LwVO3tQ7r1iq0aW1nzNqJzCLE3FDWYdmIhDxkOjY18K4GHrkvIS1DsUzuRLOf6szWutR ZtyMFG0JzFYfucQbA0PXUMGLnc7qmrrPjq4ttRJnyg99tKEzbFn810kAijBbvuXnAlCe 2khhvK1g1n1DVk2nOWkiHaJSOpBr909cF/Q/m8n0pKPxv2il4DyK0VF0kYIThsXDNcxM Q2w70i6NrNI1LzOL1svivtdHk3+zA+utYtrtRdp5GeT/kcMiL7M/9w7Dlml8YSc6JKJ3 TlIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LdShYhT6EQrLVHl+0PZ3U9EB4Wx5zUovoSRv7pyVvlc=; b=mroDm4zSuR6SOGDx6UUnPbCezIbPqw/tyNYELhvpFLf1jYGXFbcNBOM/ReLnMScMXc hCpkV81WLazs5Nk7j+rU83neEZ/C8JbRO9LwyHKeUx6KdVCBg3QWr+RzyWlxq/vxLrdA LXQ3Kewi9fCWOCTmoHeU+nqXI2e65KrnY/ATeww4GQ3eaB4FHAD5P3hrFi9kg54F+e1c XyMwRnSAuWk5OfLWF1OMcpOTHU/a45EZ2ShBVE43DueT9rvTG4b2KqEylKF+HgMnFCkg 1427GS8RX5re2mf/voEU73hdFH7kML9cwebAx3+IBfps9joE1PmeMXlSZLAO3ym00Tv0 XvqQ== X-Gm-Message-State: APjAAAWqDK6sef3uBMJMKfb5/OR5xS7OcBBeS9sA1YaODCuYGmDI2Swc gGFHI51QwxY7EbcXSTiTmm+lQg== X-Received: by 2002:a7b:ca4b:: with SMTP id m11mr4585914wml.144.1568220601841; Wed, 11 Sep 2019 09:50:01 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id f17sm17979624wru.29.2019.09.11.09.50.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2019 09:50:00 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 168511FF8C; Wed, 11 Sep 2019 17:50:00 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: peter.maydell@linaro.org Date: Wed, 11 Sep 2019 17:49:55 +0100 Message-Id: <20190911164959.11003-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190911164959.11003-1-alex.bennee@linaro.org> References: <20190911164959.11003-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH v5 1/5] tests/tcg: clean-up some comments after the de-tangling X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These were missed in the recent de-tangling so have been updated to be more actuate. I've also built up ARM_TESTS in a manner similar to AARCH64_TESTS for better consistency. Signed-off-by: Alex Bennée --- tests/tcg/Makefile.target | 7 +++++-- tests/tcg/aarch64/Makefile.target | 3 ++- tests/tcg/arm/Makefile.target | 15 ++++++++------- 3 files changed, 15 insertions(+), 10 deletions(-) -- 2.20.1 Reviewed-by: Peter Maydell diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target index 8808beaf74b..679eb56bd37 100644 --- a/tests/tcg/Makefile.target +++ b/tests/tcg/Makefile.target @@ -74,8 +74,11 @@ TIMEOUT=15 endif ifdef CONFIG_USER_ONLY -# The order we include is important. We include multiarch, base arch -# and finally arch if it's not the same as base arch. +# The order we include is important. We include multiarch first and +# then the target. If there are common tests shared between +# sub-targets (e.g. ARM & AArch64) then it is up to +# $(TARGET_NAME)/Makefile.target to include the common parent +# architecture in its VPATH. -include $(SRC_PATH)/tests/tcg/multiarch/Makefile.target -include $(SRC_PATH)/tests/tcg/$(TARGET_NAME)/Makefile.target diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index e763dd9da37..9758f89f905 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -8,7 +8,7 @@ VPATH += $(ARM_SRC) AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64 VPATH += $(AARCH64_SRC) -# we don't build any other ARM test +# Float-convert Tests AARCH64_TESTS=fcvt fcvt: LDFLAGS+=-lm @@ -17,6 +17,7 @@ run-fcvt: fcvt $(call run-test,$<,$(QEMU) $<, "$< on $(TARGET_NAME)") $(call diff-out,$<,$(AARCH64_SRC)/fcvt.ref) +# Pauth Tests AARCH64_TESTS += pauth-1 pauth-2 run-pauth-%: QEMU_OPTS += -cpu max diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target index aa4e4e3782c..7347d3d0adb 100644 --- a/tests/tcg/arm/Makefile.target +++ b/tests/tcg/arm/Makefile.target @@ -8,25 +8,26 @@ ARM_SRC=$(SRC_PATH)/tests/tcg/arm # Set search path for all sources VPATH += $(ARM_SRC) -ARM_TESTS=hello-arm test-arm-iwmmxt - -TESTS += $(ARM_TESTS) fcvt - +# Basic Hello World +ARM_TESTS = hello-arm hello-arm: CFLAGS+=-marm -ffreestanding hello-arm: LDFLAGS+=-nostdlib +# IWMXT floating point extensions +ARM_TESTS += test-arm-iwmmxt test-arm-iwmmxt: CFLAGS+=-marm -march=iwmmxt -mabi=aapcs -mfpu=fpv4-sp-d16 test-arm-iwmmxt: test-arm-iwmmxt.S $(CC) $(CFLAGS) $< -o $@ $(LDFLAGS) -ifeq ($(TARGET_NAME), arm) +# Float-convert Tests +ARM_TESTS += fcvt fcvt: LDFLAGS+=-lm # fcvt: CFLAGS+=-march=armv8.2-a+fp16 -mfpu=neon-fp-armv8 - run-fcvt: fcvt $(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)") $(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref) -endif + +TESTS += $(ARM_TESTS) # On ARM Linux only supports 4k pages EXTRA_RUNS+=run-test-mmap-4096 From patchwork Wed Sep 11 16:49:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 173623 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp997462ilq; Wed, 11 Sep 2019 09:54:16 -0700 (PDT) X-Google-Smtp-Source: APXvYqxq6EZVvwTH2+g4TulGBLdkjWGyolJOFf5wlsbthuX/AyMn+2oYhcT+F57iGqwehjadScnH X-Received: by 2002:a17:906:6403:: with SMTP id d3mr21216667ejm.99.1568220856322; Wed, 11 Sep 2019 09:54:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1568220856; cv=none; d=google.com; s=arc-20160816; b=FUENvG2DgD3mlchP9f7RrTdAKh7RKMCWKhvBFIKkvaI6alVB1HfkeYlahIJF8k+zDh NlCqtqUn3pF9YvaBKLAfrUNpGWhJ/gWhqkKkb4nCjvCfJH0IubUAdwos4UF5gUm/mOJT 4BlTx/ya0U8P86rL72hhsllp3ifeiuPe37UD0l6yHSSHEzIR34ttcvzLXNPfi+Xio/Yp ANBraa/jFXg0aQ3Mh7TlAzwHUmwFNLIr7DdSkZaQvQDlU9iwuZ5iB9xpZh1omleXEG5m Nr9E/Og9uyqa3E6TcaQgZ3bAViigAPQvG3qqBIFnbzjElMtU9JJ0mj9t8G1dqdOfBf6u kZAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=uRjmOsEbXk15ydPmEJ99gd5DAhkd0VbLE+A+syxTleE=; b=ChG+kIOGmmD6okcbwr1UdGgL1NKMLnMs0DYS16Let8Q/mNhV9OMnlL4NjS7VzvoNUo LL00BEwz4mjur6dYspEAPRH8OF7yD2P55AOMTfDutLcFVpfYjceiN08RXHVSzt8TnwWY kgkSVZkbyM2WOCEhHWZroO265g5QRK51uQCAlvt+Rp0QHM40JTpIspaD5Q03u9XsAd0N pPEVskivYRJypn0wo1K36l2GBPzRfMcrPNJ6F+pIlOO6hVwUsmTr1AWMgsZ1BPv+Ag/b zBPKI5F7Y3uz2dBbD3l6JBzBTX2h3Zec/wN00VaKzGkMgsHcA+UpKTl+zTSAbp0e71L5 RxKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=i6wfyfdH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a8si4102734edn.332.2019.09.11.09.54.16 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 11 Sep 2019 09:54:16 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=i6wfyfdH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53862 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i85sl-0002Op-Ae for patch@linaro.org; Wed, 11 Sep 2019 12:54:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43490) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i85oj-0006Uc-57 for qemu-devel@nongnu.org; Wed, 11 Sep 2019 12:50:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i85oh-00048K-Ry for qemu-devel@nongnu.org; Wed, 11 Sep 2019 12:50:05 -0400 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:44432) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1i85oh-00047m-Lf for qemu-devel@nongnu.org; Wed, 11 Sep 2019 12:50:03 -0400 Received: by mail-wr1-x443.google.com with SMTP id k6so13226334wrn.11 for ; Wed, 11 Sep 2019 09:50:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uRjmOsEbXk15ydPmEJ99gd5DAhkd0VbLE+A+syxTleE=; b=i6wfyfdHclxGEDVmHLKAronMHhWnsi68fRV8yW7768Cwv6sjVsiIsU6ev0HN1/OJGQ 8zw7UiLInPgXcFW97vv1wqe+CyWfs6bZ3eU92iGB8HcTig4odYz6hqNMiy4HsLiHvKhT QIe3f9BSAlS7syrbFtwA96e9adlBDQ8WHM75IXfrYmiHoScqG87nIk5lr6ncJ4oWAwyY uXbIkp7LIE4AL44io5OIKcou4EulLMDcEMeqfdN9vRfzjrHJ1XAu+SkKlALLAhj52N5/ gpJQjQg5qgNe33f3Uve8W0gJod59kAQ6s05ouM/1+gaV0dlo11jyXMS6/F9y9/Xl3D7u M6cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uRjmOsEbXk15ydPmEJ99gd5DAhkd0VbLE+A+syxTleE=; b=SxeAtpvEZJjBFLD0IGF+j6nWwy38/mlhfkzVEnR/WRM7/voS6ll2QAkvBKRCQOdFUz Ska94hQ1IMgcgKkwyyJ0mlI5g+1++KY+Uxyb4DOfpjBne0vwBOF+aJ97GNdyXwujXsHH NDKyqlhnTKUWqiRnEb2LDutT3RUDkbOIl3rm5VzO1x8f+6lLe/xb3CpWzxEaNrLNhZiS VMCUH/04h1FFWl5r3DE6XLf+TwBQA3cD7Oji+6bojMcEnHUgENqve7dOJVd3Pi5b6FMA Vrl0M38uc4ccbEhJRDyI++s727mx1W74eQ5veXe0bfgtZYUo8x8GIRUXKkukqQQ5TYEO EQvA== X-Gm-Message-State: APjAAAXdvPDz2jurcT6f/jyqUVarcCssnb4zcdqqM2gG8yWRMh6CItRM ywWaRKp0w2Lm4f8ejAgDeaPaPg== X-Received: by 2002:a05:6000:b:: with SMTP id h11mr1957174wrx.270.1568220602581; Wed, 11 Sep 2019 09:50:02 -0700 (PDT) Received: from zen.linaroharston ([51.148.130.216]) by smtp.gmail.com with ESMTPSA id h21sm16378463wrc.71.2019.09.11.09.50.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Sep 2019 09:50:01 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 4A1F71FF8F; Wed, 11 Sep 2019 17:50:00 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: peter.maydell@linaro.org Date: Wed, 11 Sep 2019 17:49:56 +0100 Message-Id: <20190911164959.11003-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190911164959.11003-1-alex.bennee@linaro.org> References: <20190911164959.11003-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH v5 2/5] target/arm: handle M-profile semihosting at translate time X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We do this for other semihosting calls so we might as well do it for M-profile as well. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- v2 - update for change to gen_exception_internal_insn API v3 - update for decode tree v4 - use !IS_USER --- target/arm/m_helper.c | 18 ++++++------------ target/arm/translate.c | 8 +++++++- 2 files changed, 13 insertions(+), 13 deletions(-) -- 2.20.1 diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 884d35d2b02..27cd2f3f964 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -2114,19 +2114,13 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) break; } break; + case EXCP_SEMIHOST: + qemu_log_mask(CPU_LOG_INT, + "...handling as semihosting call 0x%x\n", + env->regs[0]); + env->regs[0] = do_arm_semihosting(env); + return; case EXCP_BKPT: - if (semihosting_enabled()) { - int nr; - nr = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) & 0xff; - if (nr == 0xab) { - env->regs[15] += 2; - qemu_log_mask(CPU_LOG_INT, - "...handling as semihosting call 0x%x\n", - env->regs[0]); - env->regs[0] = do_arm_semihosting(env); - return; - } - } armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false); break; case EXCP_IRQ: diff --git a/target/arm/translate.c b/target/arm/translate.c index 34bb280e3da..6689acc911e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8424,7 +8424,13 @@ static bool trans_BKPT(DisasContext *s, arg_BKPT *a) if (!ENABLE_ARCH_5) { return false; } - gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false)); + if (arm_dc_feature(s, ARM_FEATURE_M) && + semihosting_enabled() && !IS_USER(s) && + (a->imm == 0xab)) { + gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST); + } else { + gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false)); + } return true; } From patchwork Wed Sep 11 16:49:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 173622 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp995094ilq; Wed, 11 Sep 2019 09:52:04 -0700 (PDT) X-Google-Smtp-Source: APXvYqxiXVhMOj+p9kltqgFbaO3LVpgttbcYbbjuDRtARL+v57/yHrENZ/vZ7N6spA+M/A7BtCtB X-Received: by 2002:a0c:f5c5:: with SMTP id q5mr22631621qvm.154.1568220723900; Wed, 11 Sep 2019 09:52:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1568220723; cv=none; d=google.com; s=arc-20160816; b=PPhSKnMfpyyhtDjIS8CKjtT2dIDNXvZzu0C4NVy6iDe26/JPYrgWL/KIicSf93PMB7 +Nw4+ydwMnTHRc0e+AF0nBMTCWhdw12N9OMBYJUuvEgcZjV7wsQY/mN7f/M8n3qwP1qh SdlllVOuThtGVsL/7OSn3g4ZURobA7hom5hMDY9h6UUnbuM6ck039vo5KWq7HZJnsfpP p2dBK7BdLaFUbN+7qiZmp0bEq9Cx7puAY4GIfBL2SigUOX4XPiQbSMYPLtr8Sp/aWP5J eFrbCXCP3Wclk1lKVhorl07k+SOCK7hqPlyKprEwsGt1hFBvx9ermPyFa1GD09P8DT7b rx/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=tZDnbxA1tgGLPJyp4aIprnZlr8V2xMzpBpOE4T56/8w=; b=uiTvqk/hQghAXrxk1qKai9nJzn7t2+Lem1HN8NpcTVItAI0Z8YeP1ZAhu1uhFmFUBl YwY2yKBszYv9NUhsKZodGriC2U+Si16W1aw/BhNQYyVuAy6Q2bd501Tp82Q2bupBIZwA 9Snbd69nnlmSJeld8ypnYzuyP0NZyvyZsyaZVtWHf4AfusvI++QkPiEZOwRSvdsoojON 3LldmYYEpULszntLW4Kib6TPp2MqTYjtZkaYyNpNHGExc6SZmavwa13BYZ4QIygHG8Hz Ut1/Darmsn+AFnsE7xQ17pKOviMui3JdOF9ThYjWapwtoo233D/fim98OItkgXh4OrrY uQbA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Y17WVTPu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH v5 3/5] target/arm: handle A-profile semihosting at translate time X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" As for the other semihosting calls we can resolve this at translate time. Signed-off-by: Alex Bennée --- v2 - update for change to gen_exception_internal_insn API v3 - update for decode tree, merge T32 & A32 commits - dropped r-b due to changes v4 - !IS_USER and !arm_dc_feature(s, ARM_FEATURE_M) v5 - only if !IS_USER for softmmu, linux-user is still allowed --- target/arm/translate.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) -- 2.20.1 Reviewed-by: Peter Maydell diff --git a/target/arm/translate.c b/target/arm/translate.c index 6689acc911e..fac791c4b06 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10219,14 +10219,25 @@ static bool trans_CBZ(DisasContext *s, arg_CBZ *a) } /* - * Supervisor call + * Supervisor call - both T32 & A32 come here so we need to check + * which mode we are in when checking for semihosting. */ static bool trans_SVC(DisasContext *s, arg_SVC *a) { - gen_set_pc_im(s, s->base.pc_next); - s->svc_imm = a->imm; - s->base.is_jmp = DISAS_SWI; + const uint32_t semihost_imm = s->thumb ? 0xab : 0x123456; + + if (!arm_dc_feature(s, ARM_FEATURE_M) && semihosting_enabled() && +#ifndef CONFIG_USER_ONLY + !IS_USER(s) && +#endif + (a->imm == semihost_imm)) { + gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST); + } else { + gen_set_pc_im(s, s->base.pc_next); + s->svc_imm = a->imm; + s->base.is_jmp = DISAS_SWI; + } return true; } From patchwork Wed Sep 11 16:49:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 173624 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp999358ilq; Wed, 11 Sep 2019 09:55:53 -0700 (PDT) X-Google-Smtp-Source: APXvYqyoATWBvd8/Wclyp8EWi7FC3vfYMhZPcIgQ0vItqVtydGQJT+dxBb8izqZR1iqDA0GSmmME X-Received: by 2002:a17:906:1995:: with SMTP id g21mr30643282ejd.226.1568220953564; Wed, 11 Sep 2019 09:55:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1568220953; cv=none; d=google.com; s=arc-20160816; b=LMjVLp1lzt+DFIL8v2GSpcWe71/6vBgbB5ngkb5i80YYjHuYf8EgMQuf7lY/gR1lpk rWsS4gFqBFCsgFjy+h57FGOKYwpYGH3LXUFue4imQIuzZ38KZb8yYFVrTOrz0TvIiG3t Qpj1nI8dRHY16KIpYctmIr3EGgCJKaLmrfi1ZxKzcaV59JkSMyTWFE+AoLtoSvdTBwkf CeX8E3ot/+5YpH/Ic3kLlqD9oUzcZE0OL/f067/cSFiDSKewTHzcehnCZ1dnAZlBQ+9m fB+2CHwZKR6jcySk4PPecmvsj4U++hl5LuQMu9LU4nWlZ01xs51NqJWlPEzjM9bzF+kX h6IA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=zlpCkLPxW/plsVCAFKM/m8fldNY7IYpuz4hZ7EfXmKg=; b=mRIab/zSlfMJEp/v3+/xCdHEbJ2mMSI4JGnOmaZ6SCVSq+eZAMIUfwB9cc9sg3MQnG gE56j4ErinAWfOHVMqzrNX5x+HfufqZBkS5haa8o2i3ujl4CqxxX9u4cMDkqrBk4l43J G8MkcomYBMWK378U+UEWQxL9pb8jsFKL/scuyIZ/0do1WyiufTNw6G4lhxNjmohLR4+9 xrso6vTUwb2/TpFgT8HMgmGqDV5aPVtu1xVvASVTzOlGPVUrMWxFJQWJK0igSagqWskw uIRoZmtRBzymPxWWvnJ43rTWDP2Bn+yjT8/xIVPQF604Vx8oSBBghCewysKEUfaAa4TN uDQg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=WvuURnZn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH v5 4/5] target/arm: remove run time semihosting checks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now we do all our checking and use a common EXCP_SEMIHOST for semihosting operations we can make helper code a lot simpler. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- v2 - fix re-base conflicts - hoist EXCP_SEMIHOST check - comment cleanups v5 - move CONFIG_TCG ifdefs --- target/arm/helper.c | 96 +++++++++++---------------------------------- 1 file changed, 22 insertions(+), 74 deletions(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 507026c9154..a87ae6d46a1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8339,88 +8339,32 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) new_el, env->pc, pstate_read(env)); } -static inline bool check_for_semihosting(CPUState *cs) -{ +/* + * Do semihosting call and set the appropriate return value. All the + * permission and validity checks have been done at translate time. + * + * We only see semihosting exceptions in TCG only as they are not + * trapped to the hypervisor in KVM. + */ #ifdef CONFIG_TCG - /* Check whether this exception is a semihosting call; if so - * then handle it and return true; otherwise return false. - */ +static void handle_semihosting(CPUState *cs) +{ ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; if (is_a64(env)) { - if (cs->exception_index == EXCP_SEMIHOST) { - /* This is always the 64-bit semihosting exception. - * The "is this usermode" and "is semihosting enabled" - * checks have been done at translate time. - */ - qemu_log_mask(CPU_LOG_INT, - "...handling as semihosting call 0x%" PRIx64 "\n", - env->xregs[0]); - env->xregs[0] = do_arm_semihosting(env); - return true; - } - return false; + qemu_log_mask(CPU_LOG_INT, + "...handling as semihosting call 0x%" PRIx64 "\n", + env->xregs[0]); + env->xregs[0] = do_arm_semihosting(env); } else { - uint32_t imm; - - /* Only intercept calls from privileged modes, to provide some - * semblance of security. - */ - if (cs->exception_index != EXCP_SEMIHOST && - (!semihosting_enabled() || - ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR))) { - return false; - } - - switch (cs->exception_index) { - case EXCP_SEMIHOST: - /* This is always a semihosting call; the "is this usermode" - * and "is semihosting enabled" checks have been done at - * translate time. - */ - break; - case EXCP_SWI: - /* Check for semihosting interrupt. */ - if (env->thumb) { - imm = arm_lduw_code(env, env->regs[15] - 2, arm_sctlr_b(env)) - & 0xff; - if (imm == 0xab) { - break; - } - } else { - imm = arm_ldl_code(env, env->regs[15] - 4, arm_sctlr_b(env)) - & 0xffffff; - if (imm == 0x123456) { - break; - } - } - return false; - case EXCP_BKPT: - /* See if this is a semihosting syscall. */ - if (env->thumb) { - imm = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) - & 0xff; - if (imm == 0xab) { - env->regs[15] += 2; - break; - } - } - return false; - default: - return false; - } - qemu_log_mask(CPU_LOG_INT, "...handling as semihosting call 0x%x\n", env->regs[0]); env->regs[0] = do_arm_semihosting(env); - return true; } -#else - return false; -#endif } +#endif /* Handle a CPU exception for A and R profile CPUs. * Do any appropriate logging, handle PSCI calls, and then hand off @@ -8451,13 +8395,17 @@ void arm_cpu_do_interrupt(CPUState *cs) return; } - /* Semihosting semantics depend on the register width of the - * code that caused the exception, not the target exception level, - * so must be handled here. + /* + * Semihosting semantics depend on the register width of the code + * that caused the exception, not the target exception level, so + * must be handled here. */ - if (check_for_semihosting(cs)) { +#ifdef CONFIG_TCG + if (cs->exception_index == EXCP_SEMIHOST) { + handle_semihosting(cs); return; } +#endif /* Hooks may change global state so BQL should be held, also the * BQL needs to be held for any modification of From patchwork Wed Sep 11 16:49:59 2019 Content-Type: text/plain; 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X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH v5 5/5] target/arm: remove run-time semihosting checks for linux-user X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Riku Voipio , qemu-arm@nongnu.org, =?utf-8?q?Alex_?= =?utf-8?q?Benn=C3=A9e?= , qemu-devel@nongnu.org, Laurent Vivier Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now we do all our checking at translate time we can make cpu_loop a little bit simpler. We also introduce a simple linux-user semihosting test case to defend the functionality. The out-of-tree softmmu based semihosting tests are still more comprehensive. Signed-off-by: Alex Bennée --- linux-user/arm/cpu_loop.c | 3 --- linux-user/arm/target_syscall.h | 3 --- tests/tcg/aarch64/Makefile.target | 5 ++++ tests/tcg/arm/Makefile.target | 5 ++++ tests/tcg/arm/semihosting.c | 45 +++++++++++++++++++++++++++++++ 5 files changed, 55 insertions(+), 6 deletions(-) create mode 100644 tests/tcg/arm/semihosting.c -- 2.20.1 diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index 8d65de5b9f4..e28c45cd4ab 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -325,9 +325,6 @@ void cpu_loop(CPUARMState *env) if (n == ARM_NR_cacheflush) { /* nop */ - } else if (n == ARM_NR_semihosting - || n == ARM_NR_thumb_semihosting) { - env->regs[0] = do_arm_semihosting (env); } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) { /* linux syscall */ if (env->thumb || n == 0) { diff --git a/linux-user/arm/target_syscall.h b/linux-user/arm/target_syscall.h index afc0772e194..f85cbdaf56f 100644 --- a/linux-user/arm/target_syscall.h +++ b/linux-user/arm/target_syscall.h @@ -18,9 +18,6 @@ struct target_pt_regs { #define ARM_NR_set_tls (ARM_NR_BASE + 5) #define ARM_NR_get_tls (ARM_NR_BASE + 6) -#define ARM_NR_semihosting 0x123456 -#define ARM_NR_thumb_semihosting 0xAB - #if defined(TARGET_WORDS_BIGENDIAN) #define UNAME_MACHINE "armv5teb" #else diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 9758f89f905..509f1afa93d 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -21,4 +21,9 @@ run-fcvt: fcvt AARCH64_TESTS += pauth-1 pauth-2 run-pauth-%: QEMU_OPTS += -cpu max +# Semihosting smoke test for linux-user +AARCH64_TESTS += semihosting +run-semihosting: semihosting + $(call run-test,$<,$(QEMU) $< 2> $<.err, "$< on $(TARGET_NAME)") + TESTS += $(AARCH64_TESTS) diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target index 7347d3d0adb..3b7fc9a64be 100644 --- a/tests/tcg/arm/Makefile.target +++ b/tests/tcg/arm/Makefile.target @@ -27,6 +27,11 @@ run-fcvt: fcvt $(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)") $(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref) +# Semihosting smoke test for linux-user +ARM_TESTS += semihosting +run-semihosting: semihosting + $(call run-test,$<,$(QEMU) $< 2> $<.err, "$< on $(TARGET_NAME)") + TESTS += $(ARM_TESTS) # On ARM Linux only supports 4k pages diff --git a/tests/tcg/arm/semihosting.c b/tests/tcg/arm/semihosting.c new file mode 100644 index 00000000000..09c89cb481a --- /dev/null +++ b/tests/tcg/arm/semihosting.c @@ -0,0 +1,45 @@ +/* + * linux-user semihosting checks + * + * Copyright (c) 2019 + * Written by Alex Bennée + * + * SPDX-License-Identifier: GPL-3.0-or-later + */ + +#include + +#define SYS_WRITE0 0x04 +#define SYS_REPORTEXC 0x18 + +void __semi_call(uintptr_t type, uintptr_t arg0) +{ +#if defined(__arm__) + register uintptr_t t asm("r0") = type; + register uintptr_t a0 asm("r1") = arg0; + asm("svc 0xab" + : /* no return */ + : "r" (t), "r" (a0)); +#else + register uintptr_t t asm("x0") = type; + register uintptr_t a0 asm("x1") = arg0; + asm("hlt 0xf000" + : /* no return */ + : "r" (t), "r" (a0)); +#endif +} + +int main(int argc, char *argv[argc]) +{ +#if defined(__arm__) + uintptr_t exit_code = 0x20026; +#else + uintptr_t exit_block[2] = {0x20026, 0}; + uintptr_t exit_code = (uintptr_t) &exit_block; +#endif + + __semi_call(SYS_WRITE0, (uintptr_t) "Hello World"); + __semi_call(SYS_REPORTEXC, exit_code); + /* if we get here we failed */ + return -1; +}