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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:11 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 01/28] spi: s3c64xx: explicitly include Date: Thu, 25 Jan 2024 14:49:39 +0000 Message-ID: <20240125145007.748295-2-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The driver uses readl() but does not include . It is good practice to directly include all headers used, it avoids implicit dependencies and spurious breakage if someone rearranges headers and causes the implicit include to vanish. Include the missing header. Fixes: 230d42d422e7 ("spi: Add s3c64xx SPI Controller driver") Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 7f7eb8f742e4..c1cbc4780a3b 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include From patchwork Thu Jan 25 14:49:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 766127 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E938A6EB56 for ; Thu, 25 Jan 2024 14:50:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194218; cv=none; b=nkMl/gSgUGOCWvPEq9QpHVlpJ+mx7GGluZd31tnZaK3QyOLtL5s4I81LH3Q8N4KQwbzzHoZt2rsHBtLkco2sDpfN/u0+jcgxmavY7HaA2ZU/OUXIvW7wF2+mRbx+PU1TJJWkUJ6gEE9TA3mKu2EwkwavlOVOxcY1ESe4Hz+vsPQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194218; c=relaxed/simple; bh=kM3TvYJuXO/2fu3NMZYphC4cXulYUhqSFXQCMxVbb5I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kFLN0QU7Jt3REoc17qi/7K4mX/9sV3rRGn9lvMdjlpiogA6ZlKJVd4VC5O+ojuMXUZt6SIgZat05+ci3mLol/UfskI9VA2KcLb3jugxUsdEbeUcTLKAzGYJtULzyvMMImXUtI6xoEn5HPiE48Qrdr8GQcmDBQQzYsHAy43uA9UY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=eu4YonSw; arc=none smtp.client-ip=209.85.128.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="eu4YonSw" Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-40eacb6067dso54900205e9.1 for ; Thu, 25 Jan 2024 06:50:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706194214; x=1706799014; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jF19RJft8z+RVxLTw4w4Iz/5TESrFLzi3P4+GrCzRsY=; b=eu4YonSwpVXoKhkxJ0gK+4tjqKJGpZCK0qBz/9qjzD9zks7xpcvnNk9rkOhSeh4AYZ DrgpTEHG6XFGFVr8hKQsSkNIbmpNHBfVhBPhVtQ/QLl4eH1/Uk9MTxqVBvQp9KagLZZT 99pocgqmQILOZ7QoS2eEOWHFpSGFHvBRe4Ic6dQ20O7g52rht75D0KentimB8JunnoT1 /MH1zw2xweGhMnApcmInQKiN0BxgdeQG9/gnw8zBWhThNBLpk856H3mUohAgjMQYQmTH 8djT7+/KT0emeYnFqeXu+KKZNSn5PfZXcLdvMXX9Ht+mY//BcvOaGR/CtHn2X9jg9cIY dNbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706194214; x=1706799014; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jF19RJft8z+RVxLTw4w4Iz/5TESrFLzi3P4+GrCzRsY=; b=j7KX64ZjyrtzfA+aIGdEg3ReYQJwyhfE18Yzf49E9A2ipTtK/LF2kiZOmVW7UbH+3o a2wkV+kOobjorFirhXOtKHoGewRJ6RSLJguUo1dXLM8RcQUTn8qx3oGJb+YsnhbY9Agc eOugrRalAXXhCRVM/JfCffnSl6f0fVgomtSwrga4JgvE03+KDnNeSLdb+ukd2ElsjVWC iPwHoeZFAdm1trhlxOkxEA9hmq5LdFtGNsxSEa/TpyliVo5bIUTinvozrH6YtMToCgMM GtFtAXUVXR4wwOLu6PTZi6+H4/6Gog7P+SQIC22uZQcoEzVFYmQyxrvNjkS6Ku6Z+ASD 6YOQ== X-Gm-Message-State: AOJu0YzBMISyog4I0HTTnJf8JA5IVc0wkDTW6TevSsMoXDcTlHz6ascm FQ++UB0EhfzRFFRPqvK715xHzDCKnmAPMnwwg/myBg7szSXFv2L4OSaqnsFwYso= X-Google-Smtp-Source: AGHT+IEHoREsOegc3WurYtU5U/rBHZhVnyI3Hhay3VuRSOXGnBpm1+f1t0k7hs57nCO7FwSA9TxYig== X-Received: by 2002:a1c:7c19:0:b0:40e:67e9:ae0 with SMTP id x25-20020a1c7c19000000b0040e67e90ae0mr366973wmc.235.1706194214090; Thu, 25 Jan 2024 06:50:14 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:13 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus , Krzysztof Kozlowski Subject: [PATCH v2 04/28] spi: dt-bindings: samsung: add google,gs101-spi compatible Date: Thu, 25 Jan 2024 14:49:42 +0000 Message-ID: <20240125145007.748295-5-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add "google,gs101-spi" dedicated compatible for representing SPI of Google GS101 SoC. Reviewed-by: Sam Protsenko Reviewed-by: Krzysztof Kozlowski Acked-by: Andi Shyti Signed-off-by: Tudor Ambarus --- Documentation/devicetree/bindings/spi/samsung,spi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/samsung,spi.yaml b/Documentation/devicetree/bindings/spi/samsung,spi.yaml index f71099852653..2f0a0835ecfb 100644 --- a/Documentation/devicetree/bindings/spi/samsung,spi.yaml +++ b/Documentation/devicetree/bindings/spi/samsung,spi.yaml @@ -17,6 +17,7 @@ properties: compatible: oneOf: - enum: + - google,gs101-spi - samsung,s3c2443-spi # for S3C2443, S3C2416 and S3C2450 - samsung,s3c6410-spi - samsung,s5pv210-spi # for S5PV210 and S5PC110 From patchwork Thu Jan 25 14:49:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 766126 Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B11516EB4D for ; Thu, 25 Jan 2024 14:50:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194219; cv=none; b=uj/O51uE2jx46iN8unQFTjYKYbALbGS5b+RqqR6j1/JiCh8zrZiD+RSj5QatlbiJ1CxeQgfoQ/VWiRWdWeJb5QpRQARkyC48iMn6tDW+4CGYIouBIzo1zCq6k1mCHp8yzb2G+zD4bIEmpM8N/NOzetm9Q4yP78PE0GkFEK1YqNM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194219; c=relaxed/simple; bh=HUS+pk9N92y7YBQl1ZH9U+K4lAXt5pbyiE0NqzVBDmw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dJAea+p+63eDWxwSiLYnywwL8sPihNlS9FbmRnEtitg0Toviw6IlAbgCPmtmejtO/poFrG4WCkZVlUWrGcEW2Ix0m2hCvCZcZDOUQLf566GGoTF/Jz6JpKEKRxoUyKUEupRVF3bMeOc09R2rGpPVttt/FoR/moD6O2BFLz6DE+Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=V4dykocY; arc=none smtp.client-ip=209.85.221.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="V4dykocY" Received: by mail-wr1-f53.google.com with SMTP id ffacd0b85a97d-337d58942c9so6832353f8f.0 for ; Thu, 25 Jan 2024 06:50:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706194215; x=1706799015; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7RbS7SdUaAw1K/g37Ed+dGAKWi2x8GPreQeT5KyvnlQ=; b=V4dykocYyNiq/b404iwjiGVNGxpPEcxyPahcaPuBwOuNqhWN8R1e+JCpmY7RQ04qeB lm05XVAZDP0n+uBQ7y7ZQbimlaXIF4YABCWW4t/CMe56MwPI7THCrZEHrex2ToE1B/eS hcyqzDkFWJiUq+6GU11pJiERa2s7rNa3mRLexhCjfYBpPBhKW0pDE23GGMHueHrJ8BKg xjCZd5eZzy6g73DR4Ulq8bn7ZqPBLbkF43hAKtmxZ5Lm9TpWk5Obit0+aSWDwkANsne/ 0FqcVAD1J343oDazgNUHv4svlDDGUmSCfxMLWLCBtM7Pn0KqESuGibgiKCk1fA4BsTQ/ J5fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706194215; x=1706799015; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7RbS7SdUaAw1K/g37Ed+dGAKWi2x8GPreQeT5KyvnlQ=; b=cqJbJ7aBpw58GKtZN1U9r0Um8Wc9Z4G3SpInLZdrQ7gGH1VIaELE7vWjbiiPR9VluA S367bSjEGHCpoQmaX/b8MYJPdL+MEOUrJOhVDkQ4BPOJ3APgtqsTLQll84VovOPlH9os Nf18DDWgW5k9aiQt7MOLEi+tnX5WUadc9vovr9F6e80uGrVgX9JJ9CAuXfjHXzP1SJ5J qoYAgoK3BgO4EBVq2yRCIgXpCgDJI3ApLzdDc8c/zlNlyMpqWnoQnuccAcyG6DqdiNm8 Ug2xPTVEIC2zuQXiRZlQeiT8bDVLHqRddXgdUHozKYQYQh/ekA555ZskulLrXvukdkOt sM8w== X-Gm-Message-State: AOJu0YyRIp/HJj9eZBTTuos/tuN0o8BoE6R01DPguaC0LzvRSdlLkqVj csGrlkr0RPN+WqO51ljyyFe6Kdfr9voyl2THvWgn+cHSWRLlGpJbsxmAlo+0Gp0= X-Google-Smtp-Source: AGHT+IF3rsjwZxEnfNF6i1Zh7SUR5ZRZ73j3LOKjqeaRMZmPLsyBw6tsN1pEQ9sr6wHSVaZZSQO7zQ== X-Received: by 2002:a05:600c:1c99:b0:40e:cc93:2f6b with SMTP id k25-20020a05600c1c9900b0040ecc932f6bmr604869wms.151.1706194214900; Thu, 25 Jan 2024 06:50:14 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:14 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 05/28] spi: dt-bindings: samsung: add samsung, spi-fifosize property Date: Thu, 25 Jan 2024 14:49:43 +0000 Message-ID: <20240125145007.748295-6-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Up to now the SPI alias was used as an index into an array defined in the SPI driver to determine the SPI FIFO size. Drop the dependency on the SPI alias and allow the SPI nodes to specify their SPI FIFO size. Signed-off-by: Tudor Ambarus --- Documentation/devicetree/bindings/spi/samsung,spi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/samsung,spi.yaml b/Documentation/devicetree/bindings/spi/samsung,spi.yaml index 2f0a0835ecfb..4ad5b8fe57aa 100644 --- a/Documentation/devicetree/bindings/spi/samsung,spi.yaml +++ b/Documentation/devicetree/bindings/spi/samsung,spi.yaml @@ -72,6 +72,11 @@ properties: reg: maxItems: 1 + samsung,spi-fifosize: + description: The fifo size supported by the SPI instance. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [64, 256] + required: - compatible - clocks From patchwork Thu Jan 25 14:49:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 766125 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9246A74E00 for ; Thu, 25 Jan 2024 14:50:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194221; cv=none; b=h+qGqM4oLb++rASPBkR2h6AeoKQJtYQmi+AXYv+mXl3tmMNjd+nUQuXIOw+wgC9WBfHCPdeZFiieAhv+sifUISXLsJyCzuKiclrNXmDge49KWAQXDQCYPivKj7cgUQehTDh56B8iiHFJwsqgV/cdBIRdmS/rYCQ4t+xNLwmg+I0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194221; c=relaxed/simple; bh=ham+cV2mcKCIhHRsWeNlCLcmQmBEqa3Yf08zGUNpCnA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NbLCnxNmOvX9mAiAK/8X/NrRAYFJuTAqdU6Oe/QHV5bqYfTcAjDL4NLxWSdUQ2PYQeOGDypnK8OjdLfsU+v7IJLJ6r0+fx/vAuXnzbYIQb7miwUyqQE7/TweoFoguvjH6ETdogjfbX5Dczm8vpcqAgkBRLH6oUivEt6AiCqjdJw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=G+Vk2Pnu; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="G+Vk2Pnu" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-40eccf4a91dso14288115e9.2 for ; Thu, 25 Jan 2024 06:50:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706194216; x=1706799016; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gfapMhR078yFz2BCJ06O4fPl8ddG0C3B6BN3m2+gI9M=; b=G+Vk2Pnut3I0t0k1kx3ilAMIQKTNOkaZojAhQwN63KbwZhVV1gMl/814du1TerQVgy iVAXgQCUswzersAgMO8aOSDExIAz4rnXPo1i4Jj/YITO5UmyT4J3huxn14eY9D8Y3HpQ YXo0XQWO69oTfFWiV7/uwXU7ScGwjMdj/NyNccMOwYAhYdcL5c/UQ0P4We8tJut8aVxB XjOQmcOSP5D0XY+d9pum/+RjHWENVqnp2i2XOq06pd5j74YBs+crB5nBYdPfTYFr1Zd7 vrT9CCHm2LjuzCMcbTB9DBNjJFCZgwCrUj/1iV1xFLB2pcabCuwlqbh51i1lqOajp8wS gIJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706194216; x=1706799016; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gfapMhR078yFz2BCJ06O4fPl8ddG0C3B6BN3m2+gI9M=; b=qKxV/m2u2YYPa5EMz4WX+aTdRPZZTKvSvghlQ3DouWjS962yxbsUlY6JT/2BT0ZVPm lP2F+BVZ3zbwOwtggycuufzoLt7Us6aHazLLuZ/7oyu+hOycWygwXA79V4VBEpFZDoWL WeTpC0o4hBjUz75c6GoGzKy3MlqRcDzYqeT50zolyVeTj+ehiA6wYpclbjR53sIexXnD L7Bli44IzHXI+/DRssCPDsFcttF1gVmqbWVZxewT1E7omYVxz3Xwalr6kwCew/fWlwQH p6eJalH+wYfWy9AFseZHk6ZMNV6m5sY3WTy5KjvMZTEm5jsK9IMJMQiXwwZSJu2NEzHg 90xg== X-Gm-Message-State: AOJu0Yw6dBeMFpuc20q2NiYMN/Enhr3S+MUQuwTagBa2tPQ2Q0IqZRK6 +6QO02SEg24vLU7cYwi1Ez8sdhbhBEOougKYFZzX3G+pGevCr4RPJJILNng3cCI= X-Google-Smtp-Source: AGHT+IGKMPYcJt5PfYIPyPZWi6QgWizho+wseuLkKZqmdgxi7otGRqXHMWOgPklU52YF7k7f3SrRKA== X-Received: by 2002:a05:600c:378a:b0:40e:a302:5ce9 with SMTP id o10-20020a05600c378a00b0040ea3025ce9mr655114wmr.39.1706194216523; Thu, 25 Jan 2024 06:50:16 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:16 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 07/28] spi: s3c64xx: remove unneeded (void *) casts in of_match_table Date: Thu, 25 Jan 2024 14:49:45 +0000 Message-ID: <20240125145007.748295-8-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 of_device_id::data is an opaque pointer. No explicit cast is needed. Remove unneeded (void *) casts in of_match_table. While here align the compatible and data members. Reviewed-by: Andi Shyti Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 45 +++++++++++++++++++++++---------------- 1 file changed, 27 insertions(+), 18 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 230fda2b3417..137faf9f2697 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1511,32 +1511,41 @@ static const struct platform_device_id s3c64xx_spi_driver_ids[] = { }; static const struct of_device_id s3c64xx_spi_dt_match[] = { - { .compatible = "samsung,s3c2443-spi", - .data = (void *)&s3c2443_spi_port_config, + { + .compatible = "samsung,s3c2443-spi", + .data = &s3c2443_spi_port_config, }, - { .compatible = "samsung,s3c6410-spi", - .data = (void *)&s3c6410_spi_port_config, + { + .compatible = "samsung,s3c6410-spi", + .data = &s3c6410_spi_port_config, }, - { .compatible = "samsung,s5pv210-spi", - .data = (void *)&s5pv210_spi_port_config, + { + .compatible = "samsung,s5pv210-spi", + .data = &s5pv210_spi_port_config, }, - { .compatible = "samsung,exynos4210-spi", - .data = (void *)&exynos4_spi_port_config, + { + .compatible = "samsung,exynos4210-spi", + .data = &exynos4_spi_port_config, }, - { .compatible = "samsung,exynos7-spi", - .data = (void *)&exynos7_spi_port_config, + { + .compatible = "samsung,exynos7-spi", + .data = &exynos7_spi_port_config, }, - { .compatible = "samsung,exynos5433-spi", - .data = (void *)&exynos5433_spi_port_config, + { + .compatible = "samsung,exynos5433-spi", + .data = &exynos5433_spi_port_config, }, - { .compatible = "samsung,exynos850-spi", - .data = (void *)&exynos850_spi_port_config, + { + .compatible = "samsung,exynos850-spi", + .data = &exynos850_spi_port_config, }, - { .compatible = "samsung,exynosautov9-spi", - .data = (void *)&exynosautov9_spi_port_config, + { + .compatible = "samsung,exynosautov9-spi", + .data = &exynosautov9_spi_port_config, }, - { .compatible = "tesla,fsd-spi", - .data = (void *)&fsd_spi_port_config, + { + .compatible = "tesla,fsd-spi", + .data = &fsd_spi_port_config, }, { }, }; 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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:17 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 09/28] spi: s3c64xx: use bitfield access macros Date: Thu, 25 Jan 2024 14:49:47 +0000 Message-ID: <20240125145007.748295-10-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Use the bitfield access macros in order to clean and to make the driver easier to read. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 196 +++++++++++++++++++------------------- 1 file changed, 99 insertions(+), 97 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 1e44b24f6401..d046810da51f 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -4,6 +4,7 @@ // Jaswinder Singh #include +#include #include #include #include @@ -18,91 +19,91 @@ #include #include -#define MAX_SPI_PORTS 12 -#define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1) -#define AUTOSUSPEND_TIMEOUT 2000 +#define MAX_SPI_PORTS 12 +#define S3C64XX_SPI_QUIRK_CS_AUTO BIT(1) +#define AUTOSUSPEND_TIMEOUT 2000 /* Registers and bit-fields */ -#define S3C64XX_SPI_CH_CFG 0x00 -#define S3C64XX_SPI_CLK_CFG 0x04 -#define S3C64XX_SPI_MODE_CFG 0x08 -#define S3C64XX_SPI_CS_REG 0x0C -#define S3C64XX_SPI_INT_EN 0x10 -#define S3C64XX_SPI_STATUS 0x14 -#define S3C64XX_SPI_TX_DATA 0x18 -#define S3C64XX_SPI_RX_DATA 0x1C -#define S3C64XX_SPI_PACKET_CNT 0x20 -#define S3C64XX_SPI_PENDING_CLR 0x24 -#define S3C64XX_SPI_SWAP_CFG 0x28 -#define S3C64XX_SPI_FB_CLK 0x2C - -#define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */ -#define S3C64XX_SPI_CH_SW_RST (1<<5) -#define S3C64XX_SPI_CH_SLAVE (1<<4) -#define S3C64XX_SPI_CPOL_L (1<<3) -#define S3C64XX_SPI_CPHA_B (1<<2) -#define S3C64XX_SPI_CH_RXCH_ON (1<<1) -#define S3C64XX_SPI_CH_TXCH_ON (1<<0) - -#define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9) -#define S3C64XX_SPI_CLKSEL_SRCSHFT 9 -#define S3C64XX_SPI_ENCLK_ENABLE (1<<8) -#define S3C64XX_SPI_PSR_MASK 0xff - -#define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29) -#define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29) -#define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29) -#define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29) -#define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17) -#define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17) -#define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17) -#define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17) +#define S3C64XX_SPI_CH_CFG 0x00 +#define S3C64XX_SPI_CLK_CFG 0x04 +#define S3C64XX_SPI_MODE_CFG 0x08 +#define S3C64XX_SPI_CS_REG 0x0C +#define S3C64XX_SPI_INT_EN 0x10 +#define S3C64XX_SPI_STATUS 0x14 +#define S3C64XX_SPI_TX_DATA 0x18 +#define S3C64XX_SPI_RX_DATA 0x1C +#define S3C64XX_SPI_PACKET_CNT 0x20 +#define S3C64XX_SPI_PENDING_CLR 0x24 +#define S3C64XX_SPI_SWAP_CFG 0x28 +#define S3C64XX_SPI_FB_CLK 0x2C + +#define S3C64XX_SPI_CH_HS_EN BIT(6) /* High Speed Enable */ +#define S3C64XX_SPI_CH_SW_RST BIT(5) +#define S3C64XX_SPI_CH_SLAVE BIT(4) +#define S3C64XX_SPI_CPOL_L BIT(3) +#define S3C64XX_SPI_CPHA_B BIT(2) +#define S3C64XX_SPI_CH_RXCH_ON BIT(1) +#define S3C64XX_SPI_CH_TXCH_ON BIT(0) + +#define S3C64XX_SPI_CLKSEL_SRCMSK GENMASK(10, 9) +#define S3C64XX_SPI_ENCLK_ENABLE BIT(8) +#define S3C64XX_SPI_PSR_MASK GENMASK(15, 0) + +#define S3C64XX_SPI_MODE_CH_TSZ_MASK GENMASK(30, 29) +#define S3C64XX_SPI_MODE_CH_TSZ_BYTE 0 +#define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD 1 +#define S3C64XX_SPI_MODE_CH_TSZ_WORD 2 +#define S3C64XX_SPI_MAX_TRAILCNT_MASK GENMASK(28, 19) +#define S3C64XX_SPI_MODE_BUS_TSZ_MASK GENMASK(18, 17) +#define S3C64XX_SPI_MODE_BUS_TSZ_BYTE 0 +#define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD 1 +#define S3C64XX_SPI_MODE_BUS_TSZ_WORD 2 #define S3C64XX_SPI_MODE_RX_RDY_LVL GENMASK(16, 11) -#define S3C64XX_SPI_MODE_RX_RDY_LVL_SHIFT 11 -#define S3C64XX_SPI_MODE_SELF_LOOPBACK (1<<3) -#define S3C64XX_SPI_MODE_RXDMA_ON (1<<2) -#define S3C64XX_SPI_MODE_TXDMA_ON (1<<1) -#define S3C64XX_SPI_MODE_4BURST (1<<0) - -#define S3C64XX_SPI_CS_NSC_CNT_2 (2<<4) -#define S3C64XX_SPI_CS_AUTO (1<<1) -#define S3C64XX_SPI_CS_SIG_INACT (1<<0) - -#define S3C64XX_SPI_INT_TRAILING_EN (1<<6) -#define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5) -#define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4) -#define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3) -#define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2) -#define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) -#define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) - -#define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) -#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) -#define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3) -#define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2) -#define S3C64XX_SPI_ST_RX_FIFORDY (1<<1) -#define S3C64XX_SPI_ST_TX_FIFORDY (1<<0) - -#define S3C64XX_SPI_PACKET_CNT_EN (1<<16) +#define S3C64XX_SPI_MODE_SELF_LOOPBACK BIT(3) +#define S3C64XX_SPI_MODE_RXDMA_ON BIT(2) +#define S3C64XX_SPI_MODE_TXDMA_ON BIT(1) +#define S3C64XX_SPI_MODE_4BURST BIT(0) + +#define S3C64XX_SPI_CS_NSC_CNT_MASK GENMASK(9, 4) +#define S3C64XX_SPI_CS_NSC_CNT_2 2 +#define S3C64XX_SPI_CS_AUTO BIT(1) +#define S3C64XX_SPI_CS_SIG_INACT BIT(0) + +#define S3C64XX_SPI_INT_TRAILING_EN BIT(6) +#define S3C64XX_SPI_INT_RX_OVERRUN_EN BIT(5) +#define S3C64XX_SPI_INT_RX_UNDERRUN_EN BIT(4) +#define S3C64XX_SPI_INT_TX_OVERRUN_EN BIT(3) +#define S3C64XX_SPI_INT_TX_UNDERRUN_EN BIT(2) +#define S3C64XX_SPI_INT_RX_FIFORDY_EN BIT(1) +#define S3C64XX_SPI_INT_TX_FIFORDY_EN BIT(0) + +#define S3C64XX_SPI_ST_RX_OVERRUN_ERR BIT(5) +#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR BIT(4) +#define S3C64XX_SPI_ST_TX_OVERRUN_ERR BIT(3) +#define S3C64XX_SPI_ST_TX_UNDERRUN_ERR BIT(2) +#define S3C64XX_SPI_ST_RX_FIFORDY BIT(1) +#define S3C64XX_SPI_ST_TX_FIFORDY BIT(0) + +#define S3C64XX_SPI_PACKET_CNT_EN BIT(16) #define S3C64XX_SPI_PACKET_CNT_MASK GENMASK(15, 0) -#define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4) -#define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3) -#define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2) -#define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1) -#define S3C64XX_SPI_PND_TRAILING_CLR (1<<0) +#define S3C64XX_SPI_PND_TX_UNDERRUN_CLR BIT(4) +#define S3C64XX_SPI_PND_TX_OVERRUN_CLR BIT(3) +#define S3C64XX_SPI_PND_RX_UNDERRUN_CLR BIT(2) +#define S3C64XX_SPI_PND_RX_OVERRUN_CLR BIT(1) +#define S3C64XX_SPI_PND_TRAILING_CLR BIT(0) -#define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7) -#define S3C64XX_SPI_SWAP_RX_BYTE (1<<6) -#define S3C64XX_SPI_SWAP_RX_BIT (1<<5) -#define S3C64XX_SPI_SWAP_RX_EN (1<<4) -#define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3) -#define S3C64XX_SPI_SWAP_TX_BYTE (1<<2) -#define S3C64XX_SPI_SWAP_TX_BIT (1<<1) -#define S3C64XX_SPI_SWAP_TX_EN (1<<0) +#define S3C64XX_SPI_SWAP_RX_HALF_WORD BIT(7) +#define S3C64XX_SPI_SWAP_RX_BYTE BIT(6) +#define S3C64XX_SPI_SWAP_RX_BIT BIT(5) +#define S3C64XX_SPI_SWAP_RX_EN BIT(4) +#define S3C64XX_SPI_SWAP_TX_HALF_WORD BIT(3) +#define S3C64XX_SPI_SWAP_TX_BYTE BIT(2) +#define S3C64XX_SPI_SWAP_TX_BIT BIT(1) +#define S3C64XX_SPI_SWAP_TX_EN BIT(0) -#define S3C64XX_SPI_FBCLK_MSK (3<<0) +#define S3C64XX_SPI_FBCLK_MASK GENMASK(1, 0) #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ @@ -112,18 +113,13 @@ FIFO_LVL_MASK(i)) #define FIFO_DEPTH(i) ((FIFO_LVL_MASK(i) >> 1) + 1) -#define S3C64XX_SPI_MAX_TRAILCNT 0x3ff -#define S3C64XX_SPI_TRAILCNT_OFF 19 - -#define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT - #define S3C64XX_SPI_POLLING_SIZE 32 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) #define is_polling(x) (x->cntrlr_info->polling) -#define RXBUSY (1<<2) -#define TXBUSY (1<<3) +#define RXBUSY BIT(2) +#define TXBUSY BIT(3) struct s3c64xx_spi_dma_data { struct dma_chan *ch; @@ -342,8 +338,9 @@ static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable) } else { u32 ssel = readl(sdd->regs + S3C64XX_SPI_CS_REG); - ssel |= (S3C64XX_SPI_CS_AUTO | - S3C64XX_SPI_CS_NSC_CNT_2); + ssel |= S3C64XX_SPI_CS_AUTO | + FIELD_PREP(S3C64XX_SPI_CS_NSC_CNT_MASK, + S3C64XX_SPI_CS_NSC_CNT_2); writel(ssel, sdd->regs + S3C64XX_SPI_CS_REG); } } else { @@ -666,16 +663,22 @@ static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) switch (sdd->cur_bpw) { case 32: - val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD; - val |= S3C64XX_SPI_MODE_CH_TSZ_WORD; + val |= FIELD_PREP(S3C64XX_SPI_MODE_BUS_TSZ_MASK, + S3C64XX_SPI_MODE_BUS_TSZ_WORD) | + FIELD_PREP(S3C64XX_SPI_MODE_CH_TSZ_MASK, + S3C64XX_SPI_MODE_CH_TSZ_WORD); break; case 16: - val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD; - val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD; + val |= FIELD_PREP(S3C64XX_SPI_MODE_BUS_TSZ_MASK, + S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD) | + FIELD_PREP(S3C64XX_SPI_MODE_CH_TSZ_MASK, + S3C64XX_SPI_MODE_CH_TSZ_HALFWORD); break; default: - val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE; - val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE; + val |= FIELD_PREP(S3C64XX_SPI_MODE_BUS_TSZ_MASK, + S3C64XX_SPI_MODE_BUS_TSZ_BYTE) | + FIELD_PREP(S3C64XX_SPI_MODE_CH_TSZ_MASK, + S3C64XX_SPI_MODE_CH_TSZ_BYTE); break; } @@ -801,7 +804,7 @@ static int s3c64xx_spi_transfer_one(struct spi_controller *host, val = readl(sdd->regs + S3C64XX_SPI_MODE_CFG); val &= ~S3C64XX_SPI_MODE_RX_RDY_LVL; - val |= (rdy_lv << S3C64XX_SPI_MODE_RX_RDY_LVL_SHIFT); + val |= FIELD_PREP(S3C64XX_SPI_MODE_RX_RDY_LVL, rdy_lv); writel(val, sdd->regs + S3C64XX_SPI_MODE_CFG); /* Enable FIFO_RDY_EN IRQ */ @@ -1074,8 +1077,8 @@ static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd) writel(0, regs + S3C64XX_SPI_INT_EN); if (!sdd->port_conf->clk_from_cmu) - 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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:19 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 11/28] spi: s3c64xx: move common code outside if else Date: Thu, 25 Jan 2024 14:49:49 +0000 Message-ID: <20240125145007.748295-12-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Move common code outside if else to avoid code duplication. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index b048e81e6207..107b4200ab00 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -286,20 +286,18 @@ static int prepare_dma(struct s3c64xx_spi_dma_data *dma, if (dma->direction == DMA_DEV_TO_MEM) { sdd = container_of((void *)dma, struct s3c64xx_spi_driver_data, rx_dma); - config.direction = dma->direction; config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA; config.src_addr_width = sdd->cur_bpw / 8; config.src_maxburst = 1; - dmaengine_slave_config(dma->ch, &config); } else { sdd = container_of((void *)dma, struct s3c64xx_spi_driver_data, tx_dma); - config.direction = dma->direction; config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA; config.dst_addr_width = sdd->cur_bpw / 8; config.dst_maxburst = 1; - dmaengine_slave_config(dma->ch, &config); } + config.direction = dma->direction; + dmaengine_slave_config(dma->ch, &config); desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents, dma->direction, DMA_PREP_INTERRUPT); From patchwork Thu Jan 25 14:49:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 766122 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16A887CF3C for ; Thu, 25 Jan 2024 14:50:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194226; cv=none; b=N86+ejjU80A0er4dod0e8Vz+5UDU2vw+/UwMwmEtseE6tPQbEK4vqkOBtdoyqQFLiFGrJRYDhYwQAS/v43TmE1UomIFyTio1lZ+3z+q3rlU4QR7wg6jE+IjzRelWQ0ENLtClQEvXr2wWGKaCLDJ6f7IfTecafbbZfFEjeIArq6c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194226; c=relaxed/simple; bh=0hd5os3t/LKdK2NVB2IaIPXKDa42n9CplbFuM7q+HYw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cNN4VrXKn0xoru7l7Aqs49AVaKaOZDiFKrZF9YPSqnLVeCDiJnCnUvH75pp7uBvGCp0NVIaGeTa+ZezzXSkWcuglvVGliSbY+GofijZqIhWju/ogeI/GgctVV31RNNPxikmGiCkhKRQN7bqCUixYDfZtREnr+DTYSyhfy4s4AD0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=GSGQn1W3; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="GSGQn1W3" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-40ed4690ee4so1792355e9.2 for ; Thu, 25 Jan 2024 06:50:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706194222; x=1706799022; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Uo5/6sMsEJXgYbE8BbPRJoYau3RC+fqPHaLcagZG9d0=; b=GSGQn1W3wzLBRTPAdWO7t0YYBUJGXWZcw9ecHlXEH1kk3Y2qHMDgGCT6emMi+PI6MF DpEzICWo/HaMXR9tCsEMijCl//cwT5lyLXJ33fawGWrGe/ozBvAf8ql3mM29HANAHOs7 7gi4G4xIsFpLKfPSrnJwzcbx8vrigRjdAxY2w1Srxc7X4d062ue7AF6YNwVmYVR1qXVs foZ+Q//inmoiMmEfdHs4S5uVPIAdQsOcDBX7D1DyQ3cbgUInrOb5NfRu2JA1I5HtEH1d Xbjx5/YUxdXibWMxCzql7WhnrPbFGhA7xiWsVIi+qEhYXuy0ZB7yJoaoipMj9s2mlQ7h Brkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706194222; x=1706799022; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Uo5/6sMsEJXgYbE8BbPRJoYau3RC+fqPHaLcagZG9d0=; b=pOcDEvCU0HPyF/6T6ZJ5Mc7cJ5R+hEAejNcPD006rJ/q8Kd6CDJUZzecXcjO+WW6pg 1cXx5zEmxusK8SiHfCR3SxamQ1MxILiic42PxXHuPGNtAKLRG21zDOmGQlRi7RLB00Wf //Wt4kts2nMLR9+xQapvTOrCE1v51XD17wAlQcbnWLf73ZpzIQH0cocgtBFvvj8HDo5R KF8K2gcEemZGqKstlI7Pt03hVHI2vwzkzWTqRKNdTHbFgmWn7ZZe7ZlK579Q44I0uv4a a2QsGsOHVsLeq3zivoCyC2tv5t2+4Xj+xOEA93cNoSxIlHT16JbmRqZNEUweVbeTOi31 IFQw== X-Gm-Message-State: AOJu0Yy87Tf0/2iIfnCz/H3DiRAqFox/Su/x7pjUhg8OxlyYj2G19s6p 0EyMlAX+8DNhJD/Lli34cgw5+tVFSA2p3C7opm/dlMQXimkIR5Vsd40KkDxtKHA= X-Google-Smtp-Source: AGHT+IHsYPm1PY8Cgk3AI9vhaP569ziBX3qB1QLXw/TjefWa12gW37HqQ58L1YMoxQHBrVjXHblYBg== X-Received: by 2002:a05:600c:511a:b0:40d:8914:cee3 with SMTP id o26-20020a05600c511a00b0040d8914cee3mr611949wms.108.1706194222303; Thu, 25 Jan 2024 06:50:22 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:21 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 13/28] spi: s3c64xx: propagate the dma_submit_error() error code Date: Thu, 25 Jan 2024 14:49:51 +0000 Message-ID: <20240125145007.748295-14-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Propagate the dma_submit_error() error code, don't overwrite it. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 48b87c5e2dd2..25d642f99278 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -316,7 +316,7 @@ static int prepare_dma(struct s3c64xx_spi_dma_data *dma, ret = dma_submit_error(dma->cookie); if (ret) { dev_err(&sdd->pdev->dev, "DMA submission failed"); - return -EIO; + return ret; } dma_async_issue_pending(dma->ch); From patchwork Thu Jan 25 14:49:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 766121 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA59981208 for ; Thu, 25 Jan 2024 14:50:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194228; cv=none; b=XLookv+c5Jz2Dft91m/STHI6ZTCkRIWPnfJsRUvOUy4ENdFE8BbEG3FU6aIZmBDbmDNkSdpKuXGoBJ9/5TYsS55eZGqrd9bKT+JnzKDgq++TaXmfl6abeKU49ETeYALLGLQ1o5b0bzuu4Qimv/Ey7N+8ZLbE+ZYkxLHMnXhJNoc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194228; c=relaxed/simple; bh=BMnHD2dtw0Q+/VBvgqPiw6zeufZq9wG7qlcCmbu3aCw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rCZn3GP8Lq7WheqQ17zVia7mHu/bZe/cFYItY+3/ScART1MBkVjVR6hY42Rfihw8gNHzd4SnYl9QpF7Za7FSGoAbHN/XkZAEYyaPA1HpNWJgZTSLmDyKdFaFuy3GyaZkOAQLytCjLvKOSM2BqoQ0O1gvTEIVvvoqvJ/Veb2PM0M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=Xq00kVaa; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Xq00kVaa" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-40e7065b7bdso79949365e9.3 for ; Thu, 25 Jan 2024 06:50:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706194224; x=1706799024; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+YODKSwwosS+Boh3Md8IudPiFt2ZVlyI0co3V0SoeDA=; b=Xq00kVaaLgJocw69dajORWZrvF+jg106QL8zKSK1pE4yZgFFl/8JVExa3PbN0oezme 0oJvTkVdH7VOx/i63chNWnZ2UZe83zryqZr3TqFLkXaLRHekP7bpZfEyXWHAKBY+dbL2 gQuRqkWqnaTxJe1qo8resDhFcuW1h6SAqWI+qcH8/v6lrdMpYgDoiaF1f2QtsUugoGlC QBsTpWgsIaysBUWMIggNh+eo6Fpq86E3+bKTroSDA84cYoYFvKpfNzfSRApQ9e9R6vur vijPxe3guc/gX5ECGeufRmtDCnQMvNU7tT9llhGPZ9rM68VzQC2a0VEQsHkqCWVlmhIx MgUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706194224; x=1706799024; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+YODKSwwosS+Boh3Md8IudPiFt2ZVlyI0co3V0SoeDA=; b=pHl1OPSwWxOrwSiyqYFl4S+hIrntoNivksACatDj9qWnK1BMFIK9A77I8L1HBJSqXJ CXBOuuqZlxP/OMZMsIPZ/TUqYmpyxuaj8DPDEIngid1VmmEszRYnjj05SucXhTGm6Cao Vjxrxq0WzzrdTMwNAVdBC3boUxjHwjD9r4Wf7ZaP9a6c5+4xAJugLo0vFocFvXG6R+6x PwwKY3+5fGEq+u8qzhZFJ7TmgMxMb6B+T8AkLAAY5JZdYx3J6JWW/cYMH9JXER9/4UfX bhoE+SGL7+LcwMFytEV12+4xXSMxjBnQKRv3u/oS5h0JHMpgfhhjMppLU05tZKyb8sn2 2oMA== X-Gm-Message-State: AOJu0YydWmzEJ2gIWQbHseL+qFahNQQiyXy/hemfFPKDZ26ZTe0ea4m8 8E2z/SQKIKFUfjbn9Ls7RDY5L41RW5N+1nPTNRM9vT7HYqg6R7PJIbV6W6zvrro= X-Google-Smtp-Source: AGHT+IHQibS5o6WlTuiDCwT7ZjkLtBnPKNQkGAG1I79CB9wOZ7GILO1eVGmHw8GQaGabYq+jMXwkKQ== X-Received: by 2002:a05:600c:6b03:b0:40e:6f03:45b5 with SMTP id jn3-20020a05600c6b0300b0040e6f0345b5mr390308wmb.261.1706194224044; Thu, 25 Jan 2024 06:50:24 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:23 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 15/28] spi: s3c64xx: return ETIMEDOUT for wait_for_completion_timeout() Date: Thu, 25 Jan 2024 14:49:53 +0000 Message-ID: <20240125145007.748295-16-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 ETIMEDOUT is more specific than EIO, use it for wait_for_completion_timeout(). Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 447320788697..d2dd28ff00c6 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -523,7 +523,7 @@ static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd, /* * If the previous xfer was completed within timeout, then - * proceed further else return -EIO. + * proceed further else return -ETIMEDOUT. * DmaTx returns after simply writing data in the FIFO, * w/o waiting for real transmission on the bus to finish. * DmaRx returns only after Dma read data from FIFO which @@ -544,7 +544,7 @@ static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd, /* If timed out while checking rx/tx status return error */ if (!val) - return -EIO; + return -ETIMEDOUT; return 0; } @@ -574,7 +574,7 @@ static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd, if (use_irq) { val = msecs_to_jiffies(ms); if (!wait_for_completion_timeout(&sdd->xfer_completion, val)) - return -EIO; + return -ETIMEDOUT; } val = msecs_to_loops(ms); From patchwork Thu Jan 25 14:49:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 766120 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84B817CF3C for ; Thu, 25 Jan 2024 14:50:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194230; cv=none; b=Gzv1qsflGB22+4HBBaJGC1SSt43BM8f1ZLxtAZm46jD6XpNX/F2NDp97+v2xwThi32rmoOT0Yclsb7s40sQkhNNvpz5GnE1tPu3pud7ScIAJSa0J7iUNYxH/aW3oP7+NiKzh5nEuOhNnynC7RNWFbmjw9nyffunuFSCDWE4jNCc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194230; c=relaxed/simple; bh=cmo+MmUsz01GpSNW65Xw553FLyTVDtBzORTVJdMj4JY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=quRCkekc9SBw9TwSEzBfJ2xEG8U7GSEU1b7s86T2+7gW95c1n60NQs2q8IvhVz9a2qWbDOgrlcNrWGItnwtQ0ZBwT/c1c9FbB6etK+wZJb/iFhWTOl7uStCojV1KbRYtv735st52F/saLTnMbi1zFAbzvxLaWGMtLbVyhdoQ0uA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=dvuCZLGS; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="dvuCZLGS" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-40ed28f8666so5690335e9.3 for ; Thu, 25 Jan 2024 06:50:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706194225; x=1706799025; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4mb9+bEM/5blhATmtgMhoiewq5VCGJ6TCsXtGi2uVOU=; b=dvuCZLGSxIzTuxdjzfjM1ra4qlZHLgF0PC+FrfmO97Hj1gxXmGQJMv/uSCU2I0iLrw oRTdjQQ4AuMwXjrBvlRGEbV0xojGFaupz8sxJI4LHGmy0BGHsyBUDfkWNt8DSzThkwrb Ktcon6EZnfH6QmI6l9+MBPHTdDdXLKd4omSUWgjq6WfKCtTYxg0mK8B90i+EtZ4yq9WX YhY42bkGVGB78DHff3iFRLQ1GH78SjgWW8ZQSYQyfjH7YKR5wOSbjHqROX1j4MlTUm2A 5jQ7IkZPZ1en1ACQ7AbnH4sDUhpPvZitjNdWTxLTV4KF8UtfDhQOoIXuEX7EbODjDzTY /K9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706194225; x=1706799025; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4mb9+bEM/5blhATmtgMhoiewq5VCGJ6TCsXtGi2uVOU=; b=lcOfe/3hGnIPj8pxg4VM9EJaDgBOIHkk7bQzTOEyL7U7jlCbijekEPIfIxjEkQYcgU zN4j+lvhobXQq2ZPIVeF7p5CvTfnPDBayT+zFJ0QlyTEuc/5sgzv4KmRSIiab456BXW2 jGu2H2EfQu7Ao8VMkQ+CBSlG0swvwcAaCT3+DLt86ZMeCY4QhN+oKzLiHvdL79c8AV8m kbx6ZX4kgy6WQqQIY9hCunCrg8oGuh1+4CIzJvIqc6B1U+OjScVO8wseJjq+VftWHPX0 c/n5Aqpw4il/yGP5gOVgiCHUf0mpGLT9KoePpjZ5f5phe9j9nwXRYN4Vfc7VybII3PnF Tfpg== X-Gm-Message-State: AOJu0YwxieEcTJR8afCUu2JjOxiCy4nvJZRaBngbZF6gyu3eJJYmsjlc 92V45+psaaiaZ5LsMFZCJGQ6Cg6hkw9rXogRxQZYNH1sm5Y+igQbbJAjxejJfJ0= X-Google-Smtp-Source: AGHT+IEpkD3F0Js2iaSYc1hvfcPWWEOr3Z70uQBq/1WFhCQpetg0oRQUfIM4XY7tyVLSl4yTXJPtSg== X-Received: by 2002:a05:600c:b8d:b0:40e:d21d:571f with SMTP id fl13-20020a05600c0b8d00b0040ed21d571fmr476176wmb.51.1706194225631; Thu, 25 Jan 2024 06:50:25 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:24 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 17/28] spi: s3c64xx: drop blank line between declarations Date: Thu, 25 Jan 2024 14:49:55 +0000 Message-ID: <20240125145007.748295-18-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Drop the blank line and move the logical operation in the body of the function rather than in initialization list. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 00a0878aeb80..bb6d9bf390a8 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1282,8 +1282,9 @@ static int s3c64xx_spi_suspend(struct device *dev) { struct spi_controller *host = dev_get_drvdata(dev); struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); + int ret; - int ret = spi_controller_suspend(host); + ret = spi_controller_suspend(host); if (ret) return ret; From patchwork Thu Jan 25 14:49:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 766119 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8FB9286ADE for ; Thu, 25 Jan 2024 14:50:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194232; cv=none; b=onZMyhim2WQDQ+z3LfAkMHOpd811WY0lQ2DltQHvxKIdPhIXlTZtob8w9cjtyHsE0qu5+8AtpMncXKisEvfo2IoPPiaxQcy9zJDBpZEqw8wNrjsBgDkJqbRLc7YzZ88yAtYc4pDBPQ76/kEHsdD7k3OOqBuVOy4oMsypzyej1zc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194232; c=relaxed/simple; bh=ky++lUpjV2xM2yr5R8NgpgcPYQ2XfXR8n2IS4sf5ezM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mvV2+o4f02D882icPa0xWt3ppPgNQEInJNdZJ/sqIR7Y4RkLYxJvAGsvk9v5GcIPmFD9IQM6P4J6kJCkC113H67PUerjTTXjXyCWLlaAvfCv1hOy0jMcrZrhpjcGdxU6ea+HjM8rw4iwjh5CxBK/5c0aEOGKCrsang3NJbjZXnM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=TmiF/IpX; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="TmiF/IpX" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-40e913e3f03so85545025e9.3 for ; Thu, 25 Jan 2024 06:50:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706194227; x=1706799027; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FCsZDfh5Q5K/DwuAunrdWzuUCnvHISTW4ss32NHF9x0=; b=TmiF/IpX82/+fZtReS65al6nyoIPbF+9gOTJy/uf03WRKAwroyl+mHFPkd/bcZElIU vq1eurdLj7biNPfJyDPcFk0LkZjHSmDaQUOQdWqjx//IkDIkv7dHghniA5wI3XotMKpM SP/cOW6ABt91oyFYWYl/zABPiIHMvUEx4OAzT90oSz0QzZ+tSybNi25VtbG0vhBGUdT3 KyDe7QDzHNdS13owh9M39+nRsY6EdsOQ0HnWaB+3gJDvxJ7T8GtjpIQXiv+9I9UoDmUC 7gw20vQi2Z46I8a08zYcf2aR52zuFsUvaiBBNFfLPWJn81oKVbY+bIUIymjaJVDXI/1O YZLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706194227; x=1706799027; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FCsZDfh5Q5K/DwuAunrdWzuUCnvHISTW4ss32NHF9x0=; b=tV+XvwUxL3niVTWdnQI8DOI1IL9NZKqJ4SLE9a6U9JaE/GDO5hb07jJ05Qp+L3RSjy cma2PXRzVibZt4DoYuve4UBAnzkSwT4EGFTTgbd/HlhGk25CHAAD3gX9jTfd0gsY4QKu OzE6GKqvFbrF8ulow5M9GIjqbTirbir7lzISQhN1JdEnoRck7jjYLj4cpHjLsrtXcw6M 18tPBf3yiicblMV0aV2F9JWignGxokIZ49II1thhAQj/GpO2y5qa2VhkCkz9Pr1kvGNE LR1md8sPcqTcG/nuCri4gn0gT6rcr4tNBlVLImurjcT1XF+u6gjpNAf8DkIsn2B3ZC1m 58Aw== X-Gm-Message-State: AOJu0YxB1rXdTBBfY8QQVVb+HvsjHVtC/6n4aUrj69UFrBKgb4ONVeen nCYL9Wr3QqA8yVB+ZNwGd+cfgsaYPBFw6P4v+G/s2/O24DA8vAE+GNShZLdsWSg= X-Google-Smtp-Source: AGHT+IGh12BcHV/dAPX9rARaa3uM3thpkF0/DbdSBRI+KmJZrJjj10wwGpQaaYX5IgM25eGiIJcLTg== X-Received: by 2002:a05:600c:418a:b0:40e:4ac1:8609 with SMTP id p10-20020a05600c418a00b0040e4ac18609mr575275wmh.86.1706194227540; Thu, 25 Jan 2024 06:50:27 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:26 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 19/28] spi: s3c64xx: downgrade dev_warn to dev_dbg for optional dt props Date: Thu, 25 Jan 2024 14:49:57 +0000 Message-ID: <20240125145007.748295-20-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 "samsung,spi-src-clk" and "num-cs" are optional dt properties. Downgrade the message from warning to debug message. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 692ccb7828f8..fc5fffc019e0 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1071,14 +1071,14 @@ static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) return ERR_PTR(-ENOMEM); if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) { - dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n"); + dev_dbg(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n"); sci->src_clk_nr = 0; } else { sci->src_clk_nr = temp; } if (of_property_read_u32(dev->of_node, "num-cs", &temp)) { - dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n"); + dev_dbg(dev, "number of chip select lines not specified, assuming 1 chip select line\n"); sci->num_cs = 1; } else { sci->num_cs = temp; From patchwork Thu Jan 25 14:50:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 766118 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1029F77621 for ; Thu, 25 Jan 2024 14:50:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194235; cv=none; b=ltn4K83oH6ih8+vBfeZBEB800OYytGP2L79FIL+29kgxf1D5u1R6Hk+b78nDbjv2eYXDDCfxlNz/ehqSg+Zb4AWyv4eUYp74NpbI3wQjJoVStRcqaKuz4tIYdFUCPiva/BfbDMCTKBdFZ7F13oKDQfkQLQKNkynIRHDYROlPu/g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194235; c=relaxed/simple; bh=qxc7sbniUDyQV364D2RhlbEnDsCBptc6ZkMAL9cwgPs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QF2185jHMs5zsp2QGs5sLQpjvyAkkSruIIgSFglOQBU+SKib9kQKZ6JaTp6oFsIbIjVv5pqfWUqi6dzILTfMp/tc/b2nPvdbhgdXKAkVXjzxJHuYQopkEK+rHfNrZSHDBvvEQ0A03baUSysd1ARMxYCuIBDeNPYDEm1haykSyKo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=aSIWXzIi; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="aSIWXzIi" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-40e80046264so85758105e9.0 for ; Thu, 25 Jan 2024 06:50:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706194230; x=1706799030; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JtNtOah4q0k+JGCPgSMuID7OmymIk1nPxql5oxULauE=; b=aSIWXzIi7O/UnNLSv4Rh5ATOd4wCcaWnjqDZBdTRxOlvWjxPvczxvBOLPFH5k0vxup pK2NE0/7bxvVBwiqSHG48/cFwVRwX4i4v375ZV1c+n9UYugs4WxalG9MRJJ4OEboZRRP XiumQUndHvjPv8UbnhbFBe5qO1ewhW5qfcZajqMKUiW5N4laYUkrEJ7xTdgeSOW2PLST q2p5nW++lIkfkvK9tQAh50b++1Q4q6hCHvf4MjQcxoYbLRjt8K0ShOL+behXHYbC7AVh 8GSx1E1yOUT75VTtwu0DGJtrWJMqjOu7VAkkZ0O3+X830hGoDtRqzkxb5FYjGsKCGP+2 RjSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706194230; x=1706799030; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JtNtOah4q0k+JGCPgSMuID7OmymIk1nPxql5oxULauE=; b=tNuC8POiawnQ8vCwVUboR6CBaM6NVhDKHHKRKX3xqB6ERquijUePc1dVe1xthQM9T9 ZYm8WX7w0T3GxRV/AKYHP2UBnADkim0a10nDzm28W8QdElrI4Wm/NvBLACz7rYSDGRLf 2GK3IIskqv3e/cV8gKrwG8YUNplMYJN13rulIK3Ltxk3tikT4ZjlYZZnJK2WqER9V/fj M9UQE1OZ6Y9kXqgiQCfslYGbACntP78ekFj19h+A2qwoQDnzbVwhf5AUQ6p87l+BDYkf D/63aYdnXt/1VDi570CkJ28LLyyTkCm2VggJumEs3PuAB/dVM4lbWK7pQ2ozf9bHFVTE mQOQ== X-Gm-Message-State: AOJu0YzIVUQhoPTEWQWb8XiKuLjJVmyEMn2WJjCEpWsc9WqLv7k9QZzn xviY/Aq6tE0O3r9iNu/XnCNFuBKhNhddmcQAAUSgncERtbNf3eyGDYyit9Zuf3E= X-Google-Smtp-Source: AGHT+IHbggNgNKsbigSPf6qnK9OAL7RN+AXot/5cZEw4S6FkZlNDOIGl4jCVyK8EYQh9E6qMazSeuQ== X-Received: by 2002:a05:600c:384e:b0:40e:c1a9:6829 with SMTP id s14-20020a05600c384e00b0040ec1a96829mr575554wmr.120.1706194230059; Thu, 25 Jan 2024 06:50:30 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:29 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 22/28] spi: s3c64xx: drop dependency on of_alias where possible Date: Thu, 25 Jan 2024 14:50:00 +0000 Message-ID: <20240125145007.748295-23-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Remove the dependency on the OF alias for SoCs that use the same FIFO size for all the instances of the SPI IP. The driver failed to probe if an SPI alias was not provided, which is obviously wrong. We now let the SPI core determine the SPI alias, either by getting the alias ID, or by allocating a dynamic bus number when the alias is absent. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 61 ++++++++++++++++++++++++--------------- 1 file changed, 38 insertions(+), 23 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index b86eb0a77b60..7a99f6b02319 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -107,10 +107,9 @@ #define S3C64XX_SPI_FBCLK_MASK GENMASK(1, 0) -#define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) -#define FIFO_DEPTH(i) ((FIFO_LVL_MASK(i) >> 1) + 1) +#define FIFO_DEPTH(x) (((x) >> 1) + 1) #define S3C64XX_SPI_POLLING_SIZE 32 @@ -197,7 +196,6 @@ struct s3c64xx_spi_driver_data { struct s3c64xx_spi_dma_data rx_dma; struct s3c64xx_spi_dma_data tx_dma; const struct s3c64xx_spi_port_config *port_conf; - unsigned int port_id; unsigned int fifosize; }; @@ -1110,6 +1108,37 @@ static inline const struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( return (const struct s3c64xx_spi_port_config *)platform_get_device_id(pdev)->driver_data; } +static int s3c64xx_spi_get_fifosize(const struct platform_device *pdev, + struct s3c64xx_spi_driver_data *sdd) +{ + const struct s3c64xx_spi_port_config *port = sdd->port_conf; + const int *fifo_lvl_mask = port->fifo_lvl_mask; + struct device_node *np = pdev->dev.of_node; + int id; + + if (!np) { + if (pdev->id < 0) + return dev_err_probe(&pdev->dev, -EINVAL, + "Negative platform ID is not allowed\n"); + id = pdev->id; + sdd->fifosize = FIFO_DEPTH(fifo_lvl_mask[id]); + return 0; + } + + if (port->fifosize) { + sdd->fifosize = port->fifosize; + return 0; + } + + id = of_alias_get_id(np, "spi"); + if (id < 0) + return dev_err_probe(&pdev->dev, id, + "Failed to get alias id\n"); + sdd->fifosize = FIFO_DEPTH(fifo_lvl_mask[id]); + + return 0; +} + static int s3c64xx_spi_probe(struct platform_device *pdev) { struct resource *mem_res; @@ -1142,34 +1171,20 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) sdd = spi_controller_get_devdata(host); sdd->port_conf = s3c64xx_spi_get_port_config(pdev); + ret = s3c64xx_spi_get_fifosize(pdev, sdd); + if (ret) + return ret; + sdd->host = host; sdd->cntrlr_info = sci; sdd->pdev = pdev; - if (pdev->dev.of_node) { - ret = of_alias_get_id(pdev->dev.of_node, "spi"); - if (ret < 0) - return dev_err_probe(&pdev->dev, ret, - "Failed to get alias id\n"); - sdd->port_id = ret; - } else { - if (pdev->id < 0) - return dev_err_probe(&pdev->dev, -EINVAL, - "Negative platform ID is not allowed\n"); - sdd->port_id = pdev->id; - } - - if (sdd->port_conf->fifosize) - sdd->fifosize = sdd->port_conf->fifosize; - else - sdd->fifosize = FIFO_DEPTH(sdd); - sdd->cur_bpw = 8; sdd->tx_dma.direction = DMA_MEM_TO_DEV; sdd->rx_dma.direction = DMA_DEV_TO_MEM; host->dev.of_node = pdev->dev.of_node; - host->bus_num = sdd->port_id; + host->bus_num = -1; host->setup = s3c64xx_spi_setup; host->cleanup = s3c64xx_spi_cleanup; host->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; @@ -1250,7 +1265,7 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) } dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Targets attached\n", - sdd->port_id, host->num_chipselect); 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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:30 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 23/28] spi: s3c64xx: retrieve the FIFO size from the device tree Date: Thu, 25 Jan 2024 14:50:01 +0000 Message-ID: <20240125145007.748295-24-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Allow SoCs that have multiple instances of the SPI IP with different FIFO sizes to specify their FIFO size via the "samsung,spi-fifosize" device tree property. With this we can break the dependency between the SPI alias, the fifo_lvl_mask and the FIFO size. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 7a99f6b02319..3e7797d915c5 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1114,7 +1114,7 @@ static int s3c64xx_spi_get_fifosize(const struct platform_device *pdev, const struct s3c64xx_spi_port_config *port = sdd->port_conf; const int *fifo_lvl_mask = port->fifo_lvl_mask; struct device_node *np = pdev->dev.of_node; - int id; + int id, ret; if (!np) { if (pdev->id < 0) @@ -1130,6 +1130,10 @@ static int s3c64xx_spi_get_fifosize(const struct platform_device *pdev, return 0; } + ret = of_property_read_u32(np, "samsung,spi-fifosize", &sdd->fifosize); + if (ret == 0) + return 0; + id = of_alias_get_id(np, "spi"); if (id < 0) return dev_err_probe(&pdev->dev, id, From patchwork Thu Jan 25 14:50:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 766116 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A38F12A162 for ; Thu, 25 Jan 2024 14:50:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194238; cv=none; b=Z2dZlL75yfckOHglcFOlDtvTo3BIQLU0SOQse1JlIzcN5+t8VgXoU1lg8LUsBgc6bzLzGqFxVaokbAJuNKubDGf3NedvOqAQuhF96jF7/yNb64oJKbut0EbhH5OlU2Q0fjH57+CmrPfZ3P4xgQGmsc0e7zPMS63NdW/tfxsMdTs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706194238; c=relaxed/simple; bh=kCchjwxWRpfAc5+SmKGpjAGXAy+gVUkzX3d3/qq1C+8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ggHt4nhPJwLKZ1R2zH3DHdAJbYWWgeJRkKcgsDwf+6UqO8GhgP5Na5XQdMA6bEdzy8uxwZH5yozNn69jeVB2bnuNvfPOcV9QDwq1D7bxMN2ZPqp10/5qfIPCVmOLcFOy/e8PnWLB9b+FfuNjuAdWrRqq6ZnrAiFUhhOTj4Y3Yac= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=VmslO8nu; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="VmslO8nu" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-40e7e2e04f0so74516685e9.1 for ; Thu, 25 Jan 2024 06:50:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706194233; x=1706799033; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=S9fJpsc9ntkK7Gm49ODwE4XlmIeMd92uqdDuqa4hcJ8=; b=VmslO8nulUoK1cB42SU+hb42Lj4xjfvtL7CS0Mi3KSKxH7uKuHVQuKuD3Y+tiwWW/a yu5uoVIn+NE+gxboumCDBovm1WqjRnUt/BXpB64GSG7vlLkLKTq3EWfLzr3YbIJAH310 I4InOywqmlEsmSxWCnsvBl+ulzuhufvXgb6uDQ10RTss7mcShaUf+j5Nx0WUULmQJKI/ T0t10GPJKv6WGgeLMewxHU9BNPe+5tSQsBaPawyeuQTJNqIbV/lppLT76C1EePoLvsNx C2sHpAT1/i3SWAjR1JxxcWoW/0ir/jeNhiV5Ne9toKa7TGI0MVATgX3PcFmypVUenqkY MCGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706194233; x=1706799033; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=S9fJpsc9ntkK7Gm49ODwE4XlmIeMd92uqdDuqa4hcJ8=; b=nOtTUneVZM0REHzA6+wp1tHhi64uXqHHfIrjRU5kOBv26ekf0/uubH/udZIXtuVRMo QokdMQgeSbA/Icw562IKYwTu8FQk95G5Ix/Mod/25xe8NPq2jwSiRC+SRJsR3+fvdkna ZrUMBQikqrVc462nPKpCxsHe79dYemw+XWG5U6Y2EPdJhVRNti7yMWfcQtH4ha3fzbTa IEhWckxQh5l8wPlD5KwJCpgAY8ITHKqDb+qIYWRrmTXtlrhot6h+Nnwfo0cObvKgpaP2 s9c6NUQbf8QQnjjLaLvXzB0Hszg20N8doxOpDZbgigXabsNAN5YwcMX6b00VSuvRmx5S 5sRw== X-Gm-Message-State: AOJu0Yx+vSXmFxbyIGcP5v7KWqxSfAnSvsgngFj84CqVeOY2+DAtCYYc kbMoGal9Gqhh9JYpzRs1MSqZ01ru3IConmHG+gOdMinyqPRjyjNVlRRxf4mZVZE= X-Google-Smtp-Source: AGHT+IHav9r3fWyDiEX8CdSvB/U4xaT1J9Vfk5kfMl/b6781KqaxDQ9QxWNs1mhHIC22Ki2pTVXdRg== X-Received: by 2002:a05:600c:2907:b0:40e:6fa9:345 with SMTP id i7-20020a05600c290700b0040e6fa90345mr406881wmd.66.1706194233577; Thu, 25 Jan 2024 06:50:33 -0800 (PST) Received: from ta2.c.googlers.com.com (88.140.78.34.bc.googleusercontent.com. [34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:32 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 25/28] asm-generic/io.h: add iowrite{8,16}_32 accessors Date: Thu, 25 Jan 2024 14:50:03 +0000 Message-ID: <20240125145007.748295-26-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This will allow devices that require 32 bits register accesses to write data in chunks of 8 or 16 bits. One SoC that requires 32 bit register accesses is the google gs101. A typical use case is SPI, where the clients can request transfers in words of 8 bits. Signed-off-by: Tudor Ambarus --- include/asm-generic/io.h | 50 +++++++++++++++++++++++++++++++++++++ include/asm-generic/iomap.h | 2 ++ 2 files changed, 52 insertions(+) diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index bac63e874c7b..1e224d1ccc98 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -476,6 +476,21 @@ static inline void writesb(volatile void __iomem *addr, const void *buffer, } #endif +#ifndef writesb_l +#define writesb_l writesb_l +static inline void writesb_l(volatile void __iomem *addr, const void *buffer, + unsigned int count) +{ + if (count) { + const u8 *buf = buffer; + + do { + __raw_writel(*buf++, addr); + } while (--count); + } +} +#endif + #ifndef writesw #define writesw writesw static inline void writesw(volatile void __iomem *addr, const void *buffer, @@ -491,6 +506,21 @@ static inline void writesw(volatile void __iomem *addr, const void *buffer, } #endif +#ifndef writesw_l +#define writesw_l writesw_l +static inline void writesw_l(volatile void __iomem *addr, const void *buffer, + unsigned int count) +{ + if (count) { + const u16 *buf = buffer; + + do { + __raw_writel(*buf++, addr); + } while (--count); + } +} +#endif + #ifndef writesl #define writesl writesl static inline void writesl(volatile void __iomem *addr, const void *buffer, @@ -956,6 +986,16 @@ static inline void iowrite8_rep(volatile void __iomem *addr, } #endif +#ifndef iowrite8_32_rep +#define iowrite8_32_rep iowrite8_32_rep +static inline void iowrite8_32_rep(volatile void __iomem *addr, + const void *buffer, + unsigned int count) +{ + writesb_l(addr, buffer, count); +} +#endif + #ifndef iowrite16_rep #define iowrite16_rep iowrite16_rep static inline void iowrite16_rep(volatile void __iomem *addr, @@ -966,6 +1006,16 @@ static inline void iowrite16_rep(volatile void __iomem *addr, } #endif +#ifndef iowrite16_32_rep +#define iowrite16_32_rep iowrite16_32_rep +static inline void iowrite16_32_rep(volatile void __iomem *addr, + const void *buffer, + unsigned int count) +{ + writesw_l(addr, buffer, count); +} +#endif + #ifndef iowrite32_rep #define iowrite32_rep iowrite32_rep static inline void iowrite32_rep(volatile void __iomem *addr, diff --git a/include/asm-generic/iomap.h b/include/asm-generic/iomap.h index 196087a8126e..9d63f9adf2db 100644 --- a/include/asm-generic/iomap.h +++ b/include/asm-generic/iomap.h @@ -84,7 +84,9 @@ extern void ioread16_rep(const void __iomem *port, void *buf, unsigned long coun extern void ioread32_rep(const void __iomem *port, void *buf, unsigned long count); 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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id v17-20020a05600c471100b0040d91fa270fsm2875875wmo.36.2024.01.25.06.50.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 06:50:34 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, arnd@arndb.de Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, semen.protsenko@linaro.org, kernel-team@android.com, willmcvicker@google.com, Tudor Ambarus Subject: [PATCH v2 27/28] spi: s3c64xx: add support for google,gs101-spi Date: Thu, 25 Jan 2024 14:50:05 +0000 Message-ID: <20240125145007.748295-28-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.429.g432eaa2c6b-goog In-Reply-To: <20240125145007.748295-1-tudor.ambarus@linaro.org> References: <20240125145007.748295-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support for GS101 SPI. All the SPI nodes on GS101 have 64 bytes FIFOs, infer the FIFO size from the compatible. GS101 allows just 32bit register accesses, otherwise a Serror Interrupt is raised. Do the write reg accesses in 32 bits. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 35a2d5554dfd..e887be6955a0 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1501,6 +1501,18 @@ static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = { .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, }; +static const struct s3c64xx_spi_port_config gs101_spi_port_config = { + .fifosize = 64, + .rx_lvl_offset = 15, + .tx_st_done = 25, + .clk_div = 4, + .high_speed = true, + .clk_from_cmu = true, + .has_loopback = true, + .use_32bit_io = true, + .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, +}; + static const struct s3c64xx_spi_port_config fsd_spi_port_config = { .fifosize = 64, .rx_lvl_offset = 15, @@ -1556,6 +1568,10 @@ static const struct of_device_id s3c64xx_spi_dt_match[] = { .compatible = "samsung,exynosautov9-spi", .data = &exynosautov9_spi_port_config, }, + { + .compatible = "google,gs101-spi", + .data = &gs101_spi_port_config, + }, { .compatible = "tesla,fsd-spi", .data = &fsd_spi_port_config,