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([178.197.215.66]) by smtp.gmail.com with ESMTPSA id ig1-20020a056402458100b0055ca5ce62ddsm1873315edb.12.2024.01.25.05.06.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 05:06:31 -0800 (PST) From: Krzysztof Kozlowski To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 1/6] arm64: dts: qcom: sm8150: describe all PCI MSI interrupts Date: Thu, 25 Jan 2024 14:06:21 +0100 Message-Id: <20240125130626.390850-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Not tested on hardware. Signed-off-by: Krzysztof Kozlowski --- Bindings now expect 8 interrupts: https://lore.kernel.org/linux-devicetree/20240125-dt-bindings-pci-qcom-split-v2-0-6b58efd91a7a@linaro.org/T/#t --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 761a6757dc26..26cf8459f74f 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1843,8 +1843,16 @@ pcie0: pcie@1c00000 { ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -1934,8 +1942,16 @@ pcie1: pcie@1c08000 { ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ From patchwork Thu Jan 25 13:06:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 766034 Received: from mail-lf1-f50.google.com (mail-lf1-f50.google.com [209.85.167.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 43A495100D for ; Thu, 25 Jan 2024 13:06:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706187999; cv=none; b=exf/ZGBKjkTV8ULe3/951JEtbUWwoZKp5FkivdtUUR76Lq3Tl+8K57JTcUkDxWzXo826oePuMPz+KB1DRpJIHCExe1g0d+SeMrQTfI3ryz3C/Md+hB2DxqTmVb99IH1+qd9Ppy5eAQQVjyhappiDVQD+/qzCt/fvW6lxGxET5tA= ARC-Message-Signature: i=1; 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([178.197.215.66]) by smtp.gmail.com with ESMTPSA id ig1-20020a056402458100b0055ca5ce62ddsm1873315edb.12.2024.01.25.05.06.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 05:06:33 -0800 (PST) From: Krzysztof Kozlowski To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 2/6] arm64: dts: qcom: sm8250: describe all PCI MSI interrupts Date: Thu, 25 Jan 2024 14:06:22 +0100 Message-Id: <20240125130626.390850-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240125130626.390850-1-krzysztof.kozlowski@linaro.org> References: <20240125130626.390850-1-krzysztof.kozlowski@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Not tested on hardware. PCIe0 was done already in commit f2819650aab5 ("arm64: dts: qcom: sm8250: provide additional MSI interrupts"). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 760501c1301a..41f5e6eb2f6b 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -2248,8 +2248,16 @@ pcie1: pcie@1c08000 { ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -2349,8 +2357,16 @@ pcie2: pcie@1c10000 { ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>, <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; 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([178.197.215.66]) by smtp.gmail.com with ESMTPSA id ig1-20020a056402458100b0055ca5ce62ddsm1873315edb.12.2024.01.25.05.06.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 05:06:35 -0800 (PST) From: Krzysztof Kozlowski To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 3/6] arm64: dts: qcom: sm8350: describe all PCI MSI interrupts Date: Thu, 25 Jan 2024 14:06:23 +0100 Message-Id: <20240125130626.390850-3-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240125130626.390850-1-krzysztof.kozlowski@linaro.org> References: <20240125130626.390850-1-krzysztof.kozlowski@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Not tested on hardware. Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index e78c83a897c2..70ac80a6dc8b 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1611,8 +1611,16 @@ pcie1: pcie@1c08000 { ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ From patchwork Thu Jan 25 13:06:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 766033 Received: from mail-ed1-f44.google.com (mail-ed1-f44.google.com [209.85.208.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 882B953E2F for ; Thu, 25 Jan 2024 13:06:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706188002; cv=none; b=gfSNzAW8CxBcwvxyjXRJEkUoC+0QIeELyYHr7n/3dRKF5pSoYe6rCUxYpC2Z2i0t7WaGO5WEgArkPkr0dXnsv3wQCvFlVOajoxhMHNLAdDD5X01JkMRmDMM0VLxS4gv6K29+l7SK2R53pf5YVM1irXthE4AWuKy3kMK5JvQ/VrE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706188002; c=relaxed/simple; bh=8XC8NJ2NcS8Kjm/9BPbg3ZBSERWHKQEz2mfwjSKoC/8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UM0eIDn7ICAfGagV5ZTqYcejQmiPq04nQJWHySqcQIWnJ2EUGYuYhPYZ2a2/drcP0EmW2g8fewXhLnfwoaCmx+SMVFuAZeZqSoGXvfm6OUaKbqGc5behurSgNvG1THuEjug7Nd0aeFEJHfCL/cN5maudYjJ7F4LbeuxpjYVnmtQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=eu6UsZaW; arc=none smtp.client-ip=209.85.208.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="eu6UsZaW" Received: by mail-ed1-f44.google.com with SMTP id 4fb4d7f45d1cf-557dcb0f870so8275097a12.2 for ; Thu, 25 Jan 2024 05:06:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706187998; x=1706792798; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jFG5WQb/wLFt5isMQsjJbaJFdl++eyZorkiaDRvi+/M=; b=eu6UsZaWWMoKIh8jKBeZ7FUvPHEcHiV8/yt9ktuCm/qaH+0l+07bylh5MmO6WC/iZ4 orEmdDnijKnvJUHizzBB3spXgfkCyBqCKRgJ+aDW9jTRYzo0/6HVJ1Or9Mh8KExBRRIz 4tee0xqiIyub2uYf//Zrw/daoOKaIPCW6CJajUFYLHhP90ZLxybs7ZTVcJ/HCAfZMTcw l+AP+f132vOb/+7rknGa4s722vN+w3FM5BGO95BcV103iAfD254PeVjyYSdiG8uyNRz5 g3oQXhh0hxt1KClzes+HT/qLxsn8PqBmvMrN7ddkqV809IWLir1kHUHRwDazxLTQmHmH cYKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706187998; x=1706792798; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jFG5WQb/wLFt5isMQsjJbaJFdl++eyZorkiaDRvi+/M=; b=YgsuG0BuBi1muxX+rG2+PDvG8D8UYJd3mCOe5HtUhc1Zeq8YCTNjrBiVw8lyFpM8F3 2odvg0+R0McxI9dt93ZI8BKmXBVkLMSWETUqm7924KDbM/ZkKRxPi0VlUCIbYrxIqUUA U7+3Q9eMjRPa18Nml0xFvahgs6YmG2lqjyGwSXB8V96f6XhBLF7Bqai3wYmr+5FPPZy4 RPkmEq6oYKYS1TvdAmjfXcEczIG/GQ58Y0Z2ETzn2YOex265ALYvjBX9XGie2eH47qFh 0u8a9T8FSg06gz8oEofBAYfOa5Le9NSMRrYnXflcqWfFPCqugxkAYOxZyH1W3dlO3pYR sYGw== X-Gm-Message-State: AOJu0Yzf/hS+V8+Ox6bveSCWi8dg0b7P/8CXkY+C3bRIuCXR1ZMZxQPC pwANvZMKXTBwqHdI4MJy5cHk2HZ6IyGMeYnXbxVHdSmuVIRal4rm5UGMGF+ghAg= X-Google-Smtp-Source: AGHT+IE6XvYnsRe9NdOXHcH+gkynxuFp3rjAzo2eH85YohKw2h78OkbY5UTossGSMmDogXwScw88BQ== X-Received: by 2002:aa7:c914:0:b0:55d:1774:b130 with SMTP id b20-20020aa7c914000000b0055d1774b130mr81105edt.85.1706187997820; Thu, 25 Jan 2024 05:06:37 -0800 (PST) Received: from krzk-bin.. ([178.197.215.66]) by smtp.gmail.com with ESMTPSA id ig1-20020a056402458100b0055ca5ce62ddsm1873315edb.12.2024.01.25.05.06.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 05:06:37 -0800 (PST) From: Krzysztof Kozlowski To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 4/6] arm64: dts: qcom: sm8450: describe all PCI MSI interrupts Date: Thu, 25 Jan 2024 14:06:24 +0100 Message-Id: <20240125130626.390850-4-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240125130626.390850-1-krzysztof.kozlowski@linaro.org> References: <20240125130626.390850-1-krzysztof.kozlowski@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Only boot tested on hardware. Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 06f183ef8c78..235e31c86e38 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1784,8 +1784,16 @@ pcie0: pcie@1c00000 { msi-map = <0x0 &gic_its 0x5981 0x1>, <0x100 &gic_its 0x5980 0x1>; msi-map-mask = <0xff00>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ @@ -1893,8 +1901,16 @@ pcie1: pcie@1c08000 { msi-map = <0x0 &gic_its 0x5a01 0x1>, <0x100 &gic_its 0x5a00 0x1>; msi-map-mask = <0xff00>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; 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([178.197.215.66]) by smtp.gmail.com with ESMTPSA id ig1-20020a056402458100b0055ca5ce62ddsm1873315edb.12.2024.01.25.05.06.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 05:06:38 -0800 (PST) From: Krzysztof Kozlowski To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 5/6] arm64: dts: qcom: sm8550: describe all PCI MSI interrupts Date: Thu, 25 Jan 2024 14:06:25 +0100 Message-Id: <20240125130626.390850-5-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240125130626.390850-1-krzysztof.kozlowski@linaro.org> References: <20240125130626.390850-1-krzysztof.kozlowski@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Only boot tested on hardware. Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index ee1ba5a8c8fc..80e31fb21055 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1713,8 +1713,16 @@ pcie0: pcie@1c00000 { linux,pci-domain = <0>; num-lanes = <2>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; @@ -1804,8 +1812,16 @@ pcie1: pcie@1c08000 { linux,pci-domain = <1>; num-lanes = <2>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; From patchwork Thu Jan 25 13:06:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 766032 Received: from mail-ed1-f48.google.com (mail-ed1-f48.google.com [209.85.208.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FA8455795 for ; Thu, 25 Jan 2024 13:06:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706188004; cv=none; b=gSupyO1GEQo0fjeN1yabftLTII171O8rmkPUShDHsLG82pzHsMKy0HEsmdlN1C0mQEzYZEfTkL2gewAUGoVEDNv0CTC+ss7Dvxev4H2g5F/l7FTc+jJOe3D2qKUt94x3b7sj/wkKwFIBNIFEVbml1CFKkWv5ZeBG7lUU7+neQm0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706188004; c=relaxed/simple; bh=Vm8FYWkCbiN6pEEwfgqVnqgx6X6dabUYF1SQcOeQgi4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Bn+SW0LqDT9zoB8D+uo8Rt2fbnmkld0aA29V0LKZPkxjSPi0U7CV76qyUV0Jhs5lycHmbzP1zr6JjeODoMSXbzsj9/lLqvm8kG1v/eA9TNQbMevfhPajzM+tXsoojKpvC6hU41QdSMYRRIcK1y62L0bY6rLzrAfSlJoH8ZGcbbY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=Ksk4o+Cd; arc=none smtp.client-ip=209.85.208.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Ksk4o+Cd" Received: by mail-ed1-f48.google.com with SMTP id 4fb4d7f45d1cf-558f523c072so7995610a12.2 for ; Thu, 25 Jan 2024 05:06:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706188001; x=1706792801; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Hz4UOUwLaTrVZVjKRBIuuQV1CZ1n1JSNcVoZKpZXtzg=; b=Ksk4o+CdSuwqgXZZ1vMSQQhoXKBocWFevZyu4NuT9i3uFKhB5ZquGNzcHPZMjuTfW7 UepuOrSB+CKGVq/Lg6tb2Jq22em++JBoBQrxUqWKF96MB8H/bp1T9iB7CCWd6TBq33cP Rqz3Y+Dn+ySFKmNKR5axj7BB/pXlkdRvPX5jdrjH2VcCsvwNihDtxS0zRH0ty7HlRpPX Obqk9BnOcmA2WM1fInPh/ANB0u2bYGUr5c+9+UCZ/bJYAZHnoVHmdKH3q/NcYevxso+a y1TXk3BSUUQWvR2pjBFZqvTbZF7zqLwo8zUb/na514yY0GolgvoCcRrSW2CTJY6z7NoI 0NyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706188001; x=1706792801; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Hz4UOUwLaTrVZVjKRBIuuQV1CZ1n1JSNcVoZKpZXtzg=; b=CWrVKM31eI7is24l9zCMqEih2bzyijYWbOC99Hn/TQSrrqpi++KO9rFLYS35djL9R6 qxvY+efFg6lVbTytf5dHU69PpBp8Cifux4Mflo/64suhSz5rXi6JsJCczkvLgt5GZXXL uPqxdSRFRind9LefjXb+FjynNTkZY5O0y1AgXf+3hDzkskZUtNCip18K1WrWinMeDgg4 vS/LgsHtGrPK1ReuK6Yo8Nq4l6Mby6Jxj/QsOGpIQ4wGGPfO0fEzQ88QvhLfC/tYBlxC s0594ilRqa/oTFvsbxxmBSPZ/2ZZK8r3cP2D5yrub49sWvSyywG9NU64b7m0yTKwfxSz Orsw== X-Gm-Message-State: AOJu0Yx3ynGefKWX74nzeNcjNVSHZFZU6w6LhXWoKA0MB9umb5GahWk5 jdGEqn3ah21AAdcldKayxnf5CZaHxeextZ4/2jD95xml6AX93sbAG1ch+tp3+YM= X-Google-Smtp-Source: AGHT+IHm6+LA7xKQVSTlAszsDlUkRYqXhWF42y0uqkcwpk8+pO6DRmRsYDU9XLKhjy6W3WVccCpC/Q== X-Received: by 2002:a50:99de:0:b0:55c:fd62:18a4 with SMTP id n30-20020a5099de000000b0055cfd6218a4mr283034edb.82.1706188001502; Thu, 25 Jan 2024 05:06:41 -0800 (PST) Received: from krzk-bin.. ([178.197.215.66]) by smtp.gmail.com with ESMTPSA id ig1-20020a056402458100b0055ca5ce62ddsm1873315edb.12.2024.01.25.05.06.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 Jan 2024 05:06:40 -0800 (PST) From: Krzysztof Kozlowski To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 6/6] arm64: dts: qcom: sm8650: describe all PCI MSI interrupts Date: Thu, 25 Jan 2024 14:06:26 +0100 Message-Id: <20240125130626.390850-6-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240125130626.390850-1-krzysztof.kozlowski@linaro.org> References: <20240125130626.390850-1-krzysztof.kozlowski@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Each group of MSI interrupts is mapped to the separate host interrupt. Describe each of interrupts in the device tree for PCIe hosts. Not tested on hardware. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index 2df77123a8c7..9fc4f3e37a8c 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -2213,8 +2213,16 @@ pcie0: pci@1c00000 { <0 0x60100000 0 0x100000>; reg-names = "parf", "dbi", "elbi", "atu", "config"; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; clocks = <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, @@ -2317,8 +2325,16 @@ pcie1: pci@1c08000 { "atu", "config"; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "msi0", "msi1", "msi2", "msi3", + "msi4", "msi5", "msi6", "msi7"; clocks = <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>,