From patchwork Tue Jan 23 22:48:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 765210 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:10c4:b0:337:62d3:c6d5 with SMTP id b4csp1840572wrx; Tue, 23 Jan 2024 14:50:09 -0800 (PST) X-Google-Smtp-Source: AGHT+IH5uea2RYY6zwT4pzpuW8Jf3Qt4yovjSFktk+PwRnodHbkaOT1MfMMA6scUyWMWVbm+8wnQ X-Received: by 2002:a05:6214:202c:b0:67f:26c9:ffdb with SMTP id 12-20020a056214202c00b0067f26c9ffdbmr491320qvf.22.1706050209443; Tue, 23 Jan 2024 14:50:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706050209; cv=none; d=google.com; s=arc-20160816; b=f5gNFO/d3rvwZgwYXCdlP8qsCfl50xNyP7pY9I3X2aIZtrO+eCZ6bWDgMFUrsQTnOS rv0i7CP0nzmPZ7eqiuMe5NQQEFGyG2aWmW3EjN4gTo9bQzpw3zSWjx2nOA/BoYUL68qx V8jlrOfDJuFAu/qHM4XClZgk6kSIVtcOBGlyshnnpcylzj3pGznQJ5K/ZrXgfq9jloZ7 g9DajJv1gjecOmwNA2u1qis/cz1mEaxyryZYuUSRqDs7xdbo9cz6yLLRnmvrtO9kX2VU CX+TKIS0/Tfdq53viMwzUG78onduhe0/fDRNVVofjHNxtyO3bQ4j8Wo7PgXTtC3iUDu2 JsgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Ne9fETa/FFUb8yRzxwXxz52suSQeNnRaNemXs5i2sTM=; fh=syX9H1Z6jvTUZoUNlfCNxZiWCwEj552WMbtCUDPMiLw=; b=Z8PYZA7dYan/R0rj83LS/HlIOfD6/HnuK2E482OwyKCN/9W7oZuw2jCKSDFSZsY0QX XHU0uV8IOHNqOYIZgBzvGPdZZSTN/EBKoiR59PLOt6HS5gtgWqtxQhtuRm1/2AoflF8G rwMMX9S+pAvjyizQZYEXAy5YSA5SIj3UlvmED19jJnfOXC+z2TBiD0JFCBIjU2kSu747 K1+dlyzKwPfgHbPWCtoTaZlcQ7B464ou96hpFwJveoEzcchVs73VmvO7nhwCG2jRyMZ1 pLw5iWoMkkzQzQjNKgbvhNBu1tBfIcN4uDUPuqbsppYwfneOhuv9XL9SjmKTeub31Ai/ lSuw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZRuyS8Qn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v18-20020a0cdd92000000b006817f6c91a1si8644474qvk.295.2024.01.23.14.50.09 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Jan 2024 14:50:09 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZRuyS8Qn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rSPZl-00070o-Lg; Tue, 23 Jan 2024 17:49:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rSPZh-000701-B9 for qemu-devel@nongnu.org; Tue, 23 Jan 2024 17:48:58 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rSPZc-0004Gf-QJ for qemu-devel@nongnu.org; Tue, 23 Jan 2024 17:48:56 -0500 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-3392291b21bso4159650f8f.1 for ; Tue, 23 Jan 2024 14:48:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706050130; x=1706654930; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ne9fETa/FFUb8yRzxwXxz52suSQeNnRaNemXs5i2sTM=; b=ZRuyS8QntMWqxs9s7HxavN5d2ok6Fulqs2JUCVXbQypc/+ztBEyHIWPblsxiVnxM8P +k5ZkCPzqB4XgUzFqQQ01YJJXkvcwEueh9Lz0xOene4T7DSBZuDibeYeG8SWd+Kg2G5K sb9rkDZuXOcaCB3+0KKZrDCdSjRDspMWQm5IBWOHuLpKQE71EWWd0PxhCXmF8fAARpRD qJy1RETk+py0JJ2Kx1FVxdD0zR+4XRlaICI4+aTCXD35DVFwVeeGX/sk1CuAXtbZa/Ec s5qgyfDA+76CV9A/RFTulO0vqnz4DZYFYeDrCmv93JdEbL2jtu/BtelRsAVXsB+NEZvx Tp1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706050130; x=1706654930; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ne9fETa/FFUb8yRzxwXxz52suSQeNnRaNemXs5i2sTM=; b=UGQ0RLR+aOyF6LO4/rvG1aokAMWZWP6J7iNQOHFtltqPyRGo8pvrcrefsoQ045Bv2z xHWSpxPOvf/RCC+0/Qj2dBfur2yaWYwrGLJun/X6c/Ds/Ky2X/S6lqxklcNZAURCxNhy 35DtfvUxBsuu6l7oe4Xty20HkbFpz/db8vsSjsFG/8E8lHF3nMQhZDf2sIRt2gMz/3vn D0y5rjhWnP1r30mbWJ5Y7ni2eEc7Znh4C8aMNPBXm6EQkoGSkWFbm6GrftGEHr14bw2K tOO6tPLOjPitcWGtRMa5b7zh3WgcrShtce7Q8ZIiP5RUDsTpIHHKPZxXSBeq3tF6Gyvb 4yYQ== X-Gm-Message-State: AOJu0Yx53vvo6uRAzSyLKXPH2GgF8drWATvHyG/iwdjSR5CGe+3k/yA4 iF8rzmKK5QdIhcd0zyfy8ObGQGHai0Ai++zyAre3m/v+S3+9OESV3MW+1nv3PBmSPo2hmtyzp7g A X-Received: by 2002:a05:6000:799:b0:339:3595:56a with SMTP id bu25-20020a056000079900b003393595056amr2564123wrb.26.1706050130455; Tue, 23 Jan 2024 14:48:50 -0800 (PST) Received: from m1x-phil.lan ([176.187.194.78]) by smtp.gmail.com with ESMTPSA id n17-20020a5d67d1000000b003392f229b60sm7627985wrw.40.2024.01.23.14.48.49 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 23 Jan 2024 14:48:50 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Joel Stanley , Andrew Jeffery , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH v2 1/5] hw/arm/aspeed: Remove dead code Date: Tue, 23 Jan 2024 23:48:38 +0100 Message-ID: <20240123224842.18485-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240123224842.18485-1-philmd@linaro.org> References: <20240123224842.18485-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Remove copy/paste typo from commit 6c323aba40 ("hw/arm/aspeed: Adding new machine Tiogapass in QEMU"). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan --- hw/arm/aspeed.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index cc59176563..4bc292ff84 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1301,7 +1301,6 @@ static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data) mc->default_ram_size = 1 * GiB; mc->default_cpus = mc->min_cpus = mc->max_cpus = aspeed_soc_num_cpus(amc->soc_name); - aspeed_soc_num_cpus(amc->soc_name); }; static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) From patchwork Tue Jan 23 22:48:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 765212 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:10c4:b0:337:62d3:c6d5 with SMTP id b4csp1840574wrx; Tue, 23 Jan 2024 14:50:09 -0800 (PST) X-Google-Smtp-Source: AGHT+IERVj6EcJPoosQ1tbMyAhOE3ifawrSRMLrRxH2EhKme77qFU6xs/df7oVcf7wKOFmKSDA/4 X-Received: by 2002:ad4:5ca7:0:b0:685:bc07:ed0d with SMTP id q7-20020ad45ca7000000b00685bc07ed0dmr1650469qvh.9.1706050209672; Tue, 23 Jan 2024 14:50:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706050209; cv=none; d=google.com; s=arc-20160816; b=aiflJTFsifRElPfGUbQxXmWV04VmJRX3lrIKksdtD442kfXt+uauO7gyrwf5LUadXW emoHi8VlaDnjcHx7XyW/Sby/Upc4e3vdAPJECyFUZz/vHcSJ3QJp59RWgTJU+cbm2eQ2 Axnza+6MO2h9iQXN62f/OZnDJD0vXdavPwtMY9l3IuZDgSryzvM2Ml9d//0+cqwgljAQ f9gBbT5t0f2kBTWiCMGmXur0oSQsBrx0UvqVDqthpRVRenQP5yJEje0z4l/ZS8jboWJD Aw3zlE5QkVhF4B6wdft4g+fY2BP0RvBeAx/2qBRHUXGL0cg7bmGWN2t7q+OGtoRUSLTy ZMvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=5rLt+18wiq79FMT/YlMa8u073Rtk4hJW2iJ8pfUwdG0=; fh=syX9H1Z6jvTUZoUNlfCNxZiWCwEj552WMbtCUDPMiLw=; b=jJ0H5F/CMAz1qnvdqynFIlSGqxwszFa5AP4plIHJxv1SpDkfOTrpvMnCeuMocQ1RrL PdysewThJRDjUtj4sNKBJgxLhEGXWxLgMZLfqcN6t/Bh0qYEDWy6pZ4RBmBP1W/WaQ38 G5Mc+tJSEjCuroiylq7XmgvtuxY9OQoVWx8c4LUJuOQygUadzJgWUVFlL+Fc6F/Ig46G Zy49jN/A9fDOixW7Zx1X0ngAjtib14CQ+b9mvi89VvFkhJxVthy3tE3CiWfIa4+aaNf8 Y8dZ8UYCsPmsa7408uCj3DRo0DDqMMRGPSYk39Vs/vUy12zHm5F7PG4cjuUM6FkZT0oa 0oSw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="MUNIN/J+"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a2-20020a05620a124200b00781e319f28esi8880126qkl.160.2024.01.23.14.50.09 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Jan 2024 14:50:09 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="MUNIN/J+"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rSPZp-00071w-Cf; Tue, 23 Jan 2024 17:49:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rSPZm-00071L-L1 for qemu-devel@nongnu.org; Tue, 23 Jan 2024 17:49:02 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rSPZi-0004IA-1V for qemu-devel@nongnu.org; Tue, 23 Jan 2024 17:49:02 -0500 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-40ec34160baso5446575e9.1 for ; Tue, 23 Jan 2024 14:48:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706050135; x=1706654935; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5rLt+18wiq79FMT/YlMa8u073Rtk4hJW2iJ8pfUwdG0=; b=MUNIN/J+CSBDqTuwGxTvAMMtblKyk2IkBhe+FbMK+UAFfHHgJ3AzHgcl5G6CKBH+QN 25PaKU+6oWPj+YSvR27tM9mlsSeYmeS4noxKX6ongTYYok6afskEy1mv+bc7qmEMI2gg db8qwIf5yVG+2JBMqv9RZIYpnnowXiiX+JhE3LVDxVxrjiV17ugf3vne1aaCCxZ6I8KY ZO/LtWa1geWgMe/ey8MGT8LIdjARMzIcKBLCMarxEENE7+tjaVyX84vt80/j7YOOkZwF +4isZASagDbB3EprQXA2FShYNSXmjaA1E23XXn9AqCda0Gp9kdZSrdzX0NZX8wtQL9XJ IPIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706050135; x=1706654935; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5rLt+18wiq79FMT/YlMa8u073Rtk4hJW2iJ8pfUwdG0=; b=btFvQcKeKZL1/jAEOegAkbYtcb84ZscH2OLJLOqz9m70EHA8IfuzVMgAoLYXGROtZ7 7t3XnicrF7UIgWevnEfWYHcTwVZhX2hiA+MMgtc5EjK6BWxP/dLj4h6sZMOCXI/37dDl DI890lrBB6KV1n2ecHJcOMf0cskFjBswHA135HnDyZSbh2iE2AD20Ge/3Sduuvtn/zgH so6XVBI7BJTezFVmXFljz3iT8DKkWC5zjktlwir453oPsYOjhWIRy2bwdr/7kDHCxl/x XliAemHW1ZsDNDy559Eq1qTQQZQxyRF5y+VqeNq8dy2N1HpoEiHLiRnau9cN+FHtUB7M kGXw== X-Gm-Message-State: AOJu0Yw9EUKmgn14fWRpETj1seNC9HhOWMWRRkCLpi0P0RcHItWk5bSo w/GT2dL4CcWtwxSTBpVL/DQ1Ozsm31i+hW5vqyfy3wHdYL5iUBykjYpX7rVUQgportBufLFyTtr p X-Received: by 2002:a05:600c:1c16:b0:40e:88be:4ef0 with SMTP id j22-20020a05600c1c1600b0040e88be4ef0mr1089273wms.0.1706050135639; Tue, 23 Jan 2024 14:48:55 -0800 (PST) Received: from m1x-phil.lan ([176.187.194.78]) by smtp.gmail.com with ESMTPSA id l39-20020a05600c1d2700b0040e50d82af5sm43887923wms.32.2024.01.23.14.48.54 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 23 Jan 2024 14:48:55 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Joel Stanley , Andrew Jeffery , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH v2 2/5] hw/arm/aspeed: Set default CPU count using aspeed_soc_num_cpus() Date: Tue, 23 Jan 2024 23:48:39 +0100 Message-ID: <20240123224842.18485-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240123224842.18485-1-philmd@linaro.org> References: <20240123224842.18485-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since commit b7f1a0cb76 ("arm/aspeed: Compute the number of CPUs from the SoC definition") Aspeed machines use the aspeed_soc_num_cpus() helper to set the number of CPUs. Use it for the ast1030-evb (commit 356b230ed1 "aspeed/soc: Add AST1030 support") and supermicrox11-bmc (commit 40a38df55e "hw/arm/aspeed: Add board model for Supermicro X11 BMC") machines. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Reviewed-by: Gavin Shan --- hw/arm/aspeed.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 4bc292ff84..5b01a4dd28 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1212,6 +1212,8 @@ static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; amc->i2c_init = palmetto_bmc_i2c_init; mc->default_ram_size = 256 * MiB; + mc->default_cpus = mc->min_cpus = mc->max_cpus = + aspeed_soc_num_cpus(amc->soc_name); } static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc, @@ -1586,11 +1588,12 @@ static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, mc->init = aspeed_minibmc_machine_init; amc->i2c_init = ast1030_evb_i2c_init; mc->default_ram_size = 0; - mc->default_cpus = mc->min_cpus = mc->max_cpus = 1; amc->fmc_model = "sst25vf032b"; amc->spi_model = "sst25vf032b"; amc->num_cs = 2; amc->macs_mask = 0; + mc->default_cpus = mc->min_cpus = mc->max_cpus = + aspeed_soc_num_cpus(amc->soc_name); } static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, From patchwork Tue Jan 23 22:48:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 765213 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:10c4:b0:337:62d3:c6d5 with SMTP id b4csp1840600wrx; Tue, 23 Jan 2024 14:50:15 -0800 (PST) X-Google-Smtp-Source: AGHT+IG6YtvWP+vMm1cHvq/NoLPsRBnKP0v8hrAEJgJiP4UETApMaZ1D3HShX84AxFcLiJnGZm7E X-Received: by 2002:a05:6214:5285:b0:685:9c9d:8cf with SMTP id kj5-20020a056214528500b006859c9d08cfmr1628600qvb.0.1706050214990; Tue, 23 Jan 2024 14:50:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706050214; cv=none; d=google.com; s=arc-20160816; b=Vdg4qmcZcFLCcSROL02rOPDLwXBFCdXJ+5W2R80PhNxGb7vGDNbWWsy4Wish4wwtkT LmkB38Rk0n/CHnkaO/iZ1OS9bbDuzlQpmShtqqLoSAfJx03UzvPIdgKcco67mJTPkzZq r3nUhZszcHqKGj0v2j/uM614eeJVHgxDwiVHMjw6KsF58inlQym2Ehx9PKme/4/FQ/bC 4IAMSAGgmeqMS/l0f0jrHT9HnYryWnUjP+CPXVcGJS9WZKpSyrCSNj9vlIYlYL21N3dl 3LlxfioZlyhLjqgycTB9XLvLtWV5z7e4zwBVJGwQvd3oR0s3FTXKuylBLJhXnXhyS1Fj nDfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=QEBEkDP6qGPzC+3ewoPUDTZ07buC9oNuSZRC+33yQxM=; fh=syX9H1Z6jvTUZoUNlfCNxZiWCwEj552WMbtCUDPMiLw=; b=JfU5ts1Hv8oSugFZqrkAoz78z+zSUOqbaf69HNJQjEA1UNZ59XBJ67ne6jj6/I7L3L caKOTBvSMUs3AcSXjjZAi88QAijgtDOPshQENK5k9jn/sZYbUuerWAjQpkQdvKllM0ng QzzmpEU/kh7xNdVZ8C/tNCHWc9Ze/PI6Uid/y33owbmn1CBGlVSHULMVcmYq+N7cSOU/ qbs8BoyJEphZ3cQ/Y30zGiwhsx32NTCzQNB7wlYMbgaQGdC6CjkAVe19fc2x+EI3eNTu odnGFXvY82dTUZPA73R09HSs3G+NyLOQXDZUqTSrQCdiEbyJ3QF9ijSoWFmarwRm0zbJ Vv5g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OIRoBZBl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id b10-20020a0c9b0a000000b0068195ac3f0dsi8895185qve.316.2024.01.23.14.50.14 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Jan 2024 14:50:14 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OIRoBZBl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rSPZu-00072n-0U; Tue, 23 Jan 2024 17:49:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rSPZp-000729-Ip for qemu-devel@nongnu.org; Tue, 23 Jan 2024 17:49:05 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rSPZm-0004L9-FA for qemu-devel@nongnu.org; Tue, 23 Jan 2024 17:49:05 -0500 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-3392b15ca41so2062829f8f.0 for ; Tue, 23 Jan 2024 14:49:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706050141; x=1706654941; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QEBEkDP6qGPzC+3ewoPUDTZ07buC9oNuSZRC+33yQxM=; b=OIRoBZBlcRKU/WphpiwVPqJekTj0nYXosCyyylIAgXn1+xtrYAM9N28a9/bfy7eaBf ImNN7m64QuGV420jNwbnXMGMIdTDwdtJJc2MU9ftGwGSYeoa6+bY6gdzcm5mWWaFxeys H31a70aU7i3NNd5/T1IkIpIiWZkWjP1noZoWM+5NtnHWyGgfnnxcahWwPwB78JjLVXD1 tyvC8k1G3Iyu4aDeXauavRwL9XJlNYUbFbmhqdB1o7lGC4awAA2vEuowp2q+74LF+D26 RfY2miS50IT2BM6NkMuqGn6jd1DNT6bfr3eFeCoRXP6F3seY/SWChfr/hoqGthwNyj2Q kPTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706050141; x=1706654941; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QEBEkDP6qGPzC+3ewoPUDTZ07buC9oNuSZRC+33yQxM=; b=E+U32fZX9nqAJKqCOfokwf9agmqPllf2TwAfxf34To7fRFZtYQHoyL/wkf/Wsyro1M pr1aa4i+BSZ0N5mVXWB0uu1blvRO6r868XG84FKgWplgCK8Mkiz8/OlQmSHcKgnsvmNf 8AyqcyeUAijBdh+bIiHHcR3bC2/bvQ7op1/pFrS9qP/sbyszYvz3TwoZ6+MQ+ss73rox CCLlgKGcQI/0U2O8nvhSpwumEoWtxTzK2L2/eq/zqHZzteK9qt1W0wSscWnWmnGgQiJ1 JV+BecKvInXkhws4fxiEB5akdtw8k4O8tLKonB5ruOoU03OdU2wspoZqp1SL/TaI3v5W YOrw== X-Gm-Message-State: AOJu0Yz94UamZfG4TWKSNJqcjBBxumG8HBccj8fF8RYQ26opzV9uQJTI aVXVpXCQYFI348qXyKj/B/04ZdtGrAku+68mBuGWstfLBhSOyu0jqOk1gjJBipBydJAZqZ11ZLM P X-Received: by 2002:a5d:64c4:0:b0:337:eea:6b24 with SMTP id f4-20020a5d64c4000000b003370eea6b24mr120947wri.69.1706050140875; Tue, 23 Jan 2024 14:49:00 -0800 (PST) Received: from m1x-phil.lan ([176.187.194.78]) by smtp.gmail.com with ESMTPSA id c11-20020a5d63cb000000b00337aed83aaasm17295972wrw.92.2024.01.23.14.48.59 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 23 Jan 2024 14:49:00 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Joel Stanley , Andrew Jeffery , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH v2 3/5] hw/arm/aspeed: Init CPU defaults in a common helper Date: Tue, 23 Jan 2024 23:48:40 +0100 Message-ID: <20240123224842.18485-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240123224842.18485-1-philmd@linaro.org> References: <20240123224842.18485-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Rework aspeed_soc_num_cpus() as a new init_cpus_defaults() helper to reduce code duplication. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan --- hw/arm/aspeed.c | 71 +++++++++++++++++++------------------------------ 1 file changed, 28 insertions(+), 43 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 5b01a4dd28..636a6269aa 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1141,10 +1141,14 @@ static void aspeed_machine_class_props_init(ObjectClass *oc) "Change the SPI Flash model"); } -static int aspeed_soc_num_cpus(const char *soc_name) +static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc) { - AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name)); - return sc->num_cpus; + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc); + AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name)); + + mc->default_cpus = mc->min_cpus + = mc->max_cpus + = sc->num_cpus; } static void aspeed_machine_class_init(ObjectClass *oc, void *data) @@ -1176,8 +1180,7 @@ static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) amc->num_cs = 1; amc->i2c_init = palmetto_bmc_i2c_init; mc->default_ram_size = 256 * MiB; - mc->default_cpus = mc->min_cpus = mc->max_cpus = - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); }; static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data) @@ -1193,8 +1196,7 @@ static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data) amc->num_cs = 1; amc->i2c_init = quanta_q71l_bmc_i2c_init; mc->default_ram_size = 128 * MiB; - mc->default_cpus = mc->min_cpus = mc->max_cpus = - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); } static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, @@ -1212,8 +1214,7 @@ static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; amc->i2c_init = palmetto_bmc_i2c_init; mc->default_ram_size = 256 * MiB; - mc->default_cpus = mc->min_cpus = mc->max_cpus = - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); } static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc, @@ -1231,8 +1232,7 @@ static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc, amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; amc->i2c_init = palmetto_bmc_i2c_init; mc->default_ram_size = 512 * MiB; - mc->default_cpus = mc->min_cpus = mc->max_cpus = - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); } static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) @@ -1248,8 +1248,7 @@ static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) amc->num_cs = 1; amc->i2c_init = ast2500_evb_i2c_init; mc->default_ram_size = 512 * MiB; - mc->default_cpus = mc->min_cpus = mc->max_cpus = - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); }; static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data) @@ -1266,8 +1265,7 @@ static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data) amc->num_cs = 2; amc->i2c_init = yosemitev2_bmc_i2c_init; mc->default_ram_size = 512 * MiB; - mc->default_cpus = mc->min_cpus = mc->max_cpus = - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); }; static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) @@ -1283,8 +1281,7 @@ static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) amc->num_cs = 2; amc->i2c_init = romulus_bmc_i2c_init; mc->default_ram_size = 512 * MiB; - mc->default_cpus = mc->min_cpus = mc->max_cpus = - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); }; static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data) @@ -1301,8 +1298,7 @@ static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data) amc->num_cs = 2; amc->i2c_init = tiogapass_bmc_i2c_init; mc->default_ram_size = 1 * GiB; - mc->default_cpus = mc->min_cpus = mc->max_cpus = - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); }; static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) @@ -1318,8 +1314,7 @@ static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) amc->num_cs = 2; amc->i2c_init = sonorapass_bmc_i2c_init; mc->default_ram_size = 512 * MiB; - mc->default_cpus = mc->min_cpus = mc->max_cpus = - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); }; static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) @@ -1335,8 +1330,7 @@ static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) amc->num_cs = 2; amc->i2c_init = witherspoon_bmc_i2c_init; mc->default_ram_size = 512 * MiB; - mc->default_cpus = mc->min_cpus = mc->max_cpus = - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); }; static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) @@ -1355,8 +1349,7 @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) ASPEED_MAC3_ON; amc->i2c_init = ast2600_evb_i2c_init; mc->default_ram_size = 1 * GiB; - mc->default_cpus = mc->min_cpus = mc->max_cpus = - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); }; static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) @@ -1374,8 +1367,7 @@ static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) amc->macs_mask = ASPEED_MAC2_ON; amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */ mc->default_ram_size = 1 * GiB; - mc->default_cpus = mc->min_cpus = mc->max_cpus = - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); }; static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) @@ -1392,8 +1384,7 @@ static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; amc->i2c_init = g220a_bmc_i2c_init; mc->default_ram_size = 1024 * MiB; - mc->default_cpus = mc->min_cpus = mc->max_cpus = - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); }; static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data) @@ -1410,8 +1401,7 @@ static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data) amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; amc->i2c_init = fp5280g2_bmc_i2c_init; mc->default_ram_size = 512 * MiB; - mc->default_cpus = mc->min_cpus = mc->max_cpus = - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); }; static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data) @@ -1429,8 +1419,7 @@ static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data) amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; amc->i2c_init = rainier_bmc_i2c_init; mc->default_ram_size = 1 * GiB; - mc->default_cpus = mc->min_cpus = mc->max_cpus = - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); }; #define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) @@ -1451,8 +1440,7 @@ static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data) amc->i2c_init = fuji_bmc_i2c_init; amc->uart_default = ASPEED_DEV_UART1; mc->default_ram_size = FUJI_BMC_RAM_SIZE; - mc->default_cpus = mc->min_cpus = mc->max_cpus = - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); }; #define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) @@ -1472,8 +1460,7 @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data) amc->macs_mask = ASPEED_MAC2_ON; amc->i2c_init = bletchley_bmc_i2c_init; mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE; - mc->default_cpus = mc->min_cpus = mc->max_cpus = - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); } static void fby35_reset(MachineState *state, ShutdownCause reason) @@ -1515,6 +1502,7 @@ static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data) amc->i2c_init = fby35_i2c_init; /* FIXME: Replace this macro with something more general */ mc->default_ram_size = FUJI_BMC_RAM_SIZE; + aspeed_machine_class_init_cpus_defaults(mc); // } #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024) @@ -1592,8 +1580,7 @@ static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc, amc->spi_model = "sst25vf032b"; amc->num_cs = 2; amc->macs_mask = 0; - mc->default_cpus = mc->min_cpus = mc->max_cpus = - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); } static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, @@ -1612,8 +1599,7 @@ static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; amc->i2c_init = qcom_dc_scm_bmc_i2c_init; mc->default_ram_size = 1 * GiB; - mc->default_cpus = mc->min_cpus = mc->max_cpus = - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); }; static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc, @@ -1632,8 +1618,7 @@ static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc, amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; amc->i2c_init = qcom_dc_scm_firework_i2c_init; mc->default_ram_size = 1 * GiB; - mc->default_cpus = mc->min_cpus = mc->max_cpus = - aspeed_soc_num_cpus(amc->soc_name); + aspeed_machine_class_init_cpus_defaults(mc); }; static const TypeInfo aspeed_machine_types[] = { From patchwork Tue Jan 23 22:48:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 765215 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:10c4:b0:337:62d3:c6d5 with SMTP id b4csp1840649wrx; Tue, 23 Jan 2024 14:50:26 -0800 (PST) X-Google-Smtp-Source: AGHT+IGfH2O1WLw8+4u8A6p+2xK5NsabmZB4U2ELUeaMR5rg+oamfZtnZ6udXH/pjvdUy4iMEaxk X-Received: by 2002:a05:620a:a0f:b0:783:3496:967a with SMTP id i15-20020a05620a0a0f00b007833496967amr428858qka.43.1706050226717; Tue, 23 Jan 2024 14:50:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706050226; cv=none; d=google.com; s=arc-20160816; b=t0zfPE4Sbr71KCvihZEkcePY3TxAXaF/TOcb8TO2RNmEy04c4Ekv5seta2tugffNiN yf9F6b7KE4uCN1jCF+IfNhNKxbQPX5/Xs0ZCABVbi8bYVuHuWWBuQ7CxgSvXc62gR3Pp KXYxFnvLh+7eJSHxsJ1UQGf7toK0dadN9YxLy2RmzViufw+eGZn2GI4NVRCmg0rMvu1q Sluz7bK5KmCZCvC4/lytBNhNLAxT1d1rMsaYx7ufB+tgpTs672wi7d4SPMhsI9pMScTE BHTFHJxGrnEqF8h/f8uFbp+xE8akA2ZrUAPSAlS9+4cSEGgqtqESL+6qg4Vx8SAuCFEf nrYg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=qbNjV/GRSEnvliPT0ZyleNqMAmiv0RWp/+WjhZ6DISw=; fh=syX9H1Z6jvTUZoUNlfCNxZiWCwEj552WMbtCUDPMiLw=; b=Yl2FdWP365NvQD/hCDYLn5M7PRR3ro75jiv6gomlGfnje+Zdv5+hhRM6tpi4oaAAMH EtQKzzCdX3Jj2IAzyJJfaWU7CbFkdv3oW8mMehJyj9I+MFsDENLfeIbjNGN7bDOEc+Kf licIz15sw7snIgR0Z89YToJPgZFEUpUon7JN0caRALuoy+UKLLI6/CVwb4G+9h7LpS9y BEBilae0YLDFJP/ESzyB21ic0Qp2EulXRvjVunza00sDwnLLyR7NRYTG9w155GIf3KVB K6z0Ry1LWJtf2ENifyW+1gWddrVKXpyMoD7LcwVIcm7GtrU1u+pioYhc6rCZN1qcLZQ4 mBNw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Wpwg7gCs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id pi36-20020a05620a37a400b007835c287b4asi8623418qkn.277.2024.01.23.14.50.26 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Jan 2024 14:50:26 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Wpwg7gCs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rSPZy-00075Z-Hn; Tue, 23 Jan 2024 17:49:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rSPZw-00073h-93 for qemu-devel@nongnu.org; Tue, 23 Jan 2024 17:49:13 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rSPZs-0004NA-1d for qemu-devel@nongnu.org; Tue, 23 Jan 2024 17:49:12 -0500 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-40e800461baso57950015e9.3 for ; Tue, 23 Jan 2024 14:49:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706050146; x=1706654946; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qbNjV/GRSEnvliPT0ZyleNqMAmiv0RWp/+WjhZ6DISw=; b=Wpwg7gCs1cH3Z7ff+0S09PwC9olTubUQFd81UOBYj3NRXI8hH0/bbZzuYXANXOEGZu QRCRYaVRZ8Mm0+ZFU6oCd84n70XgJ2QG5RhqPbamDtJ3daTX60D+giO7o+1mOyqHgVLz VBDOC1WfSWeS03p4154uHU8wYGH9QrWAG3nouyAe159xMvQo7pRMXo+2kXt3aRNbOavJ 9EgSbbFv+MxuA6PAtKWqnV+SjXqMMGHFA8PPB7AXqgjUXkF0hZTOUpBPVcqnDJjs3U5w cvQgKvZkg68ZSQ21lEMpW46GpxDnn5dzaZisV310fXp5nwA2oQleKNa8l9QB03Lm/tW3 A9PA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706050146; x=1706654946; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qbNjV/GRSEnvliPT0ZyleNqMAmiv0RWp/+WjhZ6DISw=; b=rGhyiJts+SYEbgLiVkyYQ2hoY27afTXGaO/sd41Pb7O0vOYrZgBr21HoRMyhwPzpeV /AyYGsDZ+On4UgZA6RV9+fJHZcMMwV0yqIsk/wr5HPNhA5NtFstUH9+EPfo/qP8hItf1 hk0rZbz3iTv2Bm/WEF+h4ZybfnjteN65U6Wk9+mOFAHSQRVMwMMUpLej9TF2hz6ONJ6q zPIhAGL90BjWGoRSEAaUrOfKa8MdXIEBB4JGttRKQ8ZdzGBsxOWIt/nAvPDtavk+qzxr BPaVmD9YE30dDRAN+FN1hCxhVfXl6/ZJ0b6HUmxUf+HCU/VO1fhiqtsW1OqBnmSsDe81 fGyA== X-Gm-Message-State: AOJu0YwJl6uFrlqn1q0yoUtr8thFo3DkN++CZqaIpWELeFPzDDHvWmT2 JjPCtXeEf1UKT4+EY1RE+uCGnPip0t9h8TWYO9dO2ol0LBltP3AUylDr2MkR7T2I2zDAFfP2F3r P X-Received: by 2002:a05:600c:46c5:b0:40e:617e:412f with SMTP id q5-20020a05600c46c500b0040e617e412fmr491321wmo.150.1706050146214; Tue, 23 Jan 2024 14:49:06 -0800 (PST) Received: from m1x-phil.lan ([176.187.194.78]) by smtp.gmail.com with ESMTPSA id h5-20020a05600c314500b0040e5e21cd7bsm43236968wmo.11.2024.01.23.14.49.05 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 23 Jan 2024 14:49:05 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Joel Stanley , Andrew Jeffery , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH v2 4/5] hw/arm/aspeed: Introduce aspeed_soc_cpu_type() helper Date: Tue, 23 Jan 2024 23:48:41 +0100 Message-ID: <20240123224842.18485-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240123224842.18485-1-philmd@linaro.org> References: <20240123224842.18485-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In order to alter AspeedSoCClass::cpu_type in the next commit, introduce the aspeed_soc_cpu_type() helper to retrieve the per-SoC CPU type from AspeedSoCClass. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan --- include/hw/arm/aspeed_soc.h | 1 + hw/arm/aspeed_ast10x0.c | 2 +- hw/arm/aspeed_ast2400.c | 3 ++- hw/arm/aspeed_ast2600.c | 3 ++- hw/arm/aspeed_soc_common.c | 5 +++++ 5 files changed, 11 insertions(+), 3 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index cb832bc1ee..a060a59918 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -143,6 +143,7 @@ struct AspeedSoCClass { qemu_irq (*get_irq)(AspeedSoCState *s, int dev); }; +const char *aspeed_soc_cpu_type(AspeedSoCClass *sc); enum { ASPEED_DEV_SPI_BOOT, diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 8becb146a8..dca601a3f9 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -211,7 +211,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) /* AST1030 CPU Core */ armv7m = DEVICE(&a->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 256); - qdev_prop_set_string(armv7m, "cpu-type", sc->cpu_type); + qdev_prop_set_string(armv7m, "cpu-type", aspeed_soc_cpu_type(sc)); qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk); object_property_set_link(OBJECT(&a->armv7m), "memory", OBJECT(s->memory), &error_abort); diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c index ad76035528..3baf95916d 100644 --- a/hw/arm/aspeed_ast2400.c +++ b/hw/arm/aspeed_ast2400.c @@ -156,7 +156,8 @@ static void aspeed_ast2400_soc_init(Object *obj) } for (i = 0; i < sc->num_cpus; i++) { - object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type); + object_initialize_child(obj, "cpu[*]", &a->cpu[i], + aspeed_soc_cpu_type(sc)); } snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 386a88d4e0..b264433cf0 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -158,7 +158,8 @@ static void aspeed_soc_ast2600_init(Object *obj) } for (i = 0; i < sc->num_cpus; i++) { - object_initialize_child(obj, "cpu[*]", &a->cpu[i], sc->cpu_type); + object_initialize_child(obj, "cpu[*]", &a->cpu[i], + aspeed_soc_cpu_type(sc)); } snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c index 828f61093b..36ca189ce9 100644 --- a/hw/arm/aspeed_soc_common.c +++ b/hw/arm/aspeed_soc_common.c @@ -18,6 +18,11 @@ #include "hw/char/serial.h" +const char *aspeed_soc_cpu_type(AspeedSoCClass *sc) +{ + return sc->cpu_type; +} + qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev) { return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev); From patchwork Tue Jan 23 22:48:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 765214 Delivered-To: patch@linaro.org Received: by 2002:a05:6000:10c4:b0:337:62d3:c6d5 with SMTP id b4csp1840647wrx; Tue, 23 Jan 2024 14:50:26 -0800 (PST) X-Google-Smtp-Source: AGHT+IGtIvkALlWwHBArziKjVQ2E4TG/OJl4rTSlHZyCx4XIlB4ooAZxJnsfikZIPWtOCUiXPDNf X-Received: by 2002:a25:b226:0:b0:dc2:41eb:d8b6 with SMTP id i38-20020a25b226000000b00dc241ebd8b6mr4618888ybj.23.1706050226126; Tue, 23 Jan 2024 14:50:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1706050226; cv=none; d=google.com; s=arc-20160816; b=FoyZjBdisqFgoKNz1p1/J+L7F6X5QO7Sv8+8WNdkxNufwB4k8fCusmiyuctE8O/E+6 Xfxr3LDwqg0sl6y9FTob6y2EyhWV+TS+fmnnvi2pJfctzIRYPb+YmMecFoJqGQ1Ae0Yu AYbJnALdd2VVOk58UGhgydMP1jOFe6PQXezafGT5bq/3AMx3dSKhBpg7dIDdJDfMpBVu pl5/qljiwzAY8nRn0lXnD+SYudwdaZAzvlvUaPpyzLAYNFN4Z8rqShqmjFOD1hze2nPP HsgnVoTFazKT1z6YPt0G4mnJytW/Ccvl/5wa10UJE7AWc/vXuXRLF25BotnxbXx0Fufy jJ0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=GVA2TB5jlLxfwdfpPKM9Ir1x2nVtKMiRhoeFlp+qdMA=; fh=syX9H1Z6jvTUZoUNlfCNxZiWCwEj552WMbtCUDPMiLw=; b=m8GktaYJRc2lqGRFKizACFjQJVI4Ti5MSSjFTDbpt7KTHkv2KOZuzkSGEG3GhaPexZ suRuZD1e4KpFPb/SwW0qAbYG0IdPMrZtJHHpfObQ2S+SnXXhOqfOJw5mDsxsZginuKpf H61mkKiCQ9SUiz0xEaDlx6N+v40+2N90AoZhseJDZ1eWZZaaVlPESqv64TiM5FLRMQS4 JYQ8qWWDHnUvCtL2iIJsSDXCOLbHJkkDHM5l+XdmKhtDjg2j3Fh6kkSrgyqtgUmZhkEx /J0I66a8N4CmaF7C71+v7GLnvoP0C96N8COYbNKf8i68Bz+0GZKIJNZpUKg/NqGWO87A Z+ow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="p/CCwyen"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a23-20020a0ca997000000b006817d315653si9211994qvb.160.2024.01.23.14.50.25 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 23 Jan 2024 14:50:26 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="p/CCwyen"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rSPa0-00076R-BT; Tue, 23 Jan 2024 17:49:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rSPZz-00075u-0u for qemu-devel@nongnu.org; Tue, 23 Jan 2024 17:49:15 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rSPZw-0004NV-Uv for qemu-devel@nongnu.org; Tue, 23 Jan 2024 17:49:14 -0500 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-40e7065b692so52804615e9.3 for ; Tue, 23 Jan 2024 14:49:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1706050151; x=1706654951; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GVA2TB5jlLxfwdfpPKM9Ir1x2nVtKMiRhoeFlp+qdMA=; b=p/CCwyenYnj4u7HsD86X/w8RptMN69gzHA+23yrUfVMH3Cj+xcJjbTK9DzbJjEK0Cq zhyzAmGhRNoHSuho7664bkH2MVwpx+TUaEhAXz2TmYPaPCZi0XELlu1gHIPf3XBZXpmE W3ridjtMeK8LURQ832K9HgpmtKexMHGJDjtB77OVgrgTXhjRBVcGW5qeomuXrc0d0TEp Zs/NYXV0pnqXUjSuaOTtatpXxI1vppVywNJe1Ccq0S0Ailkf011gJmmfQLUfOP6i4j4W AIW7XKcyUg3G3sj5PLOQIhZp0Jpj5XZoVCUR9+hzjZ2qdK7+swJDnhQU9eM+zYbbyt1h 9M1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706050151; x=1706654951; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GVA2TB5jlLxfwdfpPKM9Ir1x2nVtKMiRhoeFlp+qdMA=; b=JG0pZx3l/Zqhrr9K/AL8H6RyERApkq+EMtLQeBWcDdlHkB1jxTyJUSz8ce7sAl1yWE 4aNrf+oCfFcjfb/lGGeRf3ktpvchB/+2KIhlfbIQ6zbQbEpzLN3fVuHlPadrlLlcQe82 S0pe/ez1abcQtaFCOeR7eN5//vWhXHoXkzBInYb5tx6pAn+Hgvt3/6XIIo23M17/tZr0 eSP9gsNiMqUKynzQQ/jBOU5QQ4hQfgdg0DhEMaPtgqhavx7EbPTjdS0HITZpD043MaJv hs9aexmapUaW5ifbhiZic3Hw2QIjJfi1FGcyuKlanqCMg8YYZXdU5qMWzcJrfZ9Yvbmq Xu8Q== X-Gm-Message-State: AOJu0YyFeoueB6qGpm0n9Tbfju4tmYN0STSEjgtjL2VGtYfpxOgVc1WH ekPVRL6Ew96cZuZC+EnlLAo3vhFjikGxYr7RTr1gezZbrbyc/2sHb1EjhTWp38FfBVsP6sXpk3T V X-Received: by 2002:a05:600c:4750:b0:40e:bfbf:f332 with SMTP id w16-20020a05600c475000b0040ebfbff332mr540385wmo.27.1706050151410; Tue, 23 Jan 2024 14:49:11 -0800 (PST) Received: from m1x-phil.lan ([176.187.194.78]) by smtp.gmail.com with ESMTPSA id g14-20020a05600c4ece00b0040ebf340759sm3043862wmq.21.2024.01.23.14.49.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 23 Jan 2024 14:49:11 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-arm@nongnu.org, Joel Stanley , Andrew Jeffery , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PATCH v2 5/5] hw/arm/aspeed: Check for CPU types in machine_run_board_init() Date: Tue, 23 Jan 2024 23:48:42 +0100 Message-ID: <20240123224842.18485-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240123224842.18485-1-philmd@linaro.org> References: <20240123224842.18485-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Aspeed SoCs use a single CPU type (set as AspeedSoCClass::cpu_type). Convert it to a NULL-terminated array (of a single non-NULL element). Set MachineClass::valid_cpu_types[] to use the common machine code to provide hints when the requested CPU is invalid (see commit e702cbc19e ("machine: Improve is_cpu_type_supported()"). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Reviewed-by: Richard Henderson Reviewed-by: Gavin Shan --- include/hw/arm/aspeed_soc.h | 3 ++- hw/arm/aspeed.c | 1 + hw/arm/aspeed_ast10x0.c | 6 +++++- hw/arm/aspeed_ast2400.c | 12 ++++++++++-- hw/arm/aspeed_ast2600.c | 6 +++++- hw/arm/aspeed_soc_common.c | 5 ++++- 6 files changed, 27 insertions(+), 6 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index a060a59918..0db5a41e71 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -128,7 +128,8 @@ struct AspeedSoCClass { DeviceClass parent_class; const char *name; - const char *cpu_type; + /** valid_cpu_types: NULL terminated array of a single CPU type. */ + const char * const *valid_cpu_types; uint32_t silicon_rev; uint64_t sram_size; uint64_t secsram_size; diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 636a6269aa..1be3b6bcae 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -1149,6 +1149,7 @@ static void aspeed_machine_class_init_cpus_defaults(MachineClass *mc) mc->default_cpus = mc->min_cpus = mc->max_cpus = sc->num_cpus; + mc->valid_cpu_types = sc->valid_cpu_types; } static void aspeed_machine_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index dca601a3f9..c3b5116a6a 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -417,13 +417,17 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data) { + static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */ + NULL + }; DeviceClass *dc = DEVICE_CLASS(klass); AspeedSoCClass *sc = ASPEED_SOC_CLASS(dc); dc->realize = aspeed_soc_ast1030_realize; sc->name = "ast1030-a1"; - sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4"); /* TODO cortex-m4f */ + sc->valid_cpu_types = valid_cpu_types; sc->silicon_rev = AST1030_A1_SILICON_REV; sc->sram_size = 0xc0000; sc->secsram_size = 0x40000; /* 256 * KiB */ diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c index 3baf95916d..8829561bb6 100644 --- a/hw/arm/aspeed_ast2400.c +++ b/hw/arm/aspeed_ast2400.c @@ -503,6 +503,10 @@ static void aspeed_ast2400_soc_realize(DeviceState *dev, Error **errp) static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("arm926"), + NULL + }; AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); DeviceClass *dc = DEVICE_CLASS(oc); @@ -511,7 +515,7 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) dc->user_creatable = false; sc->name = "ast2400-a1"; - sc->cpu_type = ARM_CPU_TYPE_NAME("arm926"); + sc->valid_cpu_types = valid_cpu_types; sc->silicon_rev = AST2400_A1_SILICON_REV; sc->sram_size = 0x8000; sc->spis_num = 1; @@ -527,6 +531,10 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data) static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("arm1176"), + NULL + }; AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); DeviceClass *dc = DEVICE_CLASS(oc); @@ -535,7 +543,7 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data) dc->user_creatable = false; sc->name = "ast2500-a1"; - sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176"); + sc->valid_cpu_types = valid_cpu_types; sc->silicon_rev = AST2500_A1_SILICON_REV; sc->sram_size = 0x9000; sc->spis_num = 2; diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index b264433cf0..46baba0e41 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -629,13 +629,17 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) { + static const char * const valid_cpu_types[] = { + ARM_CPU_TYPE_NAME("cortex-a7"), + NULL + }; DeviceClass *dc = DEVICE_CLASS(oc); AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); dc->realize = aspeed_soc_ast2600_realize; sc->name = "ast2600-a3"; - sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); + sc->valid_cpu_types = valid_cpu_types; sc->silicon_rev = AST2600_A3_SILICON_REV; sc->sram_size = 0x16400; sc->spis_num = 2; diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c index 36ca189ce9..123a0c432c 100644 --- a/hw/arm/aspeed_soc_common.c +++ b/hw/arm/aspeed_soc_common.c @@ -20,7 +20,10 @@ const char *aspeed_soc_cpu_type(AspeedSoCClass *sc) { - return sc->cpu_type; + assert(sc->valid_cpu_types); + assert(sc->valid_cpu_types[0]); + assert(!sc->valid_cpu_types[1]); + return sc->valid_cpu_types[0]; } qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)