From patchwork Tue Sep 10 05:52:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "\(Exiting\) Baolin Wang" X-Patchwork-Id: 173436 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp5351924ilq; Mon, 9 Sep 2019 22:53:04 -0700 (PDT) X-Google-Smtp-Source: APXvYqxXOgp/Rir23CjzREbEI+tcTwvUA6sBqOrqE+rEryCgwQUvtYkZNXJBit2ll+m5zVRnuvwi X-Received: by 2002:a50:c90c:: with SMTP id o12mr12259627edh.126.1568094784571; Mon, 09 Sep 2019 22:53:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1568094784; cv=none; d=google.com; s=arc-20160816; b=YyppIUMfrvehWcvnEiWbP60h2NTNZZw7jFUfNfS/FSOhv9OKbpVRFQ6h8D22sqWkTA 1xcBvMlzBihwCQJu5Iiy0OI+EWiGVfk3WA6dkA9dKgpm+vlTSCxEkyUM2ADCSZApwrin +xLoehe2gFUjESC22UKWh0w4rc667igfeTshklmzoEAjQL3igaL0/zq+DvSvtlZcjg2f 7r4X0c3iF/7GOQqqyrc1fSBOZFCp5V5Crq/wWdVXb6YnKYW5yBxKVnuq7HH8IFG1LPr0 ELEE6yDJPOzQWMpbSUO7z4PCqXZCk1B50MieKRrcnIk13yulBD409iHNAwx0zsIEyun8 WkvA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature; bh=QRoaigyAjs5h91B30G11QGcUasyv51Jz7B4F6B0hdm0=; b=wCyvOfxw41VFGUUmTQgM8Sa6XoCw0pikjJiGHRcQtP1C3n4NuCngvTn+19w4WFet5p k8hDae4D4QwiEspEtgUpEnzxuH1gJNWl6z87Eui83suDSvN5agI+oPYQt3pLPzWWILr6 fm0Er9t2qFH5A2SzHDuI8b4oaFuDsOAXDdTzDBmQaYa+yUbY5yqGiMfxcA8L5lOezeUa D/mH5QqW1yFsJsvOXvFR+Gt6dTnOf6/WaTZqXtrROkiNe0e8Phn7jLPfWU7rtIjUSp+q nZea4CfRD1kQTCD/QEYVh9yTTVKOuGeG0MAxwet5bEBmLjU+g6WNjQguez9QpOVykLvD f6Lg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SglGk7Cu; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id dx9si8282571ejb.242.2019.09.09.22.53.03; Mon, 09 Sep 2019 22:53:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SglGk7Cu; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390578AbfIJFw6 (ORCPT + 8 others); Tue, 10 Sep 2019 01:52:58 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:42316 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390488AbfIJFw6 (ORCPT ); Tue, 10 Sep 2019 01:52:58 -0400 Received: by mail-pg1-f195.google.com with SMTP id p3so9197598pgb.9 for ; Mon, 09 Sep 2019 22:52:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=QRoaigyAjs5h91B30G11QGcUasyv51Jz7B4F6B0hdm0=; b=SglGk7CuPhqxEI7xwpMa5d33F8KaDAKlwc8PlUqMt1NE+kj0qQaUz9UVK8/XFqmQDO pGBlSLD1YnX4ys1+tmh5OV7Q1/9Q08CnrEslUDRRa+tvs5iY1RxwM94K7xHsGSND91XL SzouiZjOpvzeE01FhCZq6QrIcnztIDEHk8oVpv1+d4iHik7HTtP6uhsGYX1M3d/xNAux 5X6hAk7Da9dTdS7hjERqpmmPZlCX0JQDCBa/xxaPG8na5/hyfHA4OOrPRrHJ5LgvsReN xocpsC8qUHiAEOMYRKACMSFEFlbody6Af8PjPFLU2yhuhqTeEFTz+tyJEdnqXAE3Y9x3 nwmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=QRoaigyAjs5h91B30G11QGcUasyv51Jz7B4F6B0hdm0=; b=QPJDdHFuE5yW3rmnzHDnZpypt/vkrtvSJOQvRuBlZToHiSzev+qaT/cJ9z2vywPu2U xj0uvjn837LyRSB8ELo5r64fJ+9haKzMCfNiycDCIeQvD+JWhqpsKvO5Q3RJw90wFjD4 DAhI9B+41gwCA4RlZrJVJln7WQQpmz3BQsqHUeyQxio++7wuEOncYnxKNcHkS9DMfwTV f0nQVolLnxYVz+yAT9DQx9Rxg5pOvTVVcwXdgE5BVyEcEmdi7+f1lD9gQR1PX9OQZZkk 6sHnaH+Ng0noq2J1GTrL4HmBYD+0+cz5cIcgNjl0hptSiX9JdB+Cnaw97wh9X+ixL+Qe ZGVQ== X-Gm-Message-State: APjAAAU5ynxRx8Xc3OQ0ZmgduG5tFnrHPtHm89nRywHu/9JYj8z2PTpr ByzXA9Of6ohdL8ku3NmgXp1jnGTnvuXL/w== X-Received: by 2002:a63:2a87:: with SMTP id q129mr26549610pgq.101.1568094777634; Mon, 09 Sep 2019 22:52:57 -0700 (PDT) Received: from baolinwangubtpc.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id w69sm22264550pgd.91.2019.09.09.22.52.53 (version=TLS1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 09 Sep 2019 22:52:56 -0700 (PDT) From: Baolin Wang To: srinivas.kandagatla@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com Cc: orsonzhai@gmail.com, zhang.lyra@gmail.com, baolin.wang@linaro.org, freeman.liu@unisoc.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/2] dt-bindings: nvmem: Add Spreadtrum eFuse controller documentation Date: Tue, 10 Sep 2019 13:52:22 +0800 Message-Id: <20f750aab0e16e45fa2d4e32843cee08395c7350.1568094534.git.baolin.wang@linaro.org> X-Mailer: git-send-email 1.7.9.5 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Freeman Liu This patch adds the binding documentation for Spreadtrum eFuse controller. Signed-off-by: Freeman Liu Signed-off-by: Baolin Wang Reviewed-by: Rob Herring --- Changes from v1: - Add reviewed tag from Rob. --- .../devicetree/bindings/nvmem/sprd-efuse.txt | 39 ++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/nvmem/sprd-efuse.txt -- 1.7.9.5 diff --git a/Documentation/devicetree/bindings/nvmem/sprd-efuse.txt b/Documentation/devicetree/bindings/nvmem/sprd-efuse.txt new file mode 100644 index 0000000..96b6fee --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/sprd-efuse.txt @@ -0,0 +1,39 @@ += Spreadtrum eFuse device tree bindings = + +Required properties: +- compatible: Should be "sprd,ums312-efuse". +- reg: Specify the address offset of efuse controller. +- clock-names: Should be "enable". +- clocks: The phandle and specifier referencing the controller's clock. +- hwlocks: Reference to a phandle of a hwlock provider node. + += Data cells = +Are child nodes of eFuse, bindings of which as described in +bindings/nvmem/nvmem.txt + +Example: + + ap_efuse: efuse@32240000 { + compatible = "sprd,ums312-efuse"; + reg = <0 0x32240000 0 0x10000>; + clock-names = "enable"; + hwlocks = <&hwlock 8>; + clocks = <&aonapb_gate CLK_EFUSE_EB>; + + /* Data cells */ + thermal_calib: calib@10 { + reg = <0x10 0x2>; + }; + }; + += Data consumers = +Are device nodes which consume nvmem data cells. + +Example: + + thermal { + ... + + nvmem-cells = <&thermal_calib>; + nvmem-cell-names = "calibration"; + }; From patchwork Tue Sep 10 05:52:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "\(Exiting\) Baolin Wang" X-Patchwork-Id: 173437 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp5351939ilq; Mon, 9 Sep 2019 22:53:05 -0700 (PDT) X-Google-Smtp-Source: APXvYqyFbMAdyTX7VAMxw47Wp/n8cMUDpRaRR9vxX5t064/sPIc5jhJY34BaKcRPfoTDEnSPUwbY X-Received: by 2002:aa7:d5cb:: with SMTP id d11mr28747252eds.250.1568094785589; Mon, 09 Sep 2019 22:53:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1568094785; cv=none; d=google.com; s=arc-20160816; b=zog7POicvEux2f/Jkfo7UkgOmCpC5I1FiAyXxDQ83sJWPmsTmjFnvCcCy+19+jaidO omE3E3/wJjnoLJsGtDpCVro9McuRBwy/l/QD8dIBuDA5l/Pb23zeFjtLedXKOJAjVqrH OT0dXI5MQ8kgz18m7jpBvemZUaP7PbHdzdL8uJ0et/YiACicvFX0kKiycuxXf0zUMhwU ySaYeGIw/YEi4iUSe0kyQUuS5j2bN0eMS1BPHfx20WtSGgTisX86LXGtiEC4kxVUDeU5 TB3dIwOFSsWM4Nv65tvkpEXymK3cElUhh4vejmQUhi4GUR97mVopCgoQDEdwl7aNxsPZ nrqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=06CRS9LiJsgk7StiCyCHTyFH1WSybZ5bcZDFHj0Xl2w=; b=dIn3f55VWnTkYJ/G5PEkU2QYzr6WNTc5feJK+nMyGlvYTiLBTomzyJSaon2AeS3h8K 11pdJnRb6h1c5uZQjrD1/DuMf/jcXjj+OiUqtnSaP8hcM9zU3ET8YCzpzdrMRQl/agaV pyHuf+PHXW+V7Y9e7fEMUnMVkvfAT6r+jF7D0vUQtkSYkyphTswFfOXJmyCjQMJa5vd+ 5KyWY18aOo0GqPxvITH1VAb0b9K35QinqwfIP+OS2S7aRAQ9WDRXCfRIBj43aR7eYOin Bp7j2LfCMhUUwo+uDLqQ/7QWMH0xw4Nm01IQfQt47vhd4bb7L+Vs6+zkdEvAGz9aMDhJ ae3A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NhQBG7vU; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id dx9si8282571ejb.242.2019.09.09.22.53.05; Mon, 09 Sep 2019 22:53:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NhQBG7vU; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404426AbfIJFxC (ORCPT + 8 others); Tue, 10 Sep 2019 01:53:02 -0400 Received: from mail-pg1-f194.google.com ([209.85.215.194]:41589 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2404419AbfIJFxC (ORCPT ); Tue, 10 Sep 2019 01:53:02 -0400 Received: by mail-pg1-f194.google.com with SMTP id x15so9198843pgg.8 for ; Mon, 09 Sep 2019 22:53:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=06CRS9LiJsgk7StiCyCHTyFH1WSybZ5bcZDFHj0Xl2w=; b=NhQBG7vUB5ii5skCjnAiuW8usXMgYqHexu87UwxOJRKD0gpIMZ7uu9lttTX6U5qiqL QAPjpa4+XZrpiA6GXqJdnTxt5y5M8Ccw8Z5htbaq4a76Pl0wGqeshOcbV8t3pvRdEXGV OTtpnCuTJQx0y0QHKqo5EomUsMGlCblW5Q78KG7quuK+fW/woe57k8VTGfV+p11LCTm0 s6Q+bUEBy2XWvr3cmlTuncEmLlxmvpXaepe9td3h85f/F/FbO7MdW1KDoel1kbB4QSmt 8ZMGRdP8tKxzIUCyXdqXLHx+yymsu0nI4l1iWXqf6taQBKAs8mc2IuBhwo2upbWFDTdf g6CA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=06CRS9LiJsgk7StiCyCHTyFH1WSybZ5bcZDFHj0Xl2w=; b=NKD7ltjmSnkBpN6TmZmt3AC0MboSZmDEd5vxxzpyFcv0jVe134NXF2kuHWtVN0+xl3 mbrpYefqPwk5hrRL51PXwYoBaFeNNX+SDO0EwXENi0XlogFfKuqMxyNueC3qXKUx1jLy VmLaSvvSyO8sOZ3zWyHPL/eih12oW0fNSUB8tBoh1chXE+1irfDAwi09nh6Zn36bFEK5 hG1AN21Rd3bhFL+LTCzQgbnXpeFJN9mVwZrq+jR6sC9aZ99Opcqq9aW5giwIOKtBqJUf k4V9N+rgTHNIa5UQ6MoaH2drn//4YRG97daIYClEAQdUK1pJuGqEb5yDMq+/+WvFXWlU OwKw== X-Gm-Message-State: APjAAAV11foQfxexaiO8mdbBpSGs3xIPhcoZ92VXwhnACSttfdIcolWc DrFlVFmfKncwHKduMI13VCI/+Q== X-Received: by 2002:a63:125c:: with SMTP id 28mr25892785pgs.255.1568094781609; Mon, 09 Sep 2019 22:53:01 -0700 (PDT) Received: from baolinwangubtpc.spreadtrum.com ([117.18.48.82]) by smtp.gmail.com with ESMTPSA id w69sm22264550pgd.91.2019.09.09.22.52.57 (version=TLS1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 09 Sep 2019 22:53:00 -0700 (PDT) From: Baolin Wang To: srinivas.kandagatla@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com Cc: orsonzhai@gmail.com, zhang.lyra@gmail.com, baolin.wang@linaro.org, freeman.liu@unisoc.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/2] nvmem: sprd: Add Spreadtrum SoCs eFuse support Date: Tue, 10 Sep 2019 13:52:23 +0800 Message-Id: <1fe5cd4b656bb25d4f22bc54a83bb5326f2ecb06.1568094534.git.baolin.wang@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <20f750aab0e16e45fa2d4e32843cee08395c7350.1568094534.git.baolin.wang@linaro.org> References: <20f750aab0e16e45fa2d4e32843cee08395c7350.1568094534.git.baolin.wang@linaro.org> In-Reply-To: <20f750aab0e16e45fa2d4e32843cee08395c7350.1568094534.git.baolin.wang@linaro.org> References: <20f750aab0e16e45fa2d4e32843cee08395c7350.1568094534.git.baolin.wang@linaro.org> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Freeman Liu The Spreadtrum eFuse controller is widely used to dump chip ID, configuration setting, function select and so on, as well as supporting one-time programming. Signed-off-by: Freeman Liu Signed-off-by: Baolin Wang --- Changes from v1: - None --- drivers/nvmem/Kconfig | 11 ++ drivers/nvmem/Makefile | 2 + drivers/nvmem/sprd-efuse.c | 424 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 437 insertions(+) create mode 100644 drivers/nvmem/sprd-efuse.c -- 1.7.9.5 diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig index c2ec750..8fd425d 100644 --- a/drivers/nvmem/Kconfig +++ b/drivers/nvmem/Kconfig @@ -230,4 +230,15 @@ config NVMEM_ZYNQMP If sure, say yes. If unsure, say no. +config SPRD_EFUSE + tristate "Spreadtrum SoC eFuse Support" + depends on ARCH_SPRD || COMPILE_TEST + depends on HAS_IOMEM + help + This is a simple driver to dump specified values of Spreadtrum + SoCs from eFuse. + + This driver can also be built as a module. If so, the module + will be called nvmem-sprd-efuse. + endif diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile index e5c153d..7c19870 100644 --- a/drivers/nvmem/Makefile +++ b/drivers/nvmem/Makefile @@ -50,3 +50,5 @@ obj-$(CONFIG_SC27XX_EFUSE) += nvmem-sc27xx-efuse.o nvmem-sc27xx-efuse-y := sc27xx-efuse.o obj-$(CONFIG_NVMEM_ZYNQMP) += nvmem_zynqmp_nvmem.o nvmem_zynqmp_nvmem-y := zynqmp_nvmem.o +obj-$(CONFIG_SPRD_EFUSE) += nvmem_sprd_efuse.o +nvmem_sprd_efuse-y := sprd-efuse.o diff --git a/drivers/nvmem/sprd-efuse.c b/drivers/nvmem/sprd-efuse.c new file mode 100644 index 0000000..2f1e0fb --- /dev/null +++ b/drivers/nvmem/sprd-efuse.c @@ -0,0 +1,424 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2019 Spreadtrum Communications Inc. + +#include +#include +#include +#include +#include +#include +#include +#include + +#define SPRD_EFUSE_ENABLE 0x20 +#define SPRD_EFUSE_ERR_FLAG 0x24 +#define SPRD_EFUSE_ERR_CLR 0x28 +#define SPRD_EFUSE_MAGIC_NUM 0x2c +#define SPRD_EFUSE_FW_CFG 0x50 +#define SPRD_EFUSE_PW_SWT 0x54 +#define SPRD_EFUSE_MEM(val) (0x1000 + ((val) << 2)) + +#define SPRD_EFUSE_VDD_EN BIT(0) +#define SPRD_EFUSE_AUTO_CHECK_EN BIT(1) +#define SPRD_EFUSE_DOUBLE_EN BIT(2) +#define SPRD_EFUSE_MARGIN_RD_EN BIT(3) +#define SPRD_EFUSE_LOCK_WR_EN BIT(4) + +#define SPRD_EFUSE_ERR_CLR_MASK GENMASK(13, 0) + +#define SPRD_EFUSE_ENK1_ON BIT(0) +#define SPRD_EFUSE_ENK2_ON BIT(1) +#define SPRD_EFUSE_PROG_EN BIT(2) + +#define SPRD_EFUSE_MAGIC_NUMBER 0x8810 + +/* Block width (bytes) definitions */ +#define SPRD_EFUSE_BLOCK_WIDTH 4 + +/* + * The Spreadtrum AP efuse contains 2 parts: normal efuse and secure efuse, + * and we can only access the normal efuse in kernel. So define the normal + * block offset index and normal block numbers. + */ +#define SPRD_EFUSE_NORMAL_BLOCK_NUMS 24 +#define SPRD_EFUSE_NORMAL_BLOCK_OFFSET 72 + +/* Timeout (ms) for the trylock of hardware spinlocks */ +#define SPRD_EFUSE_HWLOCK_TIMEOUT 5000 + +/* + * Since different Spreadtrum SoC chip can have different normal block numbers + * and offset. And some SoC can support block double feature, which means + * when reading or writing data to efuse memory, the controller can save double + * data in case one data become incorrect after a long period. + * + * Thus we should save them in the device data structure. + */ +struct sprd_efuse_variant_data { + u32 blk_nums; + u32 blk_offset; + bool blk_double; +}; + +struct sprd_efuse { + struct device *dev; + struct clk *clk; + struct hwspinlock *hwlock; + struct mutex mutex; + void __iomem *base; + const struct sprd_efuse_variant_data *data; +}; + +static const struct sprd_efuse_variant_data ums312_data = { + .blk_nums = SPRD_EFUSE_NORMAL_BLOCK_NUMS, + .blk_offset = SPRD_EFUSE_NORMAL_BLOCK_OFFSET, + .blk_double = false, +}; + +/* + * On Spreadtrum platform, we have multi-subsystems will access the unique + * efuse controller, so we need one hardware spinlock to synchronize between + * the multiple subsystems. + */ +static int sprd_efuse_lock(struct sprd_efuse *efuse) +{ + int ret; + + mutex_lock(&efuse->mutex); + + ret = hwspin_lock_timeout_raw(efuse->hwlock, + SPRD_EFUSE_HWLOCK_TIMEOUT); + if (ret) { + dev_err(efuse->dev, "timeout get the hwspinlock\n"); + mutex_unlock(&efuse->mutex); + return ret; + } + + return 0; +} + +static void sprd_efuse_unlock(struct sprd_efuse *efuse) +{ + hwspin_unlock_raw(efuse->hwlock); + mutex_unlock(&efuse->mutex); +} + +static void sprd_efuse_set_prog_power(struct sprd_efuse *efuse, bool en) +{ + u32 val = readl(efuse->base + SPRD_EFUSE_PW_SWT); + + if (en) + val &= ~SPRD_EFUSE_ENK2_ON; + else + val &= ~SPRD_EFUSE_ENK1_ON; + + writel(val, efuse->base + SPRD_EFUSE_PW_SWT); + + /* Open or close efuse power need wait 1000us to make power stable. */ + usleep_range(1000, 1200); + + if (en) + val |= SPRD_EFUSE_ENK1_ON; + else + val |= SPRD_EFUSE_ENK2_ON; + + writel(val, efuse->base + SPRD_EFUSE_PW_SWT); + + /* Open or close efuse power need wait 1000us to make power stable. */ + usleep_range(1000, 1200); +} + +static void sprd_efuse_set_read_power(struct sprd_efuse *efuse, bool en) +{ + u32 val = readl(efuse->base + SPRD_EFUSE_ENABLE); + + if (en) + val |= SPRD_EFUSE_VDD_EN; + else + val &= ~SPRD_EFUSE_VDD_EN; + + writel(val, efuse->base + SPRD_EFUSE_ENABLE); + + /* Open or close efuse power need wait 1000us to make power stable. */ + usleep_range(1000, 1200); +} + +static void sprd_efuse_set_prog_lock(struct sprd_efuse *efuse, bool en) +{ + u32 val = readl(efuse->base + SPRD_EFUSE_ENABLE); + + if (en) + val |= SPRD_EFUSE_LOCK_WR_EN; + else + val &= ~SPRD_EFUSE_LOCK_WR_EN; + + writel(val, efuse->base + SPRD_EFUSE_ENABLE); +} + +static void sprd_efuse_set_auto_check(struct sprd_efuse *efuse, bool en) +{ + u32 val = readl(efuse->base + SPRD_EFUSE_ENABLE); + + if (en) + val |= SPRD_EFUSE_AUTO_CHECK_EN; + else + val &= ~SPRD_EFUSE_AUTO_CHECK_EN; + + writel(val, efuse->base + SPRD_EFUSE_ENABLE); +} + +static void sprd_efuse_set_data_double(struct sprd_efuse *efuse, bool en) +{ + u32 val = readl(efuse->base + SPRD_EFUSE_ENABLE); + + if (en) + val |= SPRD_EFUSE_DOUBLE_EN; + else + val &= ~SPRD_EFUSE_DOUBLE_EN; + + writel(val, efuse->base + SPRD_EFUSE_ENABLE); +} + +static void sprd_efuse_set_prog_en(struct sprd_efuse *efuse, bool en) +{ + u32 val = readl(efuse->base + SPRD_EFUSE_PW_SWT); + + if (en) + val |= SPRD_EFUSE_PROG_EN; + else + val &= ~SPRD_EFUSE_PROG_EN; + + writel(val, efuse->base + SPRD_EFUSE_PW_SWT); +} + +static int sprd_efuse_raw_prog(struct sprd_efuse *efuse, u32 blk, bool doub, + bool lock, u32 *data) +{ + u32 status; + int ret = 0; + + /* + * We need set the correct magic number before writing the efuse to + * allow programming, and block other programming until we clear the + * magic number. + */ + writel(SPRD_EFUSE_MAGIC_NUMBER, + efuse->base + SPRD_EFUSE_MAGIC_NUM); + + /* + * Power on the efuse, enable programme and enable double data + * if asked. + */ + sprd_efuse_set_prog_power(efuse, true); + sprd_efuse_set_prog_en(efuse, true); + sprd_efuse_set_data_double(efuse, doub); + + /* + * Enable the auto-check function to validate if the programming is + * successful. + */ + sprd_efuse_set_auto_check(efuse, true); + + writel(*data, efuse->base + SPRD_EFUSE_MEM(blk)); + + /* Disable auto-check and data double after programming */ + sprd_efuse_set_auto_check(efuse, false); + sprd_efuse_set_data_double(efuse, false); + + /* + * Check the efuse error status, if the programming is successful, + * we should lock this efuse block to avoid programming again. + */ + status = readl(efuse->base + SPRD_EFUSE_ERR_FLAG); + if (status) { + dev_err(efuse->dev, + "write error status %d of block %d\n", ret, blk); + + writel(SPRD_EFUSE_ERR_CLR_MASK, + efuse->base + SPRD_EFUSE_ERR_CLR); + ret = -EBUSY; + } else { + sprd_efuse_set_prog_lock(efuse, lock); + writel(*data, efuse->base + SPRD_EFUSE_MEM(blk)); + sprd_efuse_set_prog_lock(efuse, false); + } + + sprd_efuse_set_prog_power(efuse, false); + writel(0, efuse->base + SPRD_EFUSE_MAGIC_NUM); + + return ret; +} + +static int sprd_efuse_raw_read(struct sprd_efuse *efuse, int blk, u32 *val, + bool doub) +{ + u32 status; + + /* + * Need power on the efuse before reading data from efuse, and will + * power off the efuse after reading process. + */ + sprd_efuse_set_read_power(efuse, true); + + /* Enable double data if asked */ + sprd_efuse_set_data_double(efuse, doub); + + /* Start to read data from efuse block */ + *val = readl(efuse->base + SPRD_EFUSE_MEM(blk)); + + /* Disable double data */ + sprd_efuse_set_data_double(efuse, false); + + /* Power off the efuse */ + sprd_efuse_set_read_power(efuse, false); + + /* + * Check the efuse error status and clear them if there are some + * errors occurred. + */ + status = readl(efuse->base + SPRD_EFUSE_ERR_FLAG); + if (status) { + dev_err(efuse->dev, + "read error status %d of block %d\n", status, blk); + + writel(SPRD_EFUSE_ERR_CLR_MASK, + efuse->base + SPRD_EFUSE_ERR_CLR); + return -EBUSY; + } + + return 0; +} + +static int sprd_efuse_read(void *context, u32 offset, void *val, size_t bytes) +{ + struct sprd_efuse *efuse = context; + bool blk_double = efuse->data->blk_double; + u32 index = offset / SPRD_EFUSE_BLOCK_WIDTH + efuse->data->blk_offset; + u32 blk_offset = (offset % SPRD_EFUSE_BLOCK_WIDTH) * BITS_PER_BYTE; + u32 data; + int ret; + + ret = sprd_efuse_lock(efuse); + if (ret) + return ret; + + ret = clk_prepare_enable(efuse->clk); + if (ret) + goto unlock; + + ret = sprd_efuse_raw_read(efuse, index, &data, blk_double); + if (!ret) { + data >>= blk_offset; + memcpy(val, &data, bytes); + } + + clk_disable_unprepare(efuse->clk); + +unlock: + sprd_efuse_unlock(efuse); + return ret; +} + +static int sprd_efuse_write(void *context, u32 offset, void *val, size_t bytes) +{ + struct sprd_efuse *efuse = context; + int ret; + + ret = sprd_efuse_lock(efuse); + if (ret) + return ret; + + ret = clk_prepare_enable(efuse->clk); + if (ret) + goto unlock; + + ret = sprd_efuse_raw_prog(efuse, offset, false, false, val); + + clk_disable_unprepare(efuse->clk); + +unlock: + sprd_efuse_unlock(efuse); + return ret; +} + +static int sprd_efuse_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct nvmem_device *nvmem; + struct nvmem_config econfig = { }; + struct sprd_efuse *efuse; + const struct sprd_efuse_variant_data *pdata; + int ret; + + pdata = of_device_get_match_data(&pdev->dev); + if (!pdata) { + dev_err(&pdev->dev, "No matching driver data found\n"); + return -EINVAL; + } + + efuse = devm_kzalloc(&pdev->dev, sizeof(*efuse), GFP_KERNEL); + if (!efuse) + return -ENOMEM; + + efuse->base = devm_platform_ioremap_resource(pdev, 0); + if (!efuse->base) + return -ENOMEM; + + ret = of_hwspin_lock_get_id(np, 0); + if (ret < 0) { + dev_err(&pdev->dev, "failed to get hwlock id\n"); + return ret; + } + + efuse->hwlock = devm_hwspin_lock_request_specific(&pdev->dev, ret); + if (!efuse->hwlock) { + dev_err(&pdev->dev, "failed to request hwlock\n"); + return -ENXIO; + } + + efuse->clk = devm_clk_get(&pdev->dev, "enable"); + if (IS_ERR(efuse->clk)) { + dev_err(&pdev->dev, "failed to get enable clock\n"); + return PTR_ERR(efuse->clk); + } + + mutex_init(&efuse->mutex); + efuse->dev = &pdev->dev; + efuse->data = pdata; + + econfig.stride = 1; + econfig.word_size = 1; + econfig.read_only = false; + econfig.name = "sprd-efuse"; + econfig.size = efuse->data->blk_nums * SPRD_EFUSE_BLOCK_WIDTH; + econfig.reg_read = sprd_efuse_read; + econfig.reg_write = sprd_efuse_write; + econfig.priv = efuse; + econfig.dev = &pdev->dev; + nvmem = devm_nvmem_register(&pdev->dev, &econfig); + if (IS_ERR(nvmem)) { + dev_err(&pdev->dev, "failed to register nvmem\n"); + return PTR_ERR(nvmem); + } + + return 0; +} + +static const struct of_device_id sprd_efuse_of_match[] = { + { .compatible = "sprd,ums312-efuse", .data = &ums312_data }, + { } +}; + +static struct platform_driver sprd_efuse_driver = { + .probe = sprd_efuse_probe, + .driver = { + .name = "sprd-efuse", + .of_match_table = sprd_efuse_of_match, + }, +}; + +module_platform_driver(sprd_efuse_driver); + +MODULE_AUTHOR("Freeman Liu "); +MODULE_DESCRIPTION("Spreadtrum AP efuse driver"); +MODULE_LICENSE("GPL v2");