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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id q8-20020a7bce88000000b0040c11fbe581sm28301424wmj.27.2024.01.19.03.35.12 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:35:13 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, Daniel Hoffman , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini Subject: [PULL 01/36] hw/timer/hpet: Convert DPRINTF to trace events Date: Fri, 19 Jan 2024 12:34:30 +0100 Message-ID: <20240119113507.31951-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Daniel Hoffman This conversion is pretty straight-forward. Standardized some formatting so the +0 and +4 offset cases can recycle the same message. Signed-off-by: Daniel Hoffman Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20231118231129.2840388-1-dhoff749@gmail.com> [PMD: Fixed few string formats] Signed-off-by: Philippe Mathieu-Daudé --- hw/timer/hpet.c | 55 +++++++++++++++++-------------------------- hw/timer/trace-events | 15 ++++++++++++ 2 files changed, 37 insertions(+), 33 deletions(-) diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c index f2f1580f81..1672faa4f2 100644 --- a/hw/timer/hpet.c +++ b/hw/timer/hpet.c @@ -39,13 +39,7 @@ #include "hw/timer/i8254.h" #include "exec/address-spaces.h" #include "qom/object.h" - -//#define HPET_DEBUG -#ifdef HPET_DEBUG -#define DPRINTF printf -#else -#define DPRINTF(...) -#endif +#include "trace.h" #define HPET_MSI_SUPPORT 0 @@ -431,7 +425,7 @@ static uint64_t hpet_ram_read(void *opaque, hwaddr addr, HPETState *s = opaque; uint64_t cur_tick, index; - DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr); + trace_hpet_ram_read(addr); index = addr; /*address range of all TN regs*/ if (index >= 0x100 && index <= 0x3ff) { @@ -439,7 +433,7 @@ static uint64_t hpet_ram_read(void *opaque, hwaddr addr, HPETTimer *timer = &s->timer[timer_id]; if (timer_id > s->num_timers) { - DPRINTF("qemu: timer id out of range\n"); + trace_hpet_timer_id_out_of_range(timer_id); return 0; } @@ -457,7 +451,7 @@ static uint64_t hpet_ram_read(void *opaque, hwaddr addr, case HPET_TN_ROUTE + 4: return timer->fsb >> 32; default: - DPRINTF("qemu: invalid hpet_ram_readl\n"); + trace_hpet_ram_read_invalid(); break; } } else { @@ -469,7 +463,7 @@ static uint64_t hpet_ram_read(void *opaque, hwaddr addr, case HPET_CFG: return s->config; case HPET_CFG + 4: - DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl\n"); + trace_hpet_invalid_hpet_cfg(4); return 0; case HPET_COUNTER: if (hpet_enabled(s)) { @@ -477,7 +471,7 @@ static uint64_t hpet_ram_read(void *opaque, hwaddr addr, } else { cur_tick = s->hpet_counter; } - DPRINTF("qemu: reading counter = %" PRIx64 "\n", cur_tick); + trace_hpet_ram_read_reading_counter(0, cur_tick); return cur_tick; case HPET_COUNTER + 4: if (hpet_enabled(s)) { @@ -485,12 +479,12 @@ static uint64_t hpet_ram_read(void *opaque, hwaddr addr, } else { cur_tick = s->hpet_counter; } - DPRINTF("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick); + trace_hpet_ram_read_reading_counter(4, cur_tick); return cur_tick >> 32; case HPET_STATUS: return s->isr; default: - DPRINTF("qemu: invalid hpet_ram_readl\n"); + trace_hpet_ram_read_invalid(); break; } } @@ -504,8 +498,7 @@ static void hpet_ram_write(void *opaque, hwaddr addr, HPETState *s = opaque; uint64_t old_val, new_val, val, index; - DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = 0x%" PRIx64 "\n", - addr, value); + trace_hpet_ram_write(addr, value); index = addr; old_val = hpet_ram_read(opaque, addr, 4); new_val = value; @@ -515,14 +508,14 @@ static void hpet_ram_write(void *opaque, hwaddr addr, uint8_t timer_id = (addr - 0x100) / 0x20; HPETTimer *timer = &s->timer[timer_id]; - DPRINTF("qemu: hpet_ram_writel timer_id = 0x%x\n", timer_id); + trace_hpet_ram_write_timer_id(timer_id); if (timer_id > s->num_timers) { - DPRINTF("qemu: timer id out of range\n"); + trace_hpet_timer_id_out_of_range(timer_id); return; } switch ((addr - 0x100) % 0x20) { case HPET_TN_CFG: - DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n"); + trace_hpet_ram_write_tn_cfg(); if (activating_bit(old_val, new_val, HPET_TN_FSB_ENABLE)) { update_irq(timer, 0); } @@ -540,10 +533,10 @@ static void hpet_ram_write(void *opaque, hwaddr addr, } break; case HPET_TN_CFG + 4: // Interrupt capabilities - DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n"); + trace_hpet_ram_write_invalid_tn_cfg(4); break; case HPET_TN_CMP: // comparator register - DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP\n"); + trace_hpet_ram_write_tn_cmp(0); if (timer->config & HPET_TN_32BIT) { new_val = (uint32_t)new_val; } @@ -566,7 +559,7 @@ static void hpet_ram_write(void *opaque, hwaddr addr, } break; case HPET_TN_CMP + 4: // comparator register high order - DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n"); + trace_hpet_ram_write_tn_cmp(4); if (!timer_is_periodic(timer) || (timer->config & HPET_TN_SETVAL)) { timer->cmp = (timer->cmp & 0xffffffffULL) | new_val << 32; @@ -591,7 +584,7 @@ static void hpet_ram_write(void *opaque, hwaddr addr, timer->fsb = (new_val << 32) | (timer->fsb & 0xffffffff); break; default: - DPRINTF("qemu: invalid hpet_ram_writel\n"); + trace_hpet_ram_write_invalid(); break; } return; @@ -631,7 +624,7 @@ static void hpet_ram_write(void *opaque, hwaddr addr, } break; case HPET_CFG + 4: - DPRINTF("qemu: invalid HPET_CFG+4 write\n"); + trace_hpet_invalid_hpet_cfg(4); break; case HPET_STATUS: val = new_val & s->isr; @@ -643,24 +636,20 @@ static void hpet_ram_write(void *opaque, hwaddr addr, break; case HPET_COUNTER: if (hpet_enabled(s)) { - DPRINTF("qemu: Writing counter while HPET enabled!\n"); + trace_hpet_ram_write_counter_write_while_enabled(); } s->hpet_counter = (s->hpet_counter & 0xffffffff00000000ULL) | value; - DPRINTF("qemu: HPET counter written. ctr = 0x%" PRIx64 " -> " - "%" PRIx64 "\n", value, s->hpet_counter); + trace_hpet_ram_write_counter_written(0, value, s->hpet_counter); break; case HPET_COUNTER + 4: - if (hpet_enabled(s)) { - DPRINTF("qemu: Writing counter while HPET enabled!\n"); - } + trace_hpet_ram_write_counter_write_while_enabled(); s->hpet_counter = (s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32); - DPRINTF("qemu: HPET counter + 4 written. ctr = 0x%" PRIx64 " -> " - "%" PRIx64 "\n", value, s->hpet_counter); + trace_hpet_ram_write_counter_written(4, value, s->hpet_counter); break; default: - DPRINTF("qemu: invalid hpet_ram_writel\n"); + trace_hpet_ram_write_invalid(); break; } } diff --git a/hw/timer/trace-events b/hw/timer/trace-events index 8145e18e3d..de769f4b71 100644 --- a/hw/timer/trace-events +++ b/hw/timer/trace-events @@ -99,3 +99,18 @@ sifive_pwm_write(uint64_t data, uint64_t offset) "Write 0x%" PRIx64 " at address sh_timer_start_stop(int enable, int current) "%d (%d)" sh_timer_read(uint64_t offset) "tmu012_read 0x%" PRIx64 sh_timer_write(uint64_t offset, uint64_t value) "tmu012_write 0x%" PRIx64 " 0x%08" PRIx64 + +# hpet.c +hpet_timer_id_out_of_range(uint8_t timer_id) "timer id out of range: 0x%" PRIx8 +hpet_invalid_hpet_cfg(uint8_t reg_off) "invalid HPET_CFG + %u" PRIx8 +hpet_ram_read(uint64_t addr) "enter hpet_ram_readl at 0x%" PRIx64 +hpet_ram_read_reading_counter(uint8_t reg_off, uint64_t cur_tick) "reading counter + %" PRIu8 " = 0x%" PRIx64 +hpet_ram_read_invalid(void) "invalid hpet_ram_readl" +hpet_ram_write(uint64_t addr, uint64_t value) "enter hpet_ram_writel at 0x%" PRIx64 " = 0x%" PRIx64 +hpet_ram_write_timer_id(uint64_t timer_id) "hpet_ram_writel timer_id = 0x%" PRIx64 +hpet_ram_write_tn_cfg(void) "hpet_ram_writel HPET_TN_CFG" +hpet_ram_write_invalid_tn_cfg(uint8_t reg_off) "invalid HPET_TN_CFG + %" PRIu8 " write" +hpet_ram_write_tn_cmp(uint8_t reg_off) "hpet_ram_writel HPET_TN_CMP + %" PRIu8 +hpet_ram_write_invalid(void) "invalid hpet_ram_writel" +hpet_ram_write_counter_write_while_enabled(void) "Writing counter while HPET enabled!" +hpet_ram_write_counter_written(uint8_t reg_off, uint64_t value, uint64_t counter) "HPET counter + %" PRIu8 "written. crt = 0x%" PRIx64 " -> 0x%" PRIx64 From patchwork Fri Jan 19 11:34:31 2024 Content-Type: text/plain; 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id m26-20020a05600c3b1a00b0040e4c1dade4sm33037802wms.36.2024.01.19.03.35.17 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:35:17 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-stable@nongnu.org, zhenwei pi , Gonglei , Markus Armbruster Subject: [PULL 02/36] backends/cryptodev: Do not ignore throttle/backends Errors Date: Fri, 19 Jan 2024 12:34:31 +0100 Message-ID: <20240119113507.31951-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Both cryptodev_backend_set_throttle() and CryptoDevBackendClass::init() can set their Error** argument. Do not ignore them, return early on failure. Without that, running into another failure trips error_setv()'s assertion. Use the ERRP_GUARD() macro as suggested in commit ae7c80a7bd ("error: New macro ERRP_GUARD()"). Cc: qemu-stable@nongnu.org Fixes: e7a775fd9f ("cryptodev: Account statistics") Fixes: 2580b452ff ("cryptodev: support QoS") Reviewed-by: zhenwei pi Reviewed-by: Gonglei Reviewed-by: Markus Armbruster Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20231120150418.93443-1-philmd@linaro.org> --- backends/cryptodev.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/backends/cryptodev.c b/backends/cryptodev.c index e5006bd215..fff89fd62a 100644 --- a/backends/cryptodev.c +++ b/backends/cryptodev.c @@ -398,6 +398,7 @@ static void cryptodev_backend_set_ops(Object *obj, Visitor *v, static void cryptodev_backend_complete(UserCreatable *uc, Error **errp) { + ERRP_GUARD(); CryptoDevBackend *backend = CRYPTODEV_BACKEND(uc); CryptoDevBackendClass *bc = CRYPTODEV_BACKEND_GET_CLASS(uc); uint32_t services; @@ -406,11 +407,20 @@ cryptodev_backend_complete(UserCreatable *uc, Error **errp) QTAILQ_INIT(&backend->opinfos); value = backend->tc.buckets[THROTTLE_OPS_TOTAL].avg; cryptodev_backend_set_throttle(backend, THROTTLE_OPS_TOTAL, value, errp); + if (*errp) { + return; + } value = backend->tc.buckets[THROTTLE_BPS_TOTAL].avg; cryptodev_backend_set_throttle(backend, THROTTLE_BPS_TOTAL, value, errp); + if (*errp) { + return; + } if (bc->init) { bc->init(backend, errp); + if (*errp) { + return; + } } services = backend->conf.crypto_services; From patchwork Fri Jan 19 11:34:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763906 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp397152wrq; Fri, 19 Jan 2024 03:36:26 -0800 (PST) X-Google-Smtp-Source: AGHT+IGVox/hfXKEL8b+DnnOzkIRMzaCzisdmWZ2nayxnQlST5EgnRyQ+5ICoZ8mupXBRBetGmE/ X-Received: by 2002:ac8:5f4e:0:b0:42a:205a:fdea with SMTP id y14-20020ac85f4e000000b0042a205afdeamr1719491qta.87.1705664186654; Fri, 19 Jan 2024 03:36:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705664186; cv=none; d=google.com; s=arc-20160816; b=rDeK+nBnIofckYa8pjWWh3ZL3rsQOQLrxiuf1OtkiSWISmG0fR6JDiLQuUVJRG/I4d W9BGb60JWTi3+v6I06Nq8Hu3Sp21DRTcOqv2NE2LaCZ9X6victZa+sUtuirdXA0GsdOB S4hgr5HyGDnMgup8kGxbA4ah0sYr8Q0hE8loAg2OhzP8LpiTmfQDk515aPRGYCe5TyE0 sGoca7Ja+0Ttnek2t/7UrMeNltfUbqAQNHQ1Xi5AmYoDk1V962ywSsmoA/aEk6bApt+C k58D4QYwJR97MzLvyS2vcMBj7hbMG9k6ACl06qyZt8ZBjGMOGkhAz8wkFb2aWKOzQPGb gJzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=grikY+amHmPq7q8W8EjnJR7Fi9QeXPdA+8sNJUwVsyo=; fh=mNIn0IJuUUufB5QRXQRd5w9ZKLOgI80E423Hl3yXJsM=; b=a6ezeIzjzGxUm3CRaCCex+Npdc47utB/AUI1aaik5qBzuL3ZJssGFRZM2tcRyikkfx xDjrqzdFDvITpOPnRMarKOKwPQu5f4meCLnyK5HIuWohRS6r1SuWWnix50BWiC93Uzv8 76nZvg28YpOjDkh97Bat+946zskY8n8ZvxN6otSRdHNh87oE2oxZbgRTgZ3VuDM4JXrF W759qP1VmrrIjvf6Rr1GAkAsf6Zz09fUqsLkm56woj/ccAYXFQoWirMqJA4O7zLkW5RA ZpuTTjFKyygckX43LSXoZ3hJuwNVWlsoBhNfViDrDlt24FKps9i9Sc7bIiSo7D6lysjY UfuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=A6oNhbaa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id h4-20020a5d5044000000b0033609b71825sm6271320wrt.35.2024.01.19.03.35.21 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:35:22 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Peter Maydell , Paolo Bonzini Subject: [PULL 03/36] accel: Do not set CPUState::tcg_cflags in non-TCG accels Date: Fri, 19 Jan 2024 12:34:32 +0100 Message-ID: <20240119113507.31951-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org 'tcg_cflags' is specific to TCG. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20231130075958.21285-1-philmd@linaro.org> --- target/arm/cpu.c | 2 +- target/i386/cpu.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 826ce842c0..593695b424 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1796,8 +1796,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) int pagebits; Error *local_err = NULL; +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) /* Use pc-relative instructions in system-mode */ -#ifndef CONFIG_USER_ONLY cs->tcg_cflags |= CF_PCREL; #endif diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 2524881ce2..03822d9ba8 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7221,8 +7221,8 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) static bool ht_warned; unsigned requested_lbr_fmt; +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) /* Use pc-relative instructions in system-mode */ -#ifndef CONFIG_USER_ONLY cs->tcg_cflags |= CF_PCREL; #endif From patchwork Fri Jan 19 11:34:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763910 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp397688wrq; Fri, 19 Jan 2024 03:37:48 -0800 (PST) X-Google-Smtp-Source: AGHT+IGpg/wTx6HVqN4Sx6HbueYiy1ZxKQA08Z3LEjkrLKIuJ2EKu+P48ygKaLgjksLG1BnpnT3u X-Received: by 2002:ac8:5f4d:0:b0:42a:202c:a5ff with SMTP id y13-20020ac85f4d000000b0042a202ca5ffmr1990036qta.127.1705664268646; Fri, 19 Jan 2024 03:37:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705664268; cv=none; d=google.com; s=arc-20160816; b=XwqSCxX3dsOAmkba8jXIq0TNU4c5Ix2h7hV9npXe++xpKflEOBmEI2EJvjUbEZo1mN GqxTvmBJ1+yOEjSJZNt6yh8WFUtrBtbgZsxwUMlivSsMYX9+8ECUx7jflmKvAlOwAQrk s7AftlbcN7nAp1KmFgGfQEpCx5mTQyDNudbTgEiYrbSEr5bKJY9LouF32IC41EOoPK0P Gn0SwmUQMtm9I6zTYaWKIJ0Jz5cCtnjpeH19sUkWAHh4y/owbL2Vdah79D42n88MM3n5 V47Alqv1zcbg89YJzzTzIr3kKMzLTZy/kqt0pUUA9gyTU7967U6d0CwlYFp4dYEClDIG PyZg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=H2zlYB8RHgO8CCP+jqoBT970ZAV+LbSEyEbXoFvRXkI=; fh=7bHwpYwJTQ83+a+dvE3Bpy6AZG6gjvkTWbe0ZYqyLws=; b=qs7pmMeUrBaY27NLQuyJlZSemFpO4r2JH954xpkXVobg0oZth0wqCkTTBHr9G1kFHH okPOxlqJ5aBIGd4UYls07hlaG6Cou/9bTqKCZMMYL6PbtNr2nXLYyy++FukavSkN8jCV VVveIi6YOGVDQV2BK+TvK0GpOdGWLdLTsS0kX440suNiXLAF+qUOGRkVzHUDwlJchzkC f3i1CXgnLwGLCblhxFebYrkW6zuGLY9iEbFOXNu5HIhU++QB+R607yNXN4gPxyYu0nxr zuoSQ+jwQGPOzefcmvxxnll1rQAMv5Ruu2YCpzGUlCS6TbIcwweZ+ruEcbBfAAw8rGyR ow1g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Qzs905oI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id p10-20020a05600c358a00b0040e559e0ba7sm32395502wmq.26.2024.01.19.03.35.26 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:35:26 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Cameron Esfahani , Roman Bolshakov , Paolo Bonzini , kvm@vger.kernel.org Subject: [PULL 04/36] accel: Do not set CPUState::can_do_io in non-TCG accels Date: Fri, 19 Jan 2024 12:34:33 +0100 Message-ID: <20240119113507.31951-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org 'can_do_io' is specific to TCG. It was added to other accelerators in 626cf8f4c6 ("icount: set can_do_io outside TB execution"), then likely copy/pasted in commit c97d6d2cdf ("i386: hvf: add code base from Google's QEMU repository"). Having it set in non-TCG code is confusing, so remove it from QTest / HVF / KVM. Fixes: 626cf8f4c6 ("icount: set can_do_io outside TB execution") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20231129205037.16849-1-philmd@linaro.org> --- accel/dummy-cpus.c | 1 - accel/hvf/hvf-accel-ops.c | 1 - accel/kvm/kvm-accel-ops.c | 1 - 3 files changed, 3 deletions(-) diff --git a/accel/dummy-cpus.c b/accel/dummy-cpus.c index f4b0ec5890..20519f1ea4 100644 --- a/accel/dummy-cpus.c +++ b/accel/dummy-cpus.c @@ -27,7 +27,6 @@ static void *dummy_cpu_thread_fn(void *arg) bql_lock(); qemu_thread_get_self(cpu->thread); cpu->thread_id = qemu_get_thread_id(); - cpu->neg.can_do_io = true; current_cpu = cpu; #ifndef _WIN32 diff --git a/accel/hvf/hvf-accel-ops.c b/accel/hvf/hvf-accel-ops.c index 8eabb696fa..d94d41ab6d 100644 --- a/accel/hvf/hvf-accel-ops.c +++ b/accel/hvf/hvf-accel-ops.c @@ -428,7 +428,6 @@ static void *hvf_cpu_thread_fn(void *arg) qemu_thread_get_self(cpu->thread); cpu->thread_id = qemu_get_thread_id(); - cpu->neg.can_do_io = true; current_cpu = cpu; hvf_init_vcpu(cpu); diff --git a/accel/kvm/kvm-accel-ops.c b/accel/kvm/kvm-accel-ops.c index 45ff06e953..b3c946dc4b 100644 --- a/accel/kvm/kvm-accel-ops.c +++ b/accel/kvm/kvm-accel-ops.c @@ -36,7 +36,6 @@ static void *kvm_vcpu_thread_fn(void *arg) bql_lock(); qemu_thread_get_self(cpu->thread); cpu->thread_id = qemu_get_thread_id(); - cpu->neg.can_do_io = true; current_cpu = cpu; r = kvm_init_vcpu(cpu, &error_fatal); From patchwork Fri Jan 19 11:34:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763940 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp399803wrq; Fri, 19 Jan 2024 03:44:24 -0800 (PST) X-Google-Smtp-Source: AGHT+IHMF4VNyzDaZr8nqhvkgezDyOepyYsO1l9Fi6omkXlQSETFiBI44kly8fSdSy6HINqfuHiw X-Received: by 2002:ad4:5742:0:b0:67f:7c88:8734 with SMTP id q2-20020ad45742000000b0067f7c888734mr2805571qvx.26.1705664664161; Fri, 19 Jan 2024 03:44:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705664664; cv=none; d=google.com; s=arc-20160816; b=cIVddIXnI9BOR1fM2qqwrXQpra/c+SYXLjFLp/Xted1BGrFUhnyDlrwNtoC68QBHRW vAass5sBZYVFwYWsBqb9M2+MvQy9UxTgOXzk3NdbzwwPzKfaYiAlCUbKytfj0AtYL46N xawfC5rY8+RjCkB3tKHQHfEWM02VtnzwwzxwKpRM9ubLFr6KyN+OMw00ueFzJPeeX6hi BDhGflxyTg9ZlH/N+IrImM2w5IAKz9WkJxf/j0L/55JAURSU363wAZg1Xw0cZdeJkOBo 8Ck/gyTgjq11SKWUBtPpX19n11lMZ4sOBbi0wXabvo8mBvLaauXFrQimb6KML/+fRoxS FuIg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=JMrQlur1rdNDznxBbxffE0eHdXnWue3lFnhNe5G+YeM=; fh=PGD+nRug3lbQLQRmqJdfXASo9DDbKKfOK2qGXbkwX/w=; b=TmPaKHJyi2fH/WTGUgMbuTsM+9OCFFjd3rGiRRgAu1KXDtAcasJI7wgTZSvpGXL4TN Vm530e/zgUAKN9QA2LdpmpoHs/1/2oTrMg8FiwyUBxZrnHr60RDDRPMcSdJ9JvSbmntd Y9M41YFOC7Fn+1u6l7LERR4pjDF4GJOL+8KqoSZCWkp3k4rmgO5yElhfnbhglwPGgmCi 7n0slnZGz4ICcoOm+PjvtTcZl7cAWrOSP8gu7ymkRF94wBAZqdtIYwae2w8vAaTHCaqk dYOAukScmduuZg7RGIaMHTuHdKQzqyi0QFtCZFw5ZRuvX22n4NaH7d6I60E1BQqCf81H Z+JA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="oRZli/WQ"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id l34-20020a05600c1d2200b0040e89ade84bsm8335292wms.4.2024.01.19.03.35.30 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:35:31 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, Max Filippov , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PULL 05/36] target/xtensa: use generic instruction breakpoint infrastructure Date: Fri, 19 Jan 2024 12:34:34 +0100 Message-ID: <20240119113507.31951-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Max Filippov Don't embed ibreak exception generation into TB and don't invalidate TB on ibreak address change. Add CPUBreakpoint pointers to xtensa CPUArchState, use cpu_breakpoint_insert/cpu_breakpoint_remove_by_ref to manage ibreak breakpoints and provide TCGCPUOps::debug_check_breakpoint callback that recognizes valid instruction breakpoints. Signed-off-by: Max Filippov Reviewed-by: Richard Henderson Message-ID: <20231130171920.3798954-2-jcmvbkbc@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- target/xtensa/cpu.h | 4 ++++ target/xtensa/cpu.c | 1 + target/xtensa/dbg_helper.c | 46 +++++++++++++++++++++++++------------- target/xtensa/helper.c | 12 ++++++++++ target/xtensa/translate.c | 17 -------------- 5 files changed, 47 insertions(+), 33 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index d9c49a35fa..4b033ee924 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -229,6 +229,7 @@ enum { #define MAX_NCCOMPARE 3 #define MAX_TLB_WAY_SIZE 8 #define MAX_NDBREAK 2 +#define MAX_NIBREAK 2 #define MAX_NMEMORY 4 #define MAX_MPU_FOREGROUND_SEGMENTS 32 @@ -547,6 +548,8 @@ struct CPUArchState { /* Watchpoints for DBREAK registers */ struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK]; + /* Breakpoints for IBREAK registers */ + struct CPUBreakpoint *cpu_breakpoint[MAX_NIBREAK]; }; /** @@ -590,6 +593,7 @@ void xtensa_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr); hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +bool xtensa_debug_check_breakpoint(CPUState *cs); #endif void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, int flags); void xtensa_count_regs(const XtensaConfig *config, diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 93e782a6e0..99c0ca130f 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -233,6 +233,7 @@ static const struct TCGCPUOps xtensa_tcg_ops = { .do_interrupt = xtensa_cpu_do_interrupt, .do_transaction_failed = xtensa_cpu_do_transaction_failed, .do_unaligned_access = xtensa_cpu_do_unaligned_access, + .debug_check_breakpoint = xtensa_debug_check_breakpoint, #endif /* !CONFIG_USER_ONLY */ }; diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c index 3e0c9e8e8b..497dafca71 100644 --- a/target/xtensa/dbg_helper.c +++ b/target/xtensa/dbg_helper.c @@ -33,27 +33,21 @@ #include "exec/exec-all.h" #include "exec/address-spaces.h" -static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr) -{ - uint32_t paddr; - uint32_t page_size; - unsigned access; - int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0, - &paddr, &page_size, &access); - if (ret == 0) { - tb_invalidate_phys_addr(&address_space_memory, paddr, - MEMTXATTRS_UNSPECIFIED); - } -} - void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v) { + CPUState *cs = env_cpu(env); uint32_t change = v ^ env->sregs[IBREAKENABLE]; unsigned i; for (i = 0; i < env->config->nibreak; ++i) { if (change & (1 << i)) { - tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]); + if (v & (1 << i)) { + cpu_breakpoint_insert(cs, env->sregs[IBREAKA + i], + BP_CPU, &env->cpu_breakpoint[i]); + } else { + cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[i]); + env->cpu_breakpoint[i] = NULL; + } } } env->sregs[IBREAKENABLE] = v & ((1 << env->config->nibreak) - 1); @@ -62,12 +56,32 @@ void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v) void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v) { if (env->sregs[IBREAKENABLE] & (1 << i) && env->sregs[IBREAKA + i] != v) { - tb_invalidate_virtual_addr(env, env->sregs[IBREAKA + i]); - tb_invalidate_virtual_addr(env, v); + CPUState *cs = env_cpu(env); + + cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[i]); + cpu_breakpoint_insert(cs, v, BP_CPU, &env->cpu_breakpoint[i]); } env->sregs[IBREAKA + i] = v; } +bool xtensa_debug_check_breakpoint(CPUState *cs) +{ + XtensaCPU *cpu = XTENSA_CPU(cs); + CPUXtensaState *env = &cpu->env; + unsigned int i; + + if (xtensa_get_cintlevel(env) >= env->config->debug_level) { + return false; + } + for (i = 0; i < env->config->nibreak; ++i) { + if (env->sregs[IBREAKENABLE] & (1 << i) && + env->sregs[IBREAKA + i] == env->pc) { + return true; + } + } + return false; +} + static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka, uint32_t dbreakc) { diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index f6632df646..a9f8907083 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -231,6 +231,18 @@ void xtensa_breakpoint_handler(CPUState *cs) } cpu_loop_exit_noexc(cs); } + } else { + if (cpu_breakpoint_test(cs, env->pc, BP_GDB) + || !cpu_breakpoint_test(cs, env->pc, BP_CPU)) { + return; + } + if (env->sregs[ICOUNT] == 0xffffffff && + xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) { + debug_exception_env(env, DEBUGCAUSE_IC); + } else { + debug_exception_env(env, DEBUGCAUSE_IB); + } + cpu_loop_exit_noexc(cs); } } diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index de89940599..87947236ca 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1123,19 +1123,6 @@ static inline unsigned xtensa_insn_len(CPUXtensaState *env, DisasContext *dc) return xtensa_op0_insn_len(dc, b0); } -static void gen_ibreak_check(CPUXtensaState *env, DisasContext *dc) -{ - unsigned i; - - for (i = 0; i < dc->config->nibreak; ++i) { - if ((env->sregs[IBREAKENABLE] & (1 << i)) && - env->sregs[IBREAKA + i] == dc->pc) { - gen_debug_exception(dc, DEBUGCAUSE_IB); - break; - } - } -} - static void xtensa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) { @@ -1205,10 +1192,6 @@ static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) gen_set_label(label); } - if (dc->debug) { - gen_ibreak_check(env, dc); - } - disas_xtensa_insn(env, dc); if (dc->icount) { From patchwork Fri Jan 19 11:34:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763913 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp398703wrq; Fri, 19 Jan 2024 03:40:57 -0800 (PST) X-Google-Smtp-Source: AGHT+IH5NVTXMyoJaRH1cd8Pd6XUeFWJ04emb7Z8ZzGKZfVLNCkS5TlDcl1OGrFOx6g6c/UA5ZA1 X-Received: by 2002:a05:6214:2387:b0:681:88b2:6e41 with SMTP id fw7-20020a056214238700b0068188b26e41mr2155602qvb.104.1705664456791; Fri, 19 Jan 2024 03:40:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705664456; cv=none; d=google.com; s=arc-20160816; b=T0q5iMty9ZYfhOI6Jgw9iBfb4/hwU1/q8LyFFvwL18+0IVU2ZwzsMD+HsT+/1sIM4C vUfrydJJpUcVVzc0UJnE6zpInkh5RQ8BFBbb1w14JryE1LrQ0/RoJuZBCVB4q8kD0Kzi PAqmYF6XjaxvPtb6BVCdyKLCzDVkWq265lDLPC5deu41yJBeY8ri/a5JAdz41vHdkup2 Szq3/9o+8o5Q9KaxTG5w5XBux9GmWefxCKj+OVbRLzuFffYCPBFOhVdvIeLiIIQKQQ+I 4duTXNUZ0VIAXfoe4kTe6uDtXIZj99NeJZBGNrgLDrkzN1nxo1DAaXxqCza88JLuN1y3 7zxg== ARC-Message-Signature: i=1; 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id v9-20020a5d4b09000000b00337bfaa944bsm6284306wrq.54.2024.01.19.03.35.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:35:35 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, Max Filippov , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PULL 06/36] tests/tcg/xtensa: add icount/ibreak priority test Date: Fri, 19 Jan 2024 12:34:35 +0100 Message-ID: <20240119113507.31951-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Max Filippov When icount and ibreak exceptions are due to happen on the same address icount has higher precedence. Signed-off-by: Max Filippov Acked-by: Richard Henderson Message-ID: <20231130171920.3798954-3-jcmvbkbc@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- tests/tcg/xtensa/test_break.S | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/tests/tcg/xtensa/test_break.S b/tests/tcg/xtensa/test_break.S index 3aa18b5cec..4c618feb5b 100644 --- a/tests/tcg/xtensa/test_break.S +++ b/tests/tcg/xtensa/test_break.S @@ -129,7 +129,7 @@ test ibreak_remove 4: test_end -test ibreak_priority +test ibreak_break_priority set_vector debug_vector, 2f rsil a2, debug_level - 1 movi a2, 1f @@ -145,6 +145,29 @@ test ibreak_priority movi a3, 0x2 assert eq, a2, a3 test_end + +test ibreak_icount_priority + set_vector debug_vector, 2f + rsil a2, debug_level - 1 + movi a2, 1f + wsr a2, ibreaka0 + movi a2, 1 + wsr a2, ibreakenable + movi a2, -2 + wsr a2, icount + movi a2, 1 + wsr a2, icountlevel + isync + rsil a2, 0 + nop +1: + break 0, 0 + test_fail +2: + rsr a2, debugcause + movi a3, 0x1 + assert eq, a2, a3 +test_end #endif test icount From patchwork Fri Jan 19 11:34:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763912 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp397981wrq; Fri, 19 Jan 2024 03:38:41 -0800 (PST) X-Google-Smtp-Source: AGHT+IGra9F2eAKH4dVYpTweD5HyQ1ohdkCtkBgYX4bZT3KFCwGYuqwTLj4Z5STWHkb70UY/2FfY X-Received: by 2002:a05:620a:2406:b0:783:8c5d:da1b with SMTP id d6-20020a05620a240600b007838c5dda1bmr414351qkn.21.1705664321404; Fri, 19 Jan 2024 03:38:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705664321; cv=none; d=google.com; s=arc-20160816; b=si80Wj8lhBAzu+xPQtQeg7Pr34dcBaut4iSpS0M2cyhkHROhpVLsVRv1NtPsX0kpv5 N/ZGrq7zy1N1O5JHZkHSnRZlKV8n5uqpc0mcOTE/VjzW3x2AN9ID32qtJ+YVfSPwhYW6 eJN7QdoPpL6dUJu4e51lLkgQugayOnjJnLRrn1uZr2INo/Gh9rcuuCkckKGsJg1murSk RTJRGkHPqnxJ9c/z5dOMTvgoqMJJ18T5Sr1fIBa/VgHH/yEpzppCaejrufF/67iU5jEf werOBzy6SoJ7WafbO7pB/KvqqqS7S1bMkPIEPHvpXM2MDvTcOAuSmiadVaD0qC8u2rKC +vGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=1kHSnHH1cspbXUMLrjnX00ivshEejOmgJvy2gqACDDE=; fh=0x3oxSDM+3B1iq7MNcEDPiiYDxF4jnBXeQY/LXh8Yxc=; b=sW45FktVtBbkRfJV8U51dV1VnsRAXD8/oVwhS4iRzN0pqeEy1h4+Gso19aEWqQU0I6 6deFsLAq0U/occ1f/a8q/V9ePJBmWyuuW2rjORz00AInnijNkecsUo7zYw89hwA9rTDQ qChxMpAeUHFykpfjGvdMVmfcNLDo2lEo7w50EwPSEK2ntAPjBewL2cXRHmCbhXyOgaHm WN3NoOm+1zQGNbJANrNzp3zsp1W7wCMnV8l+qurZlIM+7KH+wQBx+L9fvy6A+/f95Wcs cEgJS4H6PNbfxv1eI+o56WWc7YOUcRaLUBsLaA/sjEsJ6GYYHRCJeC58r83m75BQjmxh M6ow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Pmp2M1qF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id r7-20020a05600c35c700b0040d1bd0e716sm28955617wmq.9.2024.01.19.03.35.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:35:40 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Subject: [PULL 07/36] accel/tcg: Remove unused tb_invalidate_phys_addr() Date: Fri, 19 Jan 2024 12:34:36 +0100 Message-ID: <20240119113507.31951-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Commit e3f7c801f1 introduced the TCGCPUOps::debug_check_breakpoint() handler, and commit 10c37828b2 "moved breakpoint recognition outside of translation", so "we no longer need to flush any TBs when changing BPs". The last target using tb_invalidate_phys_addr() was converted to the debug_check_breakpoint(), so this function is now unused. Remove it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20231130203241.31099-1-philmd@linaro.org> --- include/exec/exec-all.h | 5 ----- cpu-target.c | 29 ----------------------------- 2 files changed, 34 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index ee90ef122b..df3d93a2e2 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -518,11 +518,6 @@ static inline void tb_set_page_addr1(TranslationBlock *tb, uint32_t curr_cflags(CPUState *cpu); /* TranslationBlock invalidate API */ -#if defined(CONFIG_USER_ONLY) -void tb_invalidate_phys_addr(hwaddr addr); -#else -void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs); -#endif void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t last); void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr); diff --git a/cpu-target.c b/cpu-target.c index 5eecd7ea2d..d51adfd7e3 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -314,35 +314,6 @@ void list_cpus(void) cpu_list(); } -#if defined(CONFIG_USER_ONLY) -void tb_invalidate_phys_addr(hwaddr addr) -{ - mmap_lock(); - tb_invalidate_phys_page(addr); - mmap_unlock(); -} -#else -void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs) -{ - ram_addr_t ram_addr; - MemoryRegion *mr; - hwaddr l = 1; - - if (!tcg_enabled()) { - return; - } - - RCU_READ_LOCK_GUARD(); - mr = address_space_translate(as, addr, &addr, &l, false, attrs); - if (!(memory_region_is_ram(mr) - || memory_region_is_romd(mr))) { - return; - } - ram_addr = memory_region_get_ram_addr(mr) + addr; - tb_invalidate_phys_page(ram_addr); -} -#endif - /* enable or disable single step mode. EXCP_DEBUG is returned by the CPU loop after each instruction */ void cpu_single_step(CPUState *cpu, int enabled) From patchwork Fri Jan 19 11:34:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763918 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp398914wrq; Fri, 19 Jan 2024 03:41:41 -0800 (PST) X-Google-Smtp-Source: AGHT+IG/L2elDzu6yx8KR2bj7WGLag8Fj4TqG+NQmTQ/CXcwMMGZ07YQ6jeWyS+/OwbSFZ0gqo1d X-Received: by 2002:a05:620a:c4a:b0:783:3ca1:9d6a with SMTP id u10-20020a05620a0c4a00b007833ca19d6amr1488780qki.58.1705664500802; Fri, 19 Jan 2024 03:41:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705664500; cv=none; d=google.com; s=arc-20160816; b=PNf6uWfytHi8ZgEOekfH7ijOZtUpFktWG8uSODSrkvT561Dgr4LiPBomICrJUW1dKU MCpwYFL9A0Mi69My9HaaIYXk7zDzn5axXb7bPPK4pyHh70l5D1zJ7/Ac5mHRBp6UfDl2 lOaftbNKPuG+kY0kg+luk4dUwKYq3uWyfguzu4j8ijNmMTPAXSa+2nkxhz/kYAboRuTR 9iggBpNZ/hI3S5HIDFxd3WCzYYG7HBNV+s7XfWsSh84CR5K83n0q/g8cumfps508TtXJ np+1obMPxx6NHUrExSyM7NP+vksSrcWI6Vv752N5XL1vvqXSea0n7bWfCF1yBvHs0CgM pOnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=PRuBRVEWPg8k5cL0C9qDEuFeMVHGZcEBcpFoyN0cEVQ=; fh=0x3oxSDM+3B1iq7MNcEDPiiYDxF4jnBXeQY/LXh8Yxc=; b=ORfV9U8hzTfKhuF5lhG6nOJuNBwz3Io/6wdFgLuAPFNN44uAGGB/L3o5IzP/Q4YgHV FnGo+jw1eXj+EWhRpr2pA2icc8yI2eJYvBtrDoGrjGGjQIuysEk+W7xxZkHmr15SDfyu H78ihSrxwoJ//7Y2cSjh5rm/iJKMZxKkCAm6fyXDX/2o5tibSFMJ2L2hr8E0/kVZupjW yhgxjyjL/aRDXJg0EPtI8dGYEn5K2tBtZHXk2P0LXnKf6kbihsElKn4Rr0qyh0ggkrxV 564Td5h4AlUB1uU/mKoZxklQgOKPwoEzctHmXv6tJ4/PfUojRbJYy94+h2TKY1R9vtOS rdbw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EMVAxAMr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id r19-20020a05600c459300b0040e42391a12sm28532667wmo.13.2024.01.19.03.35.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:35:44 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Subject: [PULL 08/36] accel/tcg: Remove tb_invalidate_phys_page() from system emulation Date: Fri, 19 Jan 2024 12:34:37 +0100 Message-ID: <20240119113507.31951-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since previous commit, tb_invalidate_phys_page() is not used anymore in system emulation. Make it static for user emulation and remove its public declaration in "exec/translate-all.h". Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20231130205600.35727-1-philmd@linaro.org> Reviewed-by: Richard Henderson --- include/exec/translate-all.h | 1 - accel/tcg/tb-maint.c | 24 +----------------------- 2 files changed, 1 insertion(+), 24 deletions(-) diff --git a/include/exec/translate-all.h b/include/exec/translate-all.h index 88602ae8d8..85c9460c7c 100644 --- a/include/exec/translate-all.h +++ b/include/exec/translate-all.h @@ -23,7 +23,6 @@ /* translate-all.c */ -void tb_invalidate_phys_page(tb_page_addr_t addr); void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr); #ifdef CONFIG_USER_ONLY diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index 3d2a896220..da39a43bd8 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -1021,7 +1021,7 @@ void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t last) * Called with mmap_lock held for user-mode emulation * NOTE: this function must not be called while a TB is running. */ -void tb_invalidate_phys_page(tb_page_addr_t addr) +static void tb_invalidate_phys_page(tb_page_addr_t addr) { tb_page_addr_t start, last; @@ -1160,28 +1160,6 @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages, #endif } -/* - * Invalidate all TBs which intersect with the target physical - * address page @addr. - */ -void tb_invalidate_phys_page(tb_page_addr_t addr) -{ - struct page_collection *pages; - tb_page_addr_t start, last; - PageDesc *p; - - p = page_find(addr >> TARGET_PAGE_BITS); - if (p == NULL) { - return; - } - - start = addr & TARGET_PAGE_MASK; - last = addr | ~TARGET_PAGE_MASK; - pages = page_collection_lock(start, last); - tb_invalidate_phys_page_range__locked(pages, p, start, last, 0); - page_collection_unlock(pages); -} - /* * Invalidate all TBs which intersect with the target physical address range * [start;last]. NOTE: start and end may refer to *different* physical pages. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id r19-20020a05600c459300b0040e42391a12sm28532878wmo.13.2024.01.19.03.35.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:35:49 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 09/36] target/alpha: Extract clk_helper.c from sys_helper.c Date: Fri, 19 Jan 2024 12:34:38 +0100 Message-ID: <20240119113507.31951-10-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Except helper_load_pcc(), all helpers from sys_helper.c are system-emulation specific. In preparation of restricting sys_helper.c to system emulation, extract helper_load_pcc() to clk_helper.c. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20231207105426.49339-2-philmd@linaro.org> --- target/alpha/clk_helper.c | 32 ++++++++++++++++++++++++++++++++ target/alpha/sys_helper.c | 15 --------------- target/alpha/meson.build | 1 + 3 files changed, 33 insertions(+), 15 deletions(-) create mode 100644 target/alpha/clk_helper.c diff --git a/target/alpha/clk_helper.c b/target/alpha/clk_helper.c new file mode 100644 index 0000000000..26ffc231cd --- /dev/null +++ b/target/alpha/clk_helper.c @@ -0,0 +1,32 @@ +/* + * QEMU Alpha clock helpers. + * + * Copyright (c) 2007 Jocelyn Mayer + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/timer.h" +#include "exec/helper-proto.h" +#include "cpu.h" + +uint64_t helper_load_pcc(CPUAlphaState *env) +{ +#ifndef CONFIG_USER_ONLY + /* + * In system mode we have access to a decent high-resolution clock. + * In order to make OS-level time accounting work with the RPCC, + * present it with a well-timed clock fixed at 250MHz. + */ + return (((uint64_t)env->pcc_ofs << 32) + | (uint32_t)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) >> 2)); +#else + /* + * In user-mode, QEMU_CLOCK_VIRTUAL doesn't exist. Just pass through + * the host cpu clock ticks. Also, don't bother taking PCC_OFS into + * account. + */ + return (uint32_t)cpu_get_host_ticks(); +#endif +} diff --git a/target/alpha/sys_helper.c b/target/alpha/sys_helper.c index c83c92dd4c..98d9a0fff7 100644 --- a/target/alpha/sys_helper.c +++ b/target/alpha/sys_helper.c @@ -27,21 +27,6 @@ #include "qemu/timer.h" -uint64_t helper_load_pcc(CPUAlphaState *env) -{ -#ifndef CONFIG_USER_ONLY - /* In system mode we have access to a decent high-resolution clock. - In order to make OS-level time accounting work with the RPCC, - present it with a well-timed clock fixed at 250MHz. */ - return (((uint64_t)env->pcc_ofs << 32) - | (uint32_t)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) >> 2)); -#else - /* In user-mode, QEMU_CLOCK_VIRTUAL doesn't exist. Just pass through the host cpu - clock ticks. Also, don't bother taking PCC_OFS into account. */ - return (uint32_t)cpu_get_host_ticks(); -#endif -} - /* PALcode support special instructions */ #ifndef CONFIG_USER_ONLY void helper_tbia(CPUAlphaState *env) diff --git a/target/alpha/meson.build b/target/alpha/meson.build index d3502dd823..ea252c99a5 100644 --- a/target/alpha/meson.build +++ b/target/alpha/meson.build @@ -4,6 +4,7 @@ alpha_ss.add(files( 'fpu_helper.c', 'gdbstub.c', 'helper.c', + 'clk_helper.c', 'int_helper.c', 'mem_helper.c', 'sys_helper.c', From patchwork Fri Jan 19 11:34:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763917 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp398910wrq; Fri, 19 Jan 2024 03:41:40 -0800 (PST) X-Google-Smtp-Source: AGHT+IFHz3dJOhoN37EqznIrU0LMZN/6leoO2PxFvYvDVE+A1PBh0px1IxsaTGqYgW/bRBtYiivv X-Received: by 2002:a05:6830:18e7:b0:6dd:e970:1349 with SMTP id d7-20020a05683018e700b006dde9701349mr2586469otf.59.1705664500457; Fri, 19 Jan 2024 03:41:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705664500; cv=none; d=google.com; s=arc-20160816; b=TGRQfb5M7c82yyaNUfXwAZHKWyr2kOo6kQNB5vRHwp4iw/Ra7eCXgDiOC7UQfEpwwg q4so6WEv+wqfAcEYu1tT8T2PUbad2Jbri+O+fCcjjCOYLEnPJudxNsMkrncrGyxIwrmG TT1AuzyiYzuHFXhq4EzS3sM0yKHS8PE2BtAkzLYfnZzPMq3R2+tBqhd4UzWoeeOEBIhS jOxYS2R1jq/OQt6J7f0FqYF/pFXgUMXXam+WjbhyAmQ+L9P5irHrKG+CDCsL7Y8q8QWb e0MDArtubbvKPTy66Ii6FlvU9wh/2irfif+BIMLmFL0V8k4wljuSqWIJ2qXdvEQN9AkR lDAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=DBo2Z7Ku5vyeXLs2uqKJ4IlgAVFUCbWhBp53AWDvWSA=; fh=6tP4L9XjCvdhkEFVfS9C+TY7ruUfmb06A1hD+CUqGXU=; b=LKcdBAp3DzkkZyJv4cREeUj9TxPBlAfL4T+ldxzy5nFTtjUHlfOmgf4ZBkAtYrknfv /v1Wk4LQUYaYGwD0VT+RY1wN4ZCQQTGu45pDNwgvpFITkBOVfE78eo3IEIKajiCRYkWa A/QUjdrgFcXl+hm8j0XCEXux94yrANOUNHAuS8z/Ch5xM/MR50ziZFF3zHgbbw9gNDts asJYuYx++nVxypUxxzh+xpTwY/EycoahPH409iou1XIOrFtKzZTIv3bguTufkaRpCHeu rcwSGcIJ1yQg6OLJcAFYIV37x2V239ALgn9/oyw4N3WKTsdhiBeI7ug/98SRLT4N6zkv T+SA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RVkbTjHp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id o2-20020a5d4a82000000b00338ca0ada22sm1400094wrq.111.2024.01.19.03.35.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:35:53 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PULL 10/36] target/alpha: Only build sys_helper.c on system emulation Date: Fri, 19 Jan 2024 12:34:39 +0100 Message-ID: <20240119113507.31951-11-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=philmd@linaro.org; helo=mail-lf1-x136.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20231207105426.49339-3-philmd@linaro.org> --- target/alpha/sys_helper.c | 3 --- target/alpha/meson.build | 6 ++++-- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/target/alpha/sys_helper.c b/target/alpha/sys_helper.c index 98d9a0fff7..768116ef32 100644 --- a/target/alpha/sys_helper.c +++ b/target/alpha/sys_helper.c @@ -28,7 +28,6 @@ /* PALcode support special instructions */ -#ifndef CONFIG_USER_ONLY void helper_tbia(CPUAlphaState *env) { tlb_flush(env_cpu(env)); @@ -74,5 +73,3 @@ void helper_set_alarm(CPUAlphaState *env, uint64_t expire) timer_del(cpu->alarm_timer); } } - -#endif /* CONFIG_USER_ONLY */ diff --git a/target/alpha/meson.build b/target/alpha/meson.build index ea252c99a5..7dbbd55717 100644 --- a/target/alpha/meson.build +++ b/target/alpha/meson.build @@ -7,13 +7,15 @@ alpha_ss.add(files( 'clk_helper.c', 'int_helper.c', 'mem_helper.c', - 'sys_helper.c', 'translate.c', 'vax_helper.c', )) alpha_system_ss = ss.source_set() -alpha_system_ss.add(files('machine.c')) +alpha_system_ss.add(files( + 'machine.c', + 'sys_helper.c', +)) target_arch += {'alpha': alpha_ss} target_system_arch += {'alpha': alpha_system_ss} From patchwork Fri Jan 19 11:34:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763934 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp399563wrq; Fri, 19 Jan 2024 03:43:34 -0800 (PST) X-Google-Smtp-Source: AGHT+IFQW4NGejAu8xaG0Eww8i+ZWPOfRC31dxFUh1F6r1cSOnePWxjL6R7v5c9N9oNL/BkEJiKm X-Received: by 2002:a05:6808:1646:b0:3bd:9380:4af5 with SMTP id az6-20020a056808164600b003bd93804af5mr2898238oib.38.1705664613854; Fri, 19 Jan 2024 03:43:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705664613; cv=none; d=google.com; s=arc-20160816; b=NNR0DXnv+FYaAOxGILE5eNnYoADJkYBBL9nR3WUGnIg3qQS88fdPQZtr3HJB7AUKu9 NlBXvDjLAVZC83/kK8JjMK6JSXBFqZxL/j7sTKAqscIKkswoRNJp6YtyoNoKZhEpkcEJ cj7YPTYLSdw7NrWR95l9RKpHcQ/MQB+t7pCYLTuvwueb0PhAQB3pVBXkHQoMM5Vga6J7 Y+Xzm3VUR3lD4/ANj9/FBfEKlqL/CgRxBv303Z+U21hAKghvS3QvYLXouB6GfpBjjVWz q8IvCiWyHNl46K9t0XPlxrExnCU3P1RNnJS1qpSMe8ist8DVL11CQu7I7A4489BKA07v PSuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=bZ2ofuMw9l9dRlR/wStloN7Wq3xL/x8gLMvQvh8dxdA=; fh=0x3oxSDM+3B1iq7MNcEDPiiYDxF4jnBXeQY/LXh8Yxc=; b=kUd6NmClLjF3/xEaWKD2HjaN2VPHo+xGdvND1p01MH1jrfzusoIyCI7p3xTrRZUUHD 6gqIalNY2NWPf1QO3MS2j5QOGA3UpNTpR3disw2s4VdQi7mK9ZPLrMlyI1EXh137xli2 HtspkC0UyHniI81estS8ihd7frJLyrUP3qq+kN0GxIcC3bS/MB2mmv8jV0IVFGj9zbKo BIqmx80fiTRGZSMdfcC6bWYOlcrl1Mf2vWa9WH4g9TMSIzQCAz0uSgnnvSw6y8Rh5S17 lCWdkEDS4TWwavKn4VleH2vbwooySIoz5Qyel23tYkSmcV9myNM13MWuw6eGsydTEJQ9 v8+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LpMWM1zy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id m10-20020adffa0a000000b003392172fd60sm1114421wrr.51.2024.01.19.03.35.57 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:35:58 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Subject: [PULL 11/36] system/cpu-timers: Have icount_configure() return a boolean Date: Fri, 19 Jan 2024 12:34:40 +0100 Message-ID: <20240119113507.31951-12-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Following the example documented since commit e3fe3988d7 ("error: Document Error API usage rules"), have icount_configure() return a boolean indicating whether an error is set or not. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-ID: <20231208113529.74067-2-philmd@linaro.org> --- include/sysemu/cpu-timers.h | 10 ++++++++-- accel/tcg/icount-common.c | 16 +++++++++------- stubs/icount.c | 4 +++- system/vl.c | 3 +-- 4 files changed, 21 insertions(+), 12 deletions(-) diff --git a/include/sysemu/cpu-timers.h b/include/sysemu/cpu-timers.h index 2e786fe7fb..b70dc7692d 100644 --- a/include/sysemu/cpu-timers.h +++ b/include/sysemu/cpu-timers.h @@ -50,8 +50,14 @@ int64_t icount_get(void); */ int64_t icount_to_ns(int64_t icount); -/* configure the icount options, including "shift" */ -void icount_configure(QemuOpts *opts, Error **errp); +/** + * icount_configure: configure the icount options, including "shift" + * @opts: Options to parse + * @errp: pointer to a NULL-initialized error object + * + * Return: true on success, else false setting @errp with error + */ +bool icount_configure(QemuOpts *opts, Error **errp); /* used by tcg vcpu thread to calc icount budget */ int64_t icount_round(int64_t count); diff --git a/accel/tcg/icount-common.c b/accel/tcg/icount-common.c index ec57192be8..dc69d6a4c6 100644 --- a/accel/tcg/icount-common.c +++ b/accel/tcg/icount-common.c @@ -419,7 +419,7 @@ void icount_account_warp_timer(void) icount_warp_rt(); } -void icount_configure(QemuOpts *opts, Error **errp) +bool icount_configure(QemuOpts *opts, Error **errp) { const char *option = qemu_opt_get(opts, "shift"); bool sleep = qemu_opt_get_bool(opts, "sleep", true); @@ -429,27 +429,28 @@ void icount_configure(QemuOpts *opts, Error **errp) if (!option) { if (qemu_opt_get(opts, "align") != NULL) { error_setg(errp, "Please specify shift option when using align"); + return false; } - return; + return true; } if (align && !sleep) { error_setg(errp, "align=on and sleep=off are incompatible"); - return; + return false; } if (strcmp(option, "auto") != 0) { if (qemu_strtol(option, NULL, 0, &time_shift) < 0 || time_shift < 0 || time_shift > MAX_ICOUNT_SHIFT) { error_setg(errp, "icount: Invalid shift value"); - return; + return false; } } else if (icount_align_option) { error_setg(errp, "shift=auto and align=on are incompatible"); - return; + return false; } else if (!icount_sleep) { error_setg(errp, "shift=auto and sleep=off are incompatible"); - return; + return false; } icount_sleep = sleep; @@ -463,7 +464,7 @@ void icount_configure(QemuOpts *opts, Error **errp) if (time_shift >= 0) { timers_state.icount_time_shift = time_shift; icount_enable_precise(); - return; + return true; } icount_enable_adaptive(); @@ -491,6 +492,7 @@ void icount_configure(QemuOpts *opts, Error **errp) timer_mod(timers_state.icount_vm_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + NANOSECONDS_PER_SECOND / 10); + return true; } void icount_notify_exit(void) diff --git a/stubs/icount.c b/stubs/icount.c index 6df8c2bf7d..85c381a0ea 100644 --- a/stubs/icount.c +++ b/stubs/icount.c @@ -10,10 +10,12 @@ void icount_update(CPUState *cpu) { abort(); } -void icount_configure(QemuOpts *opts, Error **errp) +bool icount_configure(QemuOpts *opts, Error **errp) { /* signal error */ error_setg(errp, "cannot configure icount, TCG support not available"); + + return false; } int64_t icount_get_raw(void) { diff --git a/system/vl.c b/system/vl.c index 53850a1daf..404e7cf87a 100644 --- a/system/vl.c +++ b/system/vl.c @@ -2270,8 +2270,7 @@ static void user_register_global_props(void) static int do_configure_icount(void *opaque, QemuOpts *opts, Error **errp) { - icount_configure(opts, errp); - return 0; + return !icount_configure(opts, errp); } static int accelerator_set_property(void *opaque, From patchwork Fri Jan 19 11:34:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763938 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp399694wrq; Fri, 19 Jan 2024 03:44:04 -0800 (PST) X-Google-Smtp-Source: AGHT+IGfTgV9i3ZqzzIavTIT55YNpLplBcW+7S08f0Du4kvYqkw7/Upf6y+uzptbTWUK+oO6roaU X-Received: by 2002:a05:6808:f8a:b0:3bd:a4bb:b09e with SMTP id o10-20020a0568080f8a00b003bda4bbb09emr747998oiw.12.1705664644317; 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id hg14-20020a05600c538e00b0040e5cf9a6c7sm29071140wmb.13.2024.01.19.03.36.02 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:36:02 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini , Peter Maydell Subject: [PULL 12/36] system/cpu-timers: Introduce ICountMode enumerator Date: Fri, 19 Jan 2024 12:34:41 +0100 Message-ID: <20240119113507.31951-13-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Rather than having to lookup for what the 0, 1, 2, ... icount values are, use a enum definition. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-ID: <20231208113529.74067-4-philmd@linaro.org> --- include/sysemu/cpu-timers.h | 20 +++++++++++++------- accel/tcg/icount-common.c | 16 +++++++--------- stubs/icount.c | 2 +- system/cpu-timers.c | 2 +- target/arm/helper.c | 3 ++- 5 files changed, 24 insertions(+), 19 deletions(-) diff --git a/include/sysemu/cpu-timers.h b/include/sysemu/cpu-timers.h index b70dc7692d..3f05f29b10 100644 --- a/include/sysemu/cpu-timers.h +++ b/include/sysemu/cpu-timers.h @@ -17,18 +17,24 @@ void cpu_timers_init(void); /* icount - Instruction Counter API */ -/* - * icount enablement state: +/** + * ICountMode: icount enablement state: * - * 0 = Disabled - Do not count executed instructions. - * 1 = Enabled - Fixed conversion of insn to ns via "shift" option - * 2 = Enabled - Runtime adaptive algorithm to compute shift + * @ICOUNT_DISABLED: Disabled - Do not count executed instructions. + * @ICOUNT_PRECISE: Enabled - Fixed conversion of insn to ns via "shift" option + * @ICOUNT_ADAPTATIVE: Enabled - Runtime adaptive algorithm to compute shift */ +typedef enum { + ICOUNT_DISABLED = 0, + ICOUNT_PRECISE, + ICOUNT_ADAPTATIVE, +} ICountMode; + #ifdef CONFIG_TCG -extern int use_icount; +extern ICountMode use_icount; #define icount_enabled() (use_icount) #else -#define icount_enabled() 0 +#define icount_enabled() ICOUNT_DISABLED #endif /* diff --git a/accel/tcg/icount-common.c b/accel/tcg/icount-common.c index dc69d6a4c6..f0f8fc7f1c 100644 --- a/accel/tcg/icount-common.c +++ b/accel/tcg/icount-common.c @@ -49,21 +49,19 @@ static bool icount_sleep = true; /* Arbitrarily pick 1MIPS as the minimum allowable speed. */ #define MAX_ICOUNT_SHIFT 10 -/* - * 0 = Do not count executed instructions. - * 1 = Fixed conversion of insn to ns via "shift" option - * 2 = Runtime adaptive algorithm to compute shift - */ -int use_icount; +/* Do not count executed instructions */ +ICountMode use_icount = ICOUNT_DISABLED; static void icount_enable_precise(void) { - use_icount = 1; + /* Fixed conversion of insn to ns via "shift" option */ + use_icount = ICOUNT_PRECISE; } static void icount_enable_adaptive(void) { - use_icount = 2; + /* Runtime adaptive algorithm to compute shift */ + use_icount = ICOUNT_ADAPTATIVE; } /* @@ -256,7 +254,7 @@ static void icount_warp_rt(void) int64_t warp_delta; warp_delta = clock - timers_state.vm_clock_warp_start; - if (icount_enabled() == 2) { + if (icount_enabled() == ICOUNT_ADAPTATIVE) { /* * In adaptive mode, do not let QEMU_CLOCK_VIRTUAL run too far * ahead of real time (it might already be ahead so careful not diff --git a/stubs/icount.c b/stubs/icount.c index 85c381a0ea..c2c10dfb6b 100644 --- a/stubs/icount.c +++ b/stubs/icount.c @@ -4,7 +4,7 @@ /* icount - Instruction Counter API */ -int use_icount; +ICountMode use_icount = ICOUNT_DISABLED; void icount_update(CPUState *cpu) { diff --git a/system/cpu-timers.c b/system/cpu-timers.c index bdf3a41dcb..0b31c9a1b6 100644 --- a/system/cpu-timers.c +++ b/system/cpu-timers.c @@ -154,7 +154,7 @@ static bool adjust_timers_state_needed(void *opaque) static bool icount_shift_state_needed(void *opaque) { - return icount_enabled() == 2; + return icount_enabled() == ICOUNT_ADAPTATIVE; } /* diff --git a/target/arm/helper.c b/target/arm/helper.c index dc8f14f433..49665bb763 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -948,7 +948,8 @@ static int64_t cycles_ns_per(uint64_t cycles) static bool instructions_supported(CPUARMState *env) { - return icount_enabled() == 1; /* Precise instruction counting */ + /* Precise instruction counting */ + return icount_enabled() == ICOUNT_PRECISE; } static uint64_t instructions_get_count(CPUARMState *env) From patchwork Fri Jan 19 11:34:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763924 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp399177wrq; Fri, 19 Jan 2024 03:42:31 -0800 (PST) X-Google-Smtp-Source: AGHT+IGyFBZactTuJ6zm31BihvC14gbSiE2ZNO9tfF7bCwgD36m9g44bUvpdjQb0i6/F2rrrDbuW X-Received: by 2002:a05:6214:da6:b0:680:b72b:7d7f with SMTP id h6-20020a0562140da600b00680b72b7d7fmr2393450qvh.127.1705664551447; Fri, 19 Jan 2024 03:42:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705664551; cv=none; d=google.com; s=arc-20160816; b=hTf+rsyn/NfdcmqcPgVUtRdtR0Pak7G/G7eAh+8WjbixUZlQ6ZdnecqXgyfvGoHj+D aYvm9neLIs7xVBbpIcvKE6YZ59CjxvTDvmmOrDmYqR2g6cGh3i90N3vZbj5WtGIc69IT 39yDn+oN9/v6EToJlOva7auWcquYHOgqY5BHJB1eej/nTetWobEEwJqWVIJtN2RzZ2aR NEw41o8t08A+yvWW9Ac/3H358kZGZN9qXY8bThcnf0t2bb3P5O/pt+zRzKw+qFZjqT0u wQKS7xKovtaClqihq1S8pBGPx76AZekZFw6hCm9aBJbRAKfqwn8jvzPYeDSuJYV4fOnZ mxXw== ARC-Message-Signature: i=1; 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id p1-20020adfe601000000b00337bf461385sm6296931wrm.26.2024.01.19.03.36.06 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:36:06 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Peter Maydell Subject: [PULL 13/36] target/arm: Ensure icount is enabled when emulating INST_RETIRED Date: Fri, 19 Jan 2024 12:34:42 +0100 Message-ID: <20240119113507.31951-14-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org pmu_init() register its event checking the pm_event::supported() handler. For INST_RETIRED, the event is only registered and the bit enabled in the PMU Common Event Identification register when icount is enabled as ICOUNT_PRECISE. PMU events are TCG-only, hardware accelerators handle them directly. Unfortunately we register the events in non-TCG builds, leading to linking error such: ld: Undefined symbols: _icount_to_ns, referenced from: _instructions_ns_per in target_arm_helper.c.o clang: error: linker command failed with exit code 1 (use -v to see invocation) As a kludge, give a hint to the compiler by asserting the pm_event::get_count() and pm_event::ns_per_count() handler will only be called under this icount mode. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-ID: <20231208113529.74067-5-philmd@linaro.org> --- target/arm/helper.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 49665bb763..e068d35383 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -954,11 +954,13 @@ static bool instructions_supported(CPUARMState *env) static uint64_t instructions_get_count(CPUARMState *env) { + assert(icount_enabled() == ICOUNT_PRECISE); return (uint64_t)icount_get_raw(); } static int64_t instructions_ns_per(uint64_t icount) { + assert(icount_enabled() == ICOUNT_PRECISE); return icount_to_ns((int64_t)icount); } #endif From patchwork Fri Jan 19 11:34:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763933 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp399520wrq; Fri, 19 Jan 2024 03:43:30 -0800 (PST) X-Google-Smtp-Source: AGHT+IEkTQoHwTcmnsTpuqLQlq76Qib87q+QNelvULfu3dXil5oBu4s7xE1eyrCl9TyBqcxL4ubj X-Received: by 2002:ac8:5a95:0:b0:42a:2a9a:dce9 with SMTP id c21-20020ac85a95000000b0042a2a9adce9mr167969qtc.105.1705664609861; Fri, 19 Jan 2024 03:43:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705664609; cv=none; d=google.com; s=arc-20160816; b=0NnFm3UhGr65gsDgLO9BKwaBlJUIyBCK8VtABv8b7VJ1N3u41T6vtNt/WpwtnGfm96 J4gQMDiLVCCjQVTkiIoGvqHs+6iOubO9YszOcvhiavBs5VSBRCWxd7sFcK9epQP8+fxC U381wGYLLFIoQmL0TgPfE+sYhGxDe4a+V0ITLoGxjgQ/DbBb41EW5xvBKGG3omwV9IRE 36UhXgq2+b5zSkrFYDnwTr7tKGMGJodtx7vCOEVVJXx7ZwpK5oEX2ky+k/G+BE+0SzOa qhsEowgDSxn5hsj5MtWAtwmjF8HJ02qu3n/YLdzZWqxQL0Lp73iLVc3fzcQqalKUqrj3 X1Zw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=KNW2fCmz3vLZacxmspFmUgZW6wt1zZjsUlXpiy/aG9E=; fh=nv7G772+ribqGI5+maNvvILNaKKA/VNlsBf0PDEbPQ0=; b=UNbkVZfl122PFMTLLAt4//fD4/1jsVP5ozx60gMZar1qJGPW6Kafkpw94grSWAiVLN Z7iIk+J5tPEOg881TxwZVLrZw4BMi7sxN64FsaD++yFyKSsc5HmGaUYI6TRcsWZFxYpm uZBsuD98mzAzx5BALzq7HI4x5Z/pGH6iVxBfmSyy3xmg5Nggrf1YATpZ+2KzcjXMrPx0 tWRVk6c9z11HHBe7Msf7tQ/fccKHwAfrP+UorWjCy6aQ13NtKRSvvPNllF1P0CL5uhwF Q/n3FyJb/Rw5uTcAm2okLKloAhl5M83ohVJC/mrcPpksnBCIHoD6crT/1A1nqme8/K0w Xv7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wudcmL2N; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id p1-20020adfe601000000b00337bf461385sm6297076wrm.26.2024.01.19.03.36.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:36:11 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini , Stefan Hajnoczi , Fam Zheng Subject: [PULL 14/36] util/async: Only call icount_notify_exit() if icount is enabled Date: Fri, 19 Jan 2024 12:34:43 +0100 Message-ID: <20240119113507.31951-15-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-ID: <20231208113529.74067-6-philmd@linaro.org> --- accel/tcg/icount-common.c | 4 +++- stubs/icount.c | 2 +- util/async.c | 16 +++++++++------- 3 files changed, 13 insertions(+), 9 deletions(-) diff --git a/accel/tcg/icount-common.c b/accel/tcg/icount-common.c index f0f8fc7f1c..a4a747d1dc 100644 --- a/accel/tcg/icount-common.c +++ b/accel/tcg/icount-common.c @@ -495,7 +495,9 @@ bool icount_configure(QemuOpts *opts, Error **errp) void icount_notify_exit(void) { - if (icount_enabled() && current_cpu) { + assert(icount_enabled()); + + if (current_cpu) { qemu_cpu_kick(current_cpu); qemu_clock_notify(QEMU_CLOCK_VIRTUAL); } diff --git a/stubs/icount.c b/stubs/icount.c index c2c10dfb6b..1eb35b10a8 100644 --- a/stubs/icount.c +++ b/stubs/icount.c @@ -45,7 +45,7 @@ void icount_account_warp_timer(void) { abort(); } - void icount_notify_exit(void) { + abort(); } diff --git a/util/async.c b/util/async.c index 36a8e76ab0..0467890052 100644 --- a/util/async.c +++ b/util/async.c @@ -94,13 +94,15 @@ static void aio_bh_enqueue(QEMUBH *bh, unsigned new_flags) } aio_notify(ctx); - /* - * Workaround for record/replay. - * vCPU execution should be suspended when new BH is set. - * This is needed to avoid guest timeouts caused - * by the long cycles of the execution. - */ - icount_notify_exit(); + if (unlikely(icount_enabled())) { + /* + * Workaround for record/replay. + * vCPU execution should be suspended when new BH is set. + * This is needed to avoid guest timeouts caused + * by the long cycles of the execution. + */ + icount_notify_exit(); + } } /* Only called from aio_bh_poll() and aio_ctx_finalize() */ From patchwork Fri Jan 19 11:34:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763923 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp399159wrq; Fri, 19 Jan 2024 03:42:27 -0800 (PST) X-Google-Smtp-Source: AGHT+IEtoqPYezj92qOQbQJij0l/fUk0mn2J/D0G+fh4xml2ONcbCOkgwgz9V86/UHpwxPxXYcOA X-Received: by 2002:a05:620a:5657:b0:783:54e5:5456 with SMTP id vw23-20020a05620a565700b0078354e55456mr1312435qkn.141.1705664547529; Fri, 19 Jan 2024 03:42:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705664547; cv=none; d=google.com; s=arc-20160816; b=wdl/36LQ6ntgkSAFyDcS15MA7RZVnG1PO16wpCYr+VmGgSpXezhXvAq4xOWrz2TiIv jGoUesn2N0YOrwz0DvkVks3azGnUrvJ+cZ5OyWxE+uKtPVY298KfNYvfPMT/lMMoGFpr rBodUwngweFElb3VZHTfgD3OENdkzlTdfsdyMg9hJihv8/63bkdCmE/wFrWk3A1diCse 6PcQNDeAaTSo+DihkCFHr/EyZAGgYPMfg+hItS2kMoKWIvuN++G5DiFPhIKnL9jQ6c+d K4iIlOne2+dUrfZ9k6H8qAzVeENZQ5bcojGNJlpHMC/SPz7zF04VPhb3Jo0MImPotw33 ob0g== ARC-Message-Signature: i=1; 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id r17-20020a05600c459100b0040e88fbe051sm8678595wmo.48.2024.01.19.03.36.15 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:36:16 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, Samuel Tardieu , =?utf-8?q?C=C3=A9dri?= =?utf-8?q?c_Le_Goater?= , Yoshinori Sato , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , devel@lists.libvirt.org, Magnus Damm Subject: [PULL 15/36] target/sh4: Deprecate the shix machine Date: Fri, 19 Jan 2024 12:34:44 +0100 Message-ID: <20240119113507.31951-16-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Samuel Tardieu The shix machine has been designed and used at Télécom Paris from 2003 to 2010. It had been added to QEMU in 2005 and has not been maintained since. Since nobody is using the physical board anymore nor interested in maintaining the QEMU port, it is time to deprecate it. Signed-off-by: Samuel Tardieu Reviewed-by: Cédric Le Goater Reviewed-by: Yoshinori Sato Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240109083053.2581588-2-sam@rfc1149.net> Signed-off-by: Philippe Mathieu-Daudé --- docs/about/deprecated.rst | 5 +++++ hw/sh4/shix.c | 1 + 2 files changed, 6 insertions(+) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 2e15040246..e6a12c9077 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -269,6 +269,11 @@ Nios II ``10m50-ghrd`` and ``nios2-generic-nommu`` machines (since 8.2) The Nios II architecture is orphan. +``shix`` (since 9.0) +'''''''''''''''''''' + +The machine is no longer in existence and has been long unmaintained +in QEMU. Backend options --------------- diff --git a/hw/sh4/shix.c b/hw/sh4/shix.c index aa812512f0..eb3150b5bc 100644 --- a/hw/sh4/shix.c +++ b/hw/sh4/shix.c @@ -80,6 +80,7 @@ static void shix_machine_init(MachineClass *mc) mc->init = shix_init; mc->is_default = true; mc->default_cpu_type = TYPE_SH7750R_CPU; + mc->deprecation_reason = "old and unmaintained"; } DEFINE_MACHINE("shix", shix_machine_init) From patchwork Fri Jan 19 11:34:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763908 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp397239wrq; Fri, 19 Jan 2024 03:36:41 -0800 (PST) X-Google-Smtp-Source: AGHT+IG/d8vM4YSwQ9osy+H44ezfJIG/3n9eKpKM+jiKi8AzlNqR8GkHH6Vbk3JMFCXBQF9MB5UM X-Received: by 2002:a0c:f144:0:b0:682:24b1:1ea6 with SMTP id y4-20020a0cf144000000b0068224b11ea6mr847942qvl.1.1705664201763; Fri, 19 Jan 2024 03:36:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705664201; cv=none; d=google.com; s=arc-20160816; b=op2GkmhcsveY1yYTtR5W4diGNnVhGuSKWwm5t7/zYh9XWAEa5tLz94FcLMWoLyiTSd bK5snMXkWV9/TrKOhIp8AZV3g3/h6+1Qo0v1jBFTvhpyJqJO9RFn6FRCCIY5nCBnjO2D xS/OoSuDHr3DCmmpHXYD2OzftoPqQTQOyXvNh90xI07r8sysiN5YxytPTeFZeObYlrve O6NvG86IXFHtjVzkEVXyxqvNdMYolDsbK+YXW0GQo+dxy13ZrEulzPSSOy1K/n4AXjIr ElgZDBvmTReGsg/ZwXbUttF5M3fU4Ag4Z+G2FN5m55WaGFdZnmJ1KyWKcOSHMQjSGL6R 1/dw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=4V5MwJ3yzBvCl1jR3LZsLDTSMljFxa13ddLlRCJyMuc=; fh=ljlq2IERA83R/N9I+W7btu6jk8dnbNWtb9KZN1Aqt3M=; b=aVGLj1T0hN8SLi1K7chY8aizX26W6/W8ntt6ebTvfu7CLrSiKMBd6HVirLAXHstu/K kfrp1DtRLoxwvnuSgV7v6BBOTD84ZA/3qzH0NDXheDHyqSYqR+rmGaS72bNmjNQgriIF VFq/ni+CVVy09u4pY3teozjWbLa/4LeH7bUi8lAfQuEWZfCrQr1vCn+UsJ39RvCGYgXq POiYgFjZ/ciFeexedWQR2MnqCbBfi/QSXZNQ1d0rprvjQ7LOrOGWy1obqSOq0rCXxg0m oX5U9hlLLdCTat/XScpyCGGEmrvinclCvSBRMbcqtvp7Moxa9Qq/TnfCgeaXyLPz1hyd KaPA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Yjueg+Bs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id fm16-20020a05600c0c1000b0040ea10178f3sm237439wmb.21.2024.01.19.03.36.20 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:36:20 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, Samuel Tardieu , =?utf-8?q?C=C3=A9dri?= =?utf-8?q?c_Le_Goater?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , devel@lists.libvirt.org, Yoshinori Sato , Magnus Damm , Kevin Wolf , Hanna Reitz Subject: [PULL 16/36] hw/block: Deprecate the TC58128 block device Date: Fri, 19 Jan 2024 12:34:45 +0100 Message-ID: <20240119113507.31951-17-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Samuel Tardieu The 16MiB flash device is only used by the deprecated shix machine. Its code it old and unmaintained, and has never been adapted to the QOM architecture. It still contains debug statements and uses global variables. It is time to deprecate it. Signed-off-by: Samuel Tardieu Reviewed-by: Cédric Le Goater Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240109083053.2581588-3-sam@rfc1149.net> Signed-off-by: Philippe Mathieu-Daudé --- docs/about/deprecated.rst | 2 +- hw/block/tc58128.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index e6a12c9077..15e39f8bbb 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -273,7 +273,7 @@ The Nios II architecture is orphan. '''''''''''''''''''' The machine is no longer in existence and has been long unmaintained -in QEMU. +in QEMU. This also holds for the TC51828 16MiB flash that it uses. Backend options --------------- diff --git a/hw/block/tc58128.c b/hw/block/tc58128.c index d350126b27..6944cf58fa 100644 --- a/hw/block/tc58128.c +++ b/hw/block/tc58128.c @@ -202,6 +202,7 @@ static sh7750_io_device tc58128 = { int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2) { + warn_report_once("The TC58128 flash device is deprecated"); init_dev(&tc58128_devs[0], zone1); init_dev(&tc58128_devs[1], zone2); return sh7750_register_io_device(s, &tc58128); From patchwork Fri Jan 19 11:34:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763911 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp397828wrq; Fri, 19 Jan 2024 03:38:15 -0800 (PST) X-Google-Smtp-Source: AGHT+IH5s5YZHQBz5ZsRuCV3Ws7ZuAARrA6FhzRepDPETu1r8vAWpo3DgxvVObctZB4rmR5EHTN6 X-Received: by 2002:a05:620a:d53:b0:781:7a9e:69ee with SMTP id o19-20020a05620a0d5300b007817a9e69eemr1142892qkl.20.1705664295516; Fri, 19 Jan 2024 03:38:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705664295; cv=none; d=google.com; s=arc-20160816; b=XmjSVLEVubzKgzdY1QgwtMOP29kQ1oJWZUPJMdSAQJci8Fkm2EdJDY07rgJdpnMuBp bgYE5hbfKKAKLVyRYE1RTAovJx93qjZbi+UWxjBi2yxMZUc/GY5DEAu6birLpjSRosKC 706j2Zr1Y/ec49aiekS+o+gbx5XBgJEYOLTkdQAj/Ks2UE3lWsnMgIZqOUJvYkXnFWFv 2Fz7UuWYzErCez0yt4zscee+S0chNPjwWUHoqaBF/H7w9NPYD92k4rZsNhtyI5A8oVD4 XDeppRQZqAGOYFXv8Dl0DyC5BiVg7DFTEzNJ3VnRRK3uP0YdXP4SIkIFAC6dsxBA2t16 zduA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=yC7nFrc+dTucMYfwHpflpLWtq50UrK6Wx6/xFIpSsPw=; fh=596A7qXky/wnqjS7+eZMlBhXgR304MIt1wjOyoM8gmc=; b=s+P16/eQoimk7YUEoXcdhRPh3IcmRKu5YRzvv4RPgG2rfJv0VR16lOXhwzZAtW/dF1 8xZM4gFuEM3tNf6uX/kYEHnNOSAEwJ6HTDFrhWew4gTe9CiMm+Onubo03jgYT9mW+6Do JMVx8Y2gNf3j44A+U2WlwrNr7D2g1LdzwzvCNoE/ycqL0vAFL2Qt+WHNEcheR8XjDarX xT2z5f5MJQTjETgEtQvSIUQjgnasXll7AiKoIFpPse0pmYCwsq/SAXuDlWlh89ah5wam u7Gkdqn7bkfBk76IsJ/Fh18Ew9A+l+LCK3i8QknPdDGvI5KtNSD2+XgKIHmHG/UcYEPj 7c3A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hxSEOLGX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id be13-20020a05600c1e8d00b0040e96a98762sm3062837wmb.17.2024.01.19.03.36.24 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:36:25 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, Bernhard Beschow , David Woodhouse , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Richard Henderson , Eduardo Habkost , "Michael S. Tsirkin" , Marcel Apfelbaum Subject: [PULL 17/36] hw/i386/pc_piix: Make piix_intx_routing_notifier_xen() more device independent Date: Fri, 19 Jan 2024 12:34:46 +0100 Message-ID: <20240119113507.31951-18-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bernhard Beschow This is a follow-up on commit 89965db43cce "hw/isa/piix3: Avoid Xen-specific variant of piix3_write_config()" which introduced piix_intx_routing_notifier_xen(). This function is implemented in board code but accesses the PCI configuration space of the PIIX ISA function to determine the PCI interrupt routes. Avoid this by reusing pci_device_route_intx_to_irq() which makes piix_intx_routing_notifier_xen() more device-agnostic. One remaining improvement would be making piix_intx_routing_notifier_xen() agnostic towards the number of PCI interrupt routes and move it to xen-hvm. This might be useful for possible Q35 Xen efforts but remains a future exercise for now. Signed-off-by: Bernhard Beschow Reviewed-by: David Woodhouse Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240107231623.5282-1-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/pc_piix.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 042c13cdbc..abfcfe4d2b 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -92,13 +92,10 @@ static void piix_intx_routing_notifier_xen(PCIDevice *dev) { int i; - /* Scan for updates to PCI link routes (0x60-0x63). */ + /* Scan for updates to PCI link routes. */ for (i = 0; i < PIIX_NUM_PIRQS; i++) { - uint8_t v = dev->config_read(dev, PIIX_PIRQCA + i, 1); - if (v & 0x80) { - v = 0; - } - v &= 0xf; + const PCIINTxRoute route = pci_device_route_intx_to_irq(dev, i); + const uint8_t v = route.mode == PCI_INTX_ENABLED ? route.irq : 0; xen_set_pci_link_route(i, v); } } From patchwork Fri Jan 19 11:34:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763925 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp399311wrq; Fri, 19 Jan 2024 03:42:52 -0800 (PST) X-Google-Smtp-Source: AGHT+IE7M7ANQGn5M68xgqDBnq01fNLbnKUMSRr8DuepFYjLpQYzoW2Ulx8qEwyuQ3/UUogRLS8x X-Received: by 2002:ac8:7c44:0:b0:42a:4e8:e2cf with SMTP id o4-20020ac87c44000000b0042a04e8e2cfmr2990600qtv.45.1705664572156; Fri, 19 Jan 2024 03:42:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705664572; cv=none; d=google.com; s=arc-20160816; b=WbwhtZ5ao0N1jv3ktn8nOJMxwI4x7mLuIk+XV+Tx4823AsXOTVIZV5a6QqHk3OGkqj 0qFekvl8kqMuGktVo4eNpsqrllvKHGgXC8o62FZlASDpbF+KzUPhY7SopfMz06mrfbPm oR9xG+qyF1tLAsuFz0w/QCjqHsywD1kVs8X7LeTaTcLMaF697FgUCLm6D0gQoQssb/Ta 16xH+0GSD8OYhatAeRpJ7N2DyfsdtrRgpIadhDegUYEMzhIrNOJ7lGcmHx83UNW/xePJ 3b0yTicxNiejlh+EvGZHtR6yf3+8LLHBXXT1zQEO4cYu5WrUcnYonzzqiNqh/vLTciBP akBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Ti8d6bE+nqA1U4OtHFV3Ptf3sJVQ6hdYw2WwbY+h+tg=; fh=H3gzWMxIGcYpnCV3e2JUJoIjDrs6lUKJhouF472DiR4=; b=f4JwjoctRTgkU/KAhgM7uHGw/fsjoO56166PWw/0p9TcF9QbJm7FwxD9QlvB3FfuUq iD5sAmWnD4quoR1LUWDypbGvkVYuMBJjxvh+vAXz45JEt9pjyWfYoFFRO5MQIXqjvrUP q+zJ7TNY4PrTJj3gMJwVyjS7DrJXS5m6u4kiWHdmF4DWN/pt23BJXpl+25sZypesd7Qw bkOxaeUDuZ9432kHAjlHryghoUCPpvGltLRIPeE6wLhO2uJYoiAmp7wpcCU3qmVqnzgP HCbktN+bi6qPb5FQm1smnmKJb9agaaWgN3lW8Se4wdlAu8y8lWbceIKugNRWQJ2iZ5xk BY0g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jtC4+k3X; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id i7-20020a5d6307000000b00337d71bb3c0sm2533871wru.46.2024.01.19.03.36.29 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:36:29 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, Gerd Hoffmann , =?utf-8?q?Philippe_?= =?utf-8?q?Mathieu-Daud=C3=A9?= , Kevin Wolf , Hanna Reitz Subject: [PULL 18/36] hw/pflash: refactor pflash_data_write() Date: Fri, 19 Jan 2024 12:34:47 +0100 Message-ID: <20240119113507.31951-19-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Gerd Hoffmann Move the offset calculation, do it once at the start of the function and let the 'p' variable point directly to the memory location which should be updated. This makes it simpler to update other buffers than pfl->storage in an upcoming patch. No functional change. Signed-off-by: Gerd Hoffmann Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240108160900.104835-2-kraxel@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/block/pflash_cfi01.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index 3e2dc08bd7..67f1c9773a 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -403,33 +403,35 @@ static void pflash_update(PFlashCFI01 *pfl, int offset, static inline void pflash_data_write(PFlashCFI01 *pfl, hwaddr offset, uint32_t value, int width, int be) { - uint8_t *p = pfl->storage; + uint8_t *p; trace_pflash_data_write(pfl->name, offset, width, value, pfl->counter); + p = pfl->storage + offset; + switch (width) { case 1: - p[offset] = value; + p[0] = value; break; case 2: if (be) { - p[offset] = value >> 8; - p[offset + 1] = value; + p[0] = value >> 8; + p[1] = value; } else { - p[offset] = value; - p[offset + 1] = value >> 8; + p[0] = value; + p[1] = value >> 8; } break; case 4: if (be) { - p[offset] = value >> 24; - p[offset + 1] = value >> 16; - p[offset + 2] = value >> 8; - p[offset + 3] = value; + p[0] = value >> 24; + p[1] = value >> 16; + p[2] = value >> 8; + p[3] = value; } else { - p[offset] = value; - p[offset + 1] = value >> 8; - p[offset + 2] = value >> 16; - p[offset + 3] = value >> 24; + p[0] = value; + p[1] = value >> 8; + p[2] = value >> 16; + p[3] = value >> 24; } break; } From patchwork Fri Jan 19 11:34:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763942 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp399871wrq; Fri, 19 Jan 2024 03:44:34 -0800 (PST) X-Google-Smtp-Source: AGHT+IGk03hblaRrNeycCGRrnQpXY4+azdJhOQy6DyWe38pAKja9Tn9CWPS9nxMHvxGGAbrozHoK X-Received: by 2002:a05:622a:20d:b0:42a:bd1:e15d with SMTP id b13-20020a05622a020d00b0042a0bd1e15dmr3052445qtx.22.1705664674471; Fri, 19 Jan 2024 03:44:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705664674; cv=none; d=google.com; s=arc-20160816; b=EC2fjdE8Jw2LkeC2RlProtq5GahnzQs2TkNjOMrafBSveuXaY+HYYfTQu5AAnvT/Ci Zjyh7XZKL9XOf+HIj2VZeTz0yg5XAJFMGaKXY7YgFrapUiwNi4CPfalSvXz98rsRhOsQ LvFKCehaLJ0qkoXXCgI7COWyVIslsZGJWLFR4mn8gVTvqjK9eaJI8Uow6wIX6aqseDqq q4/B1C9kLIQBiWbyx9ZXHGqmC6idplwieVvqx5ryiNmqok4vvPkcj37CdCDA6uzA+Y4K EE6hdGtyrTgW0Ht9R75VLuOgd95S5PssBg7QzpU5bfvIvs2w/bhg9qYqRzblPht0ZXuJ fVTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=XRUeXWyyJ392ZohYjYrcHzpfLxHyioAU0c9SeFp2B+4=; fh=H3gzWMxIGcYpnCV3e2JUJoIjDrs6lUKJhouF472DiR4=; b=ociew855uBvYM6Z0RWpeQRJiVHCAkOvuT3VXb60kExM7kqMQUI2yjkkidLMVHsUodB Hl9VApEKEyPkB2raBwQUEocqPNtbojPfeoqqINrJ5GwQzZ8UM65APnFooXKI0ppYuJoH sy6NqIaqo6+hXbnbjauHsL7184+JFkguiqFkjo6wnSx8wUqrdizhHV3mQdOXykdgHNye mr/WWrNYQz/cm9qn6hJIi3Rqa0w6poKKbsakKwcL0ctQQmK6lmqczNTATUCWJb87tb6u wziMMNPB4C4cA+1T2CifO2fwrnDIbgpuizo3bYwKlmyxa62kEmRE0qehmQm28/Oq9Psu UREw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=U8SlidXb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id r20-20020a05600c35d400b0040d8eca092esm32803585wmq.47.2024.01.19.03.36.33 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:36:34 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, Gerd Hoffmann , =?utf-8?q?Philippe_?= =?utf-8?q?Mathieu-Daud=C3=A9?= , Kevin Wolf , Hanna Reitz Subject: [PULL 19/36] hw/pflash: use ldn_{be,le}_p and stn_{be,le}_p Date: Fri, 19 Jan 2024 12:34:48 +0100 Message-ID: <20240119113507.31951-20-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Gerd Hoffmann Use the helper functions we have to read/write multi-byte values in correct byte order. Suggested-by: Philippe Mathieu-Daudé Signed-off-by: Gerd Hoffmann Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240108160900.104835-3-kraxel@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/block/pflash_cfi01.c | 63 ++++++----------------------------------- 1 file changed, 8 insertions(+), 55 deletions(-) diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index 67f1c9773a..8434a45cab 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -225,34 +225,10 @@ static uint32_t pflash_data_read(PFlashCFI01 *pfl, hwaddr offset, uint32_t ret; p = pfl->storage; - switch (width) { - case 1: - ret = p[offset]; - break; - case 2: - if (be) { - ret = p[offset] << 8; - ret |= p[offset + 1]; - } else { - ret = p[offset]; - ret |= p[offset + 1] << 8; - } - break; - case 4: - if (be) { - ret = p[offset] << 24; - ret |= p[offset + 1] << 16; - ret |= p[offset + 2] << 8; - ret |= p[offset + 3]; - } else { - ret = p[offset]; - ret |= p[offset + 1] << 8; - ret |= p[offset + 2] << 16; - ret |= p[offset + 3] << 24; - } - break; - default: - abort(); + if (be) { + ret = ldn_be_p(p + offset, width); + } else { + ret = ldn_le_p(p + offset, width); } trace_pflash_data_read(pfl->name, offset, width, ret); return ret; @@ -408,34 +384,11 @@ static inline void pflash_data_write(PFlashCFI01 *pfl, hwaddr offset, trace_pflash_data_write(pfl->name, offset, width, value, pfl->counter); p = pfl->storage + offset; - switch (width) { - case 1: - p[0] = value; - break; - case 2: - if (be) { - p[0] = value >> 8; - p[1] = value; - } else { - p[0] = value; - p[1] = value >> 8; - } - break; - case 4: - if (be) { - p[0] = value >> 24; - p[1] = value >> 16; - p[2] = value >> 8; - p[3] = value; - } else { - p[0] = value; - p[1] = value >> 8; - p[2] = value >> 16; - p[3] = value >> 24; - } - break; + if (be) { + stn_be_p(p, width, value); + } else { + stn_le_p(p, width, value); } - } static void pflash_write(PFlashCFI01 *pfl, hwaddr offset, From patchwork Fri Jan 19 11:34:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763914 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp398724wrq; Fri, 19 Jan 2024 03:41:01 -0800 (PST) X-Google-Smtp-Source: AGHT+IH9B5bZZsgXDOW213YOosHD3cAbFQ0qpFedeKlzTIPkRuQTLH0zVQvzt5vZIu/1GOgm8k6y X-Received: by 2002:a81:6941:0:b0:5f8:cf76:e571 with SMTP id e62-20020a816941000000b005f8cf76e571mr2182544ywc.93.1705664460916; Fri, 19 Jan 2024 03:41:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705664460; cv=none; d=google.com; s=arc-20160816; b=gmilwvt9gEUERJmeLZhkKZYONz2j42OCNTzVIFHZBzOils6KJJX3CUvIDliqKJEfYV wZs6BHHIqCNAS/ZKuMTuMhwZQ6HxkOhxNv6c/T9Q1VtU7Brq67+92ESKDkajQHnx3KMe 2fAakapwdzIailP7np7YFbLIWGOP6SkekVwIWJRQfaBl9oDwl1xArO1Zr4Kt5yo0pFEu Tvn1XeRnMhsWNcsKSRJrKvkPQZlogvcrQ6GpQQeJA27l9nuF1KfBfLvcXHmkLE/DIHLd YLXeTPMx2ZH1Thq2R93HQA83ITN7NsUqlum3H4ENt/HB+e6KefL+2hHzE3EBhmdhXmMz 8umg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=1bDfprnFlfsfXltzGvRi/dALsYabn5U/Cj2d9HyuVIo=; fh=H3gzWMxIGcYpnCV3e2JUJoIjDrs6lUKJhouF472DiR4=; b=TVyF+0kkWu3gjdFYZn3a/rJn2xNCPOcNjZ7xy3iZ8mhQhdE4VoD/MHqN0f/8nNHiZS +0fzX3va9i5orvFSuRQT2gTAndm3ZZ2pRo4pUL98f2ady3Rn2n3yEiUbGAg/gUNPYcm8 kIdjaKb2HknnT221d3C0TDx10NtLCM6ZnZLLC87ax12q/VSSfoE2HNQ6zRCSr/0ZqbYl vtOPq4ApqxUFfP8cWbE5pzf2O+V2yYKYQjWcuRKus0sMyaFw7ANG4e/AzIXZ8f0/xfkW BEtHarRhqDC6XFi2ClUvTm3IRf1oXwr8x3A1oDAkq1XBpFWq7XUi3oGPzuMJwU+NFgQY vHDQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=h8Cubpe3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id h5-20020a05600c314500b0040e5e21cd7bsm28384501wmo.11.2024.01.19.03.36.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:36:38 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, Gerd Hoffmann , =?utf-8?q?Philippe_?= =?utf-8?q?Mathieu-Daud=C3=A9?= , Kevin Wolf , Hanna Reitz Subject: [PULL 20/36] hw/pflash: implement update buffer for block writes Date: Fri, 19 Jan 2024 12:34:49 +0100 Message-ID: <20240119113507.31951-21-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Gerd Hoffmann Add an update buffer where all block updates are staged. Flush or discard updates properly, so we should never see half-completed block writes in pflash storage. Drop a bunch of FIXME comments ;) Signed-off-by: Gerd Hoffmann Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240108160900.104835-4-kraxel@redhat.com> Signed-off-by: Philippe Mathieu-Daudé --- hw/block/pflash_cfi01.c | 110 ++++++++++++++++++++++++++++++---------- hw/block/pflash_cfi02.c | 2 +- hw/block/trace-events | 7 ++- 3 files changed, 89 insertions(+), 30 deletions(-) diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index 8434a45cab..f956f8bcf7 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -80,16 +80,39 @@ struct PFlashCFI01 { uint16_t ident3; uint8_t cfi_table[0x52]; uint64_t counter; - unsigned int writeblock_size; + uint32_t writeblock_size; MemoryRegion mem; char *name; void *storage; VMChangeStateEntry *vmstate; bool old_multiple_chip_handling; + + /* block update buffer */ + unsigned char *blk_bytes; + uint32_t blk_offset; }; static int pflash_post_load(void *opaque, int version_id); +static bool pflash_blk_write_state_needed(void *opaque) +{ + PFlashCFI01 *pfl = opaque; + + return (pfl->blk_offset != -1); +} + +static const VMStateDescription vmstate_pflash_blk_write = { + .name = "pflash_cfi01_blk_write", + .version_id = 1, + .minimum_version_id = 1, + .needed = pflash_blk_write_state_needed, + .fields = (const VMStateField[]) { + VMSTATE_VBUFFER_UINT32(blk_bytes, PFlashCFI01, 0, NULL, writeblock_size), + VMSTATE_UINT32(blk_offset, PFlashCFI01), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_pflash = { .name = "pflash_cfi01", .version_id = 1, @@ -101,6 +124,10 @@ static const VMStateDescription vmstate_pflash = { VMSTATE_UINT8(status, PFlashCFI01), VMSTATE_UINT64(counter, PFlashCFI01), VMSTATE_END_OF_LIST() + }, + .subsections = (const VMStateDescription * const []) { + &vmstate_pflash_blk_write, + NULL } }; @@ -376,13 +403,55 @@ static void pflash_update(PFlashCFI01 *pfl, int offset, } } +/* copy current flash content to block update buffer */ +static void pflash_blk_write_start(PFlashCFI01 *pfl, hwaddr offset) +{ + hwaddr mask = ~(pfl->writeblock_size - 1); + + trace_pflash_write_block_start(pfl->name, pfl->counter); + pfl->blk_offset = offset & mask; + memcpy(pfl->blk_bytes, pfl->storage + pfl->blk_offset, + pfl->writeblock_size); +} + +/* commit block update buffer changes */ +static void pflash_blk_write_flush(PFlashCFI01 *pfl) +{ + g_assert(pfl->blk_offset != -1); + trace_pflash_write_block_flush(pfl->name); + memcpy(pfl->storage + pfl->blk_offset, pfl->blk_bytes, + pfl->writeblock_size); + pflash_update(pfl, pfl->blk_offset, pfl->writeblock_size); + pfl->blk_offset = -1; +} + +/* discard block update buffer changes */ +static void pflash_blk_write_abort(PFlashCFI01 *pfl) +{ + trace_pflash_write_block_abort(pfl->name); + pfl->blk_offset = -1; +} + static inline void pflash_data_write(PFlashCFI01 *pfl, hwaddr offset, uint32_t value, int width, int be) { uint8_t *p; - trace_pflash_data_write(pfl->name, offset, width, value, pfl->counter); - p = pfl->storage + offset; + if (pfl->blk_offset != -1) { + /* block write: redirect writes to block update buffer */ + if ((offset < pfl->blk_offset) || + (offset + width > pfl->blk_offset + pfl->writeblock_size)) { + pfl->status |= 0x10; /* Programming error */ + return; + } + trace_pflash_data_write_block(pfl->name, offset, width, value, + pfl->counter); + p = pfl->blk_bytes + (offset - pfl->blk_offset); + } else { + /* write directly to storage */ + trace_pflash_data_write(pfl->name, offset, width, value); + p = pfl->storage + offset; + } if (be) { stn_be_p(p, width, value); @@ -503,9 +572,9 @@ static void pflash_write(PFlashCFI01 *pfl, hwaddr offset, } else { value = extract32(value, 0, pfl->bank_width * 8); } - trace_pflash_write_block(pfl->name, value); pfl->counter = value; pfl->wcycle++; + pflash_blk_write_start(pfl, offset); break; case 0x60: if (cmd == 0xd0) { @@ -536,12 +605,7 @@ static void pflash_write(PFlashCFI01 *pfl, hwaddr offset, switch (pfl->cmd) { case 0xe8: /* Block write */ /* FIXME check @offset, @width */ - if (!pfl->ro) { - /* - * FIXME writing straight to memory is *wrong*. We - * should write to a buffer, and flush it to memory - * only on confirm command (see below). - */ + if (!pfl->ro && (pfl->blk_offset != -1)) { pflash_data_write(pfl, offset, value, width, be); } else { pfl->status |= 0x10; /* Programming error */ @@ -550,18 +614,8 @@ static void pflash_write(PFlashCFI01 *pfl, hwaddr offset, pfl->status |= 0x80; if (!pfl->counter) { - hwaddr mask = pfl->writeblock_size - 1; - mask = ~mask; - trace_pflash_write(pfl->name, "block write finished"); pfl->wcycle++; - if (!pfl->ro) { - /* Flush the entire write buffer onto backing storage. */ - /* FIXME premature! */ - pflash_update(pfl, offset & mask, pfl->writeblock_size); - } else { - pfl->status |= 0x10; /* Programming error */ - } } pfl->counter--; @@ -573,20 +627,17 @@ static void pflash_write(PFlashCFI01 *pfl, hwaddr offset, case 3: /* Confirm mode */ switch (pfl->cmd) { case 0xe8: /* Block write */ - if (cmd == 0xd0) { - /* FIXME this is where we should write out the buffer */ + if ((cmd == 0xd0) && !(pfl->status & 0x10)) { + pflash_blk_write_flush(pfl); pfl->wcycle = 0; pfl->status |= 0x80; } else { - qemu_log_mask(LOG_UNIMP, - "%s: Aborting write to buffer not implemented," - " the data is already written to storage!\n" - "Flash device reset into READ mode.\n", - __func__); + pflash_blk_write_abort(pfl); goto mode_read_array; } break; default: + pflash_blk_write_abort(pfl); goto error_flash; } break; @@ -820,6 +871,9 @@ static void pflash_cfi01_realize(DeviceState *dev, Error **errp) pfl->cmd = 0x00; pfl->status = 0x80; /* WSM ready */ pflash_cfi01_fill_cfi_table(pfl); + + pfl->blk_bytes = g_malloc(pfl->writeblock_size); + pfl->blk_offset = -1; } static void pflash_cfi01_system_reset(DeviceState *dev) @@ -839,6 +893,8 @@ static void pflash_cfi01_system_reset(DeviceState *dev) * This model deliberately ignores this delay. */ pfl->status = 0x80; + + pfl->blk_offset = -1; } static Property pflash_cfi01_properties[] = { diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index 2a99b286b0..6fa56f14c0 100644 --- a/hw/block/pflash_cfi02.c +++ b/hw/block/pflash_cfi02.c @@ -546,7 +546,7 @@ static void pflash_write(void *opaque, hwaddr offset, uint64_t value, } goto reset_flash; } - trace_pflash_data_write(pfl->name, offset, width, value, 0); + trace_pflash_data_write(pfl->name, offset, width, value); if (!pfl->ro) { p = (uint8_t *)pfl->storage + offset; if (pfl->be) { diff --git a/hw/block/trace-events b/hw/block/trace-events index bab21d3a1c..cc9a9f2460 100644 --- a/hw/block/trace-events +++ b/hw/block/trace-events @@ -12,7 +12,8 @@ fdctrl_tc_pulse(int level) "TC pulse: %u" pflash_chip_erase_invalid(const char *name, uint64_t offset) "%s: chip erase: invalid address 0x%" PRIx64 pflash_chip_erase_start(const char *name) "%s: start chip erase" pflash_data_read(const char *name, uint64_t offset, unsigned size, uint32_t value) "%s: data offset:0x%04"PRIx64" size:%u value:0x%04x" -pflash_data_write(const char *name, uint64_t offset, unsigned size, uint32_t value, uint64_t counter) "%s: data offset:0x%04"PRIx64" size:%u value:0x%04x counter:0x%016"PRIx64 +pflash_data_write(const char *name, uint64_t offset, unsigned size, uint32_t value) "%s: data offset:0x%04"PRIx64" size:%u value:0x%04x" +pflash_data_write_block(const char *name, uint64_t offset, unsigned size, uint32_t value, uint64_t counter) "%s: data offset:0x%04"PRIx64" size:%u value:0x%04x counter:0x%016"PRIx64 pflash_device_id(const char *name, uint16_t id) "%s: read device ID: 0x%04x" pflash_device_info(const char *name, uint64_t offset) "%s: read device information offset:0x%04" PRIx64 pflash_erase_complete(const char *name) "%s: sector erase complete" @@ -32,7 +33,9 @@ pflash_unlock0_failed(const char *name, uint64_t offset, uint8_t cmd, uint16_t a pflash_unlock1_failed(const char *name, uint64_t offset, uint8_t cmd) "%s: unlock0 failed 0x%" PRIx64 " 0x%02x" pflash_unsupported_device_configuration(const char *name, uint8_t width, uint8_t max) "%s: unsupported device configuration: device_width:%d max_device_width:%d" pflash_write(const char *name, const char *str) "%s: %s" -pflash_write_block(const char *name, uint32_t value) "%s: block write: bytes:0x%x" +pflash_write_block_start(const char *name, uint32_t value) "%s: block write start: bytes:0x%x" +pflash_write_block_flush(const char *name) "%s: block write flush" +pflash_write_block_abort(const char *name) "%s: block write abort" pflash_write_block_erase(const char *name, uint64_t offset, uint64_t len) "%s: block erase offset:0x%" PRIx64 " bytes:0x%" PRIx64 pflash_write_failed(const char *name, uint64_t offset, uint8_t cmd) "%s: command failed 0x%" PRIx64 " 0x%02x" pflash_write_invalid(const char *name, uint8_t cmd) "%s: invalid write for command 0x%02x" From patchwork Fri Jan 19 11:34:50 2024 Content-Type: text/plain; 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id k9-20020a05600c1c8900b0040d772030c2sm28737333wms.44.2024.01.19.03.36.42 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:36:42 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Pavel Dovgalyuk , Paolo Bonzini Subject: [PULL 21/36] system/replay: Restrict icount to system emulation Date: Fri, 19 Jan 2024 12:34:50 +0100 Message-ID: <20240119113507.31951-22-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-ID: <20231208113529.74067-7-philmd@linaro.org> --- include/sysemu/cpu-timers.h | 2 +- include/sysemu/replay.h | 11 ++++++++--- stubs/icount.c | 19 ------------------- 3 files changed, 9 insertions(+), 23 deletions(-) diff --git a/include/sysemu/cpu-timers.h b/include/sysemu/cpu-timers.h index 3f05f29b10..d86738a378 100644 --- a/include/sysemu/cpu-timers.h +++ b/include/sysemu/cpu-timers.h @@ -30,7 +30,7 @@ typedef enum { ICOUNT_ADAPTATIVE, } ICountMode; -#ifdef CONFIG_TCG +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) extern ICountMode use_icount; #define icount_enabled() (use_icount) #else diff --git a/include/sysemu/replay.h b/include/sysemu/replay.h index 83995ae4bd..f229b2109c 100644 --- a/include/sysemu/replay.h +++ b/include/sysemu/replay.h @@ -1,6 +1,3 @@ -#ifndef SYSEMU_REPLAY_H -#define SYSEMU_REPLAY_H - /* * QEMU replay (system interface) * @@ -11,6 +8,12 @@ * See the COPYING file in the top-level directory. * */ +#ifndef SYSEMU_REPLAY_H +#define SYSEMU_REPLAY_H + +#ifdef CONFIG_USER_ONLY +#error Cannot include this header from user emulation +#endif #include "exec/replay-core.h" #include "qapi/qapi-types-misc.h" @@ -84,12 +87,14 @@ int64_t replay_save_clock(ReplayClockKind kind, int64_t clock, int64_t replay_read_clock(ReplayClockKind kind, int64_t raw_icount); /*! Saves or reads the clock depending on the current replay mode. */ #define REPLAY_CLOCK(clock, value) \ + !icount_enabled() ? (value) : \ (replay_mode == REPLAY_MODE_PLAY \ ? replay_read_clock((clock), icount_get_raw()) \ : replay_mode == REPLAY_MODE_RECORD \ ? replay_save_clock((clock), (value), icount_get_raw()) \ : (value)) #define REPLAY_CLOCK_LOCKED(clock, value) \ + !icount_enabled() ? (value) : \ (replay_mode == REPLAY_MODE_PLAY \ ? replay_read_clock((clock), icount_get_raw_locked()) \ : replay_mode == REPLAY_MODE_RECORD \ diff --git a/stubs/icount.c b/stubs/icount.c index 1eb35b10a8..9f9a59f55b 100644 --- a/stubs/icount.c +++ b/stubs/icount.c @@ -6,10 +6,6 @@ ICountMode use_icount = ICOUNT_DISABLED; -void icount_update(CPUState *cpu) -{ - abort(); -} bool icount_configure(QemuOpts *opts, Error **errp) { /* signal error */ @@ -22,21 +18,6 @@ int64_t icount_get_raw(void) abort(); return 0; } -int64_t icount_get(void) -{ - abort(); - return 0; -} -int64_t icount_to_ns(int64_t icount) -{ - abort(); - return 0; -} -int64_t icount_round(int64_t count) -{ - abort(); - return 0; -} void icount_start_warp_timer(void) { abort(); From patchwork Fri Jan 19 11:34:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763930 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp399460wrq; Fri, 19 Jan 2024 03:43:20 -0800 (PST) X-Google-Smtp-Source: AGHT+IHYMgoygIoTcv4tNQS6P3z+/sqG9LB2NJBNwI9PWB4ju+dpJGAkBEsRajUxoqJb4lZSFFbj X-Received: by 2002:a05:6808:1b2b:b0:3bd:5884:dbbe with SMTP id bx43-20020a0568081b2b00b003bd5884dbbemr2649452oib.54.1705664599939; Fri, 19 Jan 2024 03:43:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705664599; cv=none; d=google.com; s=arc-20160816; b=hbwbK5DZ8CLO7qxFP8t6Fszi3FVNeZtu290E/xJEXbYaR/uzpO8KiTBiNPfJeVc9Zz veRfvKSjS0nJaPnkwJT08uWM0Hho1xpVCtXt2nGzSPY+dUkRKu5MaJyCRwuUgIcXcL5g +cM+hE1pJ6SZhU/j7LA2vybu2acz2QHb9+MwcIB3UIOQli95Cyp1jibF8cuThBYVdm8R yGAg99fTqmVjfa5rM/YqJzZcBEabPsUzj4q/LtrMog8LkPjChIA5y77mwJti05TIDCpR 6fdiDsaKqKwFaxscwUiMkCauQsk0fIWyjfB1EZ33Drfuf9PyuOI7i09V4myd0rOXIPE2 YHFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=YCJoMF/gb5igTgNTbALJP1a0Tru9ZbMYu/Xtk0bIyeE=; fh=0x3oxSDM+3B1iq7MNcEDPiiYDxF4jnBXeQY/LXh8Yxc=; b=k/JDLpkkeLkmvqqT75E1h/TvNhirGK1AuH1XoEJ+oydPw/iUZS7Zf4yDfCzzHElm63 ahPVklgay5pVTc3XjIDFsgppddDDsvwY1qisokOBPTB+OZGYxpcPIk6g+hFN+tGVF2m5 eK5XYzCSfsv2Rr8fSYP1AycQpbORRWl+tcOSSABT1V5yb1A4U8tBgR5LjftmnKh2ZK24 LjVLwdZGzAQ3a/5tZ+ZdwATGQjVPbBFhomSDxP3PSp72loAsnJSgvZ82+p1CshFc0e3C aRRT+BOj+Qj6JjsiAMI4ZS41UhQUMPd31dwuqio4dIsajfwhPMMm/eFOp5xYFqNbn57P VBAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eMGH+etL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id c9-20020adfe749000000b003368d2e729bsm6307532wrn.43.2024.01.19.03.36.47 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:36:47 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Subject: [PULL 22/36] system/watchpoint: Move TCG specific code to accel/tcg/ Date: Fri, 19 Jan 2024 12:34:51 +0100 Message-ID: <20240119113507.31951-23-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Keep system/watchpoint.c accelerator-agnostic by moving TCG specific code to accel/tcg/watchpoint.c. Update meson. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240111162032.43378-1-philmd@linaro.org> --- accel/tcg/watchpoint.c | 143 +++++++++++++++++++++++++++++++++++++++++ system/watchpoint.c | 124 ----------------------------------- accel/tcg/meson.build | 1 + 3 files changed, 144 insertions(+), 124 deletions(-) create mode 100644 accel/tcg/watchpoint.c diff --git a/accel/tcg/watchpoint.c b/accel/tcg/watchpoint.c new file mode 100644 index 0000000000..d3aab11458 --- /dev/null +++ b/accel/tcg/watchpoint.c @@ -0,0 +1,143 @@ +/* + * CPU watchpoints + * + * Copyright (c) 2003 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/main-loop.h" +#include "qemu/error-report.h" +#include "exec/exec-all.h" +#include "exec/translate-all.h" +#include "sysemu/tcg.h" +#include "sysemu/replay.h" +#include "hw/core/tcg-cpu-ops.h" +#include "hw/core/cpu.h" + +/* + * Return true if this watchpoint address matches the specified + * access (ie the address range covered by the watchpoint overlaps + * partially or completely with the address range covered by the + * access). + */ +static inline bool watchpoint_address_matches(CPUWatchpoint *wp, + vaddr addr, vaddr len) +{ + /* + * We know the lengths are non-zero, but a little caution is + * required to avoid errors in the case where the range ends + * exactly at the top of the address space and so addr + len + * wraps round to zero. + */ + vaddr wpend = wp->vaddr + wp->len - 1; + vaddr addrend = addr + len - 1; + + return !(addr > wpend || wp->vaddr > addrend); +} + +/* Return flags for watchpoints that match addr + prot. */ +int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len) +{ + CPUWatchpoint *wp; + int ret = 0; + + QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { + if (watchpoint_address_matches(wp, addr, len)) { + ret |= wp->flags; + } + } + return ret; +} + +/* Generate a debug exception if a watchpoint has been hit. */ +void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, + MemTxAttrs attrs, int flags, uintptr_t ra) +{ + CPUClass *cc = CPU_GET_CLASS(cpu); + CPUWatchpoint *wp; + + assert(tcg_enabled()); + if (cpu->watchpoint_hit) { + /* + * We re-entered the check after replacing the TB. + * Now raise the debug interrupt so that it will + * trigger after the current instruction. + */ + bql_lock(); + cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG); + bql_unlock(); + return; + } + + if (cc->tcg_ops->adjust_watchpoint_address) { + /* this is currently used only by ARM BE32 */ + addr = cc->tcg_ops->adjust_watchpoint_address(cpu, addr, len); + } + + assert((flags & ~BP_MEM_ACCESS) == 0); + QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { + int hit_flags = wp->flags & flags; + + if (hit_flags && watchpoint_address_matches(wp, addr, len)) { + if (replay_running_debug()) { + /* + * replay_breakpoint reads icount. + * Force recompile to succeed, because icount may + * be read only at the end of the block. + */ + if (!cpu->neg.can_do_io) { + /* Force execution of one insn next time. */ + cpu->cflags_next_tb = 1 | CF_NOIRQ | curr_cflags(cpu); + cpu_loop_exit_restore(cpu, ra); + } + /* + * Don't process the watchpoints when we are + * in a reverse debugging operation. + */ + replay_breakpoint(); + return; + } + + wp->flags |= hit_flags << BP_HIT_SHIFT; + wp->hitaddr = MAX(addr, wp->vaddr); + wp->hitattrs = attrs; + + if (wp->flags & BP_CPU + && cc->tcg_ops->debug_check_watchpoint + && !cc->tcg_ops->debug_check_watchpoint(cpu, wp)) { + wp->flags &= ~BP_WATCHPOINT_HIT; + continue; + } + cpu->watchpoint_hit = wp; + + mmap_lock(); + /* This call also restores vCPU state */ + tb_check_watchpoint(cpu, ra); + if (wp->flags & BP_STOP_BEFORE_ACCESS) { + cpu->exception_index = EXCP_DEBUG; + mmap_unlock(); + cpu_loop_exit(cpu); + } else { + /* Force execution of one insn next time. */ + cpu->cflags_next_tb = 1 | CF_NOIRQ | curr_cflags(cpu); + mmap_unlock(); + cpu_loop_exit_noexc(cpu); + } + } else { + wp->flags &= ~BP_WATCHPOINT_HIT; + } + } +} diff --git a/system/watchpoint.c b/system/watchpoint.c index b76007ebf6..2aa2a9ea63 100644 --- a/system/watchpoint.c +++ b/system/watchpoint.c @@ -18,13 +18,8 @@ */ #include "qemu/osdep.h" -#include "qemu/main-loop.h" #include "qemu/error-report.h" #include "exec/exec-all.h" -#include "exec/translate-all.h" -#include "sysemu/tcg.h" -#include "sysemu/replay.h" -#include "hw/core/tcg-cpu-ops.h" #include "hw/core/cpu.h" /* Add a watchpoint. */ @@ -103,122 +98,3 @@ void cpu_watchpoint_remove_all(CPUState *cpu, int mask) } } } - -#ifdef CONFIG_TCG - -/* - * Return true if this watchpoint address matches the specified - * access (ie the address range covered by the watchpoint overlaps - * partially or completely with the address range covered by the - * access). - */ -static inline bool watchpoint_address_matches(CPUWatchpoint *wp, - vaddr addr, vaddr len) -{ - /* - * We know the lengths are non-zero, but a little caution is - * required to avoid errors in the case where the range ends - * exactly at the top of the address space and so addr + len - * wraps round to zero. - */ - vaddr wpend = wp->vaddr + wp->len - 1; - vaddr addrend = addr + len - 1; - - return !(addr > wpend || wp->vaddr > addrend); -} - -/* Return flags for watchpoints that match addr + prot. */ -int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len) -{ - CPUWatchpoint *wp; - int ret = 0; - - QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { - if (watchpoint_address_matches(wp, addr, len)) { - ret |= wp->flags; - } - } - return ret; -} - -/* Generate a debug exception if a watchpoint has been hit. */ -void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, - MemTxAttrs attrs, int flags, uintptr_t ra) -{ - CPUClass *cc = CPU_GET_CLASS(cpu); - CPUWatchpoint *wp; - - assert(tcg_enabled()); - if (cpu->watchpoint_hit) { - /* - * We re-entered the check after replacing the TB. - * Now raise the debug interrupt so that it will - * trigger after the current instruction. - */ - bql_lock(); - cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG); - bql_unlock(); - return; - } - - if (cc->tcg_ops->adjust_watchpoint_address) { - /* this is currently used only by ARM BE32 */ - addr = cc->tcg_ops->adjust_watchpoint_address(cpu, addr, len); - } - - assert((flags & ~BP_MEM_ACCESS) == 0); - QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) { - int hit_flags = wp->flags & flags; - - if (hit_flags && watchpoint_address_matches(wp, addr, len)) { - if (replay_running_debug()) { - /* - * replay_breakpoint reads icount. - * Force recompile to succeed, because icount may - * be read only at the end of the block. - */ - if (!cpu->neg.can_do_io) { - /* Force execution of one insn next time. */ - cpu->cflags_next_tb = 1 | CF_NOIRQ | curr_cflags(cpu); - cpu_loop_exit_restore(cpu, ra); - } - /* - * Don't process the watchpoints when we are - * in a reverse debugging operation. - */ - replay_breakpoint(); - return; - } - - wp->flags |= hit_flags << BP_HIT_SHIFT; - wp->hitaddr = MAX(addr, wp->vaddr); - wp->hitattrs = attrs; - - if (wp->flags & BP_CPU - && cc->tcg_ops->debug_check_watchpoint - && !cc->tcg_ops->debug_check_watchpoint(cpu, wp)) { - wp->flags &= ~BP_WATCHPOINT_HIT; - continue; - } - cpu->watchpoint_hit = wp; - - mmap_lock(); - /* This call also restores vCPU state */ - tb_check_watchpoint(cpu, ra); - if (wp->flags & BP_STOP_BEFORE_ACCESS) { - cpu->exception_index = EXCP_DEBUG; - mmap_unlock(); - cpu_loop_exit(cpu); - } else { - /* Force execution of one insn next time. */ - cpu->cflags_next_tb = 1 | CF_NOIRQ | curr_cflags(cpu); - mmap_unlock(); - cpu_loop_exit_noexc(cpu); - } - } else { - wp->flags &= ~BP_WATCHPOINT_HIT; - } - } -} - -#endif /* CONFIG_TCG */ diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build index d25638d6c1..c15ac9ac8f 100644 --- a/accel/tcg/meson.build +++ b/accel/tcg/meson.build @@ -24,6 +24,7 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss) specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files( 'cputlb.c', + 'watchpoint.c', )) system_ss.add(when: ['CONFIG_TCG'], if_true: files( From patchwork Fri Jan 19 11:34:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763915 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp398756wrq; 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id l9-20020a056000022900b00337d980a68asm1941011wrz.106.2024.01.19.03.36.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:36:51 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini Subject: [PULL 23/36] cpus: Restrict 'start-powered-off' property to system emulation Date: Fri, 19 Jan 2024 12:34:52 +0100 Message-ID: <20240119113507.31951-24-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22c; envelope-from=philmd@linaro.org; helo=mail-lj1-x22c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since the CPUState::start-powered-off property is irrelevant to user emulation, restrict it to system emulation. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20240111161817.43150-1-philmd@linaro.org> --- cpu-target.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/cpu-target.c b/cpu-target.c index d51adfd7e3..f6e07c3deb 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -204,6 +204,7 @@ static Property cpu_common_props[] = { DEFINE_PROP_END_OF_LIST(), }; +#ifndef CONFIG_USER_ONLY static bool cpu_get_start_powered_off(Object *obj, Error **errp) { CPUState *cpu = CPU(obj); @@ -215,12 +216,13 @@ static void cpu_set_start_powered_off(Object *obj, bool value, Error **errp) CPUState *cpu = CPU(obj); cpu->start_powered_off = value; } +#endif void cpu_class_init_props(DeviceClass *dc) { +#ifndef CONFIG_USER_ONLY ObjectClass *oc = OBJECT_CLASS(dc); - device_class_set_props(dc, cpu_common_props); /* * We can't use DEFINE_PROP_BOOL in the Property array for this * property, because we want this to be settable after realize. @@ -228,6 +230,9 @@ void cpu_class_init_props(DeviceClass *dc) object_class_property_add_bool(oc, "start-powered-off", cpu_get_start_powered_off, cpu_set_start_powered_off); +#endif + + device_class_set_props(dc, cpu_common_props); } void cpu_exec_initfn(CPUState *cpu) From patchwork Fri Jan 19 11:34:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763916 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp398759wrq; Fri, 19 Jan 2024 03:41:08 -0800 (PST) X-Google-Smtp-Source: AGHT+IHtscVVIv7UZZvUnvH35RRFcKNzbp7UJNco1QmZ5nJF5YRdk2+WBz4pmML6XN+s6oe/+9gi X-Received: by 2002:a05:622a:210:b0:429:8f67:5225 with SMTP id b16-20020a05622a021000b004298f675225mr2904956qtx.92.1705664468670; Fri, 19 Jan 2024 03:41:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705664468; cv=none; d=google.com; s=arc-20160816; b=nxb+Qzkfm5J/5soWDe3V1JKXDYqYdJvhgH5KEUiiXyuBsmzm/ICB7Ulnqn6nOFazUv 2zos8twKQqYLwx3Iqx48yyBV3BkedmjePug4cnOOWDqlaPwjBCiLPxcdwSXd/KGogRdk vEQzEePKJ2jPRHIvFIHwI+XsWguLDinMRlI2W97K+nCv6Lhsa5wnABJnfyqZp/pFW94N 5QLA0CGVq7IR0+FxgsB0FSZDbwQ1fZNw54HcyD0mEF8D5f6OUYcMWRoYlcsOSr/xjdk7 N9H8kzP5XRnubALQUNdeDla9VlRHVAH4O+osG4MRgPduQt+205qGhvH+JHIk0c0HJzcD q+cw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=wl7mxe76TBuEvV14rO6cbAGreHvKKNVNpG5LWETBxoQ=; fh=/0aowDTBust7MhosflTPkHrz6StB6kNrFDkiv8gL7GU=; b=a+2aIvvD05vbsF4hVyXWqN8/brXBZPlwjUaEK/dIbQO+MWAU8DXeZp2tn3s1WWGszX eY8jjHhxhfqGt5lQOxHH5jAmq4UfA9L5YaxfzDm4juE52lRVFlRABuCMGcwYTKuI9Etg VxueNenLdkXzP5XFylY2r78F/DjmDTJSORyLIFEgvIi+DnJ/+GYGUQtGASwABFeOYCxj qoMi5OuzcBM0KB1uMvfwg4JlQUKKrqhmRFAzFLHtZF5ImVi8Nt3Z3FXMPOQpljHsqNpF V3QMAbDZBfPveqTZhOZOYjFIPXeBSCAu86cRPjOT03jJP0w4NWMLvborGYgegZO+Bomb 5pbw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HYyucrNS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id o2-20020a5d4a82000000b00338ca0ada22sm1402247wrq.111.2024.01.19.03.36.55 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:36:56 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Daniel Henrique Barboza , Alistair Francis , Richard Henderson , Paolo Bonzini Subject: [PULL 24/36] accel: Rename accel_init_ops_interfaces() to include 'system' Date: Fri, 19 Jan 2024 12:34:53 +0100 Message-ID: <20240119113507.31951-25-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org accel_init_ops_interfaces() is system specific, so rename it as accel_system_init_ops_interfaces() to ease navigating the code. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20240111120221.35072-2-philmd@linaro.org> --- accel/accel-system.h | 2 +- accel/accel-system.c | 2 +- accel/accel-target.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/accel/accel-system.h b/accel/accel-system.h index d41c62f21b..2d37c73c97 100644 --- a/accel/accel-system.h +++ b/accel/accel-system.h @@ -10,6 +10,6 @@ #ifndef ACCEL_SYSTEM_H #define ACCEL_SYSTEM_H -void accel_init_ops_interfaces(AccelClass *ac); +void accel_system_init_ops_interfaces(AccelClass *ac); #endif /* ACCEL_SYSTEM_H */ diff --git a/accel/accel-system.c b/accel/accel-system.c index fa8f43757c..f6c947dd82 100644 --- a/accel/accel-system.c +++ b/accel/accel-system.c @@ -62,7 +62,7 @@ void accel_setup_post(MachineState *ms) } /* initialize the arch-independent accel operation interfaces */ -void accel_init_ops_interfaces(AccelClass *ac) +void accel_system_init_ops_interfaces(AccelClass *ac) { const char *ac_name; char *ops_name; diff --git a/accel/accel-target.c b/accel/accel-target.c index 7e3cbde5df..08626c00c2 100644 --- a/accel/accel-target.c +++ b/accel/accel-target.c @@ -104,7 +104,7 @@ static void accel_init_cpu_interfaces(AccelClass *ac) void accel_init_interfaces(AccelClass *ac) { #ifndef CONFIG_USER_ONLY - accel_init_ops_interfaces(ac); + accel_system_init_ops_interfaces(ac); #endif /* !CONFIG_USER_ONLY */ accel_init_cpu_interfaces(ac); From patchwork Fri Jan 19 11:34:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763928 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp399356wrq; Fri, 19 Jan 2024 03:42:59 -0800 (PST) X-Google-Smtp-Source: AGHT+IFV+YqcFbMJ10QPXcF2tSQRnqG0O27hDQ2WQi4Ta/jjZ1vCD0TI2ocli9NEe0zvjwwu/RUY X-Received: by 2002:a05:6122:d99:b0:4b6:ce08:cc76 with SMTP id bc25-20020a0561220d9900b004b6ce08cc76mr1832566vkb.9.1705664578887; Fri, 19 Jan 2024 03:42:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705664578; cv=none; d=google.com; s=arc-20160816; b=dkVnRLU/qYzrhcgp4DS0lssWSJnDKVSLfiOEr+3rx//zQE9WA9ylyJRDQRzTvnIrbf wpFKyiYUV3lPhBjygBrvxThbO4Bqs1d8x+zZjmSMXXbqlLQcSBbe09zsANHT+Wlon7Vr PFzNZvhgl7zBVkZGu0Gdd0Wx2/SFWyRiv6QZCMnNoyBQ6NCHfVbPyKylg3lK2b6W0xWf PkHu78DsC32JV5baw41saX/TJFcYNIb//dYZ1OC5uMYuKVvDdQ9D1y740cxptYxZsjTQ +VunPixTBT1hO4GMJ8ll9mMqI8MygGOH+Yx4BDPC2Sxl9AEiAXATkza76nubTjmO24o9 CMyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=CZOOriEuiBAbNMMhhXm8QlidphHeh3aLspyqOz5Ajks=; fh=tLx+m0BWvCiM+lTZagO/5rmwTauxl8DHhQS+XJFibX4=; b=Acz3fbUxgusP56FJAXubbL/4p6T4lCn5HzMtR/OPZT1TUB24c7RU7Qem3on2YVEduZ gjVpwIaEe/LmKPmcCakurwtkkr5G+OZjpI1tv/WFr299UGLd9Pk3nbiGzV4tXIHGtwA4 b/TSpi7AxWA29InuwFZ8l/Vv3M6Mahur88D+qxtFymcdU5qBljS8i22SKjEflkqEl8sM HG0tS4ifqhJzTwfpx7w+4bbwYxjNk6hpDb1w1+6CTkYGOj+RxVr5XHhcNce0OsJLlUjn iFnrNVpkQNa4BIV7KNcsfp/8013wqABUMHuB+NZ4MWJrbimb8PQkLox4zrlL1N+afhl0 m+OA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wR+AkuG9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id jg1-20020a05600ca00100b0040d4e1393dcsm32251084wmb.20.2024.01.19.03.37.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:37:00 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Daniel Henrique Barboza , Eduardo Habkost , Marcel Apfelbaum , Yanan Wang Subject: [PULL 25/36] hw/core/cpu: Rename cpu_class_init() to include 'common' Date: Fri, 19 Jan 2024 12:34:54 +0100 Message-ID: <20240119113507.31951-26-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org cpu_class_init() is common, so rename it as cpu_common_class_init() to ease navigating the code. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza Message-ID: <20240111120221.35072-3-philmd@linaro.org> --- hw/core/cpu-common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 3ccfe882e2..67db07741d 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -273,7 +273,7 @@ static int64_t cpu_common_get_arch_id(CPUState *cpu) return cpu->cpu_index; } -static void cpu_class_init(ObjectClass *klass, void *data) +static void cpu_common_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); ResettableClass *rc = RESETTABLE_CLASS(klass); @@ -304,7 +304,7 @@ static const TypeInfo cpu_type_info = { .instance_finalize = cpu_common_finalize, .abstract = true, .class_size = sizeof(CPUClass), - .class_init = cpu_class_init, + .class_init = cpu_common_class_init, }; static void cpu_register_types(void) From patchwork Fri Jan 19 11:34:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763937 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp399691wrq; Fri, 19 Jan 2024 03:44:04 -0800 (PST) X-Google-Smtp-Source: AGHT+IEVbC46QB200sSgLMukusK4Biacga5sXjHjECyVUs/9F7ilfDC55Zpt5u7+Fl4Dw+8tufjC X-Received: by 2002:a05:6214:1c8b:b0:681:14ff:3e82 with SMTP id ib11-20020a0562141c8b00b0068114ff3e82mr2406790qvb.41.1705664643977; Fri, 19 Jan 2024 03:44:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705664643; cv=none; d=google.com; s=arc-20160816; b=PoBso8YojlVUhuLbpVA+OAgh+523Y/GHR1g/P4Xx4Y0wkwc7KjteVlvK4EwO44o98f dPIPUa4PPI1+J6DT+Fmpczx7AloL2r2bXumpYKlxuotDYwxzfAM4zADnhu90cPO6cptR xPq6dFeQ/dYP9VXaRa399y8/qEdlgueEu45zKmtUDph1feHfNMDc9vrrr7O+DRBN7oGl TtSzINMtmeVmzHOrnN/REbVjQUY9GjXLtaHOKeQiJXXWsEkyUm+G5/p0ZOBCxDxUYhzg 3OP9bV4zBdNCGOmUErY3t7k05CI5/GvCiuzwag9SVrQGrfB2gQpIPHI08TQUIIyB2Bd1 AzNw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=A62n8Zh8RpmMErwo1MEyf8UlsAdx9GAivnN08aL/XMQ=; fh=XLakvtB6oC5IMcaqtPCkqGbS478DvU9x3LtFcAk/a0g=; b=Y3AvQlJaVBUKbztjVXsVKIPqdPc/p+6+Ivr0JEf/AnKvncGGj5kd89L6bHp8vdz+3V nhpEHoMoZlpSeI0AngphrxL/T1vbe1+HHTehKlRrSLQVTUJ2N4tZ9wuLW7FQl912hYL3 3/MY8ftC1NtWcEBhG8ZYa4ypXouErMcaFHt9MUJpgW8ptqgoI6RjSyMKKQGOwFG7lwF4 BV/EgWrl1GkhJpLi8/AWPKS8gaWDOMvaa/0IcagNNkxsm419Xt5MX2ZGyRwXiX9F6bc/ EbXRjQVpLNE4SQ1TbVlSkOvJnNlYmJyZcwBwNlyNHxxURfBqrCdGspjWbbsQpcLk6qiH kwXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eiUOTzRx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id x16-20020adfdd90000000b00337d6539d52sm2974212wrl.18.2024.01.19.03.37.05 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:37:05 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Thomas Huth , Eric Farman , Halil Pasic , Christian Borntraeger , Richard Henderson , David Hildenbrand , Ilya Leoshkevich Subject: [PULL 26/36] hw/s390x: Rename cpu_class_init() to include 'sclp' Date: Fri, 19 Jan 2024 12:34:55 +0100 Message-ID: <20240119113507.31951-27-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org cpu_class_init() is specific to s390x SCLP, so rename it as sclp_cpu_class_init() (as other names in this file) to ease navigating the code. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Eric Farman Message-ID: <20240111120221.35072-4-philmd@linaro.org> --- hw/s390x/sclpcpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/s390x/sclpcpu.c b/hw/s390x/sclpcpu.c index f2b1a4b037..fa79891f5a 100644 --- a/hw/s390x/sclpcpu.c +++ b/hw/s390x/sclpcpu.c @@ -73,7 +73,7 @@ static int read_event_data(SCLPEvent *event, EventBufferHeader *evt_buf_hdr, return 1; } -static void cpu_class_init(ObjectClass *oc, void *data) +static void sclp_cpu_class_init(ObjectClass *oc, void *data) { SCLPEventClass *k = SCLP_EVENT_CLASS(oc); DeviceClass *dc = DEVICE_CLASS(oc); @@ -94,7 +94,7 @@ static const TypeInfo sclp_cpu_info = { .name = TYPE_SCLP_CPU_HOTPLUG, .parent = TYPE_SCLP_EVENT, .instance_size = sizeof(SCLPEvent), - .class_init = cpu_class_init, + .class_init = sclp_cpu_class_init, .class_size = sizeof(SCLPEventClass), }; From patchwork Fri Jan 19 11:34:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763936 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp399687wrq; Fri, 19 Jan 2024 03:44:03 -0800 (PST) X-Google-Smtp-Source: AGHT+IF5eHTDT7BbQsEAMVHILSEfwZRc7fZ5N/E8/IMojyz78cSIA3G63lI2I9LqeDTXrWCSUWg4 X-Received: by 2002:a05:622a:550:b0:429:81df:888c with SMTP id m16-20020a05622a055000b0042981df888cmr2258730qtx.70.1705664642996; Fri, 19 Jan 2024 03:44:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705664642; cv=none; d=google.com; s=arc-20160816; b=x4M3pGVwwZUYU7KU4ylA3NJ7I0/qdBNIypNBvN2F0AE25sQ3fwEigXYaLRvWtL29yK UO918bDN0pqHE+8gVcLhyG33zfutOtyLwMT4K3vKKB/p7s1rq36tAsh3GWYuRPpgS/o9 EQr+sBFdaPe0JSQQvarIzuNHz0C6mB8o4jNCZ6qExmR0s8oI3gOtEFuoQOjgDs68kqhu aBMmpIAb+8m40gNeu5EXLSYc6NeMQU/tW6PpWrP+HC4ppna7/pja1S8v/OPpoxg4vtwz RQYpSYbnjTzUAgYFpSZrzfRh6wxKhe36QHBErqgOauq0DcPk6q70w+/ey2dxYYWU00wN 7oFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ejw3kKr4hdUsfv2MTceZhktCuWg4EKgMF+epEyFWJEQ=; fh=0tTSGURN6LtpKxKAmn7BdU0xqkUybLE7Sw1KoXMDz1E=; b=Grll3y42UqJ3MmZsx/Uel13kWf4bRWIhPenE4RkRxUEz+RY9AnF35EnOLZ3jc7Y3sw /LN5/YIX5+9CPkqXleJvPoEskNyL9HGbuw8/5oFDY7I+1U18JqynLKe78b5jxCgGiD1C IBGzpqVZddOe0kdW6SlsdGjZEsfjc/KgVXWwQLVOO3p146+9jpeQcbZh9ZxkD6u+RIrz p6pJA4j3gqWIPmfCKTAp6MUDwmSd1X9duyqr4+8zxu3Scvzj85qamwvp+jehz3juBHVK Ud8ZrsNgVib4oYbGSHjidnokurItgKfRYmQ+qWzDwsFC+mk5C4B1skmPdkb4w3NDfyuu H13g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PiTOekWj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id d16-20020adff2d0000000b0033668b27f8fsm6337529wrp.4.2024.01.19.03.37.09 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:37:10 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Michael Tokarev , Paolo Bonzini , Richard Henderson , Eduardo Habkost Subject: [PULL 27/36] target/i386: Rename tcg_cpu_FOO() to include 'x86' Date: Fri, 19 Jan 2024 12:34:56 +0100 Message-ID: <20240119113507.31951-28-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The tcg_cpu_FOO() names are x86 specific, so rename them as x86_tcg_cpu_FOO() (as other names in this file) to ease navigating the code. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Michael Tokarev Message-ID: <20240111120221.35072-5-philmd@linaro.org> --- target/i386/tcg/tcg-cpu.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 6e881e9e27..e56489caea 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -114,18 +114,18 @@ static const struct TCGCPUOps x86_tcg_ops = { #endif /* !CONFIG_USER_ONLY */ }; -static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) +static void x86_tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) { /* for x86, all cpus use the same set of operations */ cc->tcg_ops = &x86_tcg_ops; } -static void tcg_cpu_class_init(CPUClass *cc) +static void x86_tcg_cpu_class_init(CPUClass *cc) { - cc->init_accel_cpu = tcg_cpu_init_ops; + cc->init_accel_cpu = x86_tcg_cpu_init_ops; } -static void tcg_cpu_xsave_init(void) +static void x86_tcg_cpu_xsave_init(void) { #define XO(bit, field) \ x86_ext_save_areas[bit].offset = offsetof(X86XSaveArea, field); @@ -147,25 +147,25 @@ static void tcg_cpu_xsave_init(void) * TCG-specific defaults that override cpudef models when using TCG. * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. */ -static PropValue tcg_default_props[] = { +static PropValue x86_tcg_default_props[] = { { "vme", "off" }, { NULL, NULL }, }; -static void tcg_cpu_instance_init(CPUState *cs) +static void x86_tcg_cpu_instance_init(CPUState *cs) { X86CPU *cpu = X86_CPU(cs); X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); if (xcc->model) { /* Special cases not set in the X86CPUDefinition structs: */ - x86_cpu_apply_props(cpu, tcg_default_props); + x86_cpu_apply_props(cpu, x86_tcg_default_props); } - tcg_cpu_xsave_init(); + x86_tcg_cpu_xsave_init(); } -static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data) +static void x86_tcg_cpu_accel_class_init(ObjectClass *oc, void *data) { AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); @@ -173,18 +173,18 @@ static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data) acc->cpu_target_realize = tcg_cpu_realizefn; #endif /* CONFIG_USER_ONLY */ - acc->cpu_class_init = tcg_cpu_class_init; - acc->cpu_instance_init = tcg_cpu_instance_init; + acc->cpu_class_init = x86_tcg_cpu_class_init; + acc->cpu_instance_init = x86_tcg_cpu_instance_init; } -static const TypeInfo tcg_cpu_accel_type_info = { +static const TypeInfo x86_tcg_cpu_accel_type_info = { .name = ACCEL_CPU_NAME("tcg"), .parent = TYPE_ACCEL_CPU, - .class_init = tcg_cpu_accel_class_init, + .class_init = x86_tcg_cpu_accel_class_init, .abstract = true, }; -static void tcg_cpu_accel_register_types(void) +static void x86_tcg_cpu_accel_register_types(void) { - type_register_static(&tcg_cpu_accel_type_info); + type_register_static(&x86_tcg_cpu_accel_type_info); } -type_init(tcg_cpu_accel_register_types); +type_init(x86_tcg_cpu_accel_register_types); From patchwork Fri Jan 19 11:34:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763939 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp399737wrq; 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id f11-20020adff98b000000b00337d5cd0d8asm3184111wrr.90.2024.01.19.03.37.14 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:37:14 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Daniel Henrique Barboza , Alistair Francis , Palmer Dabbelt , Bin Meng , Weiwei Li , Liu Zhiwei Subject: [PULL 28/36] target/riscv: Rename tcg_cpu_FOO() to include 'riscv' Date: Fri, 19 Jan 2024 12:34:57 +0100 Message-ID: <20240119113507.31951-29-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The tcg_cpu_FOO() names are riscv specific, so rename them as riscv_tcg_cpu_FOO() (as other names in this file) to ease navigating the code. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20240111120221.35072-6-philmd@linaro.org> --- target/riscv/tcg/tcg-cpu.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 14133ff665..994ca1cdf9 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -929,7 +929,7 @@ static bool riscv_cpu_is_vendor(Object *cpu_obj) * -> cpu_exec_realizefn() * -> tcg_cpu_realize() (via accel_cpu_common_realize()) */ -static bool tcg_cpu_realize(CPUState *cs, Error **errp) +static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) { RISCVCPU *cpu = RISCV_CPU(cs); Error *local_err = NULL; @@ -1372,7 +1372,7 @@ static bool riscv_cpu_has_max_extensions(Object *cpu_obj) return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL; } -static void tcg_cpu_instance_init(CPUState *cs) +static void riscv_tcg_cpu_instance_init(CPUState *cs) { RISCVCPU *cpu = RISCV_CPU(cs); Object *obj = OBJECT(cpu); @@ -1386,7 +1386,7 @@ static void tcg_cpu_instance_init(CPUState *cs) } } -static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) +static void riscv_tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) { /* * All cpus use the same set of operations. @@ -1394,30 +1394,30 @@ static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) cc->tcg_ops = &riscv_tcg_ops; } -static void tcg_cpu_class_init(CPUClass *cc) +static void riscv_tcg_cpu_class_init(CPUClass *cc) { - cc->init_accel_cpu = tcg_cpu_init_ops; + cc->init_accel_cpu = riscv_tcg_cpu_init_ops; } -static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data) +static void riscv_tcg_cpu_accel_class_init(ObjectClass *oc, void *data) { AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); - acc->cpu_class_init = tcg_cpu_class_init; - acc->cpu_instance_init = tcg_cpu_instance_init; - acc->cpu_target_realize = tcg_cpu_realize; + acc->cpu_class_init = riscv_tcg_cpu_class_init; + acc->cpu_instance_init = riscv_tcg_cpu_instance_init; + acc->cpu_target_realize = riscv_tcg_cpu_realize; } -static const TypeInfo tcg_cpu_accel_type_info = { +static const TypeInfo riscv_tcg_cpu_accel_type_info = { .name = ACCEL_CPU_NAME("tcg"), .parent = TYPE_ACCEL_CPU, - .class_init = tcg_cpu_accel_class_init, + .class_init = riscv_tcg_cpu_accel_class_init, .abstract = true, }; -static void tcg_cpu_accel_register_types(void) +static void riscv_tcg_cpu_accel_register_types(void) { - type_register_static(&tcg_cpu_accel_type_info); + type_register_static(&riscv_tcg_cpu_accel_type_info); } -type_init(tcg_cpu_accel_register_types); +type_init(riscv_tcg_cpu_accel_register_types); From patchwork Fri Jan 19 11:34:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763931 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp399480wrq; Fri, 19 Jan 2024 03:43:23 -0800 (PST) X-Google-Smtp-Source: AGHT+IHVhGpH7M151RSHoU8oXHY7dTU2mUo/1DhdKCyvKOzoO2RKuRsVKHfKeU9QkkaXtVz/YcRe X-Received: by 2002:a05:622a:3cd:b0:429:f3f5:ac9b with SMTP id k13-20020a05622a03cd00b00429f3f5ac9bmr2721689qtx.54.1705664603497; Fri, 19 Jan 2024 03:43:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705664603; cv=none; d=google.com; s=arc-20160816; b=WBDUtGEXOpA+WfmII/HfWC0ym9gbnH9dnrGaSqN6KC8+yBdVsU5u/Pyzy0Pc2g/WPk N+Sta11ZG8K/c37YGrbm0LIwUQBzRAx2K2u1JKvlfW2r2OBl4SzhG4Rq/UtvXc2DU9HC 4uVmuF04rQQdZzChE8Ox8zQZjlpnTZbZ/SW8RVoc7ox42tpzvkKvDIRGxgZzvlCt3Vwf a+D0PQrq5qbfxZy2mJJ+c3Xf3uX+bpKx8n35QmxYqPaWuRLsFNRXaSvMpqMGm5jHI7eG 7eCJYlsnb0hdd8mik05J8lXZWwejCBGlLh2AQaTKcZyg25fb9KNoKFCL6wd3tgbbvy/Q VTFA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=dFDI//XvTpn1St0hBV0sdqL1iHcD9DD5+xWDU4qjjTU=; fh=AgN8TvM7pMmL5RKrQhAJxXwOmBywzcClhFxW1SQC+/4=; b=woqp+APejrzgaFgyNbeCnktTqw3eOeLtaH9BAXvA0N9Wx3XlU44GmRerdvrXLwJJXW viQ3Ux7BEYgcfS5d8iuPOcaWTs5wy1PiXWyLBhCudMtyOFK6AbAduv8bVQS+XYlkmaZx FrAO9F9lHvfhlnkvVN7DWWiuCrvjpvpTIxMUWgxZ0v/jhSCsy+PBd/NoWRIaMc0YFuVZ tHb169fHe/a1kaPR6LtpoOYaSmTeyLUSTqERTAxiUsILV5XNuOXbkK9JO58cZ5OkA1lH PgSj9YU3I17nE7t/iy42Xu/cqf+zhER3cPR2Hn/qaKfZR0bZxSk5kRydYuW49G7Ozs2W /4mA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pdGn9JtO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id c11-20020a05600c0a4b00b0040d53588d94sm32738791wmq.46.2024.01.19.03.37.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:37:18 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, Mark Cave-Ayland , Guenter Roeck , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Fam Zheng Subject: [PULL 29/36] hw/scsi/esp-pci: use correct address register for PCI DMA transfers Date: Fri, 19 Jan 2024 12:34:58 +0100 Message-ID: <20240119113507.31951-30-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Mark Cave-Ayland The current code in esp_pci_dma_memory_rw() sets the DMA address to the value of the DMA_SPA (Starting Physical Address) register which is incorrect: this means that for each callback from the SCSI layer the DMA address is set back to the starting address. In the case where only a single SCSI callback occurs (currently for transfer lengths < 128kB) this works fine, however for larger transfers the DMA address wraps back to the initial starting address, corrupting the buffer holding the data transferred to the guest. Fix esp_pci_dma_memory_rw() to use the DMA_WAC (Working Address Counter) for the DMA address which is correctly incremented across multiple SCSI layer transfers. Signed-off-by: Mark Cave-Ayland Reviewed-by: Guenter Roeck Tested-by: Guenter Roeck Message-ID: <20240112131529.515642-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daudé --- hw/scsi/esp-pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/scsi/esp-pci.c b/hw/scsi/esp-pci.c index 93b3429e0f..7117725371 100644 --- a/hw/scsi/esp-pci.c +++ b/hw/scsi/esp-pci.c @@ -275,7 +275,7 @@ static void esp_pci_dma_memory_rw(PCIESPState *pci, uint8_t *buf, int len, qemu_log_mask(LOG_UNIMP, "am53c974: MDL transfer not implemented\n"); } - addr = pci->dma_regs[DMA_SPA]; + addr = pci->dma_regs[DMA_WAC]; if (pci->dma_regs[DMA_WBC] < len) { len = pci->dma_regs[DMA_WBC]; } From patchwork Fri Jan 19 11:34:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763919 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp398955wrq; Fri, 19 Jan 2024 03:41:49 -0800 (PST) X-Google-Smtp-Source: AGHT+IF9XbKQMYO1Cv0WYBJNRzXZLHVr5lPv0+Ix0z7Si+0gMRtEZdmE0JVfQnF6f88HM2CpE4Jw X-Received: by 2002:a05:6102:519:b0:467:a854:af22 with SMTP id l25-20020a056102051900b00467a854af22mr1865572vsa.5.1705664509088; Fri, 19 Jan 2024 03:41:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705664509; cv=none; d=google.com; s=arc-20160816; b=O0ec18+iqnmIAFAAJbclb/QIMx+c1as2aXFrsnedLzHRqXM11r+5OIzZe66Tyyxi9v nzZQnxxv2Qz2KaPhQ0NmgpRf+mPFWRGtTIkwG7U66Y6+iMzR0v6uoZY8zn5NlwTVSPYc Tca92Cyw5wrnSq+cqmJVmgKlQ00JAAjMRGQKeYjSqTLo22mxsYOY5Au+qenz2QMUU5cx joq2UT79WhuChXIwnxFgHHrMbcLjyisSij7hslZ64YLzNmxnFtV9hWv2JzGJlCm2epwA gcTve8kyzeL4Ze3w+iy2od3sJ/CljlSvM7q2rHcyquhmjbLSyMF8bAhQsec1YYTA0V90 gZ1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=OAd+hsmqGnC7BEM4hV/k6DWbPNlhhbttEWZwCPVCQ9Y=; fh=AgN8TvM7pMmL5RKrQhAJxXwOmBywzcClhFxW1SQC+/4=; b=KcMhUHPBr4Mv0jyeirykwKPH6ex5ftcwmxKt3DGbpJTSkb05LduuX1QA3XTxRPF6LH uN7z0y7WnieJ1qZmHR/DzH8ii+roOmB9CSUJdz77kp79cdxeKpRy84wqwJACvPCre2xg XCvDy14I9rJgKbCH1d45D8HIFZ2kGthZtuu1r3/GUDwVsY8x/loK278am7RmgROo2AiA V3Ht6J5+8MCcvCPSDnetsFukodgAAg6eQn7n4bf6wA2QvXq1tYHSEuKWav5hkJcUpXaJ DqOR9EWXjTIA8UtHWoWCgHwvwrvQs/dcpBQaP7BEm3bIw8GVTIKWk7698/polTlOutmb HuBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JZOD6ZrJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id f6-20020a05600c4e8600b0040d6ffae526sm32950428wmq.39.2024.01.19.03.37.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:37:23 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, Mark Cave-Ayland , Guenter Roeck , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Fam Zheng Subject: [PULL 30/36] hw/scsi/esp-pci: generate PCI interrupt from separate ESP and PCI sources Date: Fri, 19 Jan 2024 12:34:59 +0100 Message-ID: <20240119113507.31951-31-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Mark Cave-Ayland The am53c974/dc390 PCI interrupt has two separate sources: the first is from the internal ESP device, and the second is from the PCI DMA transfer logic. Update the ESP interrupt handler so that it sets DMA_STAT_SCSIINT rather than driving the PCI IRQ directly, and introduce a new esp_pci_update_irq() function to generate the correct PCI IRQ level. In particular this fixes spurious interrupts being generated by setting DMA_STAT_DONE at the end of a transfer if DMA_CMD_INTE_D isn't set in the DMA_CMD register. Signed-off-by: Mark Cave-Ayland Reviewed-by: Guenter Roeck Tested-by: Guenter Roeck Message-ID: <20240112131529.515642-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daudé --- hw/scsi/esp-pci.c | 32 +++++++++++++++++++++++++++----- 1 file changed, 27 insertions(+), 5 deletions(-) diff --git a/hw/scsi/esp-pci.c b/hw/scsi/esp-pci.c index 7117725371..15dc3c004d 100644 --- a/hw/scsi/esp-pci.c +++ b/hw/scsi/esp-pci.c @@ -77,6 +77,29 @@ struct PCIESPState { ESPState esp; }; +static void esp_pci_update_irq(PCIESPState *pci) +{ + int scsi_level = !!(pci->dma_regs[DMA_STAT] & DMA_STAT_SCSIINT); + int dma_level = (pci->dma_regs[DMA_CMD] & DMA_CMD_INTE_D) ? + !!(pci->dma_regs[DMA_STAT] & DMA_STAT_DONE) : 0; + int level = scsi_level || dma_level; + + pci_set_irq(PCI_DEVICE(pci), level); +} + +static void esp_irq_handler(void *opaque, int irq_num, int level) +{ + PCIESPState *pci = PCI_ESP(opaque); + + if (level) { + pci->dma_regs[DMA_STAT] |= DMA_STAT_SCSIINT; + } else { + pci->dma_regs[DMA_STAT] &= ~DMA_STAT_SCSIINT; + } + + esp_pci_update_irq(pci); +} + static void esp_pci_handle_idle(PCIESPState *pci, uint32_t val) { ESPState *s = &pci->esp; @@ -151,6 +174,7 @@ static void esp_pci_dma_write(PCIESPState *pci, uint32_t saddr, uint32_t val) /* clear some bits on write */ uint32_t mask = DMA_STAT_ERROR | DMA_STAT_ABORT | DMA_STAT_DONE; pci->dma_regs[DMA_STAT] &= ~(val & mask); + esp_pci_update_irq(pci); } break; default: @@ -161,17 +185,14 @@ static void esp_pci_dma_write(PCIESPState *pci, uint32_t saddr, uint32_t val) static uint32_t esp_pci_dma_read(PCIESPState *pci, uint32_t saddr) { - ESPState *s = &pci->esp; uint32_t val; val = pci->dma_regs[saddr]; if (saddr == DMA_STAT) { - if (s->rregs[ESP_RSTAT] & STAT_INT) { - val |= DMA_STAT_SCSIINT; - } if (!(pci->sbac & SBAC_STATUS)) { pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_ERROR | DMA_STAT_ABORT | DMA_STAT_DONE); + esp_pci_update_irq(pci); } } @@ -350,6 +371,7 @@ static void esp_pci_command_complete(SCSIRequest *req, size_t resid) esp_command_complete(req, resid); pci->dma_regs[DMA_WBC] = 0; pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE; + esp_pci_update_irq(pci); } static const struct SCSIBusInfo esp_pci_scsi_info = { @@ -386,7 +408,7 @@ static void esp_pci_scsi_realize(PCIDevice *dev, Error **errp) "esp-io", 0x80); pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io); - s->irq = pci_allocate_irq(dev); + s->irq = qemu_allocate_irq(esp_irq_handler, pci, 0); scsi_bus_init(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info); } From patchwork Fri Jan 19 11:35:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763935 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp399658wrq; Fri, 19 Jan 2024 03:43:55 -0800 (PST) X-Google-Smtp-Source: AGHT+IHV/frl5NoZae9COKtPS4k5k6Z00+jyo0sPkwhQpckXqm6kyIENCtKNNFxR2Q2p2ian1j5T X-Received: by 2002:a05:622a:d2:b0:42a:2144:8c76 with SMTP id p18-20020a05622a00d200b0042a21448c76mr1651321qtw.3.1705664635428; Fri, 19 Jan 2024 03:43:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705664635; cv=none; d=google.com; s=arc-20160816; b=TFvUwANVvqqPR9TzFEtFvCCa3lKWg2GtrW0CtCNXT6GcnHeCiGKC+2qIZSN0gBCXMe w3wvXnCZE+RuYjy7bHHlFdwHj/5OKAdlEAp0isfzpbbulQgy0+iscGeOnfE9P7fFqW/U vmeNDnkF+3T6h8RFZmb1iRrupapz/0x5puaisFdS0+zhfiV46KOfbqysYI/teEpqEOPh tNUbRdKVHng9GvToL/IA0Jw3mpfzODda6MYBPHJbdi71tMzUl9y4vzS/Ob5N/KH1wFUO J34UkLIhBMexjPDAjUOWOuc5CDbX/nXEPkMsNogPSaZ8rqxRRt61LADlFhbiMODotY/K cGag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ODpPk4V4L74xrCSwXIUijjl6fJH0n8xXoj2+PFNQbhs=; fh=AgN8TvM7pMmL5RKrQhAJxXwOmBywzcClhFxW1SQC+/4=; b=knwd/xwzUDw7WUuq7vDYszBMtqdWrmmEGdhhBrwwO17o1BWm4gcNFSyTahDjbfjT8B GikgPXWd/MhN/ScpJ5sXYxcgAhorjr8/fDnOIuXGwa5R2U68rE8wMqxYdc9dvqKF/3J4 9v76+ZIM5Aj0ZzjwYBIO5hBQVNdzieV2tuPKu8bTJHAFb/HcfyM516GW7xd7baYMLThu hgMDtakcsqakvWu27fm0xup6lEXkUoMI4E4ZNZ2YmvFWmlNo6XCza8JpDTpZ20yXXUdo k3NxmIJQi/ii7fjfrKBym+hy8l5XjyG/ygFZxjq19fPqxG5TS2wpj+1j/MovMdjZu3Co KmQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=eIXZ1Tks; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id n13-20020a5d51cd000000b0033673ddd81csm6238840wrv.112.2024.01.19.03.37.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:37:27 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, Mark Cave-Ayland , Guenter Roeck , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Fam Zheng Subject: [PULL 31/36] hw/scsi/esp-pci: synchronise setting of DMA_STAT_DONE with ESP completion interrupt Date: Fri, 19 Jan 2024 12:35:00 +0100 Message-ID: <20240119113507.31951-32-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Mark Cave-Ayland The setting of DMA_STAT_DONE at the end of a DMA transfer can be configured to generate an interrupt, however the Linux driver manually checks for DMA_STAT_DONE being set and if it is, considers that a DMA transfer has completed. If DMA_STAT_DONE is set but the ESP device isn't indicating an interrupt then the Linux driver considers this to be a spurious interrupt. However this can occur in QEMU as there is a delay between the end of DMA transfer where DMA_STAT_DONE is set, and the ESP device raising its completion interrupt. This appears to be an incorrect assumption in the Linux driver as the ESP and PCI DMA interrupt sources are separate (and may not be raised exactly together), however we can work around this by synchronising the setting of DMA_STAT_DONE at the end of a DMA transfer with the ESP completion interrupt. In conjunction with the previous commit Linux is now able to correctly boot from an am53c974 PCI SCSI device on the hppa C3700 machine without emitting "iget: checksum invalid" and "Spurious irq, sreg=10" errors. Signed-off-by: Mark Cave-Ayland Reviewed-by: Guenter Roeck Tested-by: Guenter Roeck Message-ID: <20240112131529.515642-4-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daudé --- hw/scsi/esp-pci.c | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/hw/scsi/esp-pci.c b/hw/scsi/esp-pci.c index 15dc3c004d..875a49199d 100644 --- a/hw/scsi/esp-pci.c +++ b/hw/scsi/esp-pci.c @@ -93,6 +93,18 @@ static void esp_irq_handler(void *opaque, int irq_num, int level) if (level) { pci->dma_regs[DMA_STAT] |= DMA_STAT_SCSIINT; + + /* + * If raising the ESP IRQ to indicate end of DMA transfer, set + * DMA_STAT_DONE at the same time. In theory this should be done in + * esp_pci_dma_memory_rw(), however there is a delay between setting + * DMA_STAT_DONE and the ESP IRQ arriving which is visible to the + * guest that can cause confusion e.g. Linux + */ + if ((pci->dma_regs[DMA_CMD] & DMA_CMD_MASK) == 0x3 && + pci->dma_regs[DMA_WBC] == 0) { + pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE; + } } else { pci->dma_regs[DMA_STAT] &= ~DMA_STAT_SCSIINT; } @@ -306,9 +318,6 @@ static void esp_pci_dma_memory_rw(PCIESPState *pci, uint8_t *buf, int len, /* update status registers */ pci->dma_regs[DMA_WBC] -= len; pci->dma_regs[DMA_WAC] += len; - if (pci->dma_regs[DMA_WBC] == 0) { - pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE; - } } static void esp_pci_dma_memory_read(void *opaque, uint8_t *buf, int len) @@ -363,24 +372,13 @@ static const VMStateDescription vmstate_esp_pci_scsi = { } }; -static void esp_pci_command_complete(SCSIRequest *req, size_t resid) -{ - ESPState *s = req->hba_private; - PCIESPState *pci = container_of(s, PCIESPState, esp); - - esp_command_complete(req, resid); - pci->dma_regs[DMA_WBC] = 0; - pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE; - esp_pci_update_irq(pci); -} - static const struct SCSIBusInfo esp_pci_scsi_info = { .tcq = false, .max_target = ESP_MAX_DEVS, .max_lun = 7, .transfer_data = esp_transfer_data, - .complete = esp_pci_command_complete, + .complete = esp_command_complete, .cancel = esp_request_cancelled, }; From patchwork Fri Jan 19 11:35:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763929 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp399362wrq; Fri, 19 Jan 2024 03:42:59 -0800 (PST) X-Google-Smtp-Source: AGHT+IHADoxyuvNi+fcubMIpZpiMl8y9dorHC20yBLjeqhYWGKSOv38q/qT26fUROv8vQgKa2F8D X-Received: by 2002:a05:620a:838f:b0:783:1f65:cbb1 with SMTP id pb15-20020a05620a838f00b007831f65cbb1mr1174573qkn.31.1705664579723; Fri, 19 Jan 2024 03:42:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705664579; cv=none; d=google.com; s=arc-20160816; b=PkMKybLaPPR4mvJln1pIekddD0zw3Adui6UiZbtI2zfVthqMj4JOoC57y474pB1Cvs CYd1wh7FWlPtx6nh7ybqR+dTXXP5L6e07G24IqKt2RYi/qMVJUxDMpmJU/pDzyjdku7Z Zm7SBgJb/JAfPIsT0zmH6psKrndDIsU9KXM+nSqBVE5/Zx/Ga/gLHt1fgai44OHTHYAo dCaYmEmPDym8BRVJFjHQHfzdxC67CvrAO8dWeYPQTtAXcPZfBeLetoFTmumzcwf6tuY1 6Oz3om54I41BZf9d8wb0dBTB1Gs/1dLg9WO6DPvgCyseJa32ICI/gGLlgRroKNWbAg6V TCPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=8IaNDObNAqYNxlZ9PNSQWTtp9Qeox0bgAC84EDezcoU=; fh=AgN8TvM7pMmL5RKrQhAJxXwOmBywzcClhFxW1SQC+/4=; b=G6HqSEW4kq3tBAmYmqnc17QI9o9aXuFjpOi4qQT26wK4qAlK+Pz78nha+jgXdwBWMH OfkOPko5V3L10lRJANxXEX5lsjmkuA1yUNJX/uAJKCFrkh8eUrwiv1NyVw1j32z0P5nz +beFKzZBiLu3ThNmDQbOb/E9ECAmoj2DJXh2c+ZOzwOm0odcThDpA725lNlScu3YG7t2 8ZmKJYfABeizMtavxkk+kR8X2NcM6moR0LMFjKiVuOypHmecaJeS4by659+vwv/AUyiZ 7BFv6wYATpJGBrfVBeARAgMY3zRzKkA1kGMHszIO1sVYrJsZy5YItqFW5JMpRQQjsLJd Se8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zk7EHrNr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id j6-20020adfb306000000b00339208ecb30sm1294065wrd.68.2024.01.19.03.37.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:37:32 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, Mark Cave-Ayland , Guenter Roeck , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , Fam Zheng Subject: [PULL 32/36] hw/scsi/esp-pci: set DMA_STAT_BCMBLT when BLAST command issued Date: Fri, 19 Jan 2024 12:35:01 +0100 Message-ID: <20240119113507.31951-33-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Mark Cave-Ayland Even though the BLAST command isn't fully implemented in QEMU, the DMA_STAT_BCMBLT bit should be set after the command has been issued to indicate that the command has completed. This fixes an issue with the DC390 DOS driver which issues the BLAST command as part of its normal error recovery routine at startup, and otherwise sits in a tight loop waiting for DMA_STAT_BCMBLT to be set before continuing. Signed-off-by: Mark Cave-Ayland Reviewed-by: Guenter Roeck Tested-by: Guenter Roeck Message-ID: <20240112131529.515642-5-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daudé --- hw/scsi/esp-pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/scsi/esp-pci.c b/hw/scsi/esp-pci.c index 875a49199d..42d9d2e483 100644 --- a/hw/scsi/esp-pci.c +++ b/hw/scsi/esp-pci.c @@ -124,6 +124,7 @@ static void esp_pci_handle_blast(PCIESPState *pci, uint32_t val) { trace_esp_pci_dma_blast(val); qemu_log_mask(LOG_UNIMP, "am53c974: cmd BLAST not implemented\n"); + pci->dma_regs[DMA_STAT] |= DMA_STAT_BCMBLT; } static void esp_pci_handle_abort(PCIESPState *pci, uint32_t val) From patchwork Fri Jan 19 11:35:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763941 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp399867wrq; Fri, 19 Jan 2024 03:44:34 -0800 (PST) X-Google-Smtp-Source: AGHT+IEew/cclthiYrfFA1OTw6zDajK1IRebHjVdQqMtOjO+7+/gFEpKzM2f7qoyD3yKyvDOFRQA X-Received: by 2002:a05:6214:d06:b0:680:fa16:a40f with SMTP id 6-20020a0562140d0600b00680fa16a40fmr2369383qvh.36.1705664673930; Fri, 19 Jan 2024 03:44:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705664673; cv=none; d=google.com; s=arc-20160816; b=W6WlNuwq9MZ60rlRvN+DA0I7vg7Jen9lbvmNTt/SoyorIc4B5iW9AfocNXEpcD/os9 CdvxLBALsT5e2DZq6J2FsPhX8Y7r19zELzwGdi4cmtdaYGHQRfq10taddrTW8HW4iGJa 4KXH5My/PpDJSJGj2nwnfZdyf0L13smwpOgRSSY2Abrrxs62zedssCMq+F1spWgBCtXq Zn62rb/GKa7292PvIeO5ZjcRHPOEPOS4bEyCOQyE2c4K4kpVN6sKIqatuQfSxoQHlPW6 CpQYJkRceSxWl+HjRktgP2BmUMMih0M4qBfOYEIry4pojQiV+E2L1eg09x/VrVB2mq4z i3jg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=gdcgrGS7kL0CXr2CCXnG/ae/hIrP2R+qiFCnst8/G2g=; fh=hDgfUwIL/v7weRBofvSJVD9yTBvj7VhdNF+FEnj9zak=; b=RWxammMgnxbmUA45iG5tTw1uE7d454pWYp06vMfU/TwltMUq/womv6Gh3nN0HOFE1y srmeEgxd9D6aYYfw7A4WjftOYANNMyRX8ghgXPS7eKonQEJxZDDXUbdkshISFZ8TrY8g khuceaL1/sby6hCz/hQwpGV1w9+Y3lckIsbME4mQWtjcpmHH0L9lxgSqFKQWr19VcZdd fCKd2KD8Rl7TT+t52u5dTnnAigb5skOwcoMKJxVMyELS5s3Nd33p2sLYGYgsi5zS4b9j 8KBFE4EeKvEyRxWv1+d5GkU+G3/9qiqDzKM+JRmtHMZo35mZovroEFNRXox8jPLtHJCe 2D5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Lv0xOUsR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id i6-20020adffc06000000b003375009accesm6301614wrr.50.2024.01.19.03.37.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:37:36 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, Bin Meng , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= Subject: [PULL 33/36] hw/elf_ops: Ignore loadable segments with zero size Date: Fri, 19 Jan 2024 12:35:02 +0100 Message-ID: <20240119113507.31951-34-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bin Meng Some ELF files really do have segments of zero size, e.g.: Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flags Align RISCV_ATTRIBUT 0x00000000000025b8 0x0000000000000000 0x0000000000000000 0x000000000000003e 0x0000000000000000 R 0x1 LOAD 0x0000000000001000 0x0000000080200000 0x0000000080200000 0x00000000000001d1 0x00000000000001d1 R E 0x1000 LOAD 0x00000000000011d1 0x00000000802001d1 0x00000000802001d1 0x0000000000000e37 0x0000000000000e37 RW 0x1000 LOAD 0x0000000000000120 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x0000000000000000 0x1000 The current logic does not check for this condition, resulting in the incorrect assignment of 'lowaddr' as zero. There is already a piece of codes inside the segment traversal loop that checks for zero-sized loadable segments for not creating empty ROM blobs. Let's move this check to the beginning of the loop to cover both scenarios. Signed-off-by: Bin Meng Reviewed-by: Richard Henderson Message-ID: <20240116155049.390301-1-bmeng@tinylab.org> Signed-off-by: Philippe Mathieu-Daudé --- include/hw/elf_ops.h | 71 +++++++++++++++++++++++--------------------- 1 file changed, 37 insertions(+), 34 deletions(-) diff --git a/include/hw/elf_ops.h b/include/hw/elf_ops.h index 9c35d1b9da..3e966ddd5a 100644 --- a/include/hw/elf_ops.h +++ b/include/hw/elf_ops.h @@ -427,6 +427,16 @@ static ssize_t glue(load_elf, SZ)(const char *name, int fd, file_size = ph->p_filesz; /* Size of the allocated data */ data_offset = ph->p_offset; /* Offset where the data is located */ + /* + * Some ELF files really do have segments of zero size; + * just ignore them rather than trying to set the wrong addr, + * or create empty ROM blobs, because the zero-length blob can + * falsely trigger the overlapping-ROM-blobs check. + */ + if (mem_size == 0) { + continue; + } + if (file_size > 0) { if (g_mapped_file_get_length(mapped_file) < file_size + data_offset) { @@ -530,45 +540,38 @@ static ssize_t glue(load_elf, SZ)(const char *name, int fd, *pentry = ehdr.e_entry - ph->p_vaddr + ph->p_paddr; } - /* Some ELF files really do have segments of zero size; - * just ignore them rather than trying to create empty - * ROM blobs, because the zero-length blob can falsely - * trigger the overlapping-ROM-blobs check. - */ - if (mem_size != 0) { - if (load_rom) { - g_autofree char *label = - g_strdup_printf("%s ELF program header segment %d", - name, i); + if (load_rom) { + g_autofree char *label = + g_strdup_printf("%s ELF program header segment %d", + name, i); - /* - * rom_add_elf_program() takes its own reference to - * 'mapped_file'. - */ - rom_add_elf_program(label, mapped_file, data, file_size, - mem_size, addr, as); - } else { - MemTxResult res; + /* + * rom_add_elf_program() takes its own reference to + * 'mapped_file'. + */ + rom_add_elf_program(label, mapped_file, data, file_size, + mem_size, addr, as); + } else { + MemTxResult res; - res = address_space_write(as ? as : &address_space_memory, - addr, MEMTXATTRS_UNSPECIFIED, - data, file_size); + res = address_space_write(as ? as : &address_space_memory, + addr, MEMTXATTRS_UNSPECIFIED, + data, file_size); + if (res != MEMTX_OK) { + goto fail; + } + /* + * We need to zero'ify the space that is not copied + * from file + */ + if (file_size < mem_size) { + res = address_space_set(as ? as : &address_space_memory, + addr + file_size, 0, + mem_size - file_size, + MEMTXATTRS_UNSPECIFIED); if (res != MEMTX_OK) { goto fail; } - /* - * We need to zero'ify the space that is not copied - * from file - */ - if (file_size < mem_size) { - res = address_space_set(as ? as : &address_space_memory, - addr + file_size, 0, - mem_size - file_size, - MEMTXATTRS_UNSPECIFIED); - if (res != MEMTX_OK) { - goto fail; - } - } } } From patchwork Fri Jan 19 11:35:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763926 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp399323wrq; Fri, 19 Jan 2024 03:42:54 -0800 (PST) X-Google-Smtp-Source: AGHT+IHwfNbV7VR/aAXzntst6+rB3WbIWuIMnICEr2yjqcAW0EhiJz9VGk9SDp+kEUrda4tbCpns X-Received: by 2002:a05:6830:120a:b0:6d6:9ece:73e2 with SMTP id r10-20020a056830120a00b006d69ece73e2mr2111075otp.17.1705664573913; Fri, 19 Jan 2024 03:42:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705664573; cv=none; d=google.com; s=arc-20160816; b=Tlx8913dwmWDnMd+XSy/EywBMdR87tcc3Ft1uWzYP/ve7lwJruNkGq6quBEDUhT8IM jKeAM7jHEWq2xxNbPtDMLb8X0bx2IDCgjCza7UxxAM1pumqCtrh/ECOHAmazvGWnPfyU BhbHKwFuE70005C6PpGzzWgtQ2z530snWRXJrQwbTh1dzrSKvU770FLxdlSSpPxqIykf 3sConl/tWPpFKJrN2Pvc7h8Q15jNY/TCZ/K5KjFsTUP9sWCBhLYGC4K778bq31TRNq/C OPjiNw3bPm+FzxuP/cFQb7QZoPT2neByawSlYBaRuQmFA+r4fbkDwM0ph4z6y8/LndZY SLsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=n/Q3pfm39hWlzYJ6LfMyGawyaAzdsP1AW7mdF4S9bfM=; fh=shBiktBRRICBjJuyah2fF4bkBU1YvsgMKrbdhZxP1OE=; b=rzf6lweub5w5vekRCtDPIcN4/a0k05O3fwUVg8lLsG5VT0g6zo1NDKBS28JN6lws9s iECXHvRRPXyS6QJJFcvEl5s3Et827SjPbfxP1Gv5/H/LiaBXRxFFQSc0T7CKGoSnwd2q AeTIjJV68ISzMwf/8FOyhgSkboCVNIxyXdPuKp2QIvtZbjIPMGEPoNxoZHwu93FM9M8F JABZY665W/Z8gRyT2eM9O/sTTBFYn9H0VoT+4ZqcmC1XKWKD9g5LsaXRkbHMjHyZINPa Oazn+6gw7XujIX0SSf4AYWHVf2ZDxEh793B5AvHXMeyRRI73PjarSSgvQFkjZkueM4Rm dPKQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tgU6DI2R; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id n7-20020adff087000000b00337bb0f370dsm6313156wro.40.2024.01.19.03.37.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:37:41 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, Raphael Norwitz , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 34/36] MAINTAINERS: Update Raphael Norwitz email Date: Fri, 19 Jan 2024 12:35:03 +0100 Message-ID: <20240119113507.31951-35-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Raphael Norwitz I will be leaving Nutanix so updating my email in MAINTAINERS to my personal email for now. Signed-off-by: Raphael Norwitz Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240111192846.111699-1-raphael.norwitz@nutanix.com> Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 8e8ca270c4..760acdea66 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2555,7 +2555,7 @@ F: include/hw/virtio/virtio-gpu.h F: docs/system/devices/virtio-gpu.rst vhost-user-blk -M: Raphael Norwitz +M: Raphael Norwitz S: Maintained F: contrib/vhost-user-blk/ F: contrib/vhost-user-scsi/ From patchwork Fri Jan 19 11:35:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763920 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp399011wrq; Fri, 19 Jan 2024 03:41:59 -0800 (PST) X-Google-Smtp-Source: AGHT+IEXAaCW1b96AVDkuwHpPqmodoKG1c5rMzPOHTFaXk8yo+4rfmqOfSvQqBb+7aWyr5OTY89C X-Received: by 2002:ac8:44b3:0:b0:42a:27da:4cc5 with SMTP id a19-20020ac844b3000000b0042a27da4cc5mr546478qto.7.1705664519028; Fri, 19 Jan 2024 03:41:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705664519; cv=none; d=google.com; s=arc-20160816; b=hMnoCE/SKtOydtvrXjwuewVLq1pQASk6TQFjk+pqUoN9qfUUfIvktSwNV4UthxPeKT o2f7WNE3lhBL6sjsnlz8hQDrZHbwi4n3/VAp07990x+OhUWNaLO515JbF3xFFgjPk8WY 5palqmIGSSMmxu+3uDPgmQaYdiwDzIl2nOwJ/1k+ogdUUYa8/Ot2L734xjtoX0173px7 XeHzIR5U5p95msbDWDHrdfPFb67xRMRGVL8f+cwPFgtmkJbvqWZlvg2auAhsNPU5Hi9n DPCzylDpvj5VJAN99Gj2kIF7iyWzpRf2QHxpNFjDoxX0msjImhAJTmNv13carF1XgTWS NrFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=W6KPMPhrgsV+R1Z5ztift8+++ccJQHN9jxOgkalvdDo=; fh=PTYYIL7o5nvcKmhdZ8esiNe9bpTIp4+Nq0xgZ4+Jis8=; b=dEuY17Aogkjx9vHIUa6YEUB8mu71xidxRqfiApUHMYah3Pzl+A1qRqoVmJVebODHzw VwLSmeWFm/8KgwCxEhYIsIqQVOqheS/Pd57bonfuIFD3ley2VFLWueYHSkOKIfXyYLpY OcCz1wZuB03IimAf53tpCvLbEVHOloXyFwSUYTeLubKYE4C6lPDeluau1uq19llEQS5w +WShZiBP270QH6gIGUeavvXHsdbQR6sQwSGvdsuyozRty0PJLoMLJkJcxDXtVK/NXI4Y Ah1H4lCN2q1xCuEFvROyFTdJh2QpFKNsbtXKSEQQRrE14YcEyC/tnyIf2bhsBV/+/L3v TYeA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DdiKiNYz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id n7-20020adff087000000b00337bb0f370dsm6313328wro.40.2024.01.19.03.37.45 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:37:45 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, Zhao Liu , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PULL 35/36] MAINTAINERS: Update hw/core/cpu.c entry Date: Fri, 19 Jan 2024 12:35:04 +0100 Message-ID: <20240119113507.31951-36-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Zhao Liu The hw/core/cpu.c was split as hw/core/cpu-common.c and hw/core/cpu-sysemu.c in the commit df4fd7d5c8a3 ("cpu: Split as cpu-common / cpu-sysemu"). Update the related entry. Signed-off-by: Zhao Liu Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240115094852.3597165-2-zhao1.liu@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 760acdea66..dfaca8323e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1867,7 +1867,8 @@ M: Marcel Apfelbaum R: Philippe Mathieu-Daudé R: Yanan Wang S: Supported -F: hw/core/cpu.c +F: hw/core/cpu-common.c +F: hw/core/cpu-sysemu.c F: hw/core/machine-qmp-cmds.c F: hw/core/machine.c F: hw/core/machine-smp.c From patchwork Fri Jan 19 11:35:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763932 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp399488wrq; Fri, 19 Jan 2024 03:43:24 -0800 (PST) X-Google-Smtp-Source: AGHT+IHwkGqtTC6UAtSVdwZECmYJ9KICtRcxWyDfMHmTMjWUt/ncD5IxI5oONwrTV4lvN9J+8SJe X-Received: by 2002:a05:622a:c1:b0:42a:1857:7351 with SMTP id p1-20020a05622a00c100b0042a18577351mr2699696qtw.22.1705664603850; Fri, 19 Jan 2024 03:43:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705664603; cv=none; d=google.com; s=arc-20160816; b=c3mlAU/yiYK07zYK2++/dKvPqSD9oKZoEtzsaMol/f8SWcynTIVDNxrcmWV5/ZSIs5 tvGIjh6es6hpBpk68QtmsuFDi5HG3mrhFg1rflYYmhEplb9HBx4RpF6unFy+R4x4FLMn E+nsNGgob1MPPj58MyDt+cSog3NkmLfPSV2p5MwMYI1zLF8/zNPaxPos46H+fR0w+GIu +dBuXNC0JyLkjgUjQ7LHIQw8lXfJ38JclSdIAdQtPkRM4+PgpHJquQyBeDU+hWPeHxyy M4i0+6j0WENbsIso2P/6aZg9w+kJVNuNzlOMwf92YX62za0z8SYAj1pdFRmc0/d3xIcz lk6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Nr4OUHS+lBPFXd43ccavf7bhITrAw62IpLJRw1qHBNM=; fh=Fvwgvy80ygdP82bysZimOYQryTQSPXLk9G3SuBJkrbU=; b=EFC/EwvLjuPxfR+0Zbq+j+tRwXvs8TVeWy80hvN3+nkW8WlLIsGH0CEuhMTn1CHnqJ wgJbA2mTxBIvYj1aHdQNfCYjtQnkiTKlsvWO/ELvrTpRF8S0i7qkKMGYxitObMiKtynb QhzM497ANXc0z9gxXsLrbtnbFbo7DhZtOYNCSXTLbwzKfjicw8b+5q07HCWY8nGmwjXD f5Wk2rBklYqdFhyrURiZa3iWke8G9ee2P8UhP5W+rBcliT0QRcq85lmpQ1rhdfMb7TGA 31A+cy3QcIsSpcu3YBn2+P4hErPOAv61yebh2gbSCu2+3IHAQEngfguJTGfRPfixz+Vu 55FQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rN+smCIS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id hg14-20020a05600c538e00b0040e5cf9a6c7sm29076314wmb.13.2024.01.19.03.37.49 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 19 Jan 2024 03:37:50 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, Bibo Mao , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Paolo Bonzini , =?utf-8?q?Alex_Benn=C3=A9e?= , Thomas Huth Subject: [PULL 36/36] configure: Add linux header compile support for LoongArch Date: Fri, 19 Jan 2024 12:35:05 +0100 Message-ID: <20240119113507.31951-37-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240119113507.31951-1-philmd@linaro.org> References: <20240119113507.31951-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Bibo Mao When compiling qemu with system KVM mode for LoongArch, header files in directory linux-headers/asm-loongarch should be used firstly. Otherwise it fails to find kvm.h on system with old glibc, since latest kernel header files are not installed. This patch adds linux_arch definition for LoongArch system so that header files in directory linux-headers/asm-loongarch can be included. Fixes: 714b03c125 ("target/loongarch: Add loongarch kvm into meson build") Signed-off-by: Bibo Mao Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20240116013952.264474-1-maobibo@loongson.cn> Signed-off-by: Philippe Mathieu-Daudé --- configure | 1 + 1 file changed, 1 insertion(+) diff --git a/configure b/configure index 21ab9a64e9..3d8e24ae01 100755 --- a/configure +++ b/configure @@ -445,6 +445,7 @@ case "$cpu" in loongarch*) cpu=loongarch64 host_arch=loongarch64 + linux_arch=loongarch ;; mips64*)