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[209.51.188.17]) by mx.google.com with ESMTPS id z9-20020a05622a060900b004299a282df8si14621867qta.609.2024.01.18.12.07.51 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jan 2024 12:07:52 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HP9tV4Jq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rQYfC-0003P8-MZ; Thu, 18 Jan 2024 15:06:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQYfB-0003On-8K for qemu-devel@nongnu.org; Thu, 18 Jan 2024 15:06:57 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rQYf8-0006sF-MH for qemu-devel@nongnu.org; Thu, 18 Jan 2024 15:06:56 -0500 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-40e8801221cso224215e9.1 for ; Thu, 18 Jan 2024 12:06:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705608413; x=1706213213; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DiNAFYNzh60Xuezutbt6PuwpTTLS/OKWcI7qaHfDd9s=; b=HP9tV4Jq36w/bkNaJaAQAhsEL9TlOcgrGAG4kaObnnS1au3JwTcdyTp+yxRVllMIB6 F+/VRqZPPhIMX0+DXw89ATjT9nkK8nnlDtMc/lsMDevqebDl3SFqNbLH8PLEkn/jhZMs wtvpw7BB25G+n2O1bVvqKytAxJ8Mpk2Xucez7NDXxe4OWrDR2WMIlpOIMwPrBMKXfrdH +hQD+mn4925unUYysgyGxs+pM6XEWwYSYxw2+zcGOmby/6WfN0/qYeDEZ1hnxUCu40IW vLHwgd16yoYU7f+DEmIAHbA1ACwOLLC/U+iFCeF4buPAg41dLyoBRy6P0Ef5tgHbK8Wa VEsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705608413; x=1706213213; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DiNAFYNzh60Xuezutbt6PuwpTTLS/OKWcI7qaHfDd9s=; b=EaNq+N+HTldU79V2Cs5F22mOY2kyy2/AgO0+9EU5EkcLMtUKcGUAKkLjiwKLQeXqJE e89Y4OTnk3z0lc8IXm9+GHqX7P2Wet8fASuXy8qCJOeWcEVb+Cl5Ra+63jcqLcjjj0Oc Hp/VFNbTjIzOB6G/3S2qUplDOGODDwsxRgvfa0VpFRPcCBSbRJHZxgPDhgMQPa+7XtQI CYYKyRfyEhowNlSdsu9gKUJJu6TvQnSLXjDJJljB8WH9IVedg21HP5QHE6zMcwd6Wwa/ YTevq4DAqqqBjQcNS1lYDPz3dAiDyf1GUZHyNICV27pqsdEqqK2UOcAXZ4oR4P+JUyQl Gvpg== X-Gm-Message-State: AOJu0YyXugy2nK5sioURGPs4oljuMJFxQcH1aFRjtZABdo0SYt+eHwDI hdxEcQRCiCL8ovgzS7rvwOUqH8JXFiZVb8rqp9eSiwpANMbYsq+vPQ334WZLkAYyS0s28wBTgn+ 0GJQG3ZF5 X-Received: by 2002:a05:600c:3317:b0:40e:85fe:af82 with SMTP id q23-20020a05600c331700b0040e85feaf82mr1044508wmp.24.1705608412751; Thu, 18 Jan 2024 12:06:52 -0800 (PST) Received: from localhost.localdomain ([78.196.4.158]) by smtp.gmail.com with ESMTPSA id je6-20020a05600c1f8600b0040d8d11bf63sm26933714wmb.41.2024.01.18.12.06.50 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 18 Jan 2024 12:06:52 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Igor Mitsyanko , qemu-arm@nongnu.org, Strahinja Jankovic , "Edgar E. Iglesias" , Igor Mammedov , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eric Auger , Niek Linnenbank , "Michael S. Tsirkin" , Jan Kiszka , Marcin Juszkiewicz , Alistair Francis , Radoslaw Biernacki , Andrew Jeffery , Andrey Smirnov , Rob Herring , Shannon Zhao , Tyrone Ting , Beniamino Galvani , Alexander Graf , Leif Lindholm , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Paolo Bonzini , Jean-Christophe Dubois , Joel Stanley , Hao Wu , kvm@vger.kernel.org Subject: [PATCH 01/20] hw/arm/exynos4210: Include missing 'exec/tswap.h' header Date: Thu, 18 Jan 2024 21:06:22 +0100 Message-ID: <20240118200643.29037-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240118200643.29037-1-philmd@linaro.org> References: <20240118200643.29037-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org hw/arm/exynos4210.c calls tswap32() which is declared in "exec/tswap.h". Include it in order to avoid when refactoring unrelated headers: hw/arm/exynos4210.c:499:22: error: call to undeclared function 'tswap32'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] smpboot[n] = tswap32(smpboot[n]); ^ Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/exynos4210.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index de39fb0ece..af511a153d 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -23,6 +23,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" +#include "exec/tswap.h" #include "cpu.h" #include "hw/cpu/a9mpcore.h" #include "hw/irq.h" From patchwork Thu Jan 18 20:06:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763640 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp108871wrq; Thu, 18 Jan 2024 12:08:10 -0800 (PST) X-Google-Smtp-Source: AGHT+IELptkbD7+ZG40vFY0YVrjvO10aLhxz2zfzuzuE8kjKlBThyaPpa5WSac4d3zdC8t3usr45 X-Received: by 2002:a05:6214:20c6:b0:681:31a3:1f66 with SMTP id 6-20020a05621420c600b0068131a31f66mr1756324qve.21.1705608490249; Thu, 18 Jan 2024 12:08:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705608490; cv=none; d=google.com; s=arc-20160816; b=bexWpnZHA3XX84q/xMWQhC/Qp7MdVXVVv2M0+AQgsioLRZxpQRUnNJmYh1h6Ba57IK o0WOyst+u6Z3waOhVM4XPG5PUHmyx1f+D7v9GM3+uVLnoYNXPmAFwkJ/2/AvvPgyecFT H0DWhPcBusTXspG+AteU+KdLJM4YsGGbVXZS4WbokBM79zyldZvIKiVdk6+h8QOt1cRD Slh6cNWjweQVR7sSaHnkgYo33evrR5cYAIMDnAetP0kmNTMca7Kgzi2aklih1Elnys9O GoeTxFpCelYOZ3NfH5Rm+OUzzqtUW2x0rAfg9iWwEqWqVtN+o0lUxh1/vy+Ta2KRItSR tmkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=htALVQYUd7tctCm3cf8P5ZcYUk/HKeiXOxSFOuNuC8A=; fh=cUgEM3TMHOIH70RmHTmTZxZmItZJnKfBWHSaci49aLY=; b=rLC5wLpf3ggGqxjqUe4ppAgre9JyIAqIMT+mdwwxMsOweYyOGUvjlPQEscVUnUgFu7 3ICajm9ZXZ8WEBBu8yFvX2HyDgeRhVUExNXfGLQjoB+uS8/w/Q3DOm/Hg91010klWRGf do/ngO/g7KZ4ldFRLR3bBR4VfUYkfTl4lytGFPy0b2cLZhSSAPZG+tnTtjBfpNQdV0NJ NdfSPfwNQPpFpUV24ZYFFRC0bpquTeHx9S7hwen5a//1ta/ZxI9GHLnY8y5K8aG+Lbsa SCrB7CZkiNuzZLcGT4PYm+BR2y7FltTPjKvItMuOMSrh9WxBdC+d0x/nS6i7TkIjWGEz n7Ew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Jk7ewOyb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , Igor Mammedov , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eric Auger , Niek Linnenbank , "Michael S. Tsirkin" , Jan Kiszka , Marcin Juszkiewicz , Alistair Francis , Radoslaw Biernacki , Andrew Jeffery , Andrey Smirnov , Rob Herring , Shannon Zhao , Tyrone Ting , Beniamino Galvani , Alexander Graf , Leif Lindholm , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Paolo Bonzini , Jean-Christophe Dubois , Joel Stanley , Hao Wu , kvm@vger.kernel.org Subject: [PATCH 02/20] hw/arm/xilinx_zynq: Include missing 'exec/tswap.h' header Date: Thu, 18 Jan 2024 21:06:23 +0100 Message-ID: <20240118200643.29037-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240118200643.29037-1-philmd@linaro.org> References: <20240118200643.29037-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org hw/arm/xilinx_zynq.c calls tswap32() which is declared in "exec/tswap.h". Include it in order to avoid when refactoring unrelated headers: hw/arm/xilinx_zynq.c:103:31: error: call to undeclared function 'tswap32'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] board_setup_blob[n] = tswap32(board_setup_blob[n]); ^ Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/xilinx_zynq.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index dbb9793aa1..d4c817ecdc 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -37,6 +37,7 @@ #include "hw/qdev-clock.h" #include "sysemu/reset.h" #include "qom/object.h" +#include "exec/tswap.h" #define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9") OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE) From patchwork Thu Jan 18 20:06:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763649 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp109779wrq; Thu, 18 Jan 2024 12:10:13 -0800 (PST) X-Google-Smtp-Source: AGHT+IHpyvcYGu5J/2F6YGQkaMmJ3P6FxtM6pTcZ95CgIhMMTbPMVp2o7tAnHLicBauYh9mFb1tc X-Received: by 2002:a05:620a:454a:b0:783:841e:2b81 with SMTP id u10-20020a05620a454a00b00783841e2b81mr256885qkp.7.1705608613393; Thu, 18 Jan 2024 12:10:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705608613; cv=none; d=google.com; s=arc-20160816; b=TRZf6ZhHuMQLk0/RkePlUbsFSm5vo7gmMB1w1AeA6x08jPzcUv4TLMDpBy/l6ph6kL gzPvy2amsP/aBlT/BaG8FXW/bk8Oe3EmnA3tS+/fJ04p9Y/OON4aJqfERtDtXr1XVETa 3P8za/07Y3FEzu4sFmsU4Ytw5rFGMRMXNtDiDESMfQtoVTs8qoRYaMesxx8wY9CLYfqT vPIIDRqFm7FN1VSRo00GJO11FcuygSSmgvxn9GwLVu2HfTvZaklAzIN+ofG1NCRv9g4N p/tWjwlyChFjUwcYhRBgVWwUH+sngEmqku42oNMpirhtU77swl2rOk3uoeC6xKO9ChUw gYzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=5DV0gjEvxVYdSUXbSGfE0SOvd3u+uIvvVQeLb8GJ57M=; fh=cUgEM3TMHOIH70RmHTmTZxZmItZJnKfBWHSaci49aLY=; b=OvPu3bsMurcFv3itmPd54WIyCucjHKUKF/dUxMPCB8MCvmActk8rdrgYbwQUhci+CM KJreFSjyfVRQqFWt2CCOsg4FNkqxj1Yb9eBTmxqej7bA1am2So+BTrx+Jam2h9kyj6jm gsU/9RG0+FRqaClmwhFdOf2/82837sM8UhpWPFt2hmaptegWZlD9sFrKCSFShXWncOKc 3iI/qH+wkXljGA82iaOzrvPnEcmRBrseyFLIDZLG9I7KlsX9S+revZswlFeY36uRrryQ ocw0vCwJ9mSqe8l0TaxEiOGhV6xaoscyQqYqRJ/SgjKHF13xj6djEOrye2uy+RjS8Cyg b5LQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Lqyd6nKs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ou26-20020a05620a621a00b007831dde08ddsi14077702qkn.491.2024.01.18.12.10.13 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jan 2024 12:10:13 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Lqyd6nKs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rQYfO-0003UL-G0; Thu, 18 Jan 2024 15:07:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQYfM-0003TK-VK for qemu-devel@nongnu.org; Thu, 18 Jan 2024 15:07:08 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rQYfK-0006v6-8m for qemu-devel@nongnu.org; Thu, 18 Jan 2024 15:07:08 -0500 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-40e86a9fbd9so195945e9.1 for ; Thu, 18 Jan 2024 12:07:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705608424; x=1706213224; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5DV0gjEvxVYdSUXbSGfE0SOvd3u+uIvvVQeLb8GJ57M=; b=Lqyd6nKsMDgNVtksfCAfEXmHP74kdWZNhlNQHXfc91LR77fKjYmKhs4P9RIHv2CMez YM24Z+mHvkDYe9IhTHG3ATEdHb4f7Acg4XLrJacMu3qvAzUXAtbP4nS2p4B9mrnJo7sy Ldom26IU3nRc4Gt7y18FzHL2zm9ITs+EvQ7ByzxcmLMCLTvb6Qr9q6Xd6n5GfscAwCRx 9Bu+GoWPEZhYENSti1oCUG2KsAGArSAGfPMCZ1SxtI9BrSTB1dK6sLbF9aanGPDIMECb eI3djIa29hDskvYcXU6uEZnzr41IHwB8XtTzYESCOjmb3ulqQqXUA+zmiIBs6j0FUHPP gQng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705608424; x=1706213224; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5DV0gjEvxVYdSUXbSGfE0SOvd3u+uIvvVQeLb8GJ57M=; b=EHO6TM/zgMcUC6et3AGCf4H9v69twfL74JB6q2NGl2sDV03SHcp3Qe00Z1ZgFEcAul y/EAnF2I8I4iYEqHif9gLJMATrFFkP0I8llFXt6/VX9hqOnoFmz07orDGoTPH0KL6MiL iaDj6aP0zGqqtkr8wocO+3Z32Irt+CPaK8MJAbojwujG67CZQibLN8buyWB2RHCM4nEk swtUyfDoJF8yYgO2QBjWxPAcS8vLwOgeTalerWZ2mk7CzD1LwYd0oT9cAqqPfPP5dPvA Wie8IARibPt9VtGXrf8PW0c9K06igPRZ/mdmMCHhX4rGwxy+Z6hHJw9QQl7DRkACoP7N W7hg== X-Gm-Message-State: AOJu0YzGuaDhQdgI+vqFDLGuakS4K7+ZaajSH+zdR87M4pfc49GH/EJo Y0Oejhuacbh7Z88BrqVcgdn1+j2goryRwxH+2364brsM6pE3xSB69VT2c8zqxvGBGpYohlS5qVh bPCeIZWL9 X-Received: by 2002:a05:600c:2981:b0:40e:954d:1a1a with SMTP id r1-20020a05600c298100b0040e954d1a1amr749105wmd.76.1705608424346; Thu, 18 Jan 2024 12:07:04 -0800 (PST) Received: from localhost.localdomain ([78.196.4.158]) by smtp.gmail.com with ESMTPSA id c11-20020a05600c0a4b00b0040d53588d94sm30769470wmq.46.2024.01.18.12.07.02 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 18 Jan 2024 12:07:04 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Igor Mitsyanko , qemu-arm@nongnu.org, Strahinja Jankovic , "Edgar E. Iglesias" , Igor Mammedov , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eric Auger , Niek Linnenbank , "Michael S. Tsirkin" , Jan Kiszka , Marcin Juszkiewicz , Alistair Francis , Radoslaw Biernacki , Andrew Jeffery , Andrey Smirnov , Rob Herring , Shannon Zhao , Tyrone Ting , Beniamino Galvani , Alexander Graf , Leif Lindholm , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Paolo Bonzini , Jean-Christophe Dubois , Joel Stanley , Hao Wu , kvm@vger.kernel.org Subject: [PATCH 03/20] hw/arm/smmuv3: Include missing 'hw/registerfields.h' header Date: Thu, 18 Jan 2024 21:06:24 +0100 Message-ID: <20240118200643.29037-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240118200643.29037-1-philmd@linaro.org> References: <20240118200643.29037-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org hw/arm/smmuv3-internal.h uses the REG32() and FIELD() macros defined in "hw/registerfields.h". Include it in order to avoid when refactoring unrelated headers: In file included from ../../hw/arm/smmuv3.c:34: hw/arm/smmuv3-internal.h:36:28: error: expected identifier REG32(IDR0, 0x0) ^ hw/arm/smmuv3-internal.h:37:5: error: expected function body after function declarator FIELD(IDR0, S2P, 0 , 1) ^ Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/smmuv3-internal.h | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index 6076025ad6..e987bc4686 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -21,6 +21,7 @@ #ifndef HW_ARM_SMMUV3_INTERNAL_H #define HW_ARM_SMMUV3_INTERNAL_H +#include "hw/registerfields.h" #include "hw/arm/smmu-common.h" typedef enum SMMUTranslationStatus { From patchwork Thu Jan 18 20:06:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763644 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp109120wrq; Thu, 18 Jan 2024 12:08:46 -0800 (PST) X-Google-Smtp-Source: AGHT+IF7cckRzEzdVhGOB0PYUPt7w59ambXgP0TXtF7WlsxZT4v91ML3KGJ1FE7AxcWAjOHo52FR X-Received: by 2002:a05:622a:2cc:b0:429:f4c4:c5d7 with SMTP id a12-20020a05622a02cc00b00429f4c4c5d7mr1526919qtx.48.1705608526021; Thu, 18 Jan 2024 12:08:46 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705608526; cv=none; d=google.com; s=arc-20160816; b=J98G7FlF+lMe7vrWekVVJ0F5zn5Sp9V73u49sEkEmKfmHGXifCJObU87ish8p2fv9b N8h39ax264G8EM6wfbdxZbmZXOfJCoUFNWhc/sP/EuSXuiB6AUtUVQ7HCV8xLWYeJ+8p Gz2+d8q2iwCFp8AT7ITSxgwlTKnPiiLHRXwHRx8QACLR3hVd71vavb9vEyoKW5W+V/SJ y2ydTZss3x1YM8ruR5e+mdp1veduxJGT/0NGt6PzZTVx5gsjmx2Xd3MG9QsllD01+H36 WjNgg5NrchFnk4hxlv0u41XF5jLc/9jOTcRjgZ6/GOGz4Ny9iS1RDOw5F4LN8mjET9RH PM8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=eSJ61VYdXLhvSCoYWTAbZrzxB1wnfwdSWkLcd4JmNGA=; fh=cUgEM3TMHOIH70RmHTmTZxZmItZJnKfBWHSaci49aLY=; b=0lnfNKMnqvpykHh862SCrpt7kbJhaq+UlbCOgoRpjSqH1U5hzatJkZxoHFrmqjMO9G tq/7x33FflGES69CntgHNbYfDSmYhs6+DNLVQoVFtfOLsgkqRRsSWEgkdifUdtoY/mnd GburGUS9eYwj5ZyWjEECqJEpmAv/aYG+ovbs7pZPvZfXh6BN9EDVW+op+GFhRpeUUUf4 gga5bcyGZ3Ye56ZkOcz9RFxYHPvgapA+x8fsMjzSg+o+p3QfgOUwYxBmO9i1jpaJPgC+ aHdKG+wH4l7nU4+dt3Zox3iAvdo/tEJfvwV6qfD0rCH/WYtWk/UGLbbk9FkroGBlKsjw g1Qg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="ODQWk/C5"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , Igor Mammedov , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eric Auger , Niek Linnenbank , "Michael S. Tsirkin" , Jan Kiszka , Marcin Juszkiewicz , Alistair Francis , Radoslaw Biernacki , Andrew Jeffery , Andrey Smirnov , Rob Herring , Shannon Zhao , Tyrone Ting , Beniamino Galvani , Alexander Graf , Leif Lindholm , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Paolo Bonzini , Jean-Christophe Dubois , Joel Stanley , Hao Wu , kvm@vger.kernel.org Subject: [PATCH 04/20] hw/arm/xlnx-versal: Include missing 'cpu.h' header Date: Thu, 18 Jan 2024 21:06:25 +0100 Message-ID: <20240118200643.29037-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240118200643.29037-1-philmd@linaro.org> References: <20240118200643.29037-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org include/hw/arm/xlnx-versal.h uses the ARMCPU structure which is defined in the "target/arm/cpu.h" header. Include it in order to avoid when refactoring unrelated headers: In file included from hw/arm/xlnx-versal-virt.c:20: include/hw/arm/xlnx-versal.h:62:23: error: array has incomplete element type 'ARMCPU' (aka 'struct ArchCPU') ARMCPU cpu[XLNX_VERSAL_NR_ACPUS]; ^ Signed-off-by: Philippe Mathieu-Daudé --- include/hw/arm/xlnx-versal.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index b24fa64557..025beb5532 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -34,6 +34,7 @@ #include "hw/net/xlnx-versal-canfd.h" #include "hw/misc/xlnx-versal-cfu.h" #include "hw/misc/xlnx-versal-cframe-reg.h" +#include "target/arm/cpu.h" #define TYPE_XLNX_VERSAL "xlnx-versal" OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) From patchwork Thu Jan 18 20:06:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763643 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp109054wrq; Thu, 18 Jan 2024 12:08:36 -0800 (PST) X-Google-Smtp-Source: AGHT+IFAHhNeR4cRAP224JWY/JLrZdVmxRC6hQihC0TpH3CHfH6dvUsN3F2sFZ+xsm+2NpTF+8ha X-Received: by 2002:a05:620a:3706:b0:783:76ba:a64 with SMTP id de6-20020a05620a370600b0078376ba0a64mr230796qkb.144.1705608515678; Thu, 18 Jan 2024 12:08:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705608515; cv=none; d=google.com; s=arc-20160816; b=cRum+gEiWw5duPXIQuvx0mrhz93WjPbABOqilMLTKLyR/nnxS1SwsG/8CLTLLU4o9T Qq5sBB//dIGibPUEXP/PU+87/+1dqv3xvdQtXGvh38ebTp2nhcv8t7a/REK+kF2JvqFq BjFy4L/kccvo2Y5DhpH5v7WNMV+RcEqI/dXtv6HaHGSX382DEm5EYUGKxkB5TIm49MDd 71pftuP1gjWtmL8jHPlgAClxRMp6MYDzvW/HBc3q4iPoyN0HqTrJkgErYug4bLy6QMmm qNqE8G/J8jHB7yTXGzuI+ywgbJYXECXSSEXfGnADNE80f5oKmM3fjp0sDGIK0UrwekYd udGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=IqI4tMz2yzskRPvxs8gc/s3cCgtxYk3v0bTB1NWtJzM=; fh=cUgEM3TMHOIH70RmHTmTZxZmItZJnKfBWHSaci49aLY=; b=qAvF2bdiuGRSpFLASxAqnSY2wLyzUBnQ0Biy5A0IhkPj4hyYzRLXp4oWhvhvXOj2he W2Xnqnm7UJV6lMNUxq5PlE1oz4OmP/kH94o5ybxgCUtYwpVEx/Y3/QTy51t4Ui/G3rKa 7hy3TIFKucGnOEYsTesGP/A6sDUQ0/iGaqzw4hv/k/gfSoVtgjmyqOj1LHNPO0dGrLv2 91Y/U7HCU56vE1KNCcywOBJ9/jDhpSSuQJHgv4Z+Was5Z/jitfYWdtfVIK4k5BC/c/iB i7dgKTD9MTrMTN4xKlRwF/+3BGQDv0ZB55tRB56M0XjYbrBAKzwlcZg+LCrvHf37Yrgd 8Gbw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Zv/KyXAu"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , Igor Mammedov , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eric Auger , Niek Linnenbank , "Michael S. Tsirkin" , Jan Kiszka , Marcin Juszkiewicz , Alistair Francis , Radoslaw Biernacki , Andrew Jeffery , Andrey Smirnov , Rob Herring , Shannon Zhao , Tyrone Ting , Beniamino Galvani , Alexander Graf , Leif Lindholm , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Paolo Bonzini , Jean-Christophe Dubois , Joel Stanley , Hao Wu , kvm@vger.kernel.org Subject: [PATCH 05/20] target/arm/cpu-features: Include missing 'hw/registerfields.h' header Date: Thu, 18 Jan 2024 21:06:26 +0100 Message-ID: <20240118200643.29037-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240118200643.29037-1-philmd@linaro.org> References: <20240118200643.29037-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org target/arm/cpu-features.h uses the FIELD_EX32() macro defined in "hw/registerfields.h". Include it in order to avoid when refactoring unrelated headers: target/arm/cpu-features.h:44:12: error: call to undeclared function 'FIELD_EX32'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration] return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) != 0; ^ Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu-features.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 7a590c824c..028795ff23 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -20,6 +20,8 @@ #ifndef TARGET_ARM_FEATURES_H #define TARGET_ARM_FEATURES_H +#include "hw/registerfields.h" + /* * Naming convention for isar_feature functions: * Functions which test 32-bit ID registers should have _aa32_ in From patchwork Thu Jan 18 20:06:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763641 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp108910wrq; Thu, 18 Jan 2024 12:08:16 -0800 (PST) X-Google-Smtp-Source: AGHT+IEzoXYZMMMTNNRY8Sa7+lb4acLFVGuqUxrc+CbsLfq2ljAyJrk8rUBT5rg3Pvepjpc0AohH X-Received: by 2002:a05:6214:20ab:b0:681:1197:e7b8 with SMTP id 11-20020a05621420ab00b006811197e7b8mr4028098qvd.40.1705608496207; Thu, 18 Jan 2024 12:08:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705608496; cv=none; d=google.com; s=arc-20160816; b=l7VL/bOf7laCJQPxFFc6hHAWwMVBoQBHnFSLpHZwhImZ3eyUkW4o1agu5AAhNg2tA/ rJfVJcztVkXRlm+h8fIfrwU/uZDdyFBBhQ+vfADHV0d1vJwsCSSkqimkwb9xfoMD7Mzs KJ2Ym9SplON8+YSuSAmBJbwphf2ujT8IT7qa8SZb+j+9UwsMI0/PwNf1JSyDitEE76wh lbExQEoLAlLzyd7EPRaWOek8zhZ57umLNrYnr2kGYrwIKzDMeFTT/D/R0Z1JRGXUs9jL +RItZOxs+pqU3kD20miCJk3TY5O9qlNTMpJKf4tRCdPhqpV0CWSBSUgjQDst3jG2DfPR sblQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=nPG2WfDmNMhkMT4jWeTVRmIkZRsis0mgcrg/P3hE0Ws=; fh=cUgEM3TMHOIH70RmHTmTZxZmItZJnKfBWHSaci49aLY=; b=bIbX5prAoy6LBm6idOnDgi+zQjDhhJnXn71JyGiHcdRvoz2mPLhV/5CkEZy+FnD51Z pVhdo1sTR+SgmVNmZp1G53JW8ucQHZz/oHswQ4uX3DMi8bIzFH5HfyUUu1gblmSbsvph TIeTGOwGGTQhJMJVWxWXYi20tQKzWH/YfYrxBhpLqGVCOzLQy5oq/v+gCnM972EUb91j 6w6Kp68LJoW1eVVTMvPG6qerGMMFDYb6pI0Svq8TDJ1zP2br32CSXGj8QdFQ0TVBlcFy iNQaNy+dBSdlXjQ9S7eEs+8PgnxddhVoE3TVmRGNqjCxBy/kIxduE8+OjfJyS3oBZeA/ Fztg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hEnaDDvd; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , Igor Mammedov , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eric Auger , Niek Linnenbank , "Michael S. Tsirkin" , Jan Kiszka , Marcin Juszkiewicz , Alistair Francis , Radoslaw Biernacki , Andrew Jeffery , Andrey Smirnov , Rob Herring , Shannon Zhao , Tyrone Ting , Beniamino Galvani , Alexander Graf , Leif Lindholm , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Paolo Bonzini , Jean-Christophe Dubois , Joel Stanley , Hao Wu , kvm@vger.kernel.org Subject: [PATCH 06/20] target/arm/cpregs: Include missing 'hw/registerfields.h' header Date: Thu, 18 Jan 2024 21:06:27 +0100 Message-ID: <20240118200643.29037-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240118200643.29037-1-philmd@linaro.org> References: <20240118200643.29037-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org target/arm/cpregs.h uses the FIELD() macro defined in "hw/registerfields.h". Include it in order to avoid when refactoring unrelated headers: target/arm/cpregs.h:347:30: error: expected identifier FIELD(HFGRTR_EL2, AFSR0_EL1, 0, 1) ^ Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpregs.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index b6fdd0f3eb..ca2d6006ce 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -21,6 +21,8 @@ #ifndef TARGET_ARM_CPREGS_H #define TARGET_ARM_CPREGS_H +#include "hw/registerfields.h" + /* * ARMCPRegInfo type field bits: */ From patchwork Thu Jan 18 20:06:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763642 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp108948wrq; Thu, 18 Jan 2024 12:08:21 -0800 (PST) X-Google-Smtp-Source: AGHT+IGPhCjV4EPlk/cGEvHqBYKH64FJnrutkxGR3kYo7HCkm99mUkkCQByRkA4ao+BhuGOJb9mh X-Received: by 2002:a92:730c:0:b0:361:96c3:2f56 with SMTP id o12-20020a92730c000000b0036196c32f56mr1157273ilc.65.1705608501591; Thu, 18 Jan 2024 12:08:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705608501; cv=none; d=google.com; s=arc-20160816; b=Z1vB2eltBcDT9J7KwzmWPCOxiIBUkAltCweKXib2yM3U1S6YV3MlxkL2vqCsonMNzi lr7CTcgR9Z3u5AowhmhMrpxpyKuqjQUlK3z/Rvgpkwa6h6EE7mKxeX7/XeZVwE96xh/X 62Ocyw0msZhMWNIK4zKdIfeF0Eui/q5UGLY3M24LwwpSqrqix8ORbOdJCtzZde6E6Ve3 O1Por6bYrr8sP1qBprEuydc3k51aRFkAB56QIHzABJu0dJY/VaYGzXGhLoB7umGrpCQ8 KIhFyi71ZEY2eyv/Dm7KFl1BcMhm9X4OOPLSX5IojekuIgwiKXvYyL5yUI+bHV1v8sK/ ofTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=LrKc6a2ST12i1A3LtQl32z7hhWzowcoULUtetVq5wyM=; fh=cUgEM3TMHOIH70RmHTmTZxZmItZJnKfBWHSaci49aLY=; b=f//JjC1ng2SdZJFJcnhXlTW7d9EF5eWxhoK5zoPkG68FXLmYxBGb3IrCiCXJCCttsz xsQM1ugSbGYnw9lrysDCZQDkOMQ11A1CaCs7UO0xHo9PwyC42VPeQRugJ55MfPHHDHKe Ci7yBs0tpav/0IBwDMhY3NdT3xj0LhqNEEEMKEqHkA4ThuZJ1HgmOS9wkv0cc5Im0ZNE wWhiClF6hf5NKDSnBBPerl9mK3YrthwkuLDhVsjQaUMdbjFi/Z//aVuSVikF+a/qGZOR 1hs3L2vcMTF+MDEXeNlIpkxl5avC9PfR0SqNwA+dv6LbxCcQH0JiLNbmqvmIvNwsCWk9 EZCg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kG7OiRvl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , Igor Mammedov , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eric Auger , Niek Linnenbank , "Michael S. Tsirkin" , Jan Kiszka , Marcin Juszkiewicz , Alistair Francis , Radoslaw Biernacki , Andrew Jeffery , Andrey Smirnov , Rob Herring , Shannon Zhao , Tyrone Ting , Beniamino Galvani , Alexander Graf , Leif Lindholm , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Paolo Bonzini , Jean-Christophe Dubois , Joel Stanley , Hao Wu , kvm@vger.kernel.org Subject: [PATCH 07/20] target/arm/cpregs: Include missing 'kvm-consts.h' header Date: Thu, 18 Jan 2024 21:06:28 +0100 Message-ID: <20240118200643.29037-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240118200643.29037-1-philmd@linaro.org> References: <20240118200643.29037-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org target/arm/cpregs.h uses the CP_REG_ARCH_* definitions from "target/arm/kvm-consts.h". Include it in order to avoid when refactoring unrelated headers: target/arm/cpregs.h:191:18: error: use of undeclared identifier 'CP_REG_ARCH_MASK' if ((kvmid & CP_REG_ARCH_MASK) == CP_REG_ARM64) { ^ Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpregs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index ca2d6006ce..cc7c54378f 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -22,6 +22,7 @@ #define TARGET_ARM_CPREGS_H #include "hw/registerfields.h" +#include "target/arm/kvm-consts.h" /* * ARMCPRegInfo type field bits: From patchwork Thu Jan 18 20:06:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763655 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp110462wrq; Thu, 18 Jan 2024 12:11:46 -0800 (PST) X-Google-Smtp-Source: AGHT+IHdZMHHyCj6/ZpA+M1TbsQUNwJYdYafe2kGVAaNrjtO1xOERozSst0U8UwIRXNP6A3VfpZV X-Received: by 2002:a4a:cb8b:0:b0:599:4570:24f5 with SMTP id y11-20020a4acb8b000000b00599457024f5mr1406442ooq.0.1705608705984; Thu, 18 Jan 2024 12:11:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705608705; cv=none; d=google.com; s=arc-20160816; b=yJYK9dJy4cBaoy0mUHIwuBCS4szFGECfW2KAZkKqo9xsCkWhzyMKUenZrBgjkJONCn Ko8zz84eJZWA6S9kLjnWahi+QDZ4JsgGQw5nFy0zBUuqsvW37xzBm3RAw9z9JJ0WZ4iZ gmeadTEhkDV1oh2+32pCwhu0UKqIGbrGJwukPR4pdALOIS4TXBOawYCFux2WCtVmbYP/ gLYnEO/K+ErarSaxjSxcq0HxffydM9Smz93/axYUzcDZCk78D/7vDdoUfYuvy/RRus2F ToRrdJrqLt+gqsnAHMGIwHUHxLuCd0rQd83Kpw9Nd7wOmi72nAVvYkC/qQBsi5jc84RW 7rdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=7hzkrmNX2ysOo1dkZvzaMS1RLQpmfGYrCHnlQkXBKNY=; fh=GY0J1BHXV8JCT94Jevwcoc+qV/LriKwcR3tgpDluTBE=; b=RueM7kdq/wOnUuMNgyvd5XWFnVcspwsicgDqg0bqi1mFnnhMAxuM5kVQ6G55OdTYbO 8jxHGq1FY6NjlSRBs4TU3Mlc6flmW5sf0lm0qp0qBroiHYQE/UIzJNmVw4sshv3iF9yU P2+KsnZWLwNPnMNJMxBthooZy0CMlVtcXj+pXLfCNc0cdgmHy8+EZSvvGItdal3hn3te ou9MZX1iq7JMYSccdo/z9Q6g49lyW9t+WqfIKVRbYSeSyVF+k2nZZqFUcCLySF9dTZx+ 0weFOc17M89Vqjlqu4jylXO9FuT6XLVruRWXGI8heGBe+tYIDLxZgclc1pWo5kkzdqVO 7zcQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=O61rlZln; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , Igor Mammedov , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eric Auger , Niek Linnenbank , "Michael S. Tsirkin" , Jan Kiszka , Marcin Juszkiewicz , Alistair Francis , Radoslaw Biernacki , Andrew Jeffery , Andrey Smirnov , Rob Herring , Shannon Zhao , Tyrone Ting , Beniamino Galvani , Alexander Graf , Leif Lindholm , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Paolo Bonzini , Jean-Christophe Dubois , Joel Stanley , Hao Wu , kvm@vger.kernel.org, Richard Henderson Subject: [PATCH 08/20] target/arm: Rename arm_cpu_mp_affinity Date: Thu, 18 Jan 2024 21:06:29 +0100 Message-ID: <20240118200643.29037-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240118200643.29037-1-philmd@linaro.org> References: <20240118200643.29037-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Rename to arm_build_mp_affinity. This frees up the name for other usage, and emphasizes that the cpu object is not involved. Signed-off-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.h | 2 +- hw/arm/npcm7xx.c | 2 +- hw/arm/sbsa-ref.c | 2 +- hw/arm/virt.c | 2 +- target/arm/cpu.c | 6 +++--- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ec276fcd57..55a19e8539 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1171,7 +1171,7 @@ void arm_cpu_post_init(Object *obj); (ARM_AFF0_MASK | ARM_AFF1_MASK | ARM_AFF2_MASK | ARM_AFF3_MASK) #define ARM64_AFFINITY_INVALID (~ARM64_AFFINITY_MASK) -uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz); +uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz); #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_arm_cpu; diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index 15ff21d047..7fb0a233b2 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -474,7 +474,7 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) /* CPUs */ for (i = 0; i < nc->num_cpus; i++) { object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity", - arm_cpu_mp_affinity(i, NPCM7XX_MAX_NUM_CPUS), + arm_build_mp_affinity(i, NPCM7XX_MAX_NUM_CPUS), &error_abort); object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", NPCM7XX_GIC_CPU_IF_ADDR, &error_abort); diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 477dca0637..b8857d1e9e 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -148,7 +148,7 @@ static const int sbsa_ref_irqmap[] = { static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx) { uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER; - return arm_cpu_mp_affinity(idx, clustersz); + return arm_build_mp_affinity(idx, clustersz); } static void sbsa_fdt_add_gic_node(SBSAMachineState *sms) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 2793121cb4..3fc144236b 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1676,7 +1676,7 @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) clustersz = GICV3_TARGETLIST_BITS; } } - return arm_cpu_mp_affinity(idx, clustersz); + return arm_build_mp_affinity(idx, clustersz); } static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms, diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 826ce842c0..0bbba48faa 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1307,7 +1307,7 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags) } } -uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz) +uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz) { uint32_t Aff1 = idx / clustersz; uint32_t Aff0 = idx % clustersz; @@ -2113,8 +2113,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) * so these bits always RAZ. */ if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) { - cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index, - ARM_DEFAULT_CPUS_PER_CLUSTER); + cpu->mp_affinity = arm_build_mp_affinity(cs->cpu_index, + ARM_DEFAULT_CPUS_PER_CLUSTER); } if (cpu->reset_hivecs) { From patchwork Thu Jan 18 20:06:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763650 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp109787wrq; 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Iglesias" , Igor Mammedov , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eric Auger , Niek Linnenbank , "Michael S. Tsirkin" , Jan Kiszka , Marcin Juszkiewicz , Alistair Francis , Radoslaw Biernacki , Andrew Jeffery , Andrey Smirnov , Rob Herring , Shannon Zhao , Tyrone Ting , Beniamino Galvani , Alexander Graf , Leif Lindholm , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Paolo Bonzini , Jean-Christophe Dubois , Joel Stanley , Hao Wu , kvm@vger.kernel.org, Richard Henderson Subject: [PATCH 09/20] target/arm: Create arm_cpu_mp_affinity Date: Thu, 18 Jan 2024 21:06:30 +0100 Message-ID: <20240118200643.29037-10-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240118200643.29037-1-philmd@linaro.org> References: <20240118200643.29037-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Wrapper to return the mp affinity bits from the cpu. Signed-off-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.h | 5 +++++ hw/arm/virt-acpi-build.c | 2 +- hw/arm/virt.c | 6 +++--- hw/arm/xlnx-versal-virt.c | 3 ++- hw/misc/xlnx-versal-crl.c | 4 ++-- target/arm/arm-powerctl.c | 2 +- target/arm/hvf/hvf.c | 4 ++-- target/arm/tcg/psci.c | 2 +- 8 files changed, 17 insertions(+), 11 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 55a19e8539..d1584bdb3b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1173,6 +1173,11 @@ void arm_cpu_post_init(Object *obj); uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz); +static inline uint64_t arm_cpu_mp_affinity(ARMCPU *cpu) +{ + return cpu->mp_affinity; +} + #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_arm_cpu; diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index a22a2f43a5..2127778c1e 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -720,7 +720,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) build_append_int_noprefix(table_data, vgic_interrupt, 4); build_append_int_noprefix(table_data, 0, 8); /* GICR Base Address*/ /* MPIDR */ - build_append_int_noprefix(table_data, armcpu->mp_affinity, 8); + build_append_int_noprefix(table_data, arm_cpu_mp_affinity(armcpu), 8); /* Processor Power Efficiency Class */ build_append_int_noprefix(table_data, 0, 1); /* Reserved */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 3fc144236b..34cba9ebd8 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -370,7 +370,7 @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms) for (cpu = 0; cpu < smp_cpus; cpu++) { ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu)); - if (armcpu->mp_affinity & ARM_AFF3_MASK) { + if (arm_cpu_mp_affinity(armcpu) & ARM_AFF3_MASK) { addr_cells = 2; break; } @@ -397,10 +397,10 @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms) if (addr_cells == 2) { qemu_fdt_setprop_u64(ms->fdt, nodename, "reg", - armcpu->mp_affinity); + arm_cpu_mp_affinity(armcpu)); } else { qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", - armcpu->mp_affinity); + arm_cpu_mp_affinity(armcpu)); } if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index 537118224f..841ef69df6 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -107,7 +107,8 @@ static void fdt_add_cpu_nodes(VersalVirt *s, uint32_t psci_conduit) ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i)); qemu_fdt_add_subnode(s->fdt, name); - qemu_fdt_setprop_cell(s->fdt, name, "reg", armcpu->mp_affinity); + qemu_fdt_setprop_cell(s->fdt, name, "reg", + arm_cpu_mp_affinity(armcpu)); if (psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) { qemu_fdt_setprop_string(s->fdt, name, "enable-method", "psci"); } diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c index ac6889fcf2..9bfa9baa15 100644 --- a/hw/misc/xlnx-versal-crl.c +++ b/hw/misc/xlnx-versal-crl.c @@ -67,9 +67,9 @@ static void crl_reset_cpu(XlnxVersalCRL *s, ARMCPU *armcpu, bool rst_old, bool rst_new) { if (rst_new) { - arm_set_cpu_off(armcpu->mp_affinity); + arm_set_cpu_off(arm_cpu_mp_affinity(armcpu)); } else { - arm_set_cpu_on_and_reset(armcpu->mp_affinity); + arm_set_cpu_on_and_reset(arm_cpu_mp_affinity(armcpu)); } } diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index 8850381565..6c86e90102 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -37,7 +37,7 @@ CPUState *arm_get_cpu_by_id(uint64_t id) CPU_FOREACH(cpu) { ARMCPU *armcpu = ARM_CPU(cpu); - if (armcpu->mp_affinity == id) { + if (arm_cpu_mp_affinity(armcpu) == id) { return cpu; } } diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index a537a5bc94..659401e12c 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1016,7 +1016,7 @@ static void hvf_raise_exception(CPUState *cpu, uint32_t excp, static void hvf_psci_cpu_off(ARMCPU *arm_cpu) { - int32_t ret = arm_set_cpu_off(arm_cpu->mp_affinity); + int32_t ret = arm_set_cpu_off(arm_cpu_mp_affinity(arm_cpu)); assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS); } @@ -1045,7 +1045,7 @@ static bool hvf_handle_psci_call(CPUState *cpu) int32_t ret = 0; trace_hvf_psci_call(param[0], param[1], param[2], param[3], - arm_cpu->mp_affinity); + arm_cpu_mp_affinity(arm_cpu)); switch (param[0]) { case QEMU_PSCI_0_2_FN_PSCI_VERSION: diff --git a/target/arm/tcg/psci.c b/target/arm/tcg/psci.c index 9080a91d9c..50d4b23d26 100644 --- a/target/arm/tcg/psci.c +++ b/target/arm/tcg/psci.c @@ -215,7 +215,7 @@ err: return; cpu_off: - ret = arm_set_cpu_off(cpu->mp_affinity); + ret = arm_set_cpu_off(arm_cpu_mp_affinity(cpu)); /* notreached */ /* sanity check in case something failed */ assert(ret == QEMU_ARM_POWERCTL_RET_SUCCESS); From patchwork Thu Jan 18 20:06:31 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763639 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp108854wrq; Thu, 18 Jan 2024 12:08:07 -0800 (PST) X-Google-Smtp-Source: AGHT+IH1yd+SWpq0MrzeTidJxHmcu0ejlp7Cs1f6/AXaQgCiAYkVxyz36/t6oeDY0XAfi948Yf+J X-Received: by 2002:ad4:5f8f:0:b0:681:9227:46ad with SMTP id jp15-20020ad45f8f000000b00681922746admr1664093qvb.38.1705608487555; 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Iglesias" , Igor Mammedov , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eric Auger , Niek Linnenbank , "Michael S. Tsirkin" , Jan Kiszka , Marcin Juszkiewicz , Alistair Francis , Radoslaw Biernacki , Andrew Jeffery , Andrey Smirnov , Rob Herring , Shannon Zhao , Tyrone Ting , Beniamino Galvani , Alexander Graf , Leif Lindholm , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Paolo Bonzini , Jean-Christophe Dubois , Joel Stanley , Hao Wu , kvm@vger.kernel.org Subject: [PATCH 10/20] target/arm: Expose arm_cpu_mp_affinity() in 'multiprocessing.h' header Date: Thu, 18 Jan 2024 21:06:31 +0100 Message-ID: <20240118200643.29037-11-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240118200643.29037-1-philmd@linaro.org> References: <20240118200643.29037-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Declare arm_cpu_mp_affinity() prototype in the new "target/arm/multiprocessing.h" header so units in hw/arm/ can use it without having to include the huge target-specific "cpu.h". File list to include the new header generated using: $ git grep -lw arm_cpu_mp_affinity Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.h | 6 +----- target/arm/multiprocessing.h | 16 ++++++++++++++++ hw/arm/virt-acpi-build.c | 1 + hw/arm/virt.c | 1 + hw/arm/xlnx-versal-virt.c | 1 + hw/misc/xlnx-versal-crl.c | 1 + target/arm/arm-powerctl.c | 1 + target/arm/cpu.c | 5 +++++ target/arm/hvf/hvf.c | 1 + target/arm/tcg/psci.c | 1 + 10 files changed, 29 insertions(+), 5 deletions(-) create mode 100644 target/arm/multiprocessing.h diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d1584bdb3b..cecac4c0a1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -26,6 +26,7 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" #include "qapi/qapi-types-common.h" +#include "target/arm/multiprocessing.h" /* ARM processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) @@ -1173,11 +1174,6 @@ void arm_cpu_post_init(Object *obj); uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz); -static inline uint64_t arm_cpu_mp_affinity(ARMCPU *cpu) -{ - return cpu->mp_affinity; -} - #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_arm_cpu; diff --git a/target/arm/multiprocessing.h b/target/arm/multiprocessing.h new file mode 100644 index 0000000000..81715d345c --- /dev/null +++ b/target/arm/multiprocessing.h @@ -0,0 +1,16 @@ +/* + * ARM multiprocessor CPU helpers + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef TARGET_ARM_MULTIPROCESSING_H +#define TARGET_ARM_MULTIPROCESSING_H + +#include "target/arm/cpu-qom.h" + +uint64_t arm_cpu_mp_affinity(ARMCPU *cpu); + +#endif diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 2127778c1e..43ccc60f43 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -59,6 +59,7 @@ #include "hw/acpi/ghes.h" #include "hw/acpi/viot.h" #include "hw/virtio/virtio-acpi.h" +#include "target/arm/multiprocessing.h" #define ARM_SPI_BASE 32 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 34cba9ebd8..beba151620 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -74,6 +74,7 @@ #include "hw/arm/smmuv3.h" #include "hw/acpi/acpi.h" #include "target/arm/internals.h" +#include "target/arm/multiprocessing.h" #include "hw/mem/pc-dimm.h" #include "hw/mem/nvdimm.h" #include "hw/acpi/generic_event_device.h" diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index 841ef69df6..29f4d2c2dc 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -20,6 +20,7 @@ #include "hw/qdev-properties.h" #include "hw/arm/xlnx-versal.h" #include "hw/arm/boot.h" +#include "target/arm/multiprocessing.h" #include "qom/object.h" #define TYPE_XLNX_VERSAL_VIRT_MACHINE MACHINE_TYPE_NAME("xlnx-versal-virt") diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c index 9bfa9baa15..1f1762ef16 100644 --- a/hw/misc/xlnx-versal-crl.c +++ b/hw/misc/xlnx-versal-crl.c @@ -19,6 +19,7 @@ #include "hw/resettable.h" #include "target/arm/arm-powerctl.h" +#include "target/arm/multiprocessing.h" #include "hw/misc/xlnx-versal-crl.h" #ifndef XLNX_VERSAL_CRL_ERR_DEBUG diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c index 6c86e90102..2b2055c6ac 100644 --- a/target/arm/arm-powerctl.c +++ b/target/arm/arm-powerctl.c @@ -16,6 +16,7 @@ #include "qemu/log.h" #include "qemu/main-loop.h" #include "sysemu/tcg.h" +#include "target/arm/multiprocessing.h" #ifndef DEBUG_ARM_POWERCTL #define DEBUG_ARM_POWERCTL 0 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0bbba48faa..89e44a31fd 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1314,6 +1314,11 @@ uint64_t arm_build_mp_affinity(int idx, uint8_t clustersz) return (Aff1 << ARM_AFF1_SHIFT) | Aff0; } +uint64_t arm_cpu_mp_affinity(ARMCPU *cpu) +{ + return cpu->mp_affinity; +} + static void arm_cpu_initfn(Object *obj) { ARMCPU *cpu = ARM_CPU(obj); diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 659401e12c..71a26db188 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -28,6 +28,7 @@ #include "arm-powerctl.h" #include "target/arm/cpu.h" #include "target/arm/internals.h" +#include "target/arm/multiprocessing.h" #include "trace/trace-target_arm_hvf.h" #include "migration/vmstate.h" diff --git a/target/arm/tcg/psci.c b/target/arm/tcg/psci.c index 50d4b23d26..51d2ca3d30 100644 --- a/target/arm/tcg/psci.c +++ b/target/arm/tcg/psci.c @@ -24,6 +24,7 @@ #include "sysemu/runstate.h" #include "internals.h" #include "arm-powerctl.h" +#include "target/arm/multiprocessing.h" bool arm_is_psci_call(ARMCPU *cpu, int excp_type) { From patchwork Thu Jan 18 20:06:32 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763653 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp110203wrq; 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[209.51.188.17]) by mx.google.com with ESMTPS id h12-20020a37c44c000000b0078324ce8a91si14289469qkm.515.2024.01.18.12.11.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jan 2024 12:11:11 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NQMxz9hG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rQYg8-0004dJ-FN; Thu, 18 Jan 2024 15:07:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQYg4-000498-6d for qemu-devel@nongnu.org; Thu, 18 Jan 2024 15:07:53 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rQYg2-000700-IT for qemu-devel@nongnu.org; Thu, 18 Jan 2024 15:07:51 -0500 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-40e60e135a7so307665e9.0 for ; Thu, 18 Jan 2024 12:07:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705608469; x=1706213269; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wzXk5yiY5MpA6wV2WpkIOyNiGD0qCuniPF02smOcXHA=; b=NQMxz9hGkxsZ2QGaC5LgCOV+I2h6LPffBqiN0NEEA0eGGq82mWPG29YkzVf05pJw8i sltT6dX/HdhVotU+U9hc3e/oyvJyZqXTphfohQ2u6VGoU9LzU17Qxr/80BP1rBOJzH8Q nXE/uWEwY38g/A+pP3ZRlYEm+8oZCeLrYnbmTZP9Sficw7Mulj4d+6gAqA6JuyTMvg1g WmLsFByuJi+WP2nwNtXCdpmbjQDCIGJK62vTWtRBX+B3VleHR3xr2tRv/gKY9PgPncyp p63l9UiljsSJvQk1VA4jBDq/urOIEen6r6hQjJQCwC4cIC0BTW28idBS089breCY3lJ9 D6KA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705608469; x=1706213269; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wzXk5yiY5MpA6wV2WpkIOyNiGD0qCuniPF02smOcXHA=; b=blgBNYuIQggZfxV1OS+loDK+m9Nmpk6jt0HEND1DqelJSB9/sluZbxXfIDVehy4ME4 w0Q5HQ2+ywwcxOmCcFjpni/hlJ3HQWP2huTOg69T8T/xIjIzT3uvytmmBLi0WW7X4oK2 4FwOYKcbHdOLUah/Byqf+OkWnQ7oWYk/DGLF7jujkByCXrFtZsinMr/VivhpU/TuBd5o zRvxuaed4DCPpEeyp0+fclAmMjuECRb2/vovDnRtjYipLPsjlP4X3OyUzjz/Y0FhCdpN q6hq3d0IKA59oXksaPHPddtRosU2FEQH8JAi79jNvxjRStbZiqQ4FHlsP7GrMh54v8cf 6bYA== X-Gm-Message-State: AOJu0YwaFv+bPfInh0Zl0mmAV7j+bEs7wUX5bzRiPfTDNsqmlwf7yE5I 5wwjQutSB2Q378ofS2rJsgJRzgVz6mduc545zbQ6U4xfJPIRloqrFwQ2ElABPDm9/TmrFB+DHKv GXyk0aexv X-Received: by 2002:adf:f191:0:b0:337:cef4:ae1e with SMTP id h17-20020adff191000000b00337cef4ae1emr909314wro.20.1705608469011; Thu, 18 Jan 2024 12:07:49 -0800 (PST) Received: from localhost.localdomain ([78.196.4.158]) by smtp.gmail.com with ESMTPSA id o9-20020adfe809000000b00337bf81e06bsm4758039wrm.48.2024.01.18.12.07.47 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 18 Jan 2024 12:07:48 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Igor Mitsyanko , qemu-arm@nongnu.org, Strahinja Jankovic , "Edgar E. Iglesias" , Igor Mammedov , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eric Auger , Niek Linnenbank , "Michael S. Tsirkin" , Jan Kiszka , Marcin Juszkiewicz , Alistair Francis , Radoslaw Biernacki , Andrew Jeffery , Andrey Smirnov , Rob Herring , Shannon Zhao , Tyrone Ting , Beniamino Galvani , Alexander Graf , Leif Lindholm , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Paolo Bonzini , Jean-Christophe Dubois , Joel Stanley , Hao Wu , kvm@vger.kernel.org, Richard Henderson Subject: [PATCH 11/20] target/arm: Declare ARM_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h' Date: Thu, 18 Jan 2024 21:06:32 +0100 Message-ID: <20240118200643.29037-12-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240118200643.29037-1-philmd@linaro.org> References: <20240118200643.29037-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Missed in commit 2d56be5a29 ("target: Declare FOO_CPU_TYPE_NAME/SUFFIX in 'cpu-qom.h'"). See it for more details. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/cpu-qom.h | 3 +++ target/arm/cpu.h | 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 02b914c876..f795994135 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -33,4 +33,7 @@ typedef struct AArch64CPUClass AArch64CPUClass; DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, TYPE_AARCH64_CPU) +#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU +#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) + #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cecac4c0a1..41659d0ef1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2837,8 +2837,6 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync); #define ARM_CPUID_TI915T 0x54029152 #define ARM_CPUID_TI925T 0x54029252 -#define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU -#define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) #define CPU_RESOLVING_TYPE TYPE_ARM_CPU #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU From patchwork Thu Jan 18 20:06:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763645 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp109174wrq; Thu, 18 Jan 2024 12:08:54 -0800 (PST) X-Google-Smtp-Source: AGHT+IFBSzQ9zHocusAEnXXQFuoFaBSXgeDQoQA5Eb1ZJ8UunXi9Lnxz3mEm06e3fbutUSFAxBpL X-Received: by 2002:a05:6808:3319:b0:3bc:1316:b737 with SMTP id ca25-20020a056808331900b003bc1316b737mr1549695oib.47.1705608534529; Thu, 18 Jan 2024 12:08:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705608534; cv=none; d=google.com; s=arc-20160816; b=FzFxYAdOfzk34ZjU9gNjCi+RoezbHY1nQjU6a4GgtNwV9x2j1BjC8ztc+nWMY0kaYt BNpWDKUFo/DewL+4NlT/PwuY5m4XnLvGWWDlbZzj5EniawsbicqpcJXhy+U5nAz2YBLO YY4JfHeg40qgbRcRP6B5WvbjKf5s22aQ81Es8hHraVjxr/e1nkpafAFtNEhBdOhargLp +fM+dXzPKoStSkaE0xhqi8lTnAgR3vG+Z8mkr9A9e2VVwAOf1YYkScnUjkg3Q/HWSsou iYPUfb3/BB7a0zgC9koY8jSqjWjHUysAao41VXRrz3jtxZz3ijBvMnQRRi/8nQHbkxMB 9h4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=NepvwILR8saXQ0DwpYtr1EjRADd2IuMlIDWFe0pCcHE=; fh=cUgEM3TMHOIH70RmHTmTZxZmItZJnKfBWHSaci49aLY=; b=OWV6qfapERxQgNS9ymWzE75I6KQzXnUmScmuOknBelZ3Fudy9MTefPba2lAtDf4xul z3AQiH7pKWDfbOECHtCjwabOxo9OeJAE1rbW+kfwoeRcC9Bfnh2k/u6VY8eU0tY5WScX bJjNBPRa4t+BVsCOy1+xLk2wTRVotJ9ZhE1ZBzltVfr0Jd3P53hu073ghWE4iELMdpR1 bQuLJCmxB+/BJGsL9LLC6/Nzr+5LlHHnizhFSR4EOlFoE9CE6181B6STlq0ipTXKZ4tI s60F4DJujLVJ+zC9tGzI0HE4cLKLgxpqxHefSET4P1iCrtaJIMcSusCRlW2vfz7zi+K/ zGKA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lz9U6aLv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id r6-20020a05622a034600b0042a1e4c6241si1312425qtw.703.2024.01.18.12.08.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jan 2024 12:08:54 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lz9U6aLv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rQYgB-0004zD-Jc; Thu, 18 Jan 2024 15:07:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQYgA-0004rw-5M for qemu-devel@nongnu.org; Thu, 18 Jan 2024 15:07:58 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rQYg8-00070i-Ez for qemu-devel@nongnu.org; Thu, 18 Jan 2024 15:07:57 -0500 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-40e586a62f7so241375e9.2 for ; Thu, 18 Jan 2024 12:07:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705608475; x=1706213275; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NepvwILR8saXQ0DwpYtr1EjRADd2IuMlIDWFe0pCcHE=; b=lz9U6aLvrSKJBl62+ubSLFWpv3647QJDh2a09i+LPxxy7PwOfwyE215iuG5g3M3aLj o8HRUIBaIDvw0UPYWAaCFFqqCOLnipEY16Ls38IcI+hGFgls3DUPBrBJrgOPzJA0658w g5I4+W2yX7k1nuNf6cnR7cooPjyGT/KcvtCXNNcZE9oa2sXkHyLnldTjZfnZCNSNSvRO IAi9YA3gf4JCuf7xS/C8iXcb5u3DooYVKJfmawTdU7kqTF5s6Loazs6rdBXER6lx322I n0w7oO+Wohe+R1dPoYsCa2IlAuWbeiWDRdt5eIGRiJk5MtCDAn5NicIcv9iFP/+oTMel s2Uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705608475; x=1706213275; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NepvwILR8saXQ0DwpYtr1EjRADd2IuMlIDWFe0pCcHE=; b=EMzK/L6f3esoB3P24B4Lc1TcrdfHGyljcIA6D3y0bOilOBDKtnyghXbDGTEnBMGNA5 YisXDlW0OaTh6TCSS03FV4+ZTSu0Po1GKHRZ7YKBJ6q3QB3RoftlyztAJGbCF0+BqcDO slVJzAsTN83X5lcqkna7Zd75TTzlWZvArPyh12sXKhE+WW+P3Bny2vRXQPPZ6rA1vPXc /H0B6t7P1HhEvyOj97xNLBjrWYJU6dncT/KvsQLWH983p6gdfwnrWC/k9P1toLGeU2i+ FnCtQmENVMAp81d7ZrnAeDwScm+h+jdupBM8qr9Ut4bY5663O2UdiEfbCs+K2OFNoyEe iyOQ== X-Gm-Message-State: AOJu0Yw1MUG60X4P5BxobHsULAJdm9NzcBkO2Wk+IoZLpDzX5822WUG3 Wvkl09LnFXenGiXO5nkZm/9lDVSQa5IFwvrsysitABtt6LAd1kUDEU4PmEyC+OenkpPQ54tfZsT tgw2qbpo+ X-Received: by 2002:a1c:721a:0:b0:40e:85fe:b00d with SMTP id n26-20020a1c721a000000b0040e85feb00dmr911900wmc.97.1705608475040; Thu, 18 Jan 2024 12:07:55 -0800 (PST) Received: from localhost.localdomain ([78.196.4.158]) by smtp.gmail.com with ESMTPSA id iw7-20020a05600c54c700b0040d604dea3bsm26301559wmb.4.2024.01.18.12.07.53 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 18 Jan 2024 12:07:54 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Igor Mitsyanko , qemu-arm@nongnu.org, Strahinja Jankovic , "Edgar E. Iglesias" , Igor Mammedov , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eric Auger , Niek Linnenbank , "Michael S. Tsirkin" , Jan Kiszka , Marcin Juszkiewicz , Alistair Francis , Radoslaw Biernacki , Andrew Jeffery , Andrey Smirnov , Rob Herring , Shannon Zhao , Tyrone Ting , Beniamino Galvani , Alexander Graf , Leif Lindholm , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Paolo Bonzini , Jean-Christophe Dubois , Joel Stanley , Hao Wu , kvm@vger.kernel.org Subject: [PATCH 12/20] hw/cpu/a9mpcore: Build it only once Date: Thu, 18 Jan 2024 21:06:33 +0100 Message-ID: <20240118200643.29037-13-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240118200643.29037-1-philmd@linaro.org> References: <20240118200643.29037-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org hw/cpu/a9mpcore.c doesn't require "cpu.h" anymore. By removing it, the unit become target agnostic: we can build it once. Update meson. Signed-off-by: Philippe Mathieu-Daudé --- hw/cpu/a9mpcore.c | 2 +- hw/cpu/meson.build | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index d03f57e579..c30ef72c66 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -15,7 +15,7 @@ #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/core/cpu.h" -#include "cpu.h" +#include "target/arm/cpu-qom.h" #define A9_GIC_NUM_PRIORITY_BITS 5 diff --git a/hw/cpu/meson.build b/hw/cpu/meson.build index 6d319947ca..38cdcfbe57 100644 --- a/hw/cpu/meson.build +++ b/hw/cpu/meson.build @@ -2,5 +2,5 @@ system_ss.add(files('core.c', 'cluster.c')) system_ss.add(when: 'CONFIG_ARM11MPCORE', if_true: files('arm11mpcore.c')) system_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview_mpcore.c')) -specific_ss.add(when: 'CONFIG_A9MPCORE', if_true: files('a9mpcore.c')) +system_ss.add(when: 'CONFIG_A9MPCORE', if_true: files('a9mpcore.c')) specific_ss.add(when: 'CONFIG_A15MPCORE', if_true: files('a15mpcore.c')) From patchwork Thu Jan 18 20:06:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763647 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp109456wrq; Thu, 18 Jan 2024 12:09:31 -0800 (PST) X-Google-Smtp-Source: AGHT+IHh3mBAXTEZ17k64kBN/WzVIx9Jfs5VA8Q86sXvwmKYaj+ax70jEHHo6oMCZoH42oQysRc8 X-Received: by 2002:ac8:5954:0:b0:429:d02d:28aa with SMTP id 20-20020ac85954000000b00429d02d28aamr1443113qtz.90.1705608571039; Thu, 18 Jan 2024 12:09:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705608571; cv=none; d=google.com; s=arc-20160816; b=eCFhiDiIMNZfcpIqD1IsuCTJrMsTZj24limryDK8K3ocPpCjvu3tx5y++zHcmGRrSB WWXrpchfIgmU+1EdXUSkqYRgvcIc7grL1c3lkNFa0QntQVW9Kmv8Ipy5NNVr8FbV7A8+ 8OJYsdwRK9z1JpM+D7KU6/EK/t7adsmqld50fBu6wccckv3x3MoWzKqDIw66BbpbnMmI WOKjMSfgwDGCDKL8N1IGiexa0tuq0T+56cYDSQ1ChwGNNQZC8cIQb7V53ikX+FEBklse 4c56ikeCJtSENbv+/E8M0dWRmxJXR1GXL9a6vSJYNZPnSRGvbXufL4sHBNoo5nxMeDDg +KYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=o0rOeZxLobaeC+GA5Yjm4BlTG768XBMgHhLq69UHP94=; fh=cUgEM3TMHOIH70RmHTmTZxZmItZJnKfBWHSaci49aLY=; b=Sy/zEu8fEfqq8ll4BSvE6l8UqIwPCMz7LZo/rHe0pfN6oFHR4X6CauGCsJqZJ+mJ+q oROH6PlTMDRppqNq6fwUflI4b3CihEfRRLfgcfJBCBho1J/CtZUeZsFzke7ULUvYCGqf 7wsvEnDXPlERdu1elQgv+Y1NlCRK2Rj+RGiORRUJt73WE3M4LfDeRE6sDZqUSBAYovds ac0YrMm7IsH+E9XbSObdcZFnxBh6XKep6ROVQ3G5+xXd7ZnriorvA4S8HltYmy7WCkN9 a9SCUlE4PQNmo5IYToM/1tWe12fiDfffvyWUH2iFs4S9D172crGgysZg1qXlUbq0ZaVY xK0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=w69l6bmA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , Igor Mammedov , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eric Auger , Niek Linnenbank , "Michael S. Tsirkin" , Jan Kiszka , Marcin Juszkiewicz , Alistair Francis , Radoslaw Biernacki , Andrew Jeffery , Andrey Smirnov , Rob Herring , Shannon Zhao , Tyrone Ting , Beniamino Galvani , Alexander Graf , Leif Lindholm , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Paolo Bonzini , Jean-Christophe Dubois , Joel Stanley , Hao Wu , kvm@vger.kernel.org Subject: [PATCH 13/20] hw/misc/xlnx-versal-crl: Include generic 'cpu-qom.h' instead of 'cpu.h' Date: Thu, 18 Jan 2024 21:06:34 +0100 Message-ID: <20240118200643.29037-14-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240118200643.29037-1-philmd@linaro.org> References: <20240118200643.29037-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "target/arm/cpu.h" is target specific, any file including it becomes target specific too, thus this is the same for any file including "hw/misc/xlnx-versal-crl.h". "hw/misc/xlnx-versal-crl.h" doesn't require any target specific definition however, only the target-agnostic QOM definitions from "target/arm/cpu-qom.h". Include the latter header to avoid tainting unnecessary objects as target-specific. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/misc/xlnx-versal-crl.h | 2 +- hw/misc/xlnx-versal-crl.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/include/hw/misc/xlnx-versal-crl.h b/include/hw/misc/xlnx-versal-crl.h index dfb8dff197..dba6d3585d 100644 --- a/include/hw/misc/xlnx-versal-crl.h +++ b/include/hw/misc/xlnx-versal-crl.h @@ -11,7 +11,7 @@ #include "hw/sysbus.h" #include "hw/register.h" -#include "target/arm/cpu.h" +#include "target/arm/cpu-qom.h" #define TYPE_XLNX_VERSAL_CRL "xlnx-versal-crl" OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCRL, XLNX_VERSAL_CRL) diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c index 1f1762ef16..1a596f1cf5 100644 --- a/hw/misc/xlnx-versal-crl.c +++ b/hw/misc/xlnx-versal-crl.c @@ -18,6 +18,7 @@ #include "hw/register.h" #include "hw/resettable.h" +#include "target/arm/cpu.h" #include "target/arm/arm-powerctl.h" #include "target/arm/multiprocessing.h" #include "hw/misc/xlnx-versal-crl.h" From patchwork Thu Jan 18 20:06:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763648 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp109485wrq; Thu, 18 Jan 2024 12:09:34 -0800 (PST) X-Google-Smtp-Source: AGHT+IEcHeKkb5i1lZ/KHJKufv0tGxC0Ty8WwvjGd/ocxiJAs+LU5wILut3GKzyT1F3J4sYZ1ELf X-Received: by 2002:a05:6808:11c6:b0:3bd:2dcf:7539 with SMTP id p6-20020a05680811c600b003bd2dcf7539mr1532391oiv.94.1705608574781; Thu, 18 Jan 2024 12:09:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705608574; cv=none; d=google.com; s=arc-20160816; b=ZDXR/Lo5KGM4V85rVE/HggSY0xgOfKL9BP9FIWes/JNJly5Pw5cj/xhGu9AG1JeJOP U7y3uTKJ2HWeDF6tU/12LA9lnKHWkN53cCGAXuk1yEoIDmB/QLKWVU+6g7aUaLtcEMfa 6g+y98HjR979uzAycmi6eKKLjuPO/Y57i28OmSJPqzTKYPZHzewLo+w5o3BrzK97VWVu mpjq+VZKGnsbBCs4P1Mhrdq7Ek6230L1yswuIhBED00rKfAwrjKXdygj2IKV2fKyWzq4 zTdUVfkNhgxfdkKVwvcu33qxYstNGwmnO2L1Rm1f71iFdk0TxMm2WLgzn/cvnFDL1nAO rNGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=FzWbQBIfEs6OJQ0hzr//F/cyUEfiuvwBN1uqJ0c1PMQ=; fh=cUgEM3TMHOIH70RmHTmTZxZmItZJnKfBWHSaci49aLY=; b=qjreR/uYreEBbT2hEwuAIhTXokdiHkf7ZAns3EQ5GilquoEC+XbcZ+pIvUju+seGuW bFaTB5963iJYo0AcdVfPERjaQtUY4idCJNLIySMcl27ZP/bgty/ge7MGKwvfYfSig2wJ 69r+9q+9yLlgeTZWRHfkVLng3kAZ3/7bFb/wobSBQ+NEajWuB7y1uFs4QfB0QbsoOHDj c+dEgpsbSg69YuyTjlIVJJwlrDmVEss9HAGdwbuzpDTYIZinRXRcMWUVdlBDF0XZiT9K HGfo3OaiU0JX/7WgpASMO3EsjL3d9+8h2mTqDHEBQ5GAnXj1b+MBm700gF8e4qahyICD RcGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kcGqJv1q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v17-20020ac85791000000b0042a1e4defacsi1317739qta.585.2024.01.18.12.09.34 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jan 2024 12:09:34 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kcGqJv1q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rQYgO-0005W0-Ed; Thu, 18 Jan 2024 15:08:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQYgL-0005RP-G5 for qemu-devel@nongnu.org; Thu, 18 Jan 2024 15:08:09 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rQYgJ-00073q-N1 for qemu-devel@nongnu.org; Thu, 18 Jan 2024 15:08:09 -0500 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-40e884ac5c8so251255e9.2 for ; Thu, 18 Jan 2024 12:08:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705608486; x=1706213286; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FzWbQBIfEs6OJQ0hzr//F/cyUEfiuvwBN1uqJ0c1PMQ=; b=kcGqJv1qb4JoInmpl5pkwOfF0hMfqUv7tyBh1GGXuCPQ3GTrdhCpgGXdmhBP3tB0zi j6G+aGUJ61T4l/+ck0RYTsUaY4Yz1Xetnc3OgiIqzHxAK5qSY7ElDb6hxyHWAFeOu7gV 2QQOy0L2Uw9YLlx/T9OkhgzgKWTQi9rT2aqOoHDmjFYG91J4ssESL4CteThKliQwKRo6 CHN0e/Qh2MGXJ+vjHI8+em67XnUerT+sOIT6y45MQ+ehlWUTOZ4rNzVCVvGbFBe2Y6MB o41Ukte5u7GDe8eu2zyrjI2FQY2FDoXrhG9Kb3BJ2jqDYyXNA3I4+rw6gjgJbY0ayvjP Isbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705608486; x=1706213286; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FzWbQBIfEs6OJQ0hzr//F/cyUEfiuvwBN1uqJ0c1PMQ=; b=AuUU2PVcNNSlIYeCPZxHC/ebmRxHKFVcVZgJvLbMxkomDb1u6QanEnzWND2FmhvI6K AVPmD87mGu5X9t2O4QFa0i2rpsk6Um7p5W0Ya5PJDX2dPHhJCRM7fscE/aVQgVH4Bmk6 1rxvP5geaYgEO6GGkGW67vJCORpuzURDA+Z7k52CbfHMCVJpDMaMqZD3BG/R6Lr1ldDT xVvSbwA8Zt2E04To5TCrHq6MlwWOPprmFOR4xkCdzotTdpqWEX5U4xn0vZ9YW2X9mD6L 36+zJLT2g+s388seLubw25RL+bLApOPsm/sOC83LwlyGHBI5DuPvfDsxns5VLfVZM3j5 UcPQ== X-Gm-Message-State: AOJu0YxNra36cTSi0NWe0DvB6Iq146qHdHJKLxGGngo8QdR6kulmrP/+ YsDilWg1k2k7yB0D+dpI6Dam2172hyLMKry9Cz5xCfrXxtMqW78FQQIyKZQtp2B2UdBVsvBgf0x wNub3EBT0 X-Received: by 2002:a05:600c:2047:b0:40e:53a0:c140 with SMTP id p7-20020a05600c204700b0040e53a0c140mr471729wmg.229.1705608486072; Thu, 18 Jan 2024 12:08:06 -0800 (PST) Received: from localhost.localdomain ([78.196.4.158]) by smtp.gmail.com with ESMTPSA id z10-20020a05600c0a0a00b0040e4bcfd826sm27279780wmp.47.2024.01.18.12.08.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 18 Jan 2024 12:08:05 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Igor Mitsyanko , qemu-arm@nongnu.org, Strahinja Jankovic , "Edgar E. Iglesias" , Igor Mammedov , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eric Auger , Niek Linnenbank , "Michael S. Tsirkin" , Jan Kiszka , Marcin Juszkiewicz , Alistair Francis , Radoslaw Biernacki , Andrew Jeffery , Andrey Smirnov , Rob Herring , Shannon Zhao , Tyrone Ting , Beniamino Galvani , Alexander Graf , Leif Lindholm , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Paolo Bonzini , Jean-Christophe Dubois , Joel Stanley , Hao Wu , kvm@vger.kernel.org Subject: [PATCH 14/20] hw/misc/xlnx-versal-crl: Build it only once Date: Thu, 18 Jan 2024 21:06:35 +0100 Message-ID: <20240118200643.29037-15-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240118200643.29037-1-philmd@linaro.org> References: <20240118200643.29037-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org hw/misc/xlnx-versal-crl.c doesn't require "cpu.h" anymore. By removing it, the unit become target agnostic: we can build it once. Update meson. Signed-off-by: Philippe Mathieu-Daudé --- hw/misc/xlnx-versal-crl.c | 1 - hw/misc/meson.build | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c index 1a596f1cf5..1f1762ef16 100644 --- a/hw/misc/xlnx-versal-crl.c +++ b/hw/misc/xlnx-versal-crl.c @@ -18,7 +18,6 @@ #include "hw/register.h" #include "hw/resettable.h" -#include "target/arm/cpu.h" #include "target/arm/arm-powerctl.h" #include "target/arm/multiprocessing.h" #include "hw/misc/xlnx-versal-crl.h" diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 36c20d5637..66820acac3 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -96,8 +96,8 @@ system_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c')) system_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c')) system_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c')) system_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c')) -specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-crl.c')) system_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files( + 'xlnx-versal-crl.c', 'xlnx-versal-xramc.c', 'xlnx-versal-pmc-iou-slcr.c', 'xlnx-versal-cfu.c', From patchwork Thu Jan 18 20:06:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763652 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp110107wrq; Thu, 18 Jan 2024 12:11:01 -0800 (PST) X-Google-Smtp-Source: AGHT+IE3/RnOBMbnSEXOE3VXBTERzI0MyrXCjEnlNxYd9BSEzUO9sCz4h4E5U/bA5Q0tXKLOfw4h X-Received: by 2002:ac8:58d4:0:b0:42a:158b:c038 with SMTP id u20-20020ac858d4000000b0042a158bc038mr1647498qta.66.1705608660913; Thu, 18 Jan 2024 12:11:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705608660; cv=none; d=google.com; s=arc-20160816; b=Fmk36JiDo1W56B8A4tf2J3SNv9ov3O0kSpbuCAW6OKcq9+4S1+QEC69UtSjTpsnDI0 54f4ImEZC0RmyylN3C17omJiAj58xQVfHOW15TBOuz314TFUNubNLctgU60BGtbY5KPI VeS6SH5AZ4R+WsFj1Tc18PAoqPK6KhozqjczBg/bWsOaalqy1h8cdtYYt2DE+rjlx48Q zGiiMoofKlBBDIMZFjqi7nmFDjf28D9igZOtXKCCo+FEfRt3dd1NqoSbm/Hn791XNef/ C4PHiplsgkDZ6BzWl35cMk8gD4IFSEJYZsNlld7la5E7MCA7jMxbEgB+md2P4DklbRDi /uog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=7RZro+jmubrqox1BtgtSrk1gGKfZgwoa/a4ZCw9lbhM=; fh=cUgEM3TMHOIH70RmHTmTZxZmItZJnKfBWHSaci49aLY=; b=EzC1R+orW38DcNhP2PWE0sde65xuFBTiyozuX1URdNx+837wAFGvsCOw5ErC6zAUkY iRCDH0Nh5/pVzr7AHAZrGIKvu3mQMQ1C19a1SByqox1Mr18l/d9bx+SIIV7rLTZyHHDP 5e/HU8vJIoqyh1y+Du2L3fZ/us+4IEiM9I78e3vSunIXEHUB1N5r5ZNOBuCIkhOk26bg cPCkyL6cYx31noqu/YVn4jVGxAuFHImFRHS2trsMK6HjjAL7XfODtx0ah3LnGl5YiqZH qDq37GUOG4BudJJ1/c2FDkIzO+Csrn3W0sqrY4rmgSYTFxAXHp1xnDUBCssHZfIXOUTW 6hQg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=s69KtmGz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a18-20020a05622a065200b00429d3c6e369si11657985qtb.78.2024.01.18.12.11.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jan 2024 12:11:00 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=s69KtmGz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rQYgZ-0005eL-Mu; Thu, 18 Jan 2024 15:08:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQYgR-0005Yj-Mn for qemu-devel@nongnu.org; Thu, 18 Jan 2024 15:08:15 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rQYgQ-00074q-2W for qemu-devel@nongnu.org; Thu, 18 Jan 2024 15:08:15 -0500 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-40e9ce530b9so315195e9.0 for ; Thu, 18 Jan 2024 12:08:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705608492; x=1706213292; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7RZro+jmubrqox1BtgtSrk1gGKfZgwoa/a4ZCw9lbhM=; b=s69KtmGz7UMVMFqdbu2nseeKRa6qd0YWvBn63QGkSHJBa0SkLtdFq5+PWDEsAC2tiM BwAhNu1Mvl9chPjDN6VoyKkRzPXwwbjOSeULbeX0dW9uaeE2oR1X2HBq3tOSiBJTRjbT G0Kx1aF2vc49RBnC3YMWAaFkYJ0Nom0q/qLkrUzzn22ly3Xi7q1ad4TKyNyaqs3rZ6P6 EM2IMKNvlzroAOaMIsRnXa0n/vq7tZJ00WCPodTr7Cq0S12n1vDRRcUM/Hb0AfJk9HHa b6MT7XWHZrcRn16n0E7bmdhMibccx0yqQ0oTMQ8Ziqz9hzTFl4sgGGV/o4pz/c/NH2Bj ri7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705608492; x=1706213292; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7RZro+jmubrqox1BtgtSrk1gGKfZgwoa/a4ZCw9lbhM=; b=jPTUkfbqezKrl/6j2VqEd5yzmPv/excnl1EPyrMEPWqTIqOlm1RuvBWhqFqS5sChYp KZuYRfKOvpx7mk4f8pwcvcbtLgoViWT6fIFe7Scy5+h4WejrAHi3i3GZsZXmIypUg9FJ HeS5NGBLir6plbQLkAuYqNi2H1/6XdcoPAVeVM7MypuovdTZkgtvfqnNp8u59gaLA44O RAI5Gg/5mJLLE9ap6U7A5kxRqqxpsqzCQ8SPARRv7NWRTUS9VBgSXWVFdnsVHaCsDN3W BAbYz3xbVKCC/snolW1r1BZ2swaEaqyvmTpTThofycqtbi3pPBG+cy/i461Vi+AU+9Uq /EdQ== X-Gm-Message-State: AOJu0YyeDD/u7rr5lU04Z0iknnBSXEZuPFxRHgMDG2Q80JTWi2iOPtp1 i0CDB0yN0jCbYHP6xY5elGNvaOcu1sa4gE5EJZHmOEZ1D8pzk0oopSKKhoiV2OLO1GfTHGomCqG ZBOX3rpnM X-Received: by 2002:a5d:6106:0:b0:336:7a58:39da with SMTP id v6-20020a5d6106000000b003367a5839damr872886wrt.106.1705608492322; Thu, 18 Jan 2024 12:08:12 -0800 (PST) Received: from localhost.localdomain ([78.196.4.158]) by smtp.gmail.com with ESMTPSA id d19-20020adf9c93000000b003365aa39d30sm4762614wre.11.2024.01.18.12.08.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 18 Jan 2024 12:08:11 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Igor Mitsyanko , qemu-arm@nongnu.org, Strahinja Jankovic , "Edgar E. Iglesias" , Igor Mammedov , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eric Auger , Niek Linnenbank , "Michael S. Tsirkin" , Jan Kiszka , Marcin Juszkiewicz , Alistair Francis , Radoslaw Biernacki , Andrew Jeffery , Andrey Smirnov , Rob Herring , Shannon Zhao , Tyrone Ting , Beniamino Galvani , Alexander Graf , Leif Lindholm , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Paolo Bonzini , Jean-Christophe Dubois , Joel Stanley , Hao Wu , kvm@vger.kernel.org Subject: [PATCH 15/20] target/arm: Expose M-profile register bank index definitions Date: Thu, 18 Jan 2024 21:06:36 +0100 Message-ID: <20240118200643.29037-16-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240118200643.29037-1-philmd@linaro.org> References: <20240118200643.29037-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The ARMv7M QDev container accesses the QDev SysTickState by its secure/non-secure bank index. In order to make the "hw/intc/armv7m_nvic.h" header target-agnostic in the next commit, first move the M-profile bank index definitions to "target/arm/cpu-qom.h". Signed-off-by: Philippe Mathieu-Daudé --- Or do we want these in a more specific header? --- target/arm/cpu-qom.h | 15 +++++++++++++++ target/arm/cpu.h | 15 --------------- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index f795994135..77bbc1f13c 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -36,4 +36,19 @@ DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) +/* For M profile, some registers are banked secure vs non-secure; + * these are represented as a 2-element array where the first element + * is the non-secure copy and the second is the secure copy. + * When the CPU does not have implement the security extension then + * only the first element is used. + * This means that the copy for the current security state can be + * accessed via env->registerfield[env->v7m.secure] (whether the security + * extension is implemented or not). + */ +enum { + M_REG_NS = 0, + M_REG_S = 1, + M_REG_NUM_BANKS = 2, +}; + #endif diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 41659d0ef1..d6a79482ad 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -73,21 +73,6 @@ #define ARMV7M_EXCP_PENDSV 14 #define ARMV7M_EXCP_SYSTICK 15 -/* For M profile, some registers are banked secure vs non-secure; - * these are represented as a 2-element array where the first element - * is the non-secure copy and the second is the secure copy. - * When the CPU does not have implement the security extension then - * only the first element is used. - * This means that the copy for the current security state can be - * accessed via env->registerfield[env->v7m.secure] (whether the security - * extension is implemented or not). - */ -enum { - M_REG_NS = 0, - M_REG_S = 1, - M_REG_NUM_BANKS = 2, -}; - /* ARM-specific interrupt pending bits. */ #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 From patchwork Thu Jan 18 20:06:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763657 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp110501wrq; Thu, 18 Jan 2024 12:11:58 -0800 (PST) X-Google-Smtp-Source: AGHT+IEktTb2fUv+j3gD94QCudmbPWCRTjxu4CXk2/uv7ZABX9etuaw7BiXOaEZEWOLMe+qqJegm X-Received: by 2002:a05:620a:404a:b0:783:306b:1d7b with SMTP id i10-20020a05620a404a00b00783306b1d7bmr226920qko.8.1705608717261; Thu, 18 Jan 2024 12:11:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705608717; cv=none; d=google.com; s=arc-20160816; b=Ot6KihmNh6sDhIjjJvjQrPHpPg9u6U/G/jJrYwWp5l/mFZQVln/gxdfPa4il5cXtT6 pZ8FiR+XkyJqpt24kC3FwMjqQRquyHsTpl6KqpYULdtIBl2QoK2HQesj7W3sTP870P2/ 3Vjy91RZDOjJdRllBsiULMI9H3dSzvQR75NDMM141Zlwh3s+G/jCGwo++7BRggU6TqL5 If8I5fnix5KT36tY5LcNeHr6WtIgpfYJ+a++4qWUqmJ2di4GuO4S17J+Oofosr0p5OBg iTViGQU96AIaEVGI355M56j5RwyQQS2BLk1kwnh0U58rsh5MB0CCQ9ETOkk+RCDMP5fZ zi7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=7i3W6cKZo6jUarGFVlLnFc+nsCmIDidPRgxq67roFM8=; fh=cUgEM3TMHOIH70RmHTmTZxZmItZJnKfBWHSaci49aLY=; b=wHuZ/XY6HX2W5KbWBBNvhPR2z3HcACpIueFfswRYvDD5LWXJSWEAPj2oH9zmhhsg5s 6QNC2J9ZlBVj6NFycrpYa9Z3TtBK2JIrqs++BWwAKB8yeaDt0jLamB7iw5LChQgU4Y39 7dok1WjAERL2G/eHLYO+OxYLteF4omSO+x1w2V/t+VdgbzNIWwR/0ALE3Shp+TazIPCt FCoHmIpNlCqzT/J1Fv9+TDi9t+ME9qbBvQFWcrddnAqvLcVU7rsU95fvAc+V2CCTjOg9 pg2QP6/QoqSFPqq0H0HwFM+0xWscRhwUWLkubTKytIocSv4Wnhm2YE8vp7zqKkRwDiIC kg+A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pojMAryF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , Igor Mammedov , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eric Auger , Niek Linnenbank , "Michael S. Tsirkin" , Jan Kiszka , Marcin Juszkiewicz , Alistair Francis , Radoslaw Biernacki , Andrew Jeffery , Andrey Smirnov , Rob Herring , Shannon Zhao , Tyrone Ting , Beniamino Galvani , Alexander Graf , Leif Lindholm , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Paolo Bonzini , Jean-Christophe Dubois , Joel Stanley , Hao Wu , kvm@vger.kernel.org Subject: [PATCH 16/20] hw/arm/armv7m: Make 'hw/intc/armv7m_nvic.h' a target agnostic header Date: Thu, 18 Jan 2024 21:06:37 +0100 Message-ID: <20240118200643.29037-17-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240118200643.29037-1-philmd@linaro.org> References: <20240118200643.29037-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Now than we can access the M-profile bank index definitions from the target-agnostic "cpu-qom.h" header, we don't need the huge "cpu.h" anymore (except in hw/arm/armv7m.c). Reduce its inclusion to the source unit. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/intc/armv7m_nvic.h | 2 +- hw/arm/armv7m.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h index 6b4ae566c9..89fe8aedaa 100644 --- a/include/hw/intc/armv7m_nvic.h +++ b/include/hw/intc/armv7m_nvic.h @@ -10,7 +10,7 @@ #ifndef HW_ARM_ARMV7M_NVIC_H #define HW_ARM_ARMV7M_NVIC_H -#include "target/arm/cpu.h" +#include "target/arm/cpu-qom.h" #include "hw/sysbus.h" #include "hw/timer/armv7m_systick.h" #include "qom/object.h" diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 1f21827773..edcd8adc74 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -21,6 +21,7 @@ #include "qemu/module.h" #include "qemu/log.h" #include "target/arm/idau.h" +#include "target/arm/cpu.h" #include "target/arm/cpu-features.h" #include "migration/vmstate.h" From patchwork Thu Jan 18 20:06:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763651 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp110094wrq; Thu, 18 Jan 2024 12:10:59 -0800 (PST) X-Google-Smtp-Source: AGHT+IHBdZTwQrbEfo7ILV5/hTZDEwK+w+Gk6GdejaFR/Vyy3BypZoQ3sEPvgotGZZLLDO89wwBO X-Received: by 2002:a05:6102:1174:b0:468:27e:7c7f with SMTP id k20-20020a056102117400b00468027e7c7fmr1606741vsg.34.1705608659564; Thu, 18 Jan 2024 12:10:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705608659; cv=none; d=google.com; s=arc-20160816; b=X9GAPrza9tedApcJqx6y7zbjRj51CNA5tK45kgktWeoQX9kjkWBGyOc+E1eUMG11da v8BwaSq3KjY6kEnmgiquamI0S4QTPmLAnxQwioSvoBE6Z+XgxW0uiYsSpER6Cl4MDX3z 1sqWEDsGMQlOO4z6QWMAG2d8s9Ws8qwk3QT+9wOAp05gpbE12+WUgTuhvL0+8/O7yOw9 n0U22B672FSiGJu+2R17i/fKzQlv81Fe9ZiQWJxfDjoA5X9gmg1kHp6XZfWOnUK/aoRQ pFnO8ibd++7SssU/oYmta15v9tt9TdECvzZfqwabDkmvI4Tp81Zaw57L/ayLU8m6zK4+ nl1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=bhQHZsizpE+F9viHPJU7AjTKXKVu3rWT2XlrMgKdqws=; fh=cUgEM3TMHOIH70RmHTmTZxZmItZJnKfBWHSaci49aLY=; b=cBB1Upv24NZC/c5m0cHvMmFtrqjltunWnrzVFScpJ4XBHv49WweibEK/bDIhmkcldY 9umSk6VtYqJVPnIJfsN82WwH5u+mxvuZqQZ7e1KqydPnytlTSF8gofH6kW0BgeWsJ4Sz KdSb8juArJxqzbekHMi3LLzf1LfYBL58Not19epuum8uctMJtLR/L5H+6x1i3FOZaZBw TbIfu05gZrPIp/DZn0ciq1wuzBkyXvFAb4lj8tbiFExhw5lyZbzZOmnGqzhFO/BbJnmL 19pbQeF6ZvwlrnkZjC/t1OUUXZENoqfzQqU4Bb+c7YOOypVTF65b7lqBpjHL+LXRV31i B/fg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bmpQPgio; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , Igor Mammedov , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eric Auger , Niek Linnenbank , "Michael S. Tsirkin" , Jan Kiszka , Marcin Juszkiewicz , Alistair Francis , Radoslaw Biernacki , Andrew Jeffery , Andrey Smirnov , Rob Herring , Shannon Zhao , Tyrone Ting , Beniamino Galvani , Alexander Graf , Leif Lindholm , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Paolo Bonzini , Jean-Christophe Dubois , Joel Stanley , Hao Wu , kvm@vger.kernel.org Subject: [PATCH 17/20] target/arm: Move ARM_CPU_IRQ/FIQ definitions to 'cpu-qom.h' header Date: Thu, 18 Jan 2024 21:06:38 +0100 Message-ID: <20240118200643.29037-18-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240118200643.29037-1-philmd@linaro.org> References: <20240118200643.29037-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The ARM_CPU_IRQ/FIQ definitions are used to index the GPIO IRQ created calling qdev_init_gpio_in() in ARMCPU instance_init() handler. To allow non-ARM code to raise interrupt on ARM cores, move they to 'target/arm/cpu-qom.h' which is non-ARM specific and can be included by any hw/ file. File list to include the new header generated using: $ git grep -wEl 'ARM_CPU_(\w*IRQ|FIQ)' Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu-qom.h | 6 ++++++ target/arm/cpu.h | 6 ------ hw/arm/allwinner-a10.c | 1 + hw/arm/allwinner-h3.c | 1 + hw/arm/allwinner-r40.c | 1 + hw/arm/armv7m.c | 1 + hw/arm/aspeed_ast2400.c | 1 + hw/arm/aspeed_ast2600.c | 1 + hw/arm/bcm2836.c | 1 + hw/arm/exynos4210.c | 1 + hw/arm/fsl-imx25.c | 1 + hw/arm/fsl-imx31.c | 1 + hw/arm/fsl-imx6.c | 1 + hw/arm/fsl-imx6ul.c | 1 + hw/arm/fsl-imx7.c | 1 + hw/arm/highbank.c | 1 + hw/arm/integratorcp.c | 1 + hw/arm/musicpal.c | 1 + hw/arm/npcm7xx.c | 1 + hw/arm/omap1.c | 1 + hw/arm/omap2.c | 1 + hw/arm/realview.c | 1 + hw/arm/sbsa-ref.c | 1 + hw/arm/strongarm.c | 1 + hw/arm/versatilepb.c | 1 + hw/arm/vexpress.c | 1 + hw/arm/virt.c | 1 + hw/arm/xilinx_zynq.c | 1 + hw/arm/xlnx-versal.c | 1 + hw/arm/xlnx-zynqmp.c | 1 + target/arm/cpu.c | 1 + 31 files changed, 35 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 77bbc1f13c..8e032691db 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -36,6 +36,12 @@ DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU, #define ARM_CPU_TYPE_SUFFIX "-" TYPE_ARM_CPU #define ARM_CPU_TYPE_NAME(name) (name ARM_CPU_TYPE_SUFFIX) +/* Meanings of the ARMCPU object's four inbound GPIO lines */ +#define ARM_CPU_IRQ 0 +#define ARM_CPU_FIQ 1 +#define ARM_CPU_VIRQ 2 +#define ARM_CPU_VFIQ 3 + /* For M profile, some registers are banked secure vs non-secure; * these are represented as a 2-element array where the first element * is the non-secure copy and the second is the secure copy. diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d6a79482ad..e8df41d642 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -93,12 +93,6 @@ #define offsetofhigh32(S, M) (offsetof(S, M) + sizeof(uint32_t)) #endif -/* Meanings of the ARMCPU object's four inbound GPIO lines */ -#define ARM_CPU_IRQ 0 -#define ARM_CPU_FIQ 1 -#define ARM_CPU_VIRQ 2 -#define ARM_CPU_VFIQ 3 - /* ARM-specific extra insn start words: * 1: Conditional execution bits * 2: Partial exception syndrome for data aborts diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c index b0ea3f7f66..7e2ae7a15f 100644 --- a/hw/arm/allwinner-a10.c +++ b/hw/arm/allwinner-a10.c @@ -26,6 +26,7 @@ #include "hw/boards.h" #include "hw/usb/hcd-ohci.h" #include "hw/loader.h" +#include "target/arm/cpu-qom.h" #define AW_A10_SRAM_A_BASE 0x00000000 #define AW_A10_DRAMC_BASE 0x01c01000 diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index f05afddf7e..2d684b5287 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -30,6 +30,7 @@ #include "hw/loader.h" #include "sysemu/sysemu.h" #include "hw/arm/allwinner-h3.h" +#include "target/arm/cpu-qom.h" /* Memory map */ const hwaddr allwinner_h3_memmap[] = { diff --git a/hw/arm/allwinner-r40.c b/hw/arm/allwinner-r40.c index a0d367c60d..65392dbc23 100644 --- a/hw/arm/allwinner-r40.c +++ b/hw/arm/allwinner-r40.c @@ -32,6 +32,7 @@ #include "sysemu/sysemu.h" #include "hw/arm/allwinner-r40.h" #include "hw/misc/allwinner-r40-dramc.h" +#include "target/arm/cpu-qom.h" /* Memory map */ const hwaddr allwinner_r40_memmap[] = { diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index edcd8adc74..7c68525a9e 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -23,6 +23,7 @@ #include "target/arm/idau.h" #include "target/arm/cpu.h" #include "target/arm/cpu-features.h" +#include "target/arm/cpu-qom.h" #include "migration/vmstate.h" /* Bitbanded IO. Each word corresponds to a single bit. */ diff --git a/hw/arm/aspeed_ast2400.c b/hw/arm/aspeed_ast2400.c index 0baa2ff96e..ad76035528 100644 --- a/hw/arm/aspeed_ast2400.c +++ b/hw/arm/aspeed_ast2400.c @@ -21,6 +21,7 @@ #include "hw/i2c/aspeed_i2c.h" #include "net/net.h" #include "sysemu/sysemu.h" +#include "target/arm/cpu-qom.h" #define ASPEED_SOC_IOMEM_SIZE 0x00200000 diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 3a9a303ab8..386a88d4e0 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -16,6 +16,7 @@ #include "hw/i2c/aspeed_i2c.h" #include "net/net.h" #include "sysemu/sysemu.h" +#include "target/arm/cpu-qom.h" #define ASPEED_SOC_IOMEM_SIZE 0x00200000 #define ASPEED_SOC_DPMCU_SIZE 0x00040000 diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index b0674a22a6..58a78780d2 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -15,6 +15,7 @@ #include "hw/arm/bcm2836.h" #include "hw/arm/raspi_platform.h" #include "hw/sysbus.h" +#include "target/arm/cpu-qom.h" struct BCM283XClass { /*< private >*/ diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index af511a153d..6c428d8eeb 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -36,6 +36,7 @@ #include "hw/arm/exynos4210.h" #include "hw/sd/sdhci.h" #include "hw/usb/hcd-ehci.h" +#include "target/arm/cpu-qom.h" #define EXYNOS4210_CHIPID_ADDR 0x10000000 diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c index 9d2fb75a68..4a49507ef1 100644 --- a/hw/arm/fsl-imx25.c +++ b/hw/arm/fsl-imx25.c @@ -28,6 +28,7 @@ #include "sysemu/sysemu.h" #include "hw/qdev-properties.h" #include "chardev/char.h" +#include "target/arm/cpu-qom.h" #define IMX25_ESDHC_CAPABILITIES 0x07e20000 diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c index c0584e4dfc..4b8d9b8e4f 100644 --- a/hw/arm/fsl-imx31.c +++ b/hw/arm/fsl-imx31.c @@ -26,6 +26,7 @@ #include "exec/address-spaces.h" #include "hw/qdev-properties.h" #include "chardev/char.h" +#include "target/arm/cpu-qom.h" static void fsl_imx31_init(Object *obj) { diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index af2e982b05..42f9058825 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -29,6 +29,7 @@ #include "chardev/char.h" #include "qemu/error-report.h" #include "qemu/module.h" +#include "target/arm/cpu-qom.h" #define IMX6_ESDHC_CAPABILITIES 0x057834b4 diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index e37b69a5e1..486a009deb 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -25,6 +25,7 @@ #include "sysemu/sysemu.h" #include "qemu/error-report.h" #include "qemu/module.h" +#include "target/arm/cpu-qom.h" #define NAME_SIZE 20 diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index 474cfdc87c..5728109491 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -26,6 +26,7 @@ #include "sysemu/sysemu.h" #include "qemu/error-report.h" #include "qemu/module.h" +#include "target/arm/cpu-qom.h" #define NAME_SIZE 20 diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index c21e18d08f..e6e27d69af 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -36,6 +36,7 @@ #include "qemu/log.h" #include "qom/object.h" #include "cpu.h" +#include "target/arm/cpu-qom.h" #define SMP_BOOT_ADDR 0x100 #define SMP_BOOT_REG 0x40 diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c index 1830e1d785..5600616a4d 100644 --- a/hw/arm/integratorcp.c +++ b/hw/arm/integratorcp.c @@ -28,6 +28,7 @@ #include "hw/sd/sd.h" #include "qom/object.h" #include "audio/audio.h" +#include "target/arm/cpu-qom.h" #define TYPE_INTEGRATOR_CM "integrator_core" OBJECT_DECLARE_SIMPLE_TYPE(IntegratorCMState, INTEGRATOR_CM) diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index 3200c9f68a..d89824f600 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -39,6 +39,7 @@ #include "hw/net/mv88w8618_eth.h" #include "audio/audio.h" #include "qemu/error-report.h" +#include "target/arm/cpu-qom.h" #define MP_MISC_BASE 0x80002000 #define MP_MISC_SIZE 0x00001000 diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index 7fb0a233b2..e3243a520d 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -26,6 +26,7 @@ #include "qapi/error.h" #include "qemu/units.h" #include "sysemu/sysemu.h" +#include "target/arm/cpu-qom.h" /* * This covers the whole MMIO space. We'll use this to catch any MMIO accesses diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c index d5438156ee..86ee336e59 100644 --- a/hw/arm/omap1.c +++ b/hw/arm/omap1.c @@ -40,6 +40,7 @@ #include "hw/sysbus.h" #include "qemu/cutils.h" #include "qemu/bcd.h" +#include "target/arm/cpu-qom.h" static inline void omap_log_badwidth(const char *funcname, hwaddr addr, int sz) { diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c index f170728e7e..f159fb73ea 100644 --- a/hw/arm/omap2.c +++ b/hw/arm/omap2.c @@ -39,6 +39,7 @@ #include "hw/sysbus.h" #include "hw/boards.h" #include "audio/audio.h" +#include "target/arm/cpu-qom.h" /* Enhanced Audio Controller (CODEC only) */ struct omap_eac_s { diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 132217b2ed..566deff9ce 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -30,6 +30,7 @@ #include "hw/i2c/arm_sbcon_i2c.h" #include "hw/sd/sd.h" #include "audio/audio.h" +#include "target/arm/cpu-qom.h" #define SMP_BOOT_ADDR 0xe0000000 #define SMP_BOOTREG_ADDR 0x10000030 diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index b8857d1e9e..d6081bfc41 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -50,6 +50,7 @@ #include "net/net.h" #include "qapi/qmp/qlist.h" #include "qom/object.h" +#include "target/arm/cpu-qom.h" #define RAMLIMIT_GB 8192 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c index fef3638aca..75637869cb 100644 --- a/hw/arm/strongarm.c +++ b/hw/arm/strongarm.c @@ -46,6 +46,7 @@ #include "qemu/cutils.h" #include "qemu/log.h" #include "qom/object.h" +#include "target/arm/cpu-qom.h" //#define DEBUG diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index 4b2257787b..15b5ed0ced 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -27,6 +27,7 @@ #include "hw/sd/sd.h" #include "qom/object.h" #include "audio/audio.h" +#include "target/arm/cpu-qom.h" #define VERSATILE_FLASH_ADDR 0x34000000 #define VERSATILE_FLASH_SIZE (64 * 1024 * 1024) diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index fd981f4c33..49dbcdcbf0 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -46,6 +46,7 @@ #include "qapi/qmp/qlist.h" #include "qom/object.h" #include "audio/audio.h" +#include "target/arm/cpu-qom.h" #define VEXPRESS_BOARD_ID 0x8e0 #define VEXPRESS_FLASH_SIZE (64 * 1024 * 1024) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index beba151620..0ab5fd9477 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -73,6 +73,7 @@ #include "standard-headers/linux/input.h" #include "hw/arm/smmuv3.h" #include "hw/acpi/acpi.h" +#include "target/arm/cpu-qom.h" #include "target/arm/internals.h" #include "target/arm/multiprocessing.h" #include "hw/mem/pc-dimm.h" diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index d4c817ecdc..5809fc32af 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -38,6 +38,7 @@ #include "sysemu/reset.h" #include "qom/object.h" #include "exec/tswap.h" +#include "target/arm/cpu-qom.h" #define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9") OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE) diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 9600551c44..87fdb39d43 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -23,6 +23,7 @@ #include "hw/misc/unimp.h" #include "hw/arm/xlnx-versal.h" #include "qemu/log.h" +#include "target/arm/cpu-qom.h" #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f") diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 5905a33015..38cb34942f 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -25,6 +25,7 @@ #include "sysemu/kvm.h" #include "sysemu/sysemu.h" #include "kvm_arm.h" +#include "target/arm/cpu-qom.h" #define GIC_NUM_SPI_INTR 160 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 89e44a31fd..07357daabe 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -48,6 +48,7 @@ #include "disas/capstone.h" #include "fpu/softfloat.h" #include "cpregs.h" +#include "target/arm/cpu-qom.h" static void arm_cpu_set_pc(CPUState *cs, vaddr value) { From patchwork Thu Jan 18 20:06:39 2024 Content-Type: text/plain; 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[209.51.188.17]) by mx.google.com with ESMTPS id i9-20020ac85e49000000b0042a0938f940si5331919qtx.191.2024.01.18.12.11.49 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jan 2024 12:11:49 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kvd3tq+e; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rQYgn-0006YM-Gh; Thu, 18 Jan 2024 15:08:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQYgj-0006Ia-4W for qemu-devel@nongnu.org; Thu, 18 Jan 2024 15:08:33 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rQYgh-00077S-HB for qemu-devel@nongnu.org; Thu, 18 Jan 2024 15:08:32 -0500 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-40e884ac5c8so255615e9.2 for ; Thu, 18 Jan 2024 12:08:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705608510; x=1706213310; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zozAuekXsv7RqlLM4guzPZsrXewV7KaaXnf3wtjaQAU=; b=kvd3tq+eapbpCngaN3Dko77VjREW5ZPXaosP/QTIDOmgoBt3YR3tgtI7OUedWpZhF9 9bYMjM/oqfkt09JPJwj7ixwubDMpIs1x23TeW/2c/3R/bvCXJkPscf81yGC7C5/AlU3Z Y+ycgmlPCfKRbWcAfVE9e+uLUUaTH4XAF4YgVVIgl2zOa6MdHh2Fmg1SwYkhBAd1xZOb gUOJGPG87pj8rRY41DYNReCGm0QoFr3L07GsBirJD2POAmixXh+sc1vCY7jCX5FIULR0 Jn5Jz9l/55feaw1kkHPj6hFHW2TKuBB/jXlgVzJjC5p6RzD2gjj0uMkp42Pha0iF7BzV tVZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705608510; x=1706213310; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zozAuekXsv7RqlLM4guzPZsrXewV7KaaXnf3wtjaQAU=; b=qswuxycYzjV9GfTPISR044z9jkGR/br7clUSqwu2A+LdrC6ViCYRSduWCzQ5VXNcFd xpSGwVJeE1gEpjDMLLCHY+LLSS2WS24hDuZ+MNGKaBgufnkbu8i3LeWMySshzoYNcIR+ 54FQyaUQ7N+Mrep+yqlA3oQ4IqaJFfyGM+kufI5zI250gyQ1UPZBq+vDMO51gRDvNoF1 e1UJTV0B+2O802wTdf0QHhqAKA4ZndYZ+jIRkZzHThR6A+Z6Ep8+LDCxf2x+SnOhxuZ+ d3A5pnyGL0/K+gPAXRdbzpjzKyD1sZKlyyAABw53PpGQVzlD8XFlS/kSL5+Z4UfjYzyN 7cXA== X-Gm-Message-State: AOJu0YyKAYi2ooUB/sQ+y1OLWpeyo2PWmo9q3rHPEZwtCxKBl0N3CZ4v jWXiEye1pSr7duro0+XFmuFeug32y9t5HoHivpOTL5Vxyrblfoz242hAMRq5887CgvHZEHPbNjE 6x1fE/mGO X-Received: by 2002:a05:600c:4216:b0:40e:4a71:e140 with SMTP id x22-20020a05600c421600b0040e4a71e140mr430671wmh.342.1705608509862; Thu, 18 Jan 2024 12:08:29 -0800 (PST) Received: from localhost.localdomain ([78.196.4.158]) by smtp.gmail.com with ESMTPSA id jg1-20020a05600ca00100b0040d4e1393dcsm30281752wmb.20.2024.01.18.12.08.28 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 18 Jan 2024 12:08:29 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Igor Mitsyanko , qemu-arm@nongnu.org, Strahinja Jankovic , "Edgar E. Iglesias" , Igor Mammedov , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eric Auger , Niek Linnenbank , "Michael S. Tsirkin" , Jan Kiszka , Marcin Juszkiewicz , Alistair Francis , Radoslaw Biernacki , Andrew Jeffery , Andrey Smirnov , Rob Herring , Shannon Zhao , Tyrone Ting , Beniamino Galvani , Alexander Graf , Leif Lindholm , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Paolo Bonzini , Jean-Christophe Dubois , Joel Stanley , Hao Wu , kvm@vger.kernel.org Subject: [PATCH 18/20] target/arm: Move e2h_access() helper around Date: Thu, 18 Jan 2024 21:06:39 +0100 Message-ID: <20240118200643.29037-19-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240118200643.29037-1-philmd@linaro.org> References: <20240118200643.29037-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org e2h_access() was added in commit bb5972e439 ("target/arm: Add VHE timer register redirection and aliasing") close to the generic_timer_cp_reginfo[] array, but isn't used until vhe_reginfo[] definition. Move it closer to the other e2h helpers. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/helper.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index dc8f14f433..1ef00e50e4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3342,20 +3342,6 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = { }, }; -static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri, - bool isread) -{ - if (arm_current_el(env) == 1) { - /* This must be a FEAT_NV access */ - /* TODO: FEAT_ECV will need to check CNTHCTL_EL2 here */ - return CP_ACCESS_OK; - } - if (!(arm_hcr_el2_eff(env) & HCR_E2H)) { - return CP_ACCESS_TRAP; - } - return CP_ACCESS_OK; -} - #else /* @@ -6543,6 +6529,21 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { }; #ifndef CONFIG_USER_ONLY + +static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) == 1) { + /* This must be a FEAT_NV access */ + /* TODO: FEAT_ECV will need to check CNTHCTL_EL2 here */ + return CP_ACCESS_OK; + } + if (!(arm_hcr_el2_eff(env) & HCR_E2H)) { + return CP_ACCESS_TRAP; + } + return CP_ACCESS_OK; +} + /* Test if system register redirection is to occur in the current state. */ static bool redirect_for_e2h(CPUARMState *env) { From patchwork Thu Jan 18 20:06:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 763654 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a08:0:b0:337:62d3:c6d5 with SMTP id m8csp110367wrq; Thu, 18 Jan 2024 12:11:33 -0800 (PST) X-Google-Smtp-Source: AGHT+IH6ZmsXpoCOR7muvJkRvfMmLmUe6LxsgNyXVPeoIAfmJjzUdl8Xgz6enoBXRvU6iVAoBg0R X-Received: by 2002:a05:6214:20c6:b0:681:77a3:7ae2 with SMTP id 6-20020a05621420c600b0068177a37ae2mr1465491qve.10.1705608692994; Thu, 18 Jan 2024 12:11:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1705608692; cv=none; d=google.com; s=arc-20160816; b=T8YKKVkVNUgzSJjsmJqSYBW7pA/N+zA7O2J+NVGvtGtGNCqGd5cHQmd0xZHcvZLhA2 GsiqJ8cCPXz9sebeg+/XPG8FniTI/gebp9yxtQ6AOjhVcli9+OwMOwe3RoLytmUaLr45 9ega09T8auMUCykCx+/hPGearYAlC3z/+MWl52h5oZEXa9tq0+b5fLhdgxEO0DV+Fxhp AN9kWxO+QReYLvsgHNg29FFZ4Zpofrc3FoCH0oF8Csnksr2Ezu+u/tuGe+DGOWCOKfYN cuhesNzmfhYzLujAFikrAfu0Od3KaKU6bA4VRvLMhmi5ufLoKtlX2uFTVu+X4HbDCAem 2g1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=MFamDoDB+NPTBY+FXQ/CqwTtVqrO47PjF46IOrgJo58=; fh=GY0J1BHXV8JCT94Jevwcoc+qV/LriKwcR3tgpDluTBE=; b=fzVWIQ9NI5kQ5TnvkD9nrMbgQUZ01zLMdYEJZYfRYxE898TnbCnVjyltCcgMroNgY0 Ymu/K/8N+x1dK+KHg/9tSi7YDA4oYPK4G1hO2Tx8ggPNC9CsjI+7aqFVGEXONm1IeIDC f5lzxt0Cp8rXq8NlvoQj/zf83KQhYOCTWdF9i4HN/aQSOJUhQwtMfHVgjFzuo54Va5rD wEOluvA9K6E8DQKqE83TQXSv3U/N4pLwXacjKQNFHgdhmy8EoQNqO2pj1K8DduCg9hoY DqFfCuClLFKjado+Oe/I7KOa7gFtvbcHt1McahwSHYufJua4PzJZ1X0fCAyDxEJ8jmdg P1Aw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Mz9xioJX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , Igor Mammedov , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eric Auger , Niek Linnenbank , "Michael S. Tsirkin" , Jan Kiszka , Marcin Juszkiewicz , Alistair Francis , Radoslaw Biernacki , Andrew Jeffery , Andrey Smirnov , Rob Herring , Shannon Zhao , Tyrone Ting , Beniamino Galvani , Alexander Graf , Leif Lindholm , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Paolo Bonzini , Jean-Christophe Dubois , Joel Stanley , Hao Wu , kvm@vger.kernel.org, Richard Henderson Subject: [PATCH 19/20] target/arm: Move GTimer definitions to new 'gtimer.h' header Date: Thu, 18 Jan 2024 21:06:40 +0100 Message-ID: <20240118200643.29037-20-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240118200643.29037-1-philmd@linaro.org> References: <20240118200643.29037-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move Arm A-class Generic Timer definitions to the new "target/arm/gtimer.h" header so units in hw/ which don't need access to ARMCPU internals can use them without having to include the huge "cpu.h". Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.h | 8 +------- target/arm/gtimer.h | 21 +++++++++++++++++++++ hw/arm/allwinner-h3.c | 1 + hw/arm/allwinner-r40.c | 1 + hw/arm/bcm2836.c | 1 + hw/arm/sbsa-ref.c | 1 + hw/arm/virt.c | 1 + hw/arm/xlnx-versal.c | 1 + hw/arm/xlnx-zynqmp.c | 1 + hw/cpu/a15mpcore.c | 1 + target/arm/cpu.c | 1 + target/arm/helper.c | 1 + target/arm/hvf/hvf.c | 1 + target/arm/kvm.c | 1 + target/arm/machine.c | 1 + 15 files changed, 35 insertions(+), 7 deletions(-) create mode 100644 target/arm/gtimer.h diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e8df41d642..d3477b1601 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -27,6 +27,7 @@ #include "exec/cpu-defs.h" #include "qapi/qapi-types-common.h" #include "target/arm/multiprocessing.h" +#include "target/arm/gtimer.h" /* ARM processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) @@ -140,13 +141,6 @@ typedef struct ARMGenericTimer { uint64_t ctl; /* Timer Control register */ } ARMGenericTimer; -#define GTIMER_PHYS 0 -#define GTIMER_VIRT 1 -#define GTIMER_HYP 2 -#define GTIMER_SEC 3 -#define GTIMER_HYPVIRT 4 -#define NUM_GTIMERS 5 - #define VTCR_NSW (1u << 29) #define VTCR_NSA (1u << 30) #define VSTCR_SW VTCR_NSW diff --git a/target/arm/gtimer.h b/target/arm/gtimer.h new file mode 100644 index 0000000000..b992941bef --- /dev/null +++ b/target/arm/gtimer.h @@ -0,0 +1,21 @@ +/* + * ARM generic timer definitions for Arm A-class CPU + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef TARGET_ARM_GTIMER_H +#define TARGET_ARM_GTIMER_H + +enum { + GTIMER_PHYS = 0, + GTIMER_VIRT = 1, + GTIMER_HYP = 2, + GTIMER_SEC = 3, + GTIMER_HYPVIRT = 4, +#define NUM_GTIMERS 5 +}; + +#endif diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index 2d684b5287..380e0ec11d 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -31,6 +31,7 @@ #include "sysemu/sysemu.h" #include "hw/arm/allwinner-h3.h" #include "target/arm/cpu-qom.h" +#include "target/arm/gtimer.h" /* Memory map */ const hwaddr allwinner_h3_memmap[] = { diff --git a/hw/arm/allwinner-r40.c b/hw/arm/allwinner-r40.c index 65392dbc23..898bef9d93 100644 --- a/hw/arm/allwinner-r40.c +++ b/hw/arm/allwinner-r40.c @@ -33,6 +33,7 @@ #include "hw/arm/allwinner-r40.h" #include "hw/misc/allwinner-r40-dramc.h" #include "target/arm/cpu-qom.h" +#include "target/arm/gtimer.h" /* Memory map */ const hwaddr allwinner_r40_memmap[] = { diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index 58a78780d2..e3ba18a8ec 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -16,6 +16,7 @@ #include "hw/arm/raspi_platform.h" #include "hw/sysbus.h" #include "target/arm/cpu-qom.h" +#include "target/arm/gtimer.h" struct BCM283XClass { /*< private >*/ diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index d6081bfc41..85cb68d546 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -51,6 +51,7 @@ #include "qapi/qmp/qlist.h" #include "qom/object.h" #include "target/arm/cpu-qom.h" +#include "target/arm/gtimer.h" #define RAMLIMIT_GB 8192 #define RAMLIMIT_BYTES (RAMLIMIT_GB * GiB) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 0ab5fd9477..bdfcf028a0 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -76,6 +76,7 @@ #include "target/arm/cpu-qom.h" #include "target/arm/internals.h" #include "target/arm/multiprocessing.h" +#include "target/arm/gtimer.h" #include "hw/mem/pc-dimm.h" #include "hw/mem/nvdimm.h" #include "hw/acpi/generic_event_device.h" diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 87fdb39d43..2798df3730 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -24,6 +24,7 @@ #include "hw/arm/xlnx-versal.h" #include "qemu/log.h" #include "target/arm/cpu-qom.h" +#include "target/arm/gtimer.h" #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f") diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 38cb34942f..65901c6e74 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -26,6 +26,7 @@ #include "sysemu/sysemu.h" #include "kvm_arm.h" #include "target/arm/cpu-qom.h" +#include "target/arm/gtimer.h" #define GIC_NUM_SPI_INTR 160 diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index bfd8aa5644..967d8d3dd5 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -26,6 +26,7 @@ #include "hw/qdev-properties.h" #include "sysemu/kvm.h" #include "kvm_arm.h" +#include "target/arm/gtimer.h" static void a15mp_priv_set_irq(void *opaque, int irq, int level) { diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 07357daabe..4c57b9c3b8 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -49,6 +49,7 @@ #include "fpu/softfloat.h" #include "cpregs.h" #include "target/arm/cpu-qom.h" +#include "target/arm/gtimer.h" static void arm_cpu_set_pc(CPUState *cs, vaddr value) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 1ef00e50e4..39e2ba25c8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -30,6 +30,7 @@ #include "semihosting/common-semi.h" #endif #include "cpregs.h" +#include "target/arm/gtimer.h" #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 71a26db188..e5f0f60093 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -29,6 +29,7 @@ #include "target/arm/cpu.h" #include "target/arm/internals.h" #include "target/arm/multiprocessing.h" +#include "target/arm/gtimer.h" #include "trace/trace-target_arm_hvf.h" #include "migration/vmstate.h" diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 8f52b211f9..81813030a5 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -38,6 +38,7 @@ #include "qemu/log.h" #include "hw/acpi/acpi.h" #include "hw/acpi/ghes.h" +#include "target/arm/gtimer.h" const KVMCapabilityInfo kvm_arch_required_capabilities[] = { KVM_CAP_LAST_INFO diff --git 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[209.51.188.17]) by mx.google.com with ESMTPS id w8-20020a0cdf88000000b006818c27e60dsi2232891qvl.539.2024.01.18.12.09.29 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 18 Jan 2024 12:09:29 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=s21r6hZo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rQYgw-00072T-Pr; Thu, 18 Jan 2024 15:08:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rQYgw-00070u-0h for qemu-devel@nongnu.org; Thu, 18 Jan 2024 15:08:46 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1rQYgt-00078n-ET for qemu-devel@nongnu.org; Thu, 18 Jan 2024 15:08:45 -0500 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-40e80046246so437705e9.1 for ; Thu, 18 Jan 2024 12:08:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1705608522; x=1706213322; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/2EqqFckSbhbAC8zOQO19ZG9GyZSFLJsrPZ+inqnxX0=; b=s21r6hZoU3IyB4qFYH7XWmswRVM7hTfqNC/yRsIECrwAoWy1MrcirwNOypkkhmPfAx AD3h8YJpfIA4gCvPdwpL589Ff1+raZ9DnTw0/ttRimTckQpktwD0D/SrSJVa44ZQTXLO IVohSQrwpWea1E6mlc/nshUAF+KKBeXBcKJn+N5MhNnkBI7YApQCY37F38Y4akGx0fFG 7eJdVwAZG5gB/rPLyZ2A2wvKNAEbiU2sqYJv2CTkqze0Z/tDrYGMsrI4l0lB3ZCjIvf3 1BzlDGMkugn6wAR9mKNVY2ACdgm+UzRniu2TaDlp3ZIugLucWeO7C1jhE/tILTnS+4bg 3qoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1705608522; x=1706213322; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/2EqqFckSbhbAC8zOQO19ZG9GyZSFLJsrPZ+inqnxX0=; b=EsujIXNywA01wcNI0Ts5z7SjOVEN9SkfeEqxQ41j/l23MVjlWdCJLQvoP+DlvfLymS aW9aPHnY+QM+eFfCVaO+NI8dXT02Vn2HdycJb6s9Fw2zTdn2fZ1Jgj9aPW7powbiH8yg Ivhd4kUVH9yU55K+yBzwsIA9P/REinh+GNmaMKUMETrpLAhTmyT0gZqgAA/czA4OgajB dXrcIM6taR7a0H05dfBKhFf4E9GYwc4Erb4ik6ll56OKCiiIq3m+elxxY9zB/G5nTxMR /WFBzouduCE6yomg5DhhJW7qRx+UOIRggKCGnZT5jhWeBbhqwRJlSd6U8/SmYPg+g5mU 1mRQ== X-Gm-Message-State: AOJu0YwxYZVSid8g/EhLlkowZssjGHcY8RKHqDcYpTpw0kFAyrxhcti8 m5AzAPvobsCqdcjta4ySQ5OZGI+pHsVK2ZaQdcNbl1JBYXsb4Nw3hJEPitlwyCJc9s/cEf5+qHf T4UNW0Vc7 X-Received: by 2002:a1c:4c18:0:b0:40d:5897:bf52 with SMTP id z24-20020a1c4c18000000b0040d5897bf52mr868484wmf.183.1705608521804; Thu, 18 Jan 2024 12:08:41 -0800 (PST) Received: from localhost.localdomain ([78.196.4.158]) by smtp.gmail.com with ESMTPSA id l22-20020a05600c4f1600b0040d6b91efd9sm30506762wmq.44.2024.01.18.12.08.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 18 Jan 2024 12:08:41 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Igor Mitsyanko , qemu-arm@nongnu.org, Strahinja Jankovic , "Edgar E. Iglesias" , Igor Mammedov , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Eric Auger , Niek Linnenbank , "Michael S. Tsirkin" , Jan Kiszka , Marcin Juszkiewicz , Alistair Francis , Radoslaw Biernacki , Andrew Jeffery , Andrey Smirnov , Rob Herring , Shannon Zhao , Tyrone Ting , Beniamino Galvani , Alexander Graf , Leif Lindholm , Ani Sinha , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Paolo Bonzini , Jean-Christophe Dubois , Joel Stanley , Hao Wu , kvm@vger.kernel.org Subject: [PATCH 20/20] hw/arm: Build various units only once Date: Thu, 18 Jan 2024 21:06:41 +0100 Message-ID: <20240118200643.29037-21-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240118200643.29037-1-philmd@linaro.org> References: <20240118200643.29037-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Various files in hw/arm/ don't require "cpu.h" anymore. Except virt-acpi-build.c, all of them don't require any ARM specific knowledge anymore and can be build once as target agnostic units. Update meson accordingly. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/collie.c | 1 - hw/arm/gumstix.c | 1 - hw/arm/integratorcp.c | 1 - hw/arm/mainstone.c | 1 - hw/arm/musicpal.c | 1 - hw/arm/omap2.c | 1 - hw/arm/omap_sx1.c | 1 - hw/arm/palm.c | 1 - hw/arm/spitz.c | 1 - hw/arm/strongarm.c | 1 - hw/arm/versatilepb.c | 1 - hw/arm/vexpress.c | 1 - hw/arm/virt-acpi-build.c | 1 - hw/arm/xilinx_zynq.c | 1 - hw/arm/xlnx-versal-virt.c | 1 - hw/arm/z2.c | 1 - hw/arm/meson.build | 23 ++++++++++++----------- 17 files changed, 12 insertions(+), 27 deletions(-) diff --git a/hw/arm/collie.c b/hw/arm/collie.c index a0ad1b8dc7..eaa5c52d45 100644 --- a/hw/arm/collie.c +++ b/hw/arm/collie.c @@ -17,7 +17,6 @@ #include "hw/arm/boot.h" #include "hw/block/flash.h" #include "exec/address-spaces.h" -#include "cpu.h" #include "qom/object.h" #include "qemu/error-report.h" diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c index 2ca4140c9f..3f2bcaa24e 100644 --- a/hw/arm/gumstix.c +++ b/hw/arm/gumstix.c @@ -44,7 +44,6 @@ #include "hw/boards.h" #include "exec/address-spaces.h" #include "sysemu/qtest.h" -#include "cpu.h" #define CONNEX_FLASH_SIZE (16 * MiB) #define CONNEX_RAM_SIZE (64 * MiB) diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c index 5600616a4d..793262eca8 100644 --- a/hw/arm/integratorcp.c +++ b/hw/arm/integratorcp.c @@ -9,7 +9,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/sysbus.h" #include "migration/vmstate.h" #include "hw/boards.h" diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c index 68329c4617..fc14e05060 100644 --- a/hw/arm/mainstone.c +++ b/hw/arm/mainstone.c @@ -23,7 +23,6 @@ #include "hw/block/flash.h" #include "hw/sysbus.h" #include "exec/address-spaces.h" -#include "cpu.h" /* Device addresses */ #define MST_FPGA_PHYS 0x08000000 diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index d89824f600..e46aa91807 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -12,7 +12,6 @@ #include "qemu/osdep.h" #include "qemu/units.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/sysbus.h" #include "migration/vmstate.h" #include "hw/arm/boot.h" diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c index f159fb73ea..d9683276c6 100644 --- a/hw/arm/omap2.c +++ b/hw/arm/omap2.c @@ -21,7 +21,6 @@ #include "qemu/osdep.h" #include "qemu/error-report.h" #include "qapi/error.h" -#include "cpu.h" #include "exec/address-spaces.h" #include "sysemu/blockdev.h" #include "sysemu/qtest.h" diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c index 4bf1579f8c..62d7915fb8 100644 --- a/hw/arm/omap_sx1.c +++ b/hw/arm/omap_sx1.c @@ -35,7 +35,6 @@ #include "hw/block/flash.h" #include "sysemu/qtest.h" #include "exec/address-spaces.h" -#include "cpu.h" #include "qemu/cutils.h" #include "qemu/error-report.h" diff --git a/hw/arm/palm.c b/hw/arm/palm.c index b86f2c331b..8c4c831614 100644 --- a/hw/arm/palm.c +++ b/hw/arm/palm.c @@ -29,7 +29,6 @@ #include "hw/input/tsc2xxx.h" #include "hw/irq.h" #include "hw/loader.h" -#include "cpu.h" #include "qemu/cutils.h" #include "qom/object.h" #include "qemu/error-report.h" diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index 1d680b61e2..643a02b180 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -33,7 +33,6 @@ #include "hw/adc/max111x.h" #include "migration/vmstate.h" #include "exec/address-spaces.h" -#include "cpu.h" #include "qom/object.h" #include "audio/audio.h" diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c index 75637869cb..7fd99a0f14 100644 --- a/hw/arm/strongarm.c +++ b/hw/arm/strongarm.c @@ -28,7 +28,6 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/qdev-properties-system.h" diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index 15b5ed0ced..1d813aa23b 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -9,7 +9,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/sysbus.h" #include "migration/vmstate.h" #include "hw/arm/boot.h" diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 49dbcdcbf0..f1b45245d5 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -24,7 +24,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/datadir.h" -#include "cpu.h" #include "hw/sysbus.h" #include "hw/arm/boot.h" #include "hw/arm/primecell.h" diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 43ccc60f43..17aeec7a6f 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -32,7 +32,6 @@ #include "qemu/error-report.h" #include "trace.h" #include "hw/core/cpu.h" -#include "target/arm/cpu.h" #include "hw/acpi/acpi-defs.h" #include "hw/acpi/acpi.h" #include "hw/nvram/fw_cfg_acpi.h" diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 5809fc32af..66d0de139f 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -18,7 +18,6 @@ #include "qemu/osdep.h" #include "qemu/units.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/sysbus.h" #include "hw/arm/boot.h" #include "net/net.h" diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index 29f4d2c2dc..94942c55df 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -16,7 +16,6 @@ #include "hw/boards.h" #include "hw/sysbus.h" #include "hw/arm/fdt.h" -#include "cpu.h" #include "hw/qdev-properties.h" #include "hw/arm/xlnx-versal.h" #include "hw/arm/boot.h" diff --git a/hw/arm/z2.c b/hw/arm/z2.c index 83741a4909..a67fba2cfd 100644 --- a/hw/arm/z2.c +++ b/hw/arm/z2.c @@ -25,7 +25,6 @@ #include "hw/audio/wm8750.h" #include "audio/audio.h" #include "exec/address-spaces.h" -#include "cpu.h" #include "qom/object.h" #include "qapi/error.h" diff --git a/hw/arm/meson.build b/hw/arm/meson.build index bb92b27db3..c401779067 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -9,23 +9,14 @@ arm_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c')) arm_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mainstone.c')) arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c')) arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c')) -arm_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c')) arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c')) arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-h405.c')) arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_boards.c')) arm_ss.add(when: 'CONFIG_NSERIES', if_true: files('nseries.c')) -arm_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c')) -arm_ss.add(when: 'CONFIG_CHEETAH', if_true: files('palm.c')) -arm_ss.add(when: 'CONFIG_GUMSTIX', if_true: files('gumstix.c')) -arm_ss.add(when: 'CONFIG_SPITZ', if_true: files('spitz.c')) -arm_ss.add(when: 'CONFIG_Z2', if_true: files('z2.c')) arm_ss.add(when: 'CONFIG_REALVIEW', if_true: files('realview.c')) arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-ref.c')) arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c')) arm_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vldiscovery.c')) -arm_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c')) -arm_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c')) -arm_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c')) arm_ss.add(when: 'CONFIG_ZYNQ', if_true: files('xilinx_zynq.c')) arm_ss.add(when: 'CONFIG_SABRELITE', if_true: files('sabrelite.c')) @@ -33,8 +24,7 @@ arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m.c')) arm_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4210.c')) arm_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx.c', 'pxa2xx_gpio.c', 'pxa2xx_pic.c')) arm_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic.c')) -arm_ss.add(when: 'CONFIG_OMAP', if_true: files('omap1.c', 'omap2.c')) -arm_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c')) +arm_ss.add(when: 'CONFIG_OMAP', if_true: files('omap1.c')) arm_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true: files('allwinner-a10.c', 'cubieboard.c')) arm_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-h3.c', 'orangepi.c')) arm_ss.add(when: 'CONFIG_ALLWINNER_R40', if_true: files('allwinner-r40.c', 'bananapi_m2u.c')) @@ -69,8 +59,19 @@ arm_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_soc.c')) arm_ss.add(when: 'CONFIG_XEN', if_true: files('xen_arm.c')) system_ss.add(when: 'CONFIG_ARM_SMMUV3', if_true: files('smmu-common.c')) +system_ss.add(when: 'CONFIG_CHEETAH', if_true: files('palm.c')) +system_ss.add(when: 'CONFIG_COLLIE', if_true: files('collie.c')) system_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('exynos4_boards.c')) +system_ss.add(when: 'CONFIG_GUMSTIX', if_true: files('gumstix.c')) +system_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c')) +system_ss.add(when: 'CONFIG_OMAP', if_true: files('omap2.c')) system_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_peripherals.c')) +system_ss.add(when: 'CONFIG_SPITZ', if_true: files('spitz.c')) +system_ss.add(when: 'CONFIG_STRONGARM', if_true: files('strongarm.c')) +system_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c')) system_ss.add(when: 'CONFIG_TOSA', if_true: files('tosa.c')) +system_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c')) +system_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c')) +system_ss.add(when: 'CONFIG_Z2', if_true: files('z2.c')) hw_arch += {'arm': arm_ss}