From patchwork Sat Sep 7 06:42:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 173314 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp1693633ilq; Fri, 6 Sep 2019 23:44:15 -0700 (PDT) X-Google-Smtp-Source: APXvYqx4S83WDgoeruebDyiYJbFC1rD52Uac6gO7Pc0Ge1aIdjZBIENRx7I1wTF5mN1D+12I17Pl X-Received: by 2002:a17:906:25d7:: with SMTP id n23mr5337127ejb.269.1567838655564; Fri, 06 Sep 2019 23:44:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567838655; cv=none; d=google.com; s=arc-20160816; b=HrxaQNE4elBbhjYCWRX8kCKzQKpnhBUGGx8Zyvxi5LzBy9+v3yeCI/YFuRD2o7EQ5o O9ubZZc7oprIT230rmQ4yByjhyCeDKAAIbaYWthEJ0svwwFH5qCcwZJZJboAPudANVxX PBbmQIDDwMV8U0nAVfbFvuQ45v48Pfqo8bOENfNkvpS1KCTkC3AfWV8ACjy7+hSAkOfd xKixorqAdqT6zu1GPjeREYIQC1bZLfyC/FMX7iZP3dOJbBVj+bVCn54moIJi1KdwGcKE jTRS9P0MnDEjSAoHXqXEJT+zTfKzGF3xZQviJwmKXwT+H7xdlJbQchju2JkNnct9TKPD znrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:cc:to:from; bh=Y2uTUa2cVEEgnQtL6Lz94sETccv1Fmx0ZVxZQwYNDrE=; b=mIWVjpBCpn7Ahaxc8C+TYu3lzFwMy3RMBvAeMy24JVNhyfwtY8LIhd2qbBt1yvYiuG +bAE7IAZt99LCPH+UctoFCsLGH8Ue29lB0/cr+Lld3GyfHkBW6pqzsY2b+X7/YTJjoIi 6nXJMUBUSvbgx77jRsDRmMFHMSN3hKzalWsUspqeZjTzP93/fIRF1d2F1geWD/fet7NQ IJGTY1TOMPCz5vcpqcCwhCsJkslNXCm+QEr9uUjD9nTVLTNPUUhAYJkfKrEqR+Ed1Z3i nQG503YwRRH3KXQN/IzQ3924n/DzfZb1oHnJ0MrwIdtKWNSBW1hhsU/XvM64trgQ7uFT D2zw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. [92.243.14.124]) by mx.google.com with ESMTP id ci20si4066477ejb.262.2019.09.06.23.44.15; Fri, 06 Sep 2019 23:44:15 -0700 (PDT) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 3EA911F263; Sat, 7 Sep 2019 08:44:09 +0200 (CEST) Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by dpdk.org (Postfix) with ESMTP id 9F95D1F18E; Sat, 7 Sep 2019 08:44:05 +0200 (CEST) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 27BE820015A; Sat, 7 Sep 2019 08:44:05 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id E76E7200690; Sat, 7 Sep 2019 08:44:02 +0200 (CEST) Received: from bf-netperf1.ap.freescale.net (bf-netperf1.ap.freescale.net [10.232.133.63]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id B0843402B1; Sat, 7 Sep 2019 14:43:59 +0800 (SGT) From: Hemant Agrawal To: dev@dpdk.org Cc: jerinj@marvell.com, stable@dpdk.org, Hemant Agrawal Date: Sat, 7 Sep 2019 12:12:05 +0530 Message-Id: <20190907064209.30686-2-hemant.agrawal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190907064209.30686-1-hemant.agrawal@nxp.com> References: <20190906103410.14996-1-hemant.agrawal@nxp.com> <20190907064209.30686-1-hemant.agrawal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH v2 1/5] event/dpaa2: fix def queue conf X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Test vector expect only one type of scheduling as default. The old code is provide support scheduling types instead of default. Fixes: 13370a3877a5 ("eventdev: fix inconsistency in queue config") Cc: stable@dpdk.org Signed-off-by: Hemant Agrawal --- drivers/event/dpaa2/dpaa2_eventdev.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/event/dpaa2/dpaa2_eventdev.c b/drivers/event/dpaa2/dpaa2_eventdev.c index 926b7edd8..b8cb437a0 100644 --- a/drivers/event/dpaa2/dpaa2_eventdev.c +++ b/drivers/event/dpaa2/dpaa2_eventdev.c @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause - * - * Copyright 2017 NXP - * + * Copyright 2017,2019 NXP */ #include @@ -470,8 +468,7 @@ dpaa2_eventdev_queue_def_conf(struct rte_eventdev *dev, uint8_t queue_id, RTE_SET_USED(queue_conf); queue_conf->nb_atomic_flows = DPAA2_EVENT_QUEUE_ATOMIC_FLOWS; - queue_conf->schedule_type = RTE_SCHED_TYPE_ATOMIC | - RTE_SCHED_TYPE_PARALLEL; + queue_conf->schedule_type = RTE_SCHED_TYPE_PARALLEL; queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL; } From patchwork Sat Sep 7 06:42:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 173316 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp1693828ilq; Fri, 6 Sep 2019 23:44:30 -0700 (PDT) X-Google-Smtp-Source: APXvYqweeyF8vTKadhRtLSuGwS7o7olIhXQTz2DHZEtgFNToVVPmpC5VJeB6YPsiRgV+/qEMUODu X-Received: by 2002:a50:ace2:: with SMTP id x89mr13577310edc.268.1567838670432; Fri, 06 Sep 2019 23:44:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567838670; cv=none; d=google.com; s=arc-20160816; b=YjXeSj5kgICX8R7BFU5pv0zDtfr51Ae/uzhzYR1SSPhbkRmtwiFKSARShTwfsNL0R1 PSDGnPxpTsEwk7ZO/B+hrBdh/glyXruXR8YYLOcdscsGu8lxBaVl90UW3qw8Fui7qTA4 OkHkauK61LfyRH4DCNjFTGotmIpeE3K5G2RC9YiBkjIdbpf8zdT0QpxQ33Tku7Mh4g5L eG1Z7yf4+8xtp4d+Rn+oftdlLQQuRUEQJI74kEpR1YNJGg1YW/IBd7bRCSeN8xLYPMHt x2heOP/0cY+f3dDsQi2YwLc0aBdM1aMcRpuWNKr+qTE4UQfSELWcnp+QoC7gdRkzMKhG /pjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:cc:to:from; bh=gkU1VMMwD5XWSCMrad8/QUfU1ApL8D0Bv87vSA2BNS4=; b=lNxy1YkjbGVGPgqivjtZOcZo9B38sk1nqD7RDJD62466aH6yReJV0UzINBB7ppBktQ USl/Rp0RyKKC5md36djACmZpuycnqKHMXrODee8qkYfDpOXwrV1B9xjpINKoWGcqlKLR XYBRYmVDKxP6rXsWkoZw12XNFRo0qhIVj2hFeGYJ2YwaFpRzWwVTfBuNIfGqpjWMwsIK WpSzkWyx+mdv01fYErsfwjAA33t+xoZLhsV74P6JtMqF6NKLfvI3jlvgCEnzpRsQkK0F DrSqnY8T3w4HsywR8AHO/Y1ePsmcyRYc2LJXHfLVJHVYfqKzMbgYYmiRnOUs0O+LUeGk wSMA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. [92.243.14.124]) by mx.google.com with ESMTP id q4si4093302ejb.186.2019.09.06.23.44.30; Fri, 06 Sep 2019 23:44:30 -0700 (PDT) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A69E91F433; Sat, 7 Sep 2019 08:44:13 +0200 (CEST) Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by dpdk.org (Postfix) with ESMTP id 134501F24B for ; Sat, 7 Sep 2019 08:44:06 +0200 (CEST) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id A3A2B20012B; Sat, 7 Sep 2019 08:44:05 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id CEB79200683; Sat, 7 Sep 2019 08:44:03 +0200 (CEST) Received: from bf-netperf1.ap.freescale.net (bf-netperf1.ap.freescale.net [10.232.133.63]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 7123940314; Sat, 7 Sep 2019 14:44:00 +0800 (SGT) From: Hemant Agrawal To: dev@dpdk.org Cc: jerinj@marvell.com, Hemant Agrawal Date: Sat, 7 Sep 2019 12:12:06 +0530 Message-Id: <20190907064209.30686-3-hemant.agrawal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190907064209.30686-1-hemant.agrawal@nxp.com> References: <20190906103410.14996-1-hemant.agrawal@nxp.com> <20190907064209.30686-1-hemant.agrawal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH v2 2/5] event/dpaa2: remove conditional compilation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch removes the conditional compilation for cryptodev event support from RTE_LIBRTE_SECURITY flag. Signed-off-by: Hemant Agrawal --- drivers/event/dpaa2/Makefile | 2 -- drivers/event/dpaa2/dpaa2_eventdev.c | 6 ------ 2 files changed, 8 deletions(-) -- 2.17.1 diff --git a/drivers/event/dpaa2/Makefile b/drivers/event/dpaa2/Makefile index 470157f25..e0bb527b1 100644 --- a/drivers/event/dpaa2/Makefile +++ b/drivers/event/dpaa2/Makefile @@ -24,10 +24,8 @@ LDLIBS += -lrte_common_dpaax CFLAGS += -I$(RTE_SDK)/drivers/net/dpaa2 CFLAGS += -I$(RTE_SDK)/drivers/net/dpaa2/mc -ifeq ($(CONFIG_RTE_LIBRTE_SECURITY),y) LDLIBS += -lrte_pmd_dpaa2_sec CFLAGS += -I$(RTE_SDK)/drivers/crypto/dpaa2_sec -endif # versioning export map EXPORT_MAP := rte_pmd_dpaa2_event_version.map diff --git a/drivers/event/dpaa2/dpaa2_eventdev.c b/drivers/event/dpaa2/dpaa2_eventdev.c index b8cb437a0..98b487603 100644 --- a/drivers/event/dpaa2/dpaa2_eventdev.c +++ b/drivers/event/dpaa2/dpaa2_eventdev.c @@ -33,9 +33,7 @@ #include #include #include -#ifdef RTE_LIBRTE_SECURITY #include -#endif #include "dpaa2_eventdev.h" #include "dpaa2_eventdev_logs.h" #include @@ -794,7 +792,6 @@ dpaa2_eventdev_eth_stop(const struct rte_eventdev *dev, return 0; } -#ifdef RTE_LIBRTE_SECURITY static int dpaa2_eventdev_crypto_caps_get(const struct rte_eventdev *dev, const struct rte_cryptodev *cdev, @@ -937,7 +934,6 @@ dpaa2_eventdev_crypto_stop(const struct rte_eventdev *dev, return 0; } -#endif static struct rte_eventdev_ops dpaa2_eventdev_ops = { .dev_infos_get = dpaa2_eventdev_info_get, @@ -960,13 +956,11 @@ static struct rte_eventdev_ops dpaa2_eventdev_ops = { .eth_rx_adapter_queue_del = dpaa2_eventdev_eth_queue_del, .eth_rx_adapter_start = dpaa2_eventdev_eth_start, .eth_rx_adapter_stop = dpaa2_eventdev_eth_stop, -#ifdef RTE_LIBRTE_SECURITY .crypto_adapter_caps_get = dpaa2_eventdev_crypto_caps_get, .crypto_adapter_queue_pair_add = dpaa2_eventdev_crypto_queue_add, .crypto_adapter_queue_pair_del = dpaa2_eventdev_crypto_queue_del, .crypto_adapter_start = dpaa2_eventdev_crypto_start, .crypto_adapter_stop = dpaa2_eventdev_crypto_stop, -#endif }; static int From patchwork Sat Sep 7 06:42:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 173315 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp1693751ilq; Fri, 6 Sep 2019 23:44:24 -0700 (PDT) X-Google-Smtp-Source: APXvYqwUxhpH28V+vY17aOsHY2KS3fx2I7cbvDCh7kRxT3TKPj4trjAuvvxrSyMKdRegbfIXCoHK X-Received: by 2002:a50:ad2c:: with SMTP id y41mr13430271edc.114.1567838663839; Fri, 06 Sep 2019 23:44:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567838663; cv=none; d=google.com; s=arc-20160816; b=Z8PWllWfOHj7xE2kQsovRi9pbKgKNBNTP5ZGbtdYE9eqJiGQav2V4MgConoMyljYea OnUZUykDU86aC1mHIRTxhYhmvwsplJezb0Y6yaJ+c7XJvc+rL7ti1YMp+HhqqmyRrzPc QvEHB8whc+9KBtaODnEy03VeCyMNWcpY/lgTp9hKRCWbnoRo5gcyZ4ejXD0JzeH6oRIJ UKYfFLaeCPCFvb3yEamcP1OGex9b7K1EVDikud5JbcuiGtiPkrdTFdmM0eBPg/iYBQRh DjhHLQOBHTHiQ36ps/Gy76kVhyWetfiZ+SGp0/czRAwsdFNyMvVvE46WrnVtWnBM7n5c RD9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:cc:to:from; bh=remTtFIjDZ4ou8m8DOyCsrPFdM47heyFRWck+l5+E8A=; b=YENCmOasXJHdZkl3cpql+c/7uL0cQhNl1ADU1R0e8cxmb/vvvymQ4sUBUCly+mj0fw 8DXfRUu+Cikak2OGQv+tYppe9wzKPtieBnd6PxTPPKHVTv+CoRZzyzAIUaEzgkuyrhmc 6X5A9Jwr4zQyO2LP+N1Qp/3MaIyaQ0Ov0M47vo9OASBpZP19R/GKjoyGx8xm0KHiP6Us Fun+djjG2Z9ScuV1JazlL6IJUSR994AWBeMyC7pEEBOjLQNzu9vl8IdGpzVB3czzHTLJ Tln7Ha1VUVzaHZ6R7csrynj7YfCWjbZGOGxdZxGBlpNgiWxWPQKL43rU6Z6hQZUNVELL R0Tw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. [92.243.14.124]) by mx.google.com with ESMTP id z13si4087543eju.97.2019.09.06.23.44.23; Fri, 06 Sep 2019 23:44:23 -0700 (PDT) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 913081F417; Sat, 7 Sep 2019 08:44:11 +0200 (CEST) Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by dpdk.org (Postfix) with ESMTP id F392D1F1A4 for ; Sat, 7 Sep 2019 08:44:05 +0200 (CEST) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id A38E91A0CF5; Sat, 7 Sep 2019 08:44:05 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id CEEE11A066D; Sat, 7 Sep 2019 08:44:03 +0200 (CEST) Received: from bf-netperf1.ap.freescale.net (bf-netperf1.ap.freescale.net [10.232.133.63]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 12F264031B; Sat, 7 Sep 2019 14:44:00 +0800 (SGT) From: Hemant Agrawal To: dev@dpdk.org Cc: jerinj@marvell.com, Hemant Agrawal Date: Sat, 7 Sep 2019 12:12:07 +0530 Message-Id: <20190907064209.30686-4-hemant.agrawal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190907064209.30686-1-hemant.agrawal@nxp.com> References: <20190906103410.14996-1-hemant.agrawal@nxp.com> <20190907064209.30686-1-hemant.agrawal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH v2 3/5] event/dpaa2: add destroy support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Hemant Agrawal --- drivers/event/dpaa2/dpaa2_eventdev.c | 35 ++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) -- 2.17.1 diff --git a/drivers/event/dpaa2/dpaa2_eventdev.c b/drivers/event/dpaa2/dpaa2_eventdev.c index 98b487603..9255de16f 100644 --- a/drivers/event/dpaa2/dpaa2_eventdev.c +++ b/drivers/event/dpaa2/dpaa2_eventdev.c @@ -1059,6 +1059,39 @@ dpaa2_eventdev_create(const char *name) return -EFAULT; } +static int +dpaa2_eventdev_destroy(const char *name) +{ + struct rte_eventdev *eventdev; + struct dpaa2_eventdev *priv; + int i; + + eventdev = rte_event_pmd_get_named_dev(name); + if (eventdev == NULL) { + RTE_EDEV_LOG_ERR("eventdev with name %s not allocated", name); + return -1; + } + + /* For secondary processes, the primary has done all the work */ + if (rte_eal_process_type() != RTE_PROC_PRIMARY) + return 0; + + priv = eventdev->data->dev_private; + for (i = 0; i < priv->max_event_queues; i++) { + if (priv->evq_info[i].dpcon) + rte_dpaa2_free_dpcon_dev(priv->evq_info[i].dpcon); + + if (priv->evq_info[i].dpci) + rte_dpaa2_free_dpci_dev(priv->evq_info[i].dpci); + + } + priv->max_event_queues = 0; + + RTE_LOG(INFO, PMD, "%s eventdev cleaned\n", name); + return 0; +} + + static int dpaa2_eventdev_probe(struct rte_vdev_device *vdev) { @@ -1077,6 +1110,8 @@ dpaa2_eventdev_remove(struct rte_vdev_device *vdev) name = rte_vdev_device_name(vdev); DPAA2_EVENTDEV_INFO("Closing %s", name); + dpaa2_eventdev_destroy(name); + return rte_event_pmd_vdev_uninit(name); } From patchwork Sat Sep 7 06:42:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hemant Agrawal X-Patchwork-Id: 173317 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp1693933ilq; Fri, 6 Sep 2019 23:44:39 -0700 (PDT) X-Google-Smtp-Source: APXvYqypLIGzM4M5nn9bqCnUbol/kJgyIyU8wHYp0Ji7te2iRtrTHKx3YW7w476omzazzSoOZM6m X-Received: by 2002:a50:c209:: with SMTP id n9mr13614124edf.215.1567838679111; Fri, 06 Sep 2019 23:44:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567838679; cv=none; d=google.com; s=arc-20160816; b=IV5SOrMW9WDP4YsbK8c1uhTbSJf5Se6XiVREFvUwfAaWItq98F1Liypzi8hp/IXSEh vB2UNfvE1/o+RAMs7krPPI983l3JcY9xqJbf3sBxlcblefdx7wfParbf4iog1Lc+NGf9 BIuA2HZXHqpYvW7zrWT0/91LqO/xDmATG7dKceFCOkGIT+WfWJ/quohxZnV4Ea+F1JcQ W4yztKYTe8UaOSfXGz5U/QkyD6zIOMi7r2CtKhFtnEW6eHkn5MVXr56c87NeXVqHOPgE wtTOAIN6z6hW5yaN5NeHdPmVjGGpjGMysYNm0WWmjuw1ARwwQaLdP60kwmTd4c5Qu7mj LS3Q== ARC-Message-Signature: i=1; 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[92.243.14.124]) by mx.google.com with ESMTP id j14si4739029eda.181.2019.09.06.23.44.38; Fri, 06 Sep 2019 23:44:39 -0700 (PDT) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E81251F469; Sat, 7 Sep 2019 08:44:15 +0200 (CEST) Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by dpdk.org (Postfix) with ESMTP id D3D1E1F263 for ; Sat, 7 Sep 2019 08:44:06 +0200 (CEST) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id B1C32200690; Sat, 7 Sep 2019 08:44:06 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 77AFB20068E; Sat, 7 Sep 2019 08:44:04 +0200 (CEST) Received: from bf-netperf1.ap.freescale.net (bf-netperf1.ap.freescale.net [10.232.133.63]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id A9EB44031C; Sat, 7 Sep 2019 14:44:01 +0800 (SGT) From: Hemant Agrawal To: dev@dpdk.org Cc: jerinj@marvell.com, Hemant Agrawal Date: Sat, 7 Sep 2019 12:12:08 +0530 Message-Id: <20190907064209.30686-5-hemant.agrawal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190907064209.30686-1-hemant.agrawal@nxp.com> References: <20190906103410.14996-1-hemant.agrawal@nxp.com> <20190907064209.30686-1-hemant.agrawal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH v2 4/5] event/dpaa2: add selftest cases X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch add support for testing dpaa2 eventdev self test for basic sanity for parallel and atomic queues. Signed-off-by: Hemant Agrawal --- drivers/event/dpaa2/Makefile | 1 + drivers/event/dpaa2/dpaa2_eventdev.c | 1 + drivers/event/dpaa2/dpaa2_eventdev.h | 2 + drivers/event/dpaa2/dpaa2_eventdev_logs.h | 6 + drivers/event/dpaa2/dpaa2_eventdev_selftest.c | 874 ++++++++++++++++++ drivers/event/dpaa2/meson.build | 3 +- 6 files changed, 886 insertions(+), 1 deletion(-) create mode 100644 drivers/event/dpaa2/dpaa2_eventdev_selftest.c -- 2.17.1 diff --git a/drivers/event/dpaa2/Makefile b/drivers/event/dpaa2/Makefile index e0bb527b1..634179383 100644 --- a/drivers/event/dpaa2/Makefile +++ b/drivers/event/dpaa2/Makefile @@ -40,5 +40,6 @@ CFLAGS += -DALLOW_EXPERIMENTAL_API # SRCS-$(CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV) += dpaa2_hw_dpcon.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV) += dpaa2_eventdev.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_DPAA2_EVENTDEV) += dpaa2_eventdev_selftest.c include $(RTE_SDK)/mk/rte.lib.mk diff --git a/drivers/event/dpaa2/dpaa2_eventdev.c b/drivers/event/dpaa2/dpaa2_eventdev.c index 9255de16f..902a80f36 100644 --- a/drivers/event/dpaa2/dpaa2_eventdev.c +++ b/drivers/event/dpaa2/dpaa2_eventdev.c @@ -951,6 +951,7 @@ static struct rte_eventdev_ops dpaa2_eventdev_ops = { .port_unlink = dpaa2_eventdev_port_unlink, .timeout_ticks = dpaa2_eventdev_timeout_ticks, .dump = dpaa2_eventdev_dump, + .dev_selftest = test_eventdev_dpaa2, .eth_rx_adapter_caps_get = dpaa2_eventdev_eth_caps_get, .eth_rx_adapter_queue_add = dpaa2_eventdev_eth_queue_add, .eth_rx_adapter_queue_del = dpaa2_eventdev_eth_queue_del, diff --git a/drivers/event/dpaa2/dpaa2_eventdev.h b/drivers/event/dpaa2/dpaa2_eventdev.h index bdac1aa56..abc038e49 100644 --- a/drivers/event/dpaa2/dpaa2_eventdev.h +++ b/drivers/event/dpaa2/dpaa2_eventdev.h @@ -98,4 +98,6 @@ struct dpaa2_eventdev { struct dpaa2_dpcon_dev *rte_dpaa2_alloc_dpcon_dev(void); void rte_dpaa2_free_dpcon_dev(struct dpaa2_dpcon_dev *dpcon); +int test_eventdev_dpaa2(void); + #endif /* __DPAA2_EVENTDEV_H__ */ diff --git a/drivers/event/dpaa2/dpaa2_eventdev_logs.h b/drivers/event/dpaa2/dpaa2_eventdev_logs.h index 86f2e5393..bb5a0e26c 100644 --- a/drivers/event/dpaa2/dpaa2_eventdev_logs.h +++ b/drivers/event/dpaa2/dpaa2_eventdev_logs.h @@ -35,4 +35,10 @@ extern int dpaa2_logtype_event; #define DPAA2_EVENTDEV_DP_WARN(fmt, args...) \ DPAA2_EVENTDEV_DP_LOG(WARNING, fmt, ## args) +#define dpaa2_evdev_info(fmt, ...) DPAA2_EVENTDEV_LOG(INFO, fmt, ##__VA_ARGS__) +#define dpaa2_evdev_dbg(fmt, ...) DPAA2_EVENTDEV_LOG(DEBUG, fmt, ##__VA_ARGS__) +#define dpaa2_evdev_err(fmt, ...) DPAA2_EVENTDEV_LOG(ERR, fmt, ##__VA_ARGS__) +#define dpaa2_evdev__func_trace dpaa2_evdev_dbg +#define dpaa2_evdev_selftest dpaa2_evdev_info + #endif /* _DPAA2_EVENTDEV_LOGS_H_ */ diff --git a/drivers/event/dpaa2/dpaa2_eventdev_selftest.c b/drivers/event/dpaa2/dpaa2_eventdev_selftest.c new file mode 100644 index 000000000..e02f0f545 --- /dev/null +++ b/drivers/event/dpaa2/dpaa2_eventdev_selftest.c @@ -0,0 +1,874 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright 2018 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dpaa2_eventdev.h" +#include "dpaa2_eventdev_logs.h" + +#define MAX_PORTS 4 +#define NUM_PACKETS (1 << 18) +//todo #define MAX_EVENTS 1024 +#define MAX_EVENTS 8 +#define DPAA2_TEST_RUN(setup, teardown, test) \ + dpaa2_test_run(setup, teardown, test, #test) + +static int total; +static int passed; +static int failed; +static int unsupported; + +static int evdev; +static struct rte_mempool *eventdev_test_mempool; + +struct event_attr { + uint32_t flow_id; + uint8_t event_type; + uint8_t sub_event_type; + uint8_t sched_type; + uint8_t queue; + uint8_t port; + uint8_t seq; +}; + +static uint32_t seqn_list_index; +static int seqn_list[NUM_PACKETS]; + +static inline void +seqn_list_init(void) +{ + RTE_BUILD_BUG_ON(NUM_PACKETS < MAX_EVENTS); + memset(seqn_list, 0, sizeof(seqn_list)); + seqn_list_index = 0; +} + +static inline int +seqn_list_update(int val) +{ + if (seqn_list_index >= NUM_PACKETS) + return -1; + + seqn_list[seqn_list_index++] = val; + rte_smp_wmb(); + return 0; +} + +static inline int +seqn_list_check(int limit) +{ + int i; + + for (i = 0; i < limit; i++) { + if (seqn_list[i] != i) { + dpaa2_evdev_dbg("Seqn mismatch %d %d", seqn_list[i], i); + return -1; + } + } + return 0; +} + +struct test_core_param { + rte_atomic32_t *total_events; + uint64_t dequeue_tmo_ticks; + uint8_t port; + uint8_t sched_type; +}; + +static int +testsuite_setup(void) +{ + const char *eventdev_name = "event_dpaa2"; + + evdev = rte_event_dev_get_dev_id(eventdev_name); + if (evdev < 0) { + dpaa2_evdev_dbg("%d: Eventdev %s not found - creating.", + __LINE__, eventdev_name); + if (rte_vdev_init(eventdev_name, NULL) < 0) { + dpaa2_evdev_dbg("Error creating eventdev %s", + eventdev_name); + return -1; + } + evdev = rte_event_dev_get_dev_id(eventdev_name); + if (evdev < 0) { + dpaa2_evdev_dbg("Error finding newly created eventdev"); + return -1; + } + } + + return 0; +} + +static void +testsuite_teardown(void) +{ + rte_event_dev_close(evdev); +} + +static inline void +devconf_set_default_sane_values(struct rte_event_dev_config *dev_conf, + struct rte_event_dev_info *info) +{ + memset(dev_conf, 0, sizeof(struct rte_event_dev_config)); + dev_conf->dequeue_timeout_ns = info->min_dequeue_timeout_ns; + dev_conf->nb_event_ports = info->max_event_ports; + dev_conf->nb_event_queues = info->max_event_queues; + dev_conf->nb_event_queue_flows = info->max_event_queue_flows; + dev_conf->nb_event_port_dequeue_depth = + info->max_event_port_dequeue_depth; + dev_conf->nb_event_port_enqueue_depth = + info->max_event_port_enqueue_depth; + dev_conf->nb_event_port_enqueue_depth = + info->max_event_port_enqueue_depth; + dev_conf->nb_events_limit = + info->max_num_events; +} + +enum { + TEST_EVENTDEV_SETUP_DEFAULT, + TEST_EVENTDEV_SETUP_PRIORITY, + TEST_EVENTDEV_SETUP_DEQUEUE_TIMEOUT, +}; + +static inline int +_eventdev_setup(int mode) +{ + int i, ret; + struct rte_event_dev_config dev_conf; + struct rte_event_dev_info info; + const char *pool_name = "evdev_dpaa2_test_pool"; + + /* Create and destrory pool for each test case to make it standalone */ + eventdev_test_mempool = rte_pktmbuf_pool_create(pool_name, + MAX_EVENTS, + 0 /*MBUF_CACHE_SIZE*/, + 0, + 512, /* Use very small mbufs */ + rte_socket_id()); + if (!eventdev_test_mempool) { + dpaa2_evdev_dbg("ERROR creating mempool"); + return -1; + } + + ret = rte_event_dev_info_get(evdev, &info); + RTE_TEST_ASSERT_SUCCESS(ret, "Failed to get event dev info"); + RTE_TEST_ASSERT(info.max_num_events >= (int32_t)MAX_EVENTS, + "ERROR max_num_events=%d < max_events=%d", + info.max_num_events, MAX_EVENTS); + + devconf_set_default_sane_values(&dev_conf, &info); + if (mode == TEST_EVENTDEV_SETUP_DEQUEUE_TIMEOUT) + dev_conf.event_dev_cfg |= RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT; + + ret = rte_event_dev_configure(evdev, &dev_conf); + RTE_TEST_ASSERT_SUCCESS(ret, "Failed to configure eventdev"); + + uint32_t queue_count; + + RTE_TEST_ASSERT_SUCCESS(rte_event_dev_attr_get(evdev, + RTE_EVENT_DEV_ATTR_QUEUE_COUNT, + &queue_count), "Queue count get failed"); + + if (mode == TEST_EVENTDEV_SETUP_PRIORITY) { + if (queue_count > 8) { + dpaa2_evdev_dbg( + "test expects the unique priority per queue"); + return -ENOTSUP; + } + + /* Configure event queues(0 to n) with + * RTE_EVENT_DEV_PRIORITY_HIGHEST to + * RTE_EVENT_DEV_PRIORITY_LOWEST + */ + uint8_t step = (RTE_EVENT_DEV_PRIORITY_LOWEST + 1) / + queue_count; + for (i = 0; i < (int)queue_count; i++) { + struct rte_event_queue_conf queue_conf; + + ret = rte_event_queue_default_conf_get(evdev, i, + &queue_conf); + RTE_TEST_ASSERT_SUCCESS(ret, "Failed to get def_conf%d", + i); + queue_conf.priority = i * step; + ret = rte_event_queue_setup(evdev, i, &queue_conf); + RTE_TEST_ASSERT_SUCCESS(ret, "Failed to setup queue=%d", + i); + } + + } else { + /* Configure event queues with default priority */ + for (i = 0; i < (int)queue_count; i++) { + ret = rte_event_queue_setup(evdev, i, NULL); + RTE_TEST_ASSERT_SUCCESS(ret, "Failed to setup queue=%d", + i); + } + } + /* Configure event ports */ + uint32_t port_count; + + RTE_TEST_ASSERT_SUCCESS(rte_event_dev_attr_get(evdev, + RTE_EVENT_DEV_ATTR_PORT_COUNT, + &port_count), "Port count get failed"); + for (i = 0; i < (int)port_count; i++) { + ret = rte_event_port_setup(evdev, i, NULL); + RTE_TEST_ASSERT_SUCCESS(ret, "Failed to setup port=%d", i); + ret = rte_event_port_link(evdev, i, NULL, NULL, 0); + RTE_TEST_ASSERT(ret >= 0, "Failed to link all queues port=%d", + i); + } + + ret = rte_event_dev_start(evdev); + RTE_TEST_ASSERT_SUCCESS(ret, "Failed to start device"); + + return 0; +} + +static inline int +eventdev_setup(void) +{ + return _eventdev_setup(TEST_EVENTDEV_SETUP_DEFAULT); +} + +static inline int +eventdev_setup_priority(void) +{ + return _eventdev_setup(TEST_EVENTDEV_SETUP_PRIORITY); +} + +static inline int +eventdev_setup_dequeue_timeout(void) +{ + return _eventdev_setup(TEST_EVENTDEV_SETUP_DEQUEUE_TIMEOUT); +} + +static inline void +eventdev_teardown(void) +{ + rte_event_dev_stop(evdev); + rte_mempool_free(eventdev_test_mempool); +} + +static inline void +update_event_and_validation_attr(struct rte_mbuf *m, struct rte_event *ev, + uint32_t flow_id, uint8_t event_type, + uint8_t sub_event_type, uint8_t sched_type, + uint8_t queue, uint8_t port, uint8_t seq) +{ + struct event_attr *attr; + + /* Store the event attributes in mbuf for future reference */ + attr = rte_pktmbuf_mtod(m, struct event_attr *); + attr->flow_id = flow_id; + attr->event_type = event_type; + attr->sub_event_type = sub_event_type; + attr->sched_type = sched_type; + attr->queue = queue; + attr->port = port; + attr->seq = seq; + + ev->flow_id = flow_id; + ev->sub_event_type = sub_event_type; + ev->event_type = event_type; + /* Inject the new event */ + ev->op = RTE_EVENT_OP_NEW; + ev->sched_type = sched_type; + ev->queue_id = queue; + ev->mbuf = m; +} + +static inline int +inject_events(uint32_t flow_id, uint8_t event_type, uint8_t sub_event_type, + uint8_t sched_type, uint8_t queue, uint8_t port, + unsigned int events) +{ + struct rte_mbuf *m; + unsigned int i; + + for (i = 0; i < events; i++) { + struct rte_event ev = {.event = 0, .u64 = 0}; + + m = rte_pktmbuf_alloc(eventdev_test_mempool); + RTE_TEST_ASSERT_NOT_NULL(m, "mempool alloc failed"); + + update_event_and_validation_attr(m, &ev, flow_id, event_type, + sub_event_type, sched_type, queue, port, i); + rte_event_enqueue_burst(evdev, port, &ev, 1); + } + return 0; +} + +static inline int +check_excess_events(uint8_t port) +{ + int i; + uint16_t valid_event; + struct rte_event ev; + + /* Check for excess events, try for a few times and exit */ + for (i = 0; i < 32; i++) { + valid_event = rte_event_dequeue_burst(evdev, port, &ev, 1, 0); + + RTE_TEST_ASSERT_SUCCESS(valid_event, + "Unexpected valid event=%d", ev.mbuf->seqn); + } + return 0; +} + +static inline int +generate_random_events(const unsigned int total_events) +{ + struct rte_event_dev_info info; + unsigned int i; + int ret; + + uint32_t queue_count; + + RTE_TEST_ASSERT_SUCCESS(rte_event_dev_attr_get(evdev, + RTE_EVENT_DEV_ATTR_QUEUE_COUNT, + &queue_count), "Queue count get failed"); + + ret = rte_event_dev_info_get(evdev, &info); + RTE_TEST_ASSERT_SUCCESS(ret, "Failed to get event dev info"); + for (i = 0; i < total_events; i++) { + ret = inject_events( + rte_rand() % info.max_event_queue_flows /*flow_id */, + RTE_EVENT_TYPE_CPU /* event_type */, + rte_rand() % 256 /* sub_event_type */, + rte_rand() % (RTE_SCHED_TYPE_PARALLEL + 1), + rte_rand() % queue_count /* queue */, + 0 /* port */, + 1 /* events */); + if (ret) + return -1; + } + return ret; +} + + +static inline int +validate_event(struct rte_event *ev) +{ + struct event_attr *attr; + + attr = rte_pktmbuf_mtod(ev->mbuf, struct event_attr *); + RTE_TEST_ASSERT_EQUAL(attr->flow_id, ev->flow_id, + "flow_id mismatch enq=%d deq =%d", + attr->flow_id, ev->flow_id); + RTE_TEST_ASSERT_EQUAL(attr->event_type, ev->event_type, + "event_type mismatch enq=%d deq =%d", + attr->event_type, ev->event_type); + RTE_TEST_ASSERT_EQUAL(attr->sub_event_type, ev->sub_event_type, + "sub_event_type mismatch enq=%d deq =%d", + attr->sub_event_type, ev->sub_event_type); + RTE_TEST_ASSERT_EQUAL(attr->sched_type, ev->sched_type, + "sched_type mismatch enq=%d deq =%d", + attr->sched_type, ev->sched_type); + RTE_TEST_ASSERT_EQUAL(attr->queue, ev->queue_id, + "queue mismatch enq=%d deq =%d", + attr->queue, ev->queue_id); + return 0; +} + +typedef int (*validate_event_cb)(uint32_t index, uint8_t port, + struct rte_event *ev); + +static inline int +consume_events(uint8_t port, const uint32_t total_events, validate_event_cb fn) +{ + int ret; + uint16_t valid_event; + uint32_t events = 0, forward_progress_cnt = 0, index = 0; + struct rte_event ev; + + while (1) { + if (++forward_progress_cnt > UINT16_MAX) { + dpaa2_evdev_dbg("Detected deadlock"); + return -1; + } + + valid_event = rte_event_dequeue_burst(evdev, port, &ev, 1, 0); + if (!valid_event) + continue; + + forward_progress_cnt = 0; + ret = validate_event(&ev); + if (ret) + return -1; + + if (fn != NULL) { + ret = fn(index, port, &ev); + RTE_TEST_ASSERT_SUCCESS(ret, + "Failed to validate test specific event"); + } + + ++index; + + rte_pktmbuf_free(ev.mbuf); + if (++events >= total_events) + break; + } + + return check_excess_events(port); +} + +static int +validate_simple_enqdeq(uint32_t index, uint8_t port, struct rte_event *ev) +{ + struct event_attr *attr; + + attr = rte_pktmbuf_mtod(ev->mbuf, struct event_attr *); + + RTE_SET_USED(port); + RTE_TEST_ASSERT_EQUAL(index, attr->seq, + "index=%d != seqn=%d", index, attr->seq); + return 0; +} + +static inline int +test_simple_enqdeq(uint8_t sched_type) +{ + int ret; + + ret = inject_events(0 /*flow_id */, + RTE_EVENT_TYPE_CPU /* event_type */, + 0 /* sub_event_type */, + sched_type, + 0 /* queue */, + 0 /* port */, + MAX_EVENTS); + if (ret) + return -1; + + return consume_events(0 /* port */, MAX_EVENTS, validate_simple_enqdeq); +} + +static int +test_simple_enqdeq_atomic(void) +{ + return test_simple_enqdeq(RTE_SCHED_TYPE_ATOMIC); +} + +static int +test_simple_enqdeq_parallel(void) +{ + return test_simple_enqdeq(RTE_SCHED_TYPE_PARALLEL); +} + +/* + * Generate a prescribed number of events and spread them across available + * queues. On dequeue, using single event port(port 0) verify the enqueued + * event attributes + */ +static int +test_multi_queue_enq_single_port_deq(void) +{ + int ret; + + ret = generate_random_events(MAX_EVENTS); + if (ret) + return -1; + + return consume_events(0 /* port */, MAX_EVENTS, NULL); +} + +static int +worker_multi_port_fn(void *arg) +{ + struct test_core_param *param = arg; + struct rte_event ev; + uint16_t valid_event; + uint8_t port = param->port; + rte_atomic32_t *total_events = param->total_events; + int ret; + + while (rte_atomic32_read(total_events) > 0) { + valid_event = rte_event_dequeue_burst(evdev, port, &ev, 1, 0); + if (!valid_event) + continue; + + ret = validate_event(&ev); + RTE_TEST_ASSERT_SUCCESS(ret, "Failed to validate event"); + rte_pktmbuf_free(ev.mbuf); + rte_atomic32_sub(total_events, 1); + } + return 0; +} + +static inline int +wait_workers_to_join(int lcore, const rte_atomic32_t *count) +{ + uint64_t cycles, print_cycles; + + RTE_SET_USED(count); + + print_cycles = cycles = rte_get_timer_cycles(); + while (rte_eal_get_lcore_state(lcore) != FINISHED) { + uint64_t new_cycles = rte_get_timer_cycles(); + + if (new_cycles - print_cycles > rte_get_timer_hz()) { + dpaa2_evdev_dbg("\r%s: events %d", __func__, + rte_atomic32_read(count)); + print_cycles = new_cycles; + } + if (new_cycles - cycles > rte_get_timer_hz() * 10) { + dpaa2_evdev_dbg( + "%s: No schedules for seconds, deadlock (%d)", + __func__, + rte_atomic32_read(count)); + rte_event_dev_dump(evdev, stdout); + cycles = new_cycles; + return -1; + } + } + rte_eal_mp_wait_lcore(); + return 0; +} + + +static inline int +launch_workers_and_wait(int (*master_worker)(void *), + int (*slave_workers)(void *), uint32_t total_events, + uint8_t nb_workers, uint8_t sched_type) +{ + uint8_t port = 0; + int w_lcore; + int ret; + struct test_core_param *param; + rte_atomic32_t atomic_total_events; + uint64_t dequeue_tmo_ticks; + + if (!nb_workers) + return 0; + + rte_atomic32_set(&atomic_total_events, total_events); + seqn_list_init(); + + param = malloc(sizeof(struct test_core_param) * nb_workers); + if (!param) + return -1; + + ret = rte_event_dequeue_timeout_ticks(evdev, + rte_rand() % 10000000/* 10ms */, &dequeue_tmo_ticks); + if (ret) { + free(param); + return -1; + } + + param[0].total_events = &atomic_total_events; + param[0].sched_type = sched_type; + param[0].port = 0; + param[0].dequeue_tmo_ticks = dequeue_tmo_ticks; + rte_smp_wmb(); + + w_lcore = rte_get_next_lcore( + /* start core */ -1, + /* skip master */ 1, + /* wrap */ 0); + rte_eal_remote_launch(master_worker, ¶m[0], w_lcore); + + for (port = 1; port < nb_workers; port++) { + param[port].total_events = &atomic_total_events; + param[port].sched_type = sched_type; + param[port].port = port; + param[port].dequeue_tmo_ticks = dequeue_tmo_ticks; + rte_smp_wmb(); + w_lcore = rte_get_next_lcore(w_lcore, 1, 0); + rte_eal_remote_launch(slave_workers, ¶m[port], w_lcore); + } + + ret = wait_workers_to_join(w_lcore, &atomic_total_events); + free(param); + return ret; +} + +/* + * Generate a prescribed number of events and spread them across available + * queues. Dequeue the events through multiple ports and verify the enqueued + * event attributes + */ +static int +test_multi_queue_enq_multi_port_deq(void) +{ + const unsigned int total_events = MAX_EVENTS; + uint32_t nr_ports; + int ret; + + ret = generate_random_events(total_events); + if (ret) + return -1; + + RTE_TEST_ASSERT_SUCCESS(rte_event_dev_attr_get(evdev, + RTE_EVENT_DEV_ATTR_PORT_COUNT, + &nr_ports), "Port count get failed"); + nr_ports = RTE_MIN(nr_ports, rte_lcore_count() - 1); + + if (!nr_ports) { + dpaa2_evdev_dbg("%s: Not enough ports=%d or workers=%d", + __func__, nr_ports, rte_lcore_count() - 1); + return 0; + } + + return launch_workers_and_wait(worker_multi_port_fn, + worker_multi_port_fn, total_events, + nr_ports, 0xff /* invalid */); +} + +static +void flush(uint8_t dev_id, struct rte_event event, void *arg) +{ + unsigned int *count = arg; + + RTE_SET_USED(dev_id); + if (event.event_type == RTE_EVENT_TYPE_CPU) + *count = *count + 1; + +} + +static int +test_dev_stop_flush(void) +{ + unsigned int total_events = MAX_EVENTS, count = 0; + int ret; + + ret = generate_random_events(total_events); + if (ret) + return -1; + + ret = rte_event_dev_stop_flush_callback_register(evdev, flush, &count); + if (ret) + return -2; + rte_event_dev_stop(evdev); + ret = rte_event_dev_stop_flush_callback_register(evdev, NULL, NULL); + if (ret) + return -3; + RTE_TEST_ASSERT_EQUAL(total_events, count, + "count mismatch total_events=%d count=%d", + total_events, count); + return 0; +} + +static int +validate_queue_to_port_single_link(uint32_t index, uint8_t port, + struct rte_event *ev) +{ + RTE_SET_USED(index); + RTE_TEST_ASSERT_EQUAL(port, ev->queue_id, + "queue mismatch enq=%d deq =%d", + port, ev->queue_id); + return 0; +} + +/* + * Link queue x to port x and check correctness of link by checking + * queue_id == x on dequeue on the specific port x + */ +static int +test_queue_to_port_single_link(void) +{ + int i, nr_links, ret; + + uint32_t port_count; + + RTE_TEST_ASSERT_SUCCESS(rte_event_dev_attr_get(evdev, + RTE_EVENT_DEV_ATTR_PORT_COUNT, + &port_count), "Port count get failed"); + + /* Unlink all connections that created in eventdev_setup */ + for (i = 0; i < (int)port_count; i++) { + ret = rte_event_port_unlink(evdev, i, NULL, 0); + RTE_TEST_ASSERT(ret >= 0, + "Failed to unlink all queues port=%d", i); + } + + uint32_t queue_count; + + RTE_TEST_ASSERT_SUCCESS(rte_event_dev_attr_get(evdev, + RTE_EVENT_DEV_ATTR_QUEUE_COUNT, + &queue_count), "Queue count get failed"); + + nr_links = RTE_MIN(port_count, queue_count); + const unsigned int total_events = MAX_EVENTS / nr_links; + + /* Link queue x to port x and inject events to queue x through port x */ + for (i = 0; i < nr_links; i++) { + uint8_t queue = (uint8_t)i; + + ret = rte_event_port_link(evdev, i, &queue, NULL, 1); + RTE_TEST_ASSERT(ret == 1, "Failed to link queue to port %d", i); + + ret = inject_events( + 0x100 /*flow_id */, + RTE_EVENT_TYPE_CPU /* event_type */, + rte_rand() % 256 /* sub_event_type */, + rte_rand() % (RTE_SCHED_TYPE_PARALLEL + 1), + queue /* queue */, + i /* port */, + total_events /* events */); + if (ret) + return -1; + } + + /* Verify the events generated from correct queue */ + for (i = 0; i < nr_links; i++) { + ret = consume_events(i /* port */, total_events, + validate_queue_to_port_single_link); + if (ret) + return -1; + } + + return 0; +} + +static int +validate_queue_to_port_multi_link(uint32_t index, uint8_t port, + struct rte_event *ev) +{ + RTE_SET_USED(index); + RTE_TEST_ASSERT_EQUAL(port, (ev->queue_id & 0x1), + "queue mismatch enq=%d deq =%d", + port, ev->queue_id); + return 0; +} + +/* + * Link all even number of queues to port 0 and all odd number of queues to + * port 1 and verify the link connection on dequeue + */ +static int +test_queue_to_port_multi_link(void) +{ + int ret, port0_events = 0, port1_events = 0; + uint8_t queue, port; + uint32_t nr_queues = 0; + uint32_t nr_ports = 0; + + RTE_TEST_ASSERT_SUCCESS(rte_event_dev_attr_get(evdev, + RTE_EVENT_DEV_ATTR_QUEUE_COUNT, + &nr_queues), "Queue count get failed"); + + RTE_TEST_ASSERT_SUCCESS(rte_event_dev_attr_get(evdev, + RTE_EVENT_DEV_ATTR_QUEUE_COUNT, + &nr_queues), "Queue count get failed"); + RTE_TEST_ASSERT_SUCCESS(rte_event_dev_attr_get(evdev, + RTE_EVENT_DEV_ATTR_PORT_COUNT, + &nr_ports), "Port count get failed"); + + if (nr_ports < 2) { + dpaa2_evdev_dbg("%s: Not enough ports to test ports=%d", + __func__, nr_ports); + return 0; + } + + /* Unlink all connections that created in eventdev_setup */ + for (port = 0; port < nr_ports; port++) { + ret = rte_event_port_unlink(evdev, port, NULL, 0); + RTE_TEST_ASSERT(ret >= 0, "Failed to unlink all queues port=%d", + port); + } + + const unsigned int total_events = MAX_EVENTS / nr_queues; + + /* Link all even number of queues to port0 and odd numbers to port 1*/ + for (queue = 0; queue < nr_queues; queue++) { + port = queue & 0x1; + ret = rte_event_port_link(evdev, port, &queue, NULL, 1); + RTE_TEST_ASSERT(ret == 1, "Failed to link queue=%d to port=%d", + queue, port); + + ret = inject_events( + 0x100 /*flow_id */, + RTE_EVENT_TYPE_CPU /* event_type */, + rte_rand() % 256 /* sub_event_type */, + rte_rand() % (RTE_SCHED_TYPE_PARALLEL + 1), + queue /* queue */, + port /* port */, + total_events /* events */); + if (ret) + return -1; + + if (port == 0) + port0_events += total_events; + else + port1_events += total_events; + } + + ret = consume_events(0 /* port */, port0_events, + validate_queue_to_port_multi_link); + if (ret) + return -1; + ret = consume_events(1 /* port */, port1_events, + validate_queue_to_port_multi_link); + if (ret) + return -1; + + return 0; +} + +static void dpaa2_test_run(int (*setup)(void), void (*tdown)(void), + int (*test)(void), const char *name) +{ + if (setup() < 0) { + RTE_LOG(INFO, PMD, "Error setting up test %s", name); + unsupported++; + } else { + if (test() < 0) { + failed++; + RTE_LOG(INFO, PMD, "%s Failed\n", name); + } else { + passed++; + RTE_LOG(INFO, PMD, "%s Passed", name); + } + } + + total++; + tdown(); +} + +int +test_eventdev_dpaa2(void) +{ + testsuite_setup(); + + DPAA2_TEST_RUN(eventdev_setup, eventdev_teardown, + test_simple_enqdeq_atomic); + DPAA2_TEST_RUN(eventdev_setup, eventdev_teardown, + test_simple_enqdeq_parallel); + DPAA2_TEST_RUN(eventdev_setup, eventdev_teardown, + test_multi_queue_enq_single_port_deq); + DPAA2_TEST_RUN(eventdev_setup, eventdev_teardown, + test_dev_stop_flush); + DPAA2_TEST_RUN(eventdev_setup, eventdev_teardown, + test_multi_queue_enq_multi_port_deq); + DPAA2_TEST_RUN(eventdev_setup, eventdev_teardown, + test_queue_to_port_single_link); + DPAA2_TEST_RUN(eventdev_setup, eventdev_teardown, + test_queue_to_port_multi_link); + + DPAA2_EVENTDEV_INFO("Total tests : %d", total); + DPAA2_EVENTDEV_INFO("Passed : %d", passed); + DPAA2_EVENTDEV_INFO("Failed : %d", failed); + DPAA2_EVENTDEV_INFO("Not supported : %d", unsupported); + + testsuite_teardown(); + + if (failed) + return -1; + + return 0; +} diff --git a/drivers/event/dpaa2/meson.build b/drivers/event/dpaa2/meson.build index f7da7fad5..72f97d4c1 100644 --- a/drivers/event/dpaa2/meson.build +++ b/drivers/event/dpaa2/meson.build @@ -9,7 +9,8 @@ if not is_linux endif deps += ['bus_vdev', 'pmd_dpaa2', 'pmd_dpaa2_sec'] sources = files('dpaa2_hw_dpcon.c', - 'dpaa2_eventdev.c') + 'dpaa2_eventdev.c', + 'dpaa2_eventdev_selftest.c') allow_experimental_apis = true includes += include_directories('../../crypto/dpaa2_sec/') From patchwork Sat Sep 7 06:42:09 2019 Content-Type: text/plain; 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[92.243.14.124]) by mx.google.com with ESMTP id o26si4622045edr.329.2019.09.06.23.44.49; Fri, 06 Sep 2019 23:44:49 -0700 (PDT) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id CC4FA1F47F; Sat, 7 Sep 2019 08:44:17 +0200 (CEST) Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by dpdk.org (Postfix) with ESMTP id 95E041F278 for ; Sat, 7 Sep 2019 08:44:09 +0200 (CEST) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 5B7F7200683; Sat, 7 Sep 2019 08:44:09 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 8774720068E; Sat, 7 Sep 2019 08:44:07 +0200 (CEST) Received: from bf-netperf1.ap.freescale.net (bf-netperf1.ap.freescale.net [10.232.133.63]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 6061B4031E; Sat, 7 Sep 2019 14:44:02 +0800 (SGT) From: Hemant Agrawal To: dev@dpdk.org Cc: jerinj@marvell.com, Hemant Agrawal Date: Sat, 7 Sep 2019 12:12:09 +0530 Message-Id: <20190907064209.30686-6-hemant.agrawal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190907064209.30686-1-hemant.agrawal@nxp.com> References: <20190906103410.14996-1-hemant.agrawal@nxp.com> <20190907064209.30686-1-hemant.agrawal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH v2 5/5] test/event: enable dpaa2 self test X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Signed-off-by: Hemant Agrawal --- app/test/test_eventdev.c | 7 +++++++ 1 file changed, 7 insertions(+) -- 2.17.1 diff --git a/app/test/test_eventdev.c b/app/test/test_eventdev.c index 783140dfe..427dbbf77 100644 --- a/app/test/test_eventdev.c +++ b/app/test/test_eventdev.c @@ -1020,9 +1020,16 @@ test_eventdev_selftest_octeontx2(void) return test_eventdev_selftest_impl("otx2_eventdev", ""); } +static int +test_eventdev_selftest_dpaa2(void) +{ + return test_eventdev_selftest_impl("event_dpaa2", ""); +} + REGISTER_TEST_COMMAND(eventdev_common_autotest, test_eventdev_common); REGISTER_TEST_COMMAND(eventdev_selftest_sw, test_eventdev_selftest_sw); REGISTER_TEST_COMMAND(eventdev_selftest_octeontx, test_eventdev_selftest_octeontx); REGISTER_TEST_COMMAND(eventdev_selftest_octeontx2, test_eventdev_selftest_octeontx2); +REGISTER_TEST_COMMAND(eventdev_selftest_dpaa2, test_eventdev_selftest_dpaa2);