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[176.184.43.236]) by smtp.gmail.com with ESMTPSA id p21-20020a05600c359500b0040e3488f16dsm1679412wmq.12.2024.01.11.04.02.30 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 11 Jan 2024 04:02:32 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Weiwei Li , Alistair Francis , qemu-s390x@nongnu.org, Michael Tokarev , David Hildenbrand , Christian Borntraeger , qemu-riscv@nongnu.org, Palmer Dabbelt , Bin Meng , qemu-trivial@nongnu.org, Halil Pasic , Paolo Bonzini , Ilya Leoshkevich , Eduardo Habkost , Laurent Vivier , Liu Zhiwei , Eric Farman , Thomas Huth , Daniel Henrique Barboza , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH 1/5] accel: Rename accel_init_ops_interfaces() to include 'system' Date: Thu, 11 Jan 2024 13:02:17 +0100 Message-ID: <20240111120221.35072-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240111120221.35072-1-philmd@linaro.org> References: <20240111120221.35072-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org accel_init_ops_interfaces() is system specific, so rename it as accel_system_init_ops_interfaces() to ease navigating the code. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- accel/accel-system.h | 2 +- accel/accel-system.c | 2 +- accel/accel-target.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/accel/accel-system.h b/accel/accel-system.h index d41c62f21b..2d37c73c97 100644 --- a/accel/accel-system.h +++ b/accel/accel-system.h @@ -10,6 +10,6 @@ #ifndef ACCEL_SYSTEM_H #define ACCEL_SYSTEM_H -void accel_init_ops_interfaces(AccelClass *ac); +void accel_system_init_ops_interfaces(AccelClass *ac); #endif /* ACCEL_SYSTEM_H */ diff --git a/accel/accel-system.c b/accel/accel-system.c index fa8f43757c..f6c947dd82 100644 --- a/accel/accel-system.c +++ b/accel/accel-system.c @@ -62,7 +62,7 @@ void accel_setup_post(MachineState *ms) } /* initialize the arch-independent accel operation interfaces */ -void accel_init_ops_interfaces(AccelClass *ac) +void accel_system_init_ops_interfaces(AccelClass *ac) { const char *ac_name; char *ops_name; diff --git a/accel/accel-target.c b/accel/accel-target.c index 7e3cbde5df..08626c00c2 100644 --- a/accel/accel-target.c +++ b/accel/accel-target.c @@ -104,7 +104,7 @@ static void accel_init_cpu_interfaces(AccelClass *ac) void accel_init_interfaces(AccelClass *ac) { #ifndef CONFIG_USER_ONLY - accel_init_ops_interfaces(ac); + accel_system_init_ops_interfaces(ac); #endif /* !CONFIG_USER_ONLY */ accel_init_cpu_interfaces(ac); From patchwork Thu Jan 11 12:02:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 761842 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp2357739wrz; Thu, 11 Jan 2024 04:05:54 -0800 (PST) X-Google-Smtp-Source: AGHT+IE7fnIqIFqMeO8ptyh0uehF1UdMM9C7phAxJtu5fR6cPkmoQ/lMfZJxmKzwzkzVBOTydsxr X-Received: by 2002:a05:6830:921:b0:6db:fde5:2edb with SMTP id v33-20020a056830092100b006dbfde52edbmr1539211ott.74.1704974754399; Thu, 11 Jan 2024 04:05:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704974754; cv=none; d=google.com; s=arc-20160816; b=qSBwgfMK/RX2p85eWaYYPl8+d9VdpmmTRE4/mZYBXJT413WqtlynHhD0gXA3gJuCic FEgwjYfXs789pteaje9mAmvRRJWYiblqUwxy8FbSgodllXAIKrUY5yo0TY/nCnARYpMb E9IWxGTuwUicpmyDux2946SvmVgzBQp4APxyY/lShHi/32zm7fgxgvIKE7jWAIWCEHPJ Gve9orWqnSWprnrksLcCP719hqCJU1WxGF6rS59timK+142lRpLnkyKfCRBIrpCSnNcQ Ufmj3Ie5N5FUKplIwjiiZ+JW6b27qpI8QfRQds9B2SOsjhv6jUNNOjrAZ9UdzG+lOLtY le4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=kbCxYAXnaPA+cdBawT/EluO8Fm76t17YXM33Yu5GMIw=; fh=y6r03noUWfICwPfR8EsTiKAurGXRKk6addDWsOQRxKo=; b=tTZke3R2eYyXkYzq+PBbDn+I4gitNIKDXeBL8G9Rzetatr1TnCOsrG8Xu1MjvuVCsU 4GU7lU0FWc6KgqKIwHPKe1sL3zv2SX8FvNIJqf156shGsdbPp2zkL679caiqpWc4Fjfz 1LX6VeuoWjIMQICOcQds0UKUW9Q7ZlXCQ77k0epVFRs3kxO5wiUtDpqv840yNtc2Epxg k/6a40S39cNp8aRf4OEk49YeeGJtUs8Xn9jGLQQNG08r5PRnaUP5pSTz2CSAa9QG0t7P vxiBCNaTNbTQ/BBCvsFCJxSTLuloINwtUjdYZ64h7zIoX8G/ZrMC208NXCZo57RRL9Uv B6Hg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=b+SRBAOg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.43.236]) by smtp.gmail.com with ESMTPSA id e16-20020a5d65d0000000b003365951cef9sm1061169wrw.55.2024.01.11.04.02.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 11 Jan 2024 04:02:38 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Weiwei Li , Alistair Francis , qemu-s390x@nongnu.org, Michael Tokarev , David Hildenbrand , Christian Borntraeger , qemu-riscv@nongnu.org, Palmer Dabbelt , Bin Meng , qemu-trivial@nongnu.org, Halil Pasic , Paolo Bonzini , Ilya Leoshkevich , Eduardo Habkost , Laurent Vivier , Liu Zhiwei , Eric Farman , Thomas Huth , Daniel Henrique Barboza , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH 2/5] hw/core/cpu: Rename cpu_class_init() to include 'common' Date: Thu, 11 Jan 2024 13:02:18 +0100 Message-ID: <20240111120221.35072-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240111120221.35072-1-philmd@linaro.org> References: <20240111120221.35072-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org cpu_class_init() is common, so rename it as cpu_common_class_init() to ease navigating the code. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza --- hw/core/cpu-common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c index 3ccfe882e2..67db07741d 100644 --- a/hw/core/cpu-common.c +++ b/hw/core/cpu-common.c @@ -273,7 +273,7 @@ static int64_t cpu_common_get_arch_id(CPUState *cpu) return cpu->cpu_index; } -static void cpu_class_init(ObjectClass *klass, void *data) +static void cpu_common_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); ResettableClass *rc = RESETTABLE_CLASS(klass); @@ -304,7 +304,7 @@ static const TypeInfo cpu_type_info = { .instance_finalize = cpu_common_finalize, .abstract = true, .class_size = sizeof(CPUClass), - .class_init = cpu_class_init, + .class_init = cpu_common_class_init, }; static void cpu_register_types(void) From patchwork Thu Jan 11 12:02:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 761840 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp2357372wrz; Thu, 11 Jan 2024 04:05:09 -0800 (PST) X-Google-Smtp-Source: AGHT+IH7W9TXbalfBD85DyRZpyWXMUSxxwX+saxpY3ueT1b2w5TrhTgzV1aaNGz9Qf2sH2fedtIL X-Received: by 2002:ac8:5c0e:0:b0:429:bbe6:450b with SMTP id i14-20020ac85c0e000000b00429bbe6450bmr582303qti.32.1704974709389; Thu, 11 Jan 2024 04:05:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704974709; cv=none; d=google.com; s=arc-20160816; b=rVkxVPbzuP/o7SjEkEZozfpezTrB3qmTGex8tFT7CeHKfXG4kl792ec7bVB1bc0Vha 0p0Q9jJjHsLabTnSPWm6VJv7cjjygRVwjaXa5Rc6zMFkcz0TurnT3w2V5IM40NQaSrU5 X/EN7QGtLz050fqvf78ph/wR0ZwB5N0g3WEZJ87F8iwHAD/+h79KIQhUkEfSKbV4OBzf 7G5e3orCTgrvmxAcHIsiwjig2zemcaerA8fiOyOdMYUA33rKA434rT+xS06zDDrkOE50 MnhqNRdBPsAVfOYN+uq5CL1LzWa2i2nEPKyoJaY7fdsbapm8QcjiDYuTJAmmx1mzW5Oc EDpA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=9oDADZ7OQkBJhilNI7y3OkwoRjc/uWOL4l0/5ZjzT+c=; fh=y6r03noUWfICwPfR8EsTiKAurGXRKk6addDWsOQRxKo=; b=Wvqh/Z/PnqqmJdWgr2WAwq1Tra0DCwSnx9mhMhw673PTkS/nsggHqrkE/pkPwFiv/f 9sh2VkxN08xfrKjjIa8WvwAF676/Ec7qRjDfqDVzE8ogtVpMB0TroC2wNCqP8tv8Fxj1 9NY/UMlvilsJlz88vPqRW8Q7a++6J5+sk5os2bi3yRrs9/Ep879YT92gnadV37R6l/z5 RAVUy76d8J8LJK75OA5cfuYw9LK3/2eWl9+4kVqTorZx4aU+2gKWfT09HFks8He0KeFg a0zRKXmr3Daj8FNGlxGdB0jgj+d7VqvNfJcqa3a7qSW11NhQbOWUvQMXLK3jCFLeRy60 Z+MQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hrWEwSN3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.43.236]) by smtp.gmail.com with ESMTPSA id t6-20020a05600c198600b0040e48abec33sm5550904wmq.45.2024.01.11.04.02.43 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 11 Jan 2024 04:02:45 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Weiwei Li , Alistair Francis , qemu-s390x@nongnu.org, Michael Tokarev , David Hildenbrand , Christian Borntraeger , qemu-riscv@nongnu.org, Palmer Dabbelt , Bin Meng , qemu-trivial@nongnu.org, Halil Pasic , Paolo Bonzini , Ilya Leoshkevich , Eduardo Habkost , Laurent Vivier , Liu Zhiwei , Eric Farman , Thomas Huth , Daniel Henrique Barboza , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH 3/5] hw/s390x: Rename cpu_class_init() to include 'sclp' Date: Thu, 11 Jan 2024 13:02:19 +0100 Message-ID: <20240111120221.35072-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240111120221.35072-1-philmd@linaro.org> References: <20240111120221.35072-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org cpu_class_init() is specific to s390x SCLP, so rename it as sclp_cpu_class_init() (as other names in this file) to ease navigating the code. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Eric Farman Reviewed-by: Thomas Huth --- hw/s390x/sclpcpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/s390x/sclpcpu.c b/hw/s390x/sclpcpu.c index f2b1a4b037..fa79891f5a 100644 --- a/hw/s390x/sclpcpu.c +++ b/hw/s390x/sclpcpu.c @@ -73,7 +73,7 @@ static int read_event_data(SCLPEvent *event, EventBufferHeader *evt_buf_hdr, return 1; } -static void cpu_class_init(ObjectClass *oc, void *data) +static void sclp_cpu_class_init(ObjectClass *oc, void *data) { SCLPEventClass *k = SCLP_EVENT_CLASS(oc); DeviceClass *dc = DEVICE_CLASS(oc); @@ -94,7 +94,7 @@ static const TypeInfo sclp_cpu_info = { .name = TYPE_SCLP_CPU_HOTPLUG, .parent = TYPE_SCLP_EVENT, .instance_size = sizeof(SCLPEvent), - .class_init = cpu_class_init, + .class_init = sclp_cpu_class_init, .class_size = sizeof(SCLPEventClass), }; From patchwork Thu Jan 11 12:02:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 761839 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp2357122wrz; Thu, 11 Jan 2024 04:04:44 -0800 (PST) X-Google-Smtp-Source: AGHT+IGwS9U/lE2tnLm2VxqJ8NBNw2P9jz/8voSWS0xg88w51v35yuXsvydqw8+UcX6bKJXKGLhk X-Received: by 2002:a05:6214:f2b:b0:680:cc64:5e6b with SMTP id iw11-20020a0562140f2b00b00680cc645e6bmr1233864qvb.3.1704974683807; Thu, 11 Jan 2024 04:04:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704974683; cv=none; d=google.com; s=arc-20160816; b=LSquC75vLv7XJbFAnXJ4rGM4/d8tUXpXz6zxaK10mXUFqBABDOuBm/c2dVGYQPBcDV ykpuy/CnGMB8jI9ilnYPECkD7WfJVYjPC0CiXq8f8pSlDiA6ws4vRYDXrlQfRyFaZ+Z8 ctnTmX1BEYQKmXfqNllFlEP4jsx+gog/+6HnavsCdG8ZLVkTebuV+yZTKEskIe+UC1La YeL4qbIrspREOTQxOgVm6cyuy/vaQuwxNtxi7csZB3YtIZtCbmYOaAzpVxwQzhyvGZbq 40++tj/XowlJC92EWs+xzCZfTwuZsVJ4OGGODq7AsHWNMKqiyJIbg7KnVUcMUjo71Uut KeGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=pZ+Rk66u59cimifcoy3fRichLBCz2Ca8YjXNADwDWao=; fh=y6r03noUWfICwPfR8EsTiKAurGXRKk6addDWsOQRxKo=; b=D+sMOuzYwO7RlrodIDb/PHkulTNI4Cv9x4tItuITcvCNHT+UABHy8p8vvmaaZAJjBR nnhGRICKvZ3fz/YwEnz9BYlPANDrgnC97vIQaBj0lbovQJTH49NlTw+JWBfLgfQaYWMb TAjPMXQsgrRbajUy+gl/+IFwxrMg3sgDBaaVKFU8D9gTvQd4UUQRVXe/B2UQmzHSxALq YNf1d93ZfdFtLPBZTU6I2fwgS+nPOSfdpqos8qEGJN/Sayek3+JDmKOnBRQ76bZ4FILQ PXwXXcV81oRBUlcBhd7gG3jfABBhJlPlOLi0QSPDV2Uq9JtUCKO4xG+udy+7lKefAouV HK8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UJSH7zge; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.43.236]) by smtp.gmail.com with ESMTPSA id d15-20020adf9c8f000000b00336c43b366fsm1082920wre.12.2024.01.11.04.02.50 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 11 Jan 2024 04:02:51 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Weiwei Li , Alistair Francis , qemu-s390x@nongnu.org, Michael Tokarev , David Hildenbrand , Christian Borntraeger , qemu-riscv@nongnu.org, Palmer Dabbelt , Bin Meng , qemu-trivial@nongnu.org, Halil Pasic , Paolo Bonzini , Ilya Leoshkevich , Eduardo Habkost , Laurent Vivier , Liu Zhiwei , Eric Farman , Thomas Huth , Daniel Henrique Barboza , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH 4/5] target/i386: Rename tcg_cpu_FOO() to include 'x86' Date: Thu, 11 Jan 2024 13:02:20 +0100 Message-ID: <20240111120221.35072-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240111120221.35072-1-philmd@linaro.org> References: <20240111120221.35072-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The tcg_cpu_FOO() names are x86 specific, so rename them as x86_tcg_cpu_FOO() (as other names in this file) to ease navigating the code. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Michael Tokarev --- target/i386/tcg/tcg-cpu.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 6e881e9e27..e56489caea 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -114,18 +114,18 @@ static const struct TCGCPUOps x86_tcg_ops = { #endif /* !CONFIG_USER_ONLY */ }; -static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) +static void x86_tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) { /* for x86, all cpus use the same set of operations */ cc->tcg_ops = &x86_tcg_ops; } -static void tcg_cpu_class_init(CPUClass *cc) +static void x86_tcg_cpu_class_init(CPUClass *cc) { - cc->init_accel_cpu = tcg_cpu_init_ops; + cc->init_accel_cpu = x86_tcg_cpu_init_ops; } -static void tcg_cpu_xsave_init(void) +static void x86_tcg_cpu_xsave_init(void) { #define XO(bit, field) \ x86_ext_save_areas[bit].offset = offsetof(X86XSaveArea, field); @@ -147,25 +147,25 @@ static void tcg_cpu_xsave_init(void) * TCG-specific defaults that override cpudef models when using TCG. * Only for builtin_x86_defs models initialized with x86_register_cpudef_types. */ -static PropValue tcg_default_props[] = { +static PropValue x86_tcg_default_props[] = { { "vme", "off" }, { NULL, NULL }, }; -static void tcg_cpu_instance_init(CPUState *cs) +static void x86_tcg_cpu_instance_init(CPUState *cs) { X86CPU *cpu = X86_CPU(cs); X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); if (xcc->model) { /* Special cases not set in the X86CPUDefinition structs: */ - x86_cpu_apply_props(cpu, tcg_default_props); + x86_cpu_apply_props(cpu, x86_tcg_default_props); } - tcg_cpu_xsave_init(); + x86_tcg_cpu_xsave_init(); } -static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data) +static void x86_tcg_cpu_accel_class_init(ObjectClass *oc, void *data) { AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); @@ -173,18 +173,18 @@ static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data) acc->cpu_target_realize = tcg_cpu_realizefn; #endif /* CONFIG_USER_ONLY */ - acc->cpu_class_init = tcg_cpu_class_init; - acc->cpu_instance_init = tcg_cpu_instance_init; + acc->cpu_class_init = x86_tcg_cpu_class_init; + acc->cpu_instance_init = x86_tcg_cpu_instance_init; } -static const TypeInfo tcg_cpu_accel_type_info = { +static const TypeInfo x86_tcg_cpu_accel_type_info = { .name = ACCEL_CPU_NAME("tcg"), .parent = TYPE_ACCEL_CPU, - .class_init = tcg_cpu_accel_class_init, + .class_init = x86_tcg_cpu_accel_class_init, .abstract = true, }; -static void tcg_cpu_accel_register_types(void) +static void x86_tcg_cpu_accel_register_types(void) { - type_register_static(&tcg_cpu_accel_type_info); + type_register_static(&x86_tcg_cpu_accel_type_info); } -type_init(tcg_cpu_accel_register_types); +type_init(x86_tcg_cpu_accel_register_types); From patchwork Thu Jan 11 12:02:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 761838 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp2357118wrz; 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[176.184.43.236]) by smtp.gmail.com with ESMTPSA id z11-20020a5d44cb000000b00336898daceasm1048278wrr.96.2024.01.11.04.02.56 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 11 Jan 2024 04:02:58 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Weiwei Li , Alistair Francis , qemu-s390x@nongnu.org, Michael Tokarev , David Hildenbrand , Christian Borntraeger , qemu-riscv@nongnu.org, Palmer Dabbelt , Bin Meng , qemu-trivial@nongnu.org, Halil Pasic , Paolo Bonzini , Ilya Leoshkevich , Eduardo Habkost , Laurent Vivier , Liu Zhiwei , Eric Farman , Thomas Huth , Daniel Henrique Barboza , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= Subject: [PATCH 5/5] target/riscv: Rename tcg_cpu_FOO() to include 'riscv' Date: Thu, 11 Jan 2024 13:02:21 +0100 Message-ID: <20240111120221.35072-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240111120221.35072-1-philmd@linaro.org> References: <20240111120221.35072-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The tcg_cpu_FOO() names are riscv specific, so rename them as riscv_tcg_cpu_FOO() (as other names in this file) to ease navigating the code. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis --- target/riscv/tcg/tcg-cpu.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 14133ff665..994ca1cdf9 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -929,7 +929,7 @@ static bool riscv_cpu_is_vendor(Object *cpu_obj) * -> cpu_exec_realizefn() * -> tcg_cpu_realize() (via accel_cpu_common_realize()) */ -static bool tcg_cpu_realize(CPUState *cs, Error **errp) +static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) { RISCVCPU *cpu = RISCV_CPU(cs); Error *local_err = NULL; @@ -1372,7 +1372,7 @@ static bool riscv_cpu_has_max_extensions(Object *cpu_obj) return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL; } -static void tcg_cpu_instance_init(CPUState *cs) +static void riscv_tcg_cpu_instance_init(CPUState *cs) { RISCVCPU *cpu = RISCV_CPU(cs); Object *obj = OBJECT(cpu); @@ -1386,7 +1386,7 @@ static void tcg_cpu_instance_init(CPUState *cs) } } -static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) +static void riscv_tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) { /* * All cpus use the same set of operations. @@ -1394,30 +1394,30 @@ static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) cc->tcg_ops = &riscv_tcg_ops; } -static void tcg_cpu_class_init(CPUClass *cc) +static void riscv_tcg_cpu_class_init(CPUClass *cc) { - cc->init_accel_cpu = tcg_cpu_init_ops; + cc->init_accel_cpu = riscv_tcg_cpu_init_ops; } -static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data) +static void riscv_tcg_cpu_accel_class_init(ObjectClass *oc, void *data) { AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); - acc->cpu_class_init = tcg_cpu_class_init; - acc->cpu_instance_init = tcg_cpu_instance_init; - acc->cpu_target_realize = tcg_cpu_realize; + acc->cpu_class_init = riscv_tcg_cpu_class_init; + acc->cpu_instance_init = riscv_tcg_cpu_instance_init; + acc->cpu_target_realize = riscv_tcg_cpu_realize; } -static const TypeInfo tcg_cpu_accel_type_info = { +static const TypeInfo riscv_tcg_cpu_accel_type_info = { .name = ACCEL_CPU_NAME("tcg"), .parent = TYPE_ACCEL_CPU, - .class_init = tcg_cpu_accel_class_init, + .class_init = riscv_tcg_cpu_accel_class_init, .abstract = true, }; -static void tcg_cpu_accel_register_types(void) +static void riscv_tcg_cpu_accel_register_types(void) { - type_register_static(&tcg_cpu_accel_type_info); + type_register_static(&riscv_tcg_cpu_accel_type_info); } -type_init(tcg_cpu_accel_register_types); +type_init(riscv_tcg_cpu_accel_register_types);