From patchwork Thu Jan 11 03:08:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 761778 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp2198270wrz; Wed, 10 Jan 2024 19:09:55 -0800 (PST) X-Google-Smtp-Source: AGHT+IEsk07D+wZEpCazPFAZU5rWQqi3pejDzj2ujy/QvCdWAsXH57c6OG1VBwiUWzmRqiYqs2mR X-Received: by 2002:a05:600c:154e:b0:40e:4919:e2f0 with SMTP id f14-20020a05600c154e00b0040e4919e2f0mr119971wmg.232.1704942595302; Wed, 10 Jan 2024 19:09:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704942595; cv=none; d=google.com; s=arc-20160816; b=NfRoG7Qxukeu2ftoDocBjhf17L4dP5hgcfMHD2fTkGxT5dSKlc/d4fF3NS5/Ju0GOo MRMbGM03v+VgM/wabpmoFojXbx3S36d/+/vfQZQUNkwT8o0LPEqPG8yLnrdUf9fWZHHE TDa+Ja2VumGqzt10OuvybDT36Qh5cDVUw/+70ruzr7YIGnKw90BrDls+k4vv8Jo2mySJ uRTmTqeKxyEYqazss880SBGwlwaRI2duiC1WkSArKmav/+NhC8klRWttSXCF4poqlWmH fmiJFbvbrvb3tqrg4CdmTrTg3ZcTIK+FROc1QkDBYgYtxyofiqSDfbESB0FXfMli5FMB llCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=T7GKXWpO2ptHHWwGN7NpFJyklyGWVbxuX5E44M+C3tk=; fh=PzVE172kMYfD8vsZrdrkQaWk4G6SF+wa//e7xu1cQV0=; b=enjMi3Nalj3oCAo9ecZzi+vMU304/uvDpE0wtZG1JDqAK/mppHEwOVhbn5W1Fr/kqk Rhwrd0bYmA9Wv+/vptSd9401hMqwmA0xxjMgCc66P4RM0PB9uoRCwAklhLcml5o4ksXr 4WRbKq5QWfb19HgpL2bus9ISBmBTHb4GxuqPiib6M4NQDwUWunt3Yk2KxkX0+w/cPQje QjynTHeKSz9hwkjwBtBuoeJ0MkDeEhFosBR9ktRS9cicfWVTueePjuOCY48WA33ds/9s gkPCWFMvISFli0RuGKZ0mjlukD5FMXNjpvsXuqZD1NBmO0CfsarB+vw1rkyoQ1Cm7b81 Sq4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tVT9q1rr; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id r20-20020adfb1d4000000b00337404f28a8si5806wra.613.2024.01.10.19.09.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 19:09:55 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tVT9q1rr; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id D612A87B05; Thu, 11 Jan 2024 04:09:22 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="tVT9q1rr"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id EC80987A36; Thu, 11 Jan 2024 04:09:19 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-oa1-x35.google.com (mail-oa1-x35.google.com [IPv6:2001:4860:4864:20::35]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id B027D87776 for ; Thu, 11 Jan 2024 04:09:13 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=semen.protsenko@linaro.org Received: by mail-oa1-x35.google.com with SMTP id 586e51a60fabf-203fed05a31so3078069fac.0 for ; Wed, 10 Jan 2024 19:09:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704942552; x=1705547352; darn=lists.denx.de; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=T7GKXWpO2ptHHWwGN7NpFJyklyGWVbxuX5E44M+C3tk=; b=tVT9q1rrijFQS8QhpGF/42t7QrvV0SjlJ9DztpAMs5SUbp4z7Noy1Ay1JNm2z1Ekan +aRizENViFlxKJ5U9pXNu+BVA46UPe6nxXMYnHI/gO8iVKWRy3l5HfHD3u2TKYUAJtlk PJ93USHza0o4gSxVfxeKxGgKusstqvmkRuzD8dI2R6NmP5aXZscIFwN7D2iazNca6dPO Ru1nTRBoymDUyJjB9+9rLkuEDRMqsQ8cJZWRZaji5ARCnCIsO+gOZk7H3Y2FlayaDcKl Cb4GDY+aU5MyQhHC2UUWdzkXvhCIkVePfJ1+5YWAJPexHduvfK+n4zsszEwfkGg13v8i 4Ctg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704942552; x=1705547352; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T7GKXWpO2ptHHWwGN7NpFJyklyGWVbxuX5E44M+C3tk=; b=sCdejecZGz2dmFkOoCmAXgijru3hqA0VrfA83KtXO1/Lpk6TWvbqs/fp4AtRbE0Ys+ or+0nCiWnZXJcUZZeXhROeAzq6rW6tzVPMQ22FgiEOEmw0g4BQfiWgy3JMaK123aTZyY M2gxmPg7qIXi1Szr7aGH5Dt0Gfvsj4C1GuFlqa2Y3eKo05rDAXjUbDX9BDvtbJ908LpE UOjUTWxg+nduCM1fIogYTmo1z2QQHZG0JY3yLGS6HS5KuqOB/Jj79FIte7gL/jbIM5d4 FvkaivDVXBwLQ8rqDRlzab54kDqnGOvR7Yll93f8+poJkB8dAVsHALXQwiI4E0YY6UQP jcSA== X-Gm-Message-State: AOJu0YxaTThXyg3B1zoSLjtZaYZtZCrzF+s0D98shosSK/kHZjJi6mos rtwwVbYJaJBmjdKIxPM0IDnOCHupXKwnRQ== X-Received: by 2002:a05:6870:5e51:b0:206:9b25:4abb with SMTP id ne17-20020a0568705e5100b002069b254abbmr119539oac.76.1704942552262; Wed, 10 Jan 2024 19:09:12 -0800 (PST) Received: from localhost ([136.62.192.75]) by smtp.gmail.com with ESMTPSA id qw23-20020a0568706f1700b002043b415eaasm8061oab.29.2024.01.10.19.09.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 19:09:11 -0800 (PST) From: Sam Protsenko To: Minkyu Kang , Tom Rini , Lukasz Majewski , Sean Anderson Cc: Simon Glass , Chanho Park , Heinrich Schuchardt , u-boot@lists.denx.de Subject: [PATCH v2 01/13] dt-bindings: soc: samsung: Add Exynos USI Date: Wed, 10 Jan 2024 21:08:57 -0600 Message-Id: <20240111030909.27373-2-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240111030909.27373-1-semen.protsenko@linaro.org> References: <20240111030909.27373-1-semen.protsenko@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add USI bindings documentation and header file. Those are taken from Linux kernel [1,2], but the documentation was reworked a bit to only describe the compatibles that will be supported in U-Boot soon. [1] Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml [2] include/dt-bindings/soc/samsung,exynos-usi.h Signed-off-by: Sam Protsenko --- Changes in v2: - (none) .../soc/samsung/exynos-usi.yaml | 162 ++++++++++++++++++ include/dt-bindings/soc/samsung,exynos-usi.h | 17 ++ 2 files changed, 179 insertions(+) create mode 100644 doc/device-tree-bindings/soc/samsung/exynos-usi.yaml create mode 100644 include/dt-bindings/soc/samsung,exynos-usi.h diff --git a/doc/device-tree-bindings/soc/samsung/exynos-usi.yaml b/doc/device-tree-bindings/soc/samsung/exynos-usi.yaml new file mode 100644 index 000000000000..8e6423f11568 --- /dev/null +++ b/doc/device-tree-bindings/soc/samsung/exynos-usi.yaml @@ -0,0 +1,162 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/samsung/exynos-usi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung's Exynos USI (Universal Serial Interface) + +maintainers: + - Sam Protsenko + +description: | + USI IP-core provides selectable serial protocol (UART, SPI or High-Speed I2C). + USI shares almost all internal circuits within each protocol, so only one + protocol can be chosen at a time. USI is modeled as a node with zero or more + child nodes, each representing a serial sub-node device. The mode setting + selects which particular function will be used. + +properties: + $nodename: + pattern: "^usi@[0-9a-f]+$" + + compatible: + enum: + - samsung,exynos850-usi + + reg: true + + clocks: true + + clock-names: true + + ranges: true + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + samsung,sysreg: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to System Register syscon node + - description: offset of SW_CONF register for this USI controller + description: + Should be phandle/offset pair. The phandle to System Register syscon node + (for the same domain where this USI controller resides) and the offset + of SW_CONF register for this USI controller. + + samsung,mode: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Selects USI function (which serial protocol to use). Refer to + for valid USI mode values. + + samsung,clkreq-on: + type: boolean + description: + Enable this property if underlying protocol requires the clock to be + continuously provided without automatic gating. As suggested by SoC + manual, it should be set in case of SPI/I2C slave, UART Rx and I2C + multi-master mode. Usually this property is needed if USI mode is set + to "UART". + + This property is optional. + +patternProperties: + "^i2c@[0-9a-f]+$": + $ref: /schemas/i2c/i2c-exynos5.yaml + description: Child node describing underlying I2C + + "^serial@[0-9a-f]+$": + $ref: /schemas/serial/samsung_uart.yaml + description: Child node describing underlying UART/serial + + "^spi@[0-9a-f]+$": + $ref: /schemas/spi/samsung,spi.yaml + description: Child node describing underlying SPI + +required: + - compatible + - ranges + - "#address-cells" + - "#size-cells" + - samsung,sysreg + - samsung,mode + +if: + properties: + compatible: + contains: + enum: + - samsung,exynos850-usi + +then: + properties: + reg: + maxItems: 1 + + clocks: + items: + - description: Bus (APB) clock + - description: Operating clock for UART/SPI/I2C protocol + + clock-names: + items: + - const: pclk + - const: ipclk + + required: + - reg + - clocks + - clock-names + +else: + properties: + reg: false + clocks: false + clock-names: false + samsung,clkreq-on: false + +additionalProperties: false + +examples: + - | + #include + #include + + usi0: usi@138200c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x138200c0 0x20>; + samsung,sysreg = <&sysreg_peri 0x1010>; + samsung,mode = ; + samsung,clkreq-on; /* needed for UART mode */ + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peri 32>, <&cmu_peri 31>; + clock-names = "pclk", "ipclk"; + + serial_0: serial@13820000 { + compatible = "samsung,exynos850-uart"; + reg = <0x13820000 0xc0>; + interrupts = ; + clocks = <&cmu_peri 32>, <&cmu_peri 31>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + hsi2c_0: i2c@13820000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x13820000 0xc0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_peri 31>, <&cmu_peri 32>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + }; diff --git a/include/dt-bindings/soc/samsung,exynos-usi.h b/include/dt-bindings/soc/samsung,exynos-usi.h new file mode 100644 index 000000000000..a01af169d249 --- /dev/null +++ b/include/dt-bindings/soc/samsung,exynos-usi.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021 Linaro Ltd. + * Author: Sam Protsenko + * + * Device Tree bindings for Samsung Exynos USI (Universal Serial Interface). + */ + +#ifndef __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H +#define __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H + +#define USI_V2_NONE 0 +#define USI_V2_UART 1 +#define USI_V2_SPI 2 +#define USI_V2_I2C 3 + +#endif /* __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H */ From patchwork Thu Jan 11 03:08:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 761777 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp2198227wrz; Wed, 10 Jan 2024 19:09:44 -0800 (PST) X-Google-Smtp-Source: AGHT+IE+n7nNgHgk075j12UzhGWKJ+Vp/v3CttdygpSpZcJHcr6T5YskMhlLPSHmg/nR/Ae5+2Bi X-Received: by 2002:a05:600c:3594:b0:40d:88c6:b9b with SMTP id p20-20020a05600c359400b0040d88c60b9bmr165250wmq.123.1704942584133; Wed, 10 Jan 2024 19:09:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704942584; cv=none; d=google.com; s=arc-20160816; b=MKuk8orGUpA1InQa7k1d7IK1dmyZFGhSpfKzuAB7JA354pXYAZnmz2Mu69qldSsZ07 fCTv6cDy42l7+Nda9lO5OdkOObr4jnbTBjbVH8eez1pYvv646DUvmF9/iyqouG9SsYdU 8vUh7oQPyqVGKOk4zEcW8Fn6oIZoHtmk5sM731Rf/cKxBxiRn2o8dBA+IIxf0H8587c/ N+Hu1lZY+vW/E8kIPRG/0WTCHVFsOBS1MYnMwrwXcQFdnAQddvRtZTd2GyJZH9T0/FyP iF09r4lJ8SfzmJCTHZHlT0//XnnuBSZyuKnxRpwmDv/ki60s5TlU8OPTsppmnNeJkHE5 K0Kg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=uH7lC7fYO/o/++oC1FKh4VtdbRytVuz40e1rB1r1WA8=; fh=PzVE172kMYfD8vsZrdrkQaWk4G6SF+wa//e7xu1cQV0=; b=NbbWVxATzI0eCJVY2m8AaVxC8pqQEXVfSbhEgG1XMQp3+VHe4sxP99GuUlnao5vNJd CEpB68p+leh3vNLnBHFPIWmADHK0uy1UvpBDKWDqZMxYaRE/nnbjE0nanC7KHUviDtUa 2DfPQ9IlKzPK2EVkQVhLGwcZBlOTfsByl2A6dHWfxC+WUtyi0p5apwYSkfJB8Yh4UHq7 LWFr1Lh/wVB8kzJXdYnxwpQfGDgcPpp4fGoMpMkELql1rtt/0YBfqr3s0dCvMPUal/qZ 9orKVnIywsyeeCO8GATz3U+bwPBmwNXDY61q6AxRF9l9xG26dF/HhMGybXp7Rn4j2E18 0X2g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="WJNZ38h/"; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id cp18-20020a056000401200b003367c51109esi3335wrb.958.2024.01.10.19.09.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 19:09:44 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="WJNZ38h/"; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 416E487AE8; Thu, 11 Jan 2024 04:09:22 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="WJNZ38h/"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 175828309D; Thu, 11 Jan 2024 04:09:20 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mail-oa1-x36.google.com (mail-oa1-x36.google.com [IPv6:2001:4860:4864:20::36]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id A25F487A4B for ; Thu, 11 Jan 2024 04:09:14 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=semen.protsenko@linaro.org Received: by mail-oa1-x36.google.com with SMTP id 586e51a60fabf-2041e117abaso2399882fac.0 for ; Wed, 10 Jan 2024 19:09:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704942553; x=1705547353; darn=lists.denx.de; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uH7lC7fYO/o/++oC1FKh4VtdbRytVuz40e1rB1r1WA8=; b=WJNZ38h/TwdK1hixamLq23bwHGBdRQO9U10+UuZlEI/ofJ3FbHJwnidd61p2yHs8dp rV4cmmhca1xYLWYfGVj5kpENHce3BoJuTlGOf9d8B0qFdV0Ou+galUCCJCe670S28ahA ETwIvOEtmNK3PpJeqq1QIc268OL86H4HghhF7xbG4vm2Fhz25w6eaK3mZ7MzUwX9vWLR LaHsqIcGVKlSdb62V4mW4gDCIeSVHB7BtvfBO1UnvzGNOSbzQuT2CAT8x4CRTpezaWlz gVnSBZqYQEJW3CyIHFStbV4PtSB3212ym07jYFWsaNFUPpmO4Aq7XURVmnkdBSd1wCf7 EM9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704942553; x=1705547353; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uH7lC7fYO/o/++oC1FKh4VtdbRytVuz40e1rB1r1WA8=; b=Do4hXXat990rQpFOu/vIKw8kv3iJOC9BPDW4BitMD3Q5XAfK1EVFgqCo3Kq3ymflx4 phT/v33xYEdk2VGKmkyBLWhgwCyiCJPHVh3keLEG+WEZkxRD7+29B2GOWI3DuemH8jl1 wNCkMzOGOVckucI5+NRyBYbiVnRkf/QRV7ctYGmM3OxhcUeAx1bzLKqzTjg/UIU0jVBI IMvEY3MydOL9ENsMmDJfUZXLl2mAlI51+dPPu2rU4Y/jd855f42lXom3EsuytvSyC4kn 5bMb4/M9vHZwHAHEqB4/imS3HxxxAO8CJwyHkCxjLebGwtvqcAZRjco1OBAVWFpE2q9P DyhA== X-Gm-Message-State: AOJu0YzKm3RhqUq0giJs8RfnFb1kfcGyzCP+5mYglAIyrdLdMWwCJTfF g/c++0IL85bkrGExeHqICHqAkLNqrEVtHQ== X-Received: by 2002:a05:6871:290:b0:204:1304:7df7 with SMTP id i16-20020a056871029000b0020413047df7mr603822oae.67.1704942553242; Wed, 10 Jan 2024 19:09:13 -0800 (PST) Received: from localhost ([136.62.192.75]) by smtp.gmail.com with ESMTPSA id pk3-20020a0568704c0300b00206892f8a80sm4623oab.48.2024.01.10.19.09.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 19:09:12 -0800 (PST) From: Sam Protsenko To: Minkyu Kang , Tom Rini , Lukasz Majewski , Sean Anderson Cc: Simon Glass , Chanho Park , Heinrich Schuchardt , u-boot@lists.denx.de Subject: [PATCH v2 02/13] dt-bindings: soc: samsung: Add Exynos PMU Date: Wed, 10 Jan 2024 21:08:58 -0600 Message-Id: <20240111030909.27373-3-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240111030909.27373-1-semen.protsenko@linaro.org> References: <20240111030909.27373-1-semen.protsenko@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add bindings documentation for Exynos PMU hardware block. It was taken from Linux kernel [1], but minimized and modified to reflect features that will be actually supported in U-Boot soon. For example, the "samsung,uart-debug-1" property is not available in Linux kernel bindings and only present in U-Boot. [1] Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml Signed-off-by: Sam Protsenko --- Changes in v2: - (none) .../soc/samsung/exynos-pmu.yaml | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 doc/device-tree-bindings/soc/samsung/exynos-pmu.yaml diff --git a/doc/device-tree-bindings/soc/samsung/exynos-pmu.yaml b/doc/device-tree-bindings/soc/samsung/exynos-pmu.yaml new file mode 100644 index 000000000000..c3e95c33b01d --- /dev/null +++ b/doc/device-tree-bindings/soc/samsung/exynos-pmu.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/samsung/exynos-pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos SoC series Power Management Unit (PMU) + +maintainers: + - Sam Protsenko + +description: |+ + PMU block controls the power and operation states of Exynos SoC. It contains + registers for changing the state of next features:: + + - Local power control. Exynos SoCs have various power domains, and it's + possible to turn them on and off independently, using corresponding + registers in PMU block + - System-level power control. That allows putting the system into power-down + modes (sleep) by turning off the power for most of the domains + - Miscellaneous PMU related features + +# Custom select to avoid matching all nodes with 'syscon' +select: + properties: + compatible: + contains: + enum: + - samsung,exynos850-pmu + required: + - compatible + +properties: + compatible: + oneOf: + - items: + - enum: + - samsung,exynos850-pmu + - const: syscon + + reg: + maxItems: 1 + + samsung,uart-debug-1: + type: boolean + description: + Enable this property if AP UART lines (Application Processor UART) must be + connected to UART_DEBUG_1 path in PMU block. That's usually needed when + the serial console is provided by uart1_pins. If this property is not + specified, the default behavior will be used (AP UART lines connected to + UART_DEBUG_0 path, which usually means uart0_pins are used for the serial + console). + + syscon-poweroff: + $ref: /schemas/power/reset/syscon-poweroff.yaml# + type: object + description: + Node for power off method + + syscon-reboot: + $ref: /schemas/power/reset/syscon-reboot.yaml# + type: object + description: + Node for reboot method + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pmu_system_controller: system-controller@11860000 { + compatible = "samsung,exynos850-pmu", "syscon"; + reg = <0x11860000 0x10000>; + + reboot: syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pmu_system_controller>; + offset = <0x3a00>; /* SYSTEM_CONFIGURATION */ + mask = <0x2>; /* SWRESET_SYSTEM */ + value = <0x2>; /* reset value */ + }; + }; From patchwork Thu Jan 11 03:08:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 761779 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp2198341wrz; Wed, 10 Jan 2024 19:10:07 -0800 (PST) X-Google-Smtp-Source: AGHT+IGDHYoXmX0yCko0uP7GjluQiosbpShjEYbNcn2oOICYDIlShTCve3rCQ6XN0+oTegGh/z6/ X-Received: by 2002:a5d:4f85:0:b0:337:49d6:d487 with SMTP id d5-20020a5d4f85000000b0033749d6d487mr221016wru.29.1704942607481; Wed, 10 Jan 2024 19:10:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704942607; cv=none; d=google.com; s=arc-20160816; b=wEW1ojx4Zl5FM+yAHSi64AYOT3+dxPf/gAZgvvLIdX0YIJ9ykkvTQEU5U8x6zQtqnL ZV3gcxmMb/rKRODVr44Hbztapt6Sj5a9soHNDREtnUeHdYf/nAuhACQdLu9wv8LxZ9BT C8KA+yyQzL8Xj2nPjXCnF8r4oEg1GvYPaPeGoluXOQ3NNZbr0WctV9cn3AS2cvypZvps KC6WDUki9N//dSPPJ7WhaOXHtaFkyNVUnELvpZSqPy48Q2yQBepZsRQ+QYFTp2G0lfRp 7SqWG8IZTWa7RULL1KlfdkR8YTEW225fW5hE55OwENlLjppyph/SnMuHwqGoOFkpFjy0 XUyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Hwu+yc+sg0E/6Uf8I/BiGgYT8GMhmJgCCFTEs7SPPL8=; fh=PzVE172kMYfD8vsZrdrkQaWk4G6SF+wa//e7xu1cQV0=; b=uLTZV8mFWNsIT2kar4eivBWgP7b13zRPEBF3ePXwd5VetYd53Xrrz28PEs7tBYwC9p TI9PQCj2dHQ/cxtZ+Ib29a6tMsbSybriU2k4MaMMhplmJsd8OJcePRMBAIU85VheX+AU OhdWOyEfHHDM2Nx4FFNpgPwoc2D894Ze+/CQoQuXqQQvxPiQUcllvADaV59nKxh1vOEM etDAYRv9+w3JGBooOqhk8KzOTip/JhDHGC1oI+zTR2iNLZtCp4yHNB7a1xRARHZd5TeU 4czouvlrF73X88XJovTtGnD8x2t6uctvM0CHq50WSRMvks4Rl0VEtarqoO2EU40TVYHT NKwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TMB4+nVz; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id y17-20020a5d4711000000b003333a052b95si7277wrq.418.2024.01.10.19.10.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 19:10:07 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TMB4+nVz; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 9A25087A99; Thu, 11 Jan 2024 04:09:24 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="TMB4+nVz"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id AFCD187B05; Thu, 11 Jan 2024 04:09:22 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mail-ot1-x334.google.com (mail-ot1-x334.google.com [IPv6:2607:f8b0:4864:20::334]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id E91B987613 for ; Thu, 11 Jan 2024 04:09:15 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=semen.protsenko@linaro.org Received: by mail-ot1-x334.google.com with SMTP id 46e09a7af769-6de6aa18e7bso608364a34.3 for ; Wed, 10 Jan 2024 19:09:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704942554; x=1705547354; darn=lists.denx.de; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Hwu+yc+sg0E/6Uf8I/BiGgYT8GMhmJgCCFTEs7SPPL8=; b=TMB4+nVzMnwzODti5yPOuDXmaYRLSvGTjWecUCC9qzIaesmTqHcBcBXZpz/ROfnISw 4KG/yOPBlZI1wmG1PK1E9DoUspeBVnrVqZ5HWcmaIRy1FGhneUEHk8j+IkvQep2eTrj8 fe+Ejnra3rnAPsuhGArr5aLbgwBbTwbcNoxeIiJT+kh4NP6iJybRaHXwiZAXGE7gkNty i5+quq4JPU2EVQzSQR/PQx4aUJkPSj6xM1rUHZ+szDWqrA24uQsFLnUmbPflkZm1z3Sn g24cU5ONqMvZJUqC0uUKmk0VY+byvHe1TP10oiq2c0vIRZKX3ZixU4XUWCX4cpBoVVRs UDqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704942554; x=1705547354; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Hwu+yc+sg0E/6Uf8I/BiGgYT8GMhmJgCCFTEs7SPPL8=; b=b+lTCp5WQlne1W7H4x+0YHO25BjJLi2YNx9arCJ5j6iigsSuwOGlzq5f+JQipdbHJF UXg/XkICxxwC/10yhYt13i7VUSzZRBzSxtF87BLJJfikKX7Bc0bpfaPjgHApuIcZkl+1 6lfP6l9D6rlik15a9k8js9eHZtEjK7LDl2dFi9cKJ/pfGqInTBGSx7Hi+HvbjdPYEHEs JuABK3mllUIQKE/gWagYTu120XGjpUZZJRfsK1r6HGLv6KCVrMlpDmOIiGZUUff11BNY 7JDIuy40aBxkXZbiBcmSb5Ne/FE/OkUuumTmH+JJOfqIFhmk/C4go4PF/MsL36h7XSGl eEdg== X-Gm-Message-State: AOJu0Yy6Gaxu+x6AnrNgj63R6uB50SsQgYJTT3j+CQICT2zaoKY48bzs qKJXnfUksL4wgupPLdSFkAU68PtZFED91A== X-Received: by 2002:a05:6871:4807:b0:205:e430:d3a0 with SMTP id qc7-20020a056871480700b00205e430d3a0mr687510oab.38.1704942554482; Wed, 10 Jan 2024 19:09:14 -0800 (PST) Received: from localhost ([136.62.192.75]) by smtp.gmail.com with ESMTPSA id pf5-20020a0568717b0500b0020683d51a4csm5221oac.46.2024.01.10.19.09.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 19:09:13 -0800 (PST) From: Sam Protsenko To: Minkyu Kang , Tom Rini , Lukasz Majewski , Sean Anderson Cc: Simon Glass , Chanho Park , Heinrich Schuchardt , u-boot@lists.denx.de Subject: [PATCH v2 03/13] dt-bindings: clock: Add Exynos850 clock controller Date: Wed, 10 Jan 2024 21:08:59 -0600 Message-Id: <20240111030909.27373-4-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240111030909.27373-1-semen.protsenko@linaro.org> References: <20240111030909.27373-1-semen.protsenko@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add bindings documentation and the header file for Exynos850 clock controller. It was taken from Linux kernel [1,2]. [1] Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml [2] include/dt-bindings/clock/exynos850.h Signed-off-by: Sam Protsenko --- Changes in v2: - (none) .../clock/samsung,exynos850-clock.yaml | 307 ++++++++++++++++ include/dt-bindings/clock/exynos850.h | 337 ++++++++++++++++++ 2 files changed, 644 insertions(+) create mode 100644 doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml create mode 100644 include/dt-bindings/clock/exynos850.h diff --git a/doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml b/doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml new file mode 100644 index 000000000000..a0906efe1223 --- /dev/null +++ b/doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml @@ -0,0 +1,307 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos850-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos850 SoC clock controller + +maintainers: + - Sam Protsenko + +description: | + Exynos850 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate device + tree nodes, and might depend on each other. Root clocks in that clock tree are + two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external + clocks must be defined as fixed-rate clocks in dts. + + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and + dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'dt-bindings/clock/exynos850.h' header. + +properties: + compatible: + enum: + - samsung,exynos850-cmu-top + - samsung,exynos850-cmu-apm + - samsung,exynos850-cmu-aud + - samsung,exynos850-cmu-cmgp + - samsung,exynos850-cmu-core + - samsung,exynos850-cmu-dpu + - samsung,exynos850-cmu-g3d + - samsung,exynos850-cmu-hsi + - samsung,exynos850-cmu-is + - samsung,exynos850-cmu-mfcmscl + - samsung,exynos850-cmu-peri + + clocks: + minItems: 1 + maxItems: 5 + + clock-names: + minItems: 1 + maxItems: 5 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-top + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + + clock-names: + items: + - const: oscclk + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-apm + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_APM bus clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_clkcmu_apm_bus + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-aud + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: AUD clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_aud + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-cmgp + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_CMGP bus clock (from CMU_APM) + + clock-names: + items: + - const: oscclk + - const: gout_clkcmu_cmgp_bus + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-core + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_CORE bus clock (from CMU_TOP) + - description: CCI clock (from CMU_TOP) + - description: eMMC clock (from CMU_TOP) + - description: SSS clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_core_bus + - const: dout_core_cci + - const: dout_core_mmc_embd + - const: dout_core_sss + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-dpu + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: DPU clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_dpu + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-g3d + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: G3D clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_g3d_switch + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-hsi + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: External RTC clock (32768 Hz) + - description: CMU_HSI bus clock (from CMU_TOP) + - description: SD card clock (from CMU_TOP) + - description: USB 2.0 DRD clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: rtcclk + - const: dout_hsi_bus + - const: dout_hsi_mmc_card + - const: dout_hsi_usb20drd + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-is + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_IS bus clock (from CMU_TOP) + - description: Image Texture Processing core clock (from CMU_TOP) + - description: Visual Recognition Accelerator clock (from CMU_TOP) + - description: Geometric Distortion Correction clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_is_bus + - const: dout_is_itp + - const: dout_is_vra + - const: dout_is_gdc + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-mfcmscl + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: Multi-Format Codec clock (from CMU_TOP) + - description: Memory to Memory Scaler clock (from CMU_TOP) + - description: Multi-Channel Scaler clock (from CMU_TOP) + - description: JPEG codec clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_mfcmscl_mfc + - const: dout_mfcmscl_m2m + - const: dout_mfcmscl_mcsc + - const: dout_mfcmscl_jpeg + + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-peri + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERI bus clock (from CMU_TOP) + - description: UART clock (from CMU_TOP) + - description: Parent clock for HSI2C and SPI (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_peri_bus + - const: dout_peri_uart + - const: dout_peri_ip + +required: + - compatible + - "#clock-cells" + - clocks + - clock-names + - reg + +additionalProperties: false + +examples: + # Clock controller node for CMU_PERI + - | + #include + + cmu_peri: clock-controller@10030000 { + compatible = "samsung,exynos850-cmu-peri"; + reg = <0x10030000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>, + <&cmu_top CLK_DOUT_PERI_UART>, + <&cmu_top CLK_DOUT_PERI_IP>; + clock-names = "oscclk", "dout_peri_bus", + "dout_peri_uart", "dout_peri_ip"; + }; + +... diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h new file mode 100644 index 000000000000..3090e09c9a55 --- /dev/null +++ b/include/dt-bindings/clock/exynos850.h @@ -0,0 +1,337 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2021 Linaro Ltd. + * Author: Sam Protsenko + * + * Device Tree binding constants for Exynos850 clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOS_850_H +#define _DT_BINDINGS_CLOCK_EXYNOS_850_H + +/* CMU_TOP */ +#define CLK_FOUT_SHARED0_PLL 1 +#define CLK_FOUT_SHARED1_PLL 2 +#define CLK_FOUT_MMC_PLL 3 +#define CLK_MOUT_SHARED0_PLL 4 +#define CLK_MOUT_SHARED1_PLL 5 +#define CLK_MOUT_MMC_PLL 6 +#define CLK_MOUT_CORE_BUS 7 +#define CLK_MOUT_CORE_CCI 8 +#define CLK_MOUT_CORE_MMC_EMBD 9 +#define CLK_MOUT_CORE_SSS 10 +#define CLK_MOUT_DPU 11 +#define CLK_MOUT_HSI_BUS 12 +#define CLK_MOUT_HSI_MMC_CARD 13 +#define CLK_MOUT_HSI_USB20DRD 14 +#define CLK_MOUT_PERI_BUS 15 +#define CLK_MOUT_PERI_UART 16 +#define CLK_MOUT_PERI_IP 17 +#define CLK_DOUT_SHARED0_DIV3 18 +#define CLK_DOUT_SHARED0_DIV2 19 +#define CLK_DOUT_SHARED1_DIV3 20 +#define CLK_DOUT_SHARED1_DIV2 21 +#define CLK_DOUT_SHARED0_DIV4 22 +#define CLK_DOUT_SHARED1_DIV4 23 +#define CLK_DOUT_CORE_BUS 24 +#define CLK_DOUT_CORE_CCI 25 +#define CLK_DOUT_CORE_MMC_EMBD 26 +#define CLK_DOUT_CORE_SSS 27 +#define CLK_DOUT_DPU 28 +#define CLK_DOUT_HSI_BUS 29 +#define CLK_DOUT_HSI_MMC_CARD 30 +#define CLK_DOUT_HSI_USB20DRD 31 +#define CLK_DOUT_PERI_BUS 32 +#define CLK_DOUT_PERI_UART 33 +#define CLK_DOUT_PERI_IP 34 +#define CLK_GOUT_CORE_BUS 35 +#define CLK_GOUT_CORE_CCI 36 +#define CLK_GOUT_CORE_MMC_EMBD 37 +#define CLK_GOUT_CORE_SSS 38 +#define CLK_GOUT_DPU 39 +#define CLK_GOUT_HSI_BUS 40 +#define CLK_GOUT_HSI_MMC_CARD 41 +#define CLK_GOUT_HSI_USB20DRD 42 +#define CLK_GOUT_PERI_BUS 43 +#define CLK_GOUT_PERI_UART 44 +#define CLK_GOUT_PERI_IP 45 +#define CLK_MOUT_CLKCMU_APM_BUS 46 +#define CLK_DOUT_CLKCMU_APM_BUS 47 +#define CLK_GOUT_CLKCMU_APM_BUS 48 +#define CLK_MOUT_AUD 49 +#define CLK_GOUT_AUD 50 +#define CLK_DOUT_AUD 51 +#define CLK_MOUT_IS_BUS 52 +#define CLK_MOUT_IS_ITP 53 +#define CLK_MOUT_IS_VRA 54 +#define CLK_MOUT_IS_GDC 55 +#define CLK_GOUT_IS_BUS 56 +#define CLK_GOUT_IS_ITP 57 +#define CLK_GOUT_IS_VRA 58 +#define CLK_GOUT_IS_GDC 59 +#define CLK_DOUT_IS_BUS 60 +#define CLK_DOUT_IS_ITP 61 +#define CLK_DOUT_IS_VRA 62 +#define CLK_DOUT_IS_GDC 63 +#define CLK_MOUT_MFCMSCL_MFC 64 +#define CLK_MOUT_MFCMSCL_M2M 65 +#define CLK_MOUT_MFCMSCL_MCSC 66 +#define CLK_MOUT_MFCMSCL_JPEG 67 +#define CLK_GOUT_MFCMSCL_MFC 68 +#define CLK_GOUT_MFCMSCL_M2M 69 +#define CLK_GOUT_MFCMSCL_MCSC 70 +#define CLK_GOUT_MFCMSCL_JPEG 71 +#define CLK_DOUT_MFCMSCL_MFC 72 +#define CLK_DOUT_MFCMSCL_M2M 73 +#define CLK_DOUT_MFCMSCL_MCSC 74 +#define CLK_DOUT_MFCMSCL_JPEG 75 +#define CLK_MOUT_G3D_SWITCH 76 +#define CLK_GOUT_G3D_SWITCH 77 +#define CLK_DOUT_G3D_SWITCH 78 + +/* CMU_APM */ +#define CLK_RCO_I3C_PMIC 1 +#define OSCCLK_RCO_APM 2 +#define CLK_RCO_APM__ALV 3 +#define CLK_DLL_DCO 4 +#define CLK_MOUT_APM_BUS_USER 5 +#define CLK_MOUT_RCO_APM_I3C_USER 6 +#define CLK_MOUT_RCO_APM_USER 7 +#define CLK_MOUT_DLL_USER 8 +#define CLK_MOUT_CLKCMU_CHUB_BUS 9 +#define CLK_MOUT_APM_BUS 10 +#define CLK_MOUT_APM_I3C 11 +#define CLK_DOUT_CLKCMU_CHUB_BUS 12 +#define CLK_DOUT_APM_BUS 13 +#define CLK_DOUT_APM_I3C 14 +#define CLK_GOUT_CLKCMU_CMGP_BUS 15 +#define CLK_GOUT_CLKCMU_CHUB_BUS 16 +#define CLK_GOUT_RTC_PCLK 17 +#define CLK_GOUT_TOP_RTC_PCLK 18 +#define CLK_GOUT_I3C_PCLK 19 +#define CLK_GOUT_I3C_SCLK 20 +#define CLK_GOUT_SPEEDY_PCLK 21 +#define CLK_GOUT_GPIO_ALIVE_PCLK 22 +#define CLK_GOUT_PMU_ALIVE_PCLK 23 +#define CLK_GOUT_SYSREG_APM_PCLK 24 + +/* CMU_AUD */ +#define CLK_DOUT_AUD_AUDIF 1 +#define CLK_DOUT_AUD_BUSD 2 +#define CLK_DOUT_AUD_BUSP 3 +#define CLK_DOUT_AUD_CNT 4 +#define CLK_DOUT_AUD_CPU 5 +#define CLK_DOUT_AUD_CPU_ACLK 6 +#define CLK_DOUT_AUD_CPU_PCLKDBG 7 +#define CLK_DOUT_AUD_FM 8 +#define CLK_DOUT_AUD_FM_SPDY 9 +#define CLK_DOUT_AUD_MCLK 10 +#define CLK_DOUT_AUD_UAIF0 11 +#define CLK_DOUT_AUD_UAIF1 12 +#define CLK_DOUT_AUD_UAIF2 13 +#define CLK_DOUT_AUD_UAIF3 14 +#define CLK_DOUT_AUD_UAIF4 15 +#define CLK_DOUT_AUD_UAIF5 16 +#define CLK_DOUT_AUD_UAIF6 17 +#define CLK_FOUT_AUD_PLL 18 +#define CLK_GOUT_AUD_ABOX_ACLK 19 +#define CLK_GOUT_AUD_ASB_CCLK 20 +#define CLK_GOUT_AUD_CA32_CCLK 21 +#define CLK_GOUT_AUD_CNT_BCLK 22 +#define CLK_GOUT_AUD_CODEC_MCLK 23 +#define CLK_GOUT_AUD_DAP_CCLK 24 +#define CLK_GOUT_AUD_GPIO_PCLK 25 +#define CLK_GOUT_AUD_PPMU_ACLK 26 +#define CLK_GOUT_AUD_PPMU_PCLK 27 +#define CLK_GOUT_AUD_SPDY_BCLK 28 +#define CLK_GOUT_AUD_SYSMMU_CLK 29 +#define CLK_GOUT_AUD_SYSREG_PCLK 30 +#define CLK_GOUT_AUD_TZPC_PCLK 31 +#define CLK_GOUT_AUD_UAIF0_BCLK 32 +#define CLK_GOUT_AUD_UAIF1_BCLK 33 +#define CLK_GOUT_AUD_UAIF2_BCLK 34 +#define CLK_GOUT_AUD_UAIF3_BCLK 35 +#define CLK_GOUT_AUD_UAIF4_BCLK 36 +#define CLK_GOUT_AUD_UAIF5_BCLK 37 +#define CLK_GOUT_AUD_UAIF6_BCLK 38 +#define CLK_GOUT_AUD_WDT_PCLK 39 +#define CLK_MOUT_AUD_CPU 40 +#define CLK_MOUT_AUD_CPU_HCH 41 +#define CLK_MOUT_AUD_CPU_USER 42 +#define CLK_MOUT_AUD_FM 43 +#define CLK_MOUT_AUD_PLL 44 +#define CLK_MOUT_AUD_TICK_USB_USER 45 +#define CLK_MOUT_AUD_UAIF0 46 +#define CLK_MOUT_AUD_UAIF1 47 +#define CLK_MOUT_AUD_UAIF2 48 +#define CLK_MOUT_AUD_UAIF3 49 +#define CLK_MOUT_AUD_UAIF4 50 +#define CLK_MOUT_AUD_UAIF5 51 +#define CLK_MOUT_AUD_UAIF6 52 +#define IOCLK_AUDIOCDCLK0 53 +#define IOCLK_AUDIOCDCLK1 54 +#define IOCLK_AUDIOCDCLK2 55 +#define IOCLK_AUDIOCDCLK3 56 +#define IOCLK_AUDIOCDCLK4 57 +#define IOCLK_AUDIOCDCLK5 58 +#define IOCLK_AUDIOCDCLK6 59 +#define TICK_USB 60 +#define CLK_GOUT_AUD_CMU_AUD_PCLK 61 + +/* CMU_CMGP */ +#define CLK_RCO_CMGP 1 +#define CLK_MOUT_CMGP_ADC 2 +#define CLK_MOUT_CMGP_USI0 3 +#define CLK_MOUT_CMGP_USI1 4 +#define CLK_DOUT_CMGP_ADC 5 +#define CLK_DOUT_CMGP_USI0 6 +#define CLK_DOUT_CMGP_USI1 7 +#define CLK_GOUT_CMGP_ADC_S0_PCLK 8 +#define CLK_GOUT_CMGP_ADC_S1_PCLK 9 +#define CLK_GOUT_CMGP_GPIO_PCLK 10 +#define CLK_GOUT_CMGP_USI0_IPCLK 11 +#define CLK_GOUT_CMGP_USI0_PCLK 12 +#define CLK_GOUT_CMGP_USI1_IPCLK 13 +#define CLK_GOUT_CMGP_USI1_PCLK 14 +#define CLK_GOUT_SYSREG_CMGP_PCLK 15 + +/* CMU_G3D */ +#define CLK_FOUT_G3D_PLL 1 +#define CLK_MOUT_G3D_PLL 2 +#define CLK_MOUT_G3D_SWITCH_USER 3 +#define CLK_MOUT_G3D_BUSD 4 +#define CLK_DOUT_G3D_BUSP 5 +#define CLK_GOUT_G3D_CMU_G3D_PCLK 6 +#define CLK_GOUT_G3D_GPU_CLK 7 +#define CLK_GOUT_G3D_TZPC_PCLK 8 +#define CLK_GOUT_G3D_GRAY2BIN_CLK 9 +#define CLK_GOUT_G3D_BUSD_CLK 10 +#define CLK_GOUT_G3D_BUSP_CLK 11 +#define CLK_GOUT_G3D_SYSREG_PCLK 12 + +/* CMU_HSI */ +#define CLK_MOUT_HSI_BUS_USER 1 +#define CLK_MOUT_HSI_MMC_CARD_USER 2 +#define CLK_MOUT_HSI_USB20DRD_USER 3 +#define CLK_MOUT_HSI_RTC 4 +#define CLK_GOUT_USB_RTC_CLK 5 +#define CLK_GOUT_USB_REF_CLK 6 +#define CLK_GOUT_USB_PHY_REF_CLK 7 +#define CLK_GOUT_USB_PHY_ACLK 8 +#define CLK_GOUT_USB_BUS_EARLY_CLK 9 +#define CLK_GOUT_GPIO_HSI_PCLK 10 +#define CLK_GOUT_MMC_CARD_ACLK 11 +#define CLK_GOUT_MMC_CARD_SDCLKIN 12 +#define CLK_GOUT_SYSREG_HSI_PCLK 13 +#define CLK_GOUT_HSI_PPMU_ACLK 14 +#define CLK_GOUT_HSI_PPMU_PCLK 15 +#define CLK_GOUT_HSI_CMU_HSI_PCLK 16 + +/* CMU_IS */ +#define CLK_MOUT_IS_BUS_USER 1 +#define CLK_MOUT_IS_ITP_USER 2 +#define CLK_MOUT_IS_VRA_USER 3 +#define CLK_MOUT_IS_GDC_USER 4 +#define CLK_DOUT_IS_BUSP 5 +#define CLK_GOUT_IS_CMU_IS_PCLK 6 +#define CLK_GOUT_IS_CSIS0_ACLK 7 +#define CLK_GOUT_IS_CSIS1_ACLK 8 +#define CLK_GOUT_IS_CSIS2_ACLK 9 +#define CLK_GOUT_IS_TZPC_PCLK 10 +#define CLK_GOUT_IS_CSIS_DMA_CLK 11 +#define CLK_GOUT_IS_GDC_CLK 12 +#define CLK_GOUT_IS_IPP_CLK 13 +#define CLK_GOUT_IS_ITP_CLK 14 +#define CLK_GOUT_IS_MCSC_CLK 15 +#define CLK_GOUT_IS_VRA_CLK 16 +#define CLK_GOUT_IS_PPMU_IS0_ACLK 17 +#define CLK_GOUT_IS_PPMU_IS0_PCLK 18 +#define CLK_GOUT_IS_PPMU_IS1_ACLK 19 +#define CLK_GOUT_IS_PPMU_IS1_PCLK 20 +#define CLK_GOUT_IS_SYSMMU_IS0_CLK 21 +#define CLK_GOUT_IS_SYSMMU_IS1_CLK 22 +#define CLK_GOUT_IS_SYSREG_PCLK 23 + +/* CMU_MFCMSCL */ +#define CLK_MOUT_MFCMSCL_MFC_USER 1 +#define CLK_MOUT_MFCMSCL_M2M_USER 2 +#define CLK_MOUT_MFCMSCL_MCSC_USER 3 +#define CLK_MOUT_MFCMSCL_JPEG_USER 4 +#define CLK_DOUT_MFCMSCL_BUSP 5 +#define CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK 6 +#define CLK_GOUT_MFCMSCL_TZPC_PCLK 7 +#define CLK_GOUT_MFCMSCL_JPEG_ACLK 8 +#define CLK_GOUT_MFCMSCL_M2M_ACLK 9 +#define CLK_GOUT_MFCMSCL_MCSC_CLK 10 +#define CLK_GOUT_MFCMSCL_MFC_ACLK 11 +#define CLK_GOUT_MFCMSCL_PPMU_ACLK 12 +#define CLK_GOUT_MFCMSCL_PPMU_PCLK 13 +#define CLK_GOUT_MFCMSCL_SYSMMU_CLK 14 +#define CLK_GOUT_MFCMSCL_SYSREG_PCLK 15 + +/* CMU_PERI */ +#define CLK_MOUT_PERI_BUS_USER 1 +#define CLK_MOUT_PERI_UART_USER 2 +#define CLK_MOUT_PERI_HSI2C_USER 3 +#define CLK_MOUT_PERI_SPI_USER 4 +#define CLK_DOUT_PERI_HSI2C0 5 +#define CLK_DOUT_PERI_HSI2C1 6 +#define CLK_DOUT_PERI_HSI2C2 7 +#define CLK_DOUT_PERI_SPI0 8 +#define CLK_GOUT_PERI_HSI2C0 9 +#define CLK_GOUT_PERI_HSI2C1 10 +#define CLK_GOUT_PERI_HSI2C2 11 +#define CLK_GOUT_GPIO_PERI_PCLK 12 +#define CLK_GOUT_HSI2C0_IPCLK 13 +#define CLK_GOUT_HSI2C0_PCLK 14 +#define CLK_GOUT_HSI2C1_IPCLK 15 +#define CLK_GOUT_HSI2C1_PCLK 16 +#define CLK_GOUT_HSI2C2_IPCLK 17 +#define CLK_GOUT_HSI2C2_PCLK 18 +#define CLK_GOUT_I2C0_PCLK 19 +#define CLK_GOUT_I2C1_PCLK 20 +#define CLK_GOUT_I2C2_PCLK 21 +#define CLK_GOUT_I2C3_PCLK 22 +#define CLK_GOUT_I2C4_PCLK 23 +#define CLK_GOUT_I2C5_PCLK 24 +#define CLK_GOUT_I2C6_PCLK 25 +#define CLK_GOUT_MCT_PCLK 26 +#define CLK_GOUT_PWM_MOTOR_PCLK 27 +#define CLK_GOUT_SPI0_IPCLK 28 +#define CLK_GOUT_SPI0_PCLK 29 +#define CLK_GOUT_SYSREG_PERI_PCLK 30 +#define CLK_GOUT_UART_IPCLK 31 +#define CLK_GOUT_UART_PCLK 32 +#define CLK_GOUT_WDT0_PCLK 33 +#define CLK_GOUT_WDT1_PCLK 34 + +/* CMU_CORE */ +#define CLK_MOUT_CORE_BUS_USER 1 +#define CLK_MOUT_CORE_CCI_USER 2 +#define CLK_MOUT_CORE_MMC_EMBD_USER 3 +#define CLK_MOUT_CORE_SSS_USER 4 +#define CLK_MOUT_CORE_GIC 5 +#define CLK_DOUT_CORE_BUSP 6 +#define CLK_GOUT_CCI_ACLK 7 +#define CLK_GOUT_GIC_CLK 8 +#define CLK_GOUT_MMC_EMBD_ACLK 9 +#define CLK_GOUT_MMC_EMBD_SDCLKIN 10 +#define CLK_GOUT_SSS_ACLK 11 +#define CLK_GOUT_SSS_PCLK 12 +#define CLK_GOUT_GPIO_CORE_PCLK 13 +#define CLK_GOUT_SYSREG_CORE_PCLK 14 + +/* CMU_DPU */ +#define CLK_MOUT_DPU_USER 1 +#define CLK_DOUT_DPU_BUSP 2 +#define CLK_GOUT_DPU_CMU_DPU_PCLK 3 +#define CLK_GOUT_DPU_DECON0_ACLK 4 +#define CLK_GOUT_DPU_DMA_ACLK 5 +#define CLK_GOUT_DPU_DPP_ACLK 6 +#define CLK_GOUT_DPU_PPMU_ACLK 7 +#define CLK_GOUT_DPU_PPMU_PCLK 8 +#define CLK_GOUT_DPU_SMMU_CLK 9 +#define CLK_GOUT_DPU_SYSREG_PCLK 10 +#define DPU_NR_CLK 11 + +#endif /* _DT_BINDINGS_CLOCK_EXYNOS_850_H */ From patchwork Thu Jan 11 03:09:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 761780 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp2198469wrz; Wed, 10 Jan 2024 19:10:29 -0800 (PST) X-Google-Smtp-Source: AGHT+IEDaiWlU/PwXJBQHtAmPwhI++vV5zcrVHf01zHUSK7eIcAfMSfEqDWkDD8fatJDW/WaCQno X-Received: by 2002:a05:600c:4ecb:b0:40e:370b:4298 with SMTP id g11-20020a05600c4ecb00b0040e370b4298mr167100wmq.121.1704942629070; Wed, 10 Jan 2024 19:10:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704942629; cv=none; d=google.com; s=arc-20160816; b=izk857RJM7LioSmc7AKOEGsBeGVMnaZmLL92pCGZPyjpeI2oI1GYWvlcwC/cCCm0DW XbYbkeiDSwfgoLUPGwLR9o2jjBgpFvAO7Zqrm37Ihs2kxlpGcPgeB982i5SuogSZQFic Tu+tCApA2XQEPoKFlfaB/RHv26vtQCFaOqbs/TuT/ijK5WogEKhfLRQLoQm/hdyp8kvh Jsw3omffNaatE2dg5C2GRbGZJnWoVnKWlxaX2e+aziYkbFsA+NSzK5kFogJsf9gxSldE qYcuJN2Kwd7L1YTGrfd/QF96nUdXpC+fo5bq4M6ukLGTs9Ev9SQ6qfYzUw6np/acS4os TvAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=juKf+qA0cmK3InW8rOb585XZUoQTeXd3cpOaxt5PQ4c=; fh=PzVE172kMYfD8vsZrdrkQaWk4G6SF+wa//e7xu1cQV0=; b=eikHj+lBqQwLCQNSWpMpfpP/dWO8v4wQyv7cfE+yUHQFray0yhhJbg0C3v0jByWHUC PMOdwVo8DS7UooW8X3TX6OEEXqGFl1XaA34LQTgUBTdFDq1H+QfQtrV1ypa+s6DyFG/r KV79KFHHXsG2AWoiurE7kQX0MKUpRVQnxUaRZdzG63jN8qZm04tuRo1f8WVSVF+yFQXT jQy0Y6rVApwuyE/OhtQSUBHUgOXoO9TSIEL2nHc+klTH8ZJIa5XhJQYnHzy+njbWTxHj 9jJWAR4UL4R/jz0JEHRPUrQE+5HMBxe5Ir3URry1g1rfAwu1w5EWmbnBo0IrWkIw8FQV Qtyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=my5BLJyo; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id az15-20020a05600c600f00b0040e5b2aeee0si75739wmb.129.2024.01.10.19.10.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 19:10:29 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=my5BLJyo; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 1E5E687B13; Thu, 11 Jan 2024 04:09:26 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="my5BLJyo"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 8300487A80; Thu, 11 Jan 2024 04:09:23 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mail-oo1-xc2a.google.com (mail-oo1-xc2a.google.com [IPv6:2607:f8b0:4864:20::c2a]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id EB9E487A82 for ; Thu, 11 Jan 2024 04:09:16 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=semen.protsenko@linaro.org Received: by mail-oo1-xc2a.google.com with SMTP id 006d021491bc7-595ac2b6c59so2707732eaf.2 for ; Wed, 10 Jan 2024 19:09:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704942555; x=1705547355; darn=lists.denx.de; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=juKf+qA0cmK3InW8rOb585XZUoQTeXd3cpOaxt5PQ4c=; b=my5BLJyot2KjQosRynxeRBKuhBDhjc/UpODf7bTMO7+eserc+6ue6RCycFbHiWjIjy PAMEIu1lfv6z9hp5zWXvoaRRBtZ7rlFew/w+XPAyupadbw5lLh7PAZG6fxuysKLVsF1Q 2thsXn6EdGebOdEMAMTwwO3EQaOF5w783dCT5CIh6FL2yN0iBQltjz7stC1OA90523Na BqrvtN1/i/mgJlVFMAU3JOGj0woegu0VE+FiGzqP2OTmB3EQXubIfFUKHcsxoYgsZ59A myxa6RFIgNsxyaI8eWheZm6FCVsWe0xnxut8cVWl7fbcNta6ru6P9TC9huQ0MUpnzwiT Nlkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704942555; x=1705547355; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=juKf+qA0cmK3InW8rOb585XZUoQTeXd3cpOaxt5PQ4c=; b=Ski58EWFVmiFosX6G+lSh8UhOP8Qk/pNjuykgKWwN4umLsF2HX5O60YM3ConXXPL7Q igqWQ5fF6iknuxwAMXKnFqE/CCZ+7+XejIBi7MWwvMUFlR2GGybP0g+1kHJ9nlhEcIGm O07jz88Y3B2ztmJIS5NIBDdDBSeDp3+hPjenNWTNu/DKWmdm3DLsxuEvW9+1d9699RHC aSU99HrZhhuFIU1aHBLE6Q0Ia/scWJW5GDK6VjE2iv2QOhEcuV/27uLuzjBuDFJv0zCw FdNvWfCo+dOlkVseGsatuQFCJBy7sEmztfcSqB/Eu8pHvf7u17VVTA97FxFU861VuWJd SSQw== X-Gm-Message-State: AOJu0YxHa0iskz1Hn97qKshgS+LxX7KuvZGqdjbANPqTvpWBc5Gm5npJ U5QxO0yhkgIBYIS94rC8n3yCWnE3wcWFNg== X-Received: by 2002:a05:6820:22a0:b0:598:7d2a:ae6b with SMTP id ck32-20020a05682022a000b005987d2aae6bmr649532oob.9.1704942555477; Wed, 10 Jan 2024 19:09:15 -0800 (PST) Received: from localhost ([136.62.192.75]) by smtp.gmail.com with ESMTPSA id k12-20020a056820016c00b0058ad7b0b1a8sm14048ood.13.2024.01.10.19.09.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 19:09:14 -0800 (PST) From: Sam Protsenko To: Minkyu Kang , Tom Rini , Lukasz Majewski , Sean Anderson Cc: Simon Glass , Chanho Park , Heinrich Schuchardt , u-boot@lists.denx.de Subject: [PATCH v2 04/13] soc: samsung: Add Exynos USI driver Date: Wed, 10 Jan 2024 21:09:00 -0600 Message-Id: <20240111030909.27373-5-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240111030909.27373-1-semen.protsenko@linaro.org> References: <20240111030909.27373-1-semen.protsenko@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean USIv2 IP-core is found on modern ARM64 Exynos SoCs (like Exynos850) and provides selectable serial protocol (one of: UART, SPI, I2C). USIv2 registers usually reside in the same register map as a particular underlying protocol it implements, but have some particular offset. E.g. on Exynos850 the USI_UART has 0x13820000 base address, where UART registers have 0x00..0x40 offsets, and USI registers have 0xc0..0xdc offsets. Desired protocol can be chosen via SW_CONF register from System Register block of the same domain as USI. Before starting to use a particular protocol, USIv2 must be configured properly: 1. Select protocol to be used via System Register 2. Clear "reset" flag in USI_CON 3. Configure HWACG behavior (e.g. for UART Rx the HWACG must be disabled, so that the IP clock is not gated automatically); this is done using USI_OPTION register 4. Keep both USI clocks (PCLK and IPCLK) running during USI registers modification This driver implements the above behavior. Of course, USIv2 driver should be probed before UART/I2C/SPI drivers. It can be achieved by embedding UART/I2C/SPI nodes inside of the USI node (in Device Tree); driver then walks underlying nodes and instantiates those. Driver also handles USI configuration on PM resume, as register contents can be lost during CPU suspend. This driver is designed with different USI versions in mind. So it should be relatively easy to add new USI revisions to it later. Driver's code was copied over from Linux kernel [1] and adapted correspondingly for U-Boot API. UCLASS_MISC is used, and although no misc operations are implemented, it makes it easier to probe the driver this way (as compared to UCLASS_NOP) and keep the code compact. [1] drivers/soc/samsung/exynos-usi.c Signed-off-by: Sam Protsenko Reviewed-by: Chanho Park Reviewed-by: Simon Glass --- Changes in v2: - Removed unnecessary 'mode' param in exynos_usi_set_sw_conf() - Removed usi->dev and used priv data instead - Used .of_plat_data callback for dts parsing - Added R-b tags drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/samsung/Kconfig | 23 ++++ drivers/soc/samsung/Makefile | 3 + drivers/soc/samsung/exynos-usi.c | 208 +++++++++++++++++++++++++++++++ 5 files changed, 236 insertions(+) create mode 100644 drivers/soc/samsung/Kconfig create mode 100644 drivers/soc/samsung/Makefile create mode 100644 drivers/soc/samsung/exynos-usi.c diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 85dac9de78a4..03433bc0e6d2 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -40,6 +40,7 @@ config SOC_XILINX_VERSAL_NET This allows other drivers to verify the SoC familiy & revision using matching SoC attributes. +source "drivers/soc/samsung/Kconfig" source "drivers/soc/ti/Kconfig" endmenu diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 84385650d46d..610bf816d40a 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -2,6 +2,7 @@ # # Makefile for the U-Boot SOC specific device drivers. +obj-$(CONFIG_SOC_SAMSUNG) += samsung/ obj-$(CONFIG_SOC_TI) += ti/ obj-$(CONFIG_SOC_DEVICE) += soc-uclass.o obj-$(CONFIG_SOC_DEVICE_TI_K3) += soc_ti_k3.o diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig new file mode 100644 index 000000000000..ffb87fe79316 --- /dev/null +++ b/drivers/soc/samsung/Kconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: GPL-2.0+ + +menuconfig SOC_SAMSUNG + bool "Samsung SoC drivers support" + +if SOC_SAMSUNG + +config EXYNOS_USI + bool "Exynos USI (Universal Serial Interface) driver" + depends on ARCH_EXYNOS + select MISC + select REGMAP + select SYSCON + help + Enable support for USI block. USI (Universal Serial Interface) is an + IP-core found in modern Samsung Exynos SoCs, like Exynos850 and + ExynosAutoV9. USI block can be configured to provide one of the + following serial protocols: UART, SPI or High Speed I2C. + + This driver allows one to configure USI for desired protocol, which + is usually done in USI node in Device Tree. + +endif diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile new file mode 100644 index 000000000000..833ac073fbfa --- /dev/null +++ b/drivers/soc/samsung/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-$(CONFIG_EXYNOS_USI) += exynos-usi.o diff --git a/drivers/soc/samsung/exynos-usi.c b/drivers/soc/samsung/exynos-usi.c new file mode 100644 index 000000000000..b746a7838e1f --- /dev/null +++ b/drivers/soc/samsung/exynos-usi.c @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Linaro Ltd. + * Author: Sam Protsenko + * + * Samsung Exynos USI driver (Universal Serial Interface). + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* USIv2: System Register: SW_CONF register bits */ +#define USI_V2_SW_CONF_NONE 0x0 +#define USI_V2_SW_CONF_UART BIT(0) +#define USI_V2_SW_CONF_SPI BIT(1) +#define USI_V2_SW_CONF_I2C BIT(2) +#define USI_V2_SW_CONF_MASK (USI_V2_SW_CONF_UART | USI_V2_SW_CONF_SPI | \ + USI_V2_SW_CONF_I2C) + +/* USIv2: USI register offsets */ +#define USI_CON 0x04 +#define USI_OPTION 0x08 + +/* USIv2: USI register bits */ +#define USI_CON_RESET BIT(0) +#define USI_OPTION_CLKREQ_ON BIT(1) +#define USI_OPTION_CLKSTOP_ON BIT(2) + +enum exynos_usi_ver { + USI_VER2 = 2, +}; + +struct exynos_usi_variant { + enum exynos_usi_ver ver; /* USI IP-core version */ + unsigned int sw_conf_mask; /* SW_CONF mask for all protocols */ + size_t min_mode; /* first index in exynos_usi_modes[] */ + size_t max_mode; /* last index in exynos_usi_modes[] */ +}; + +struct exynos_usi { + void __iomem *regs; /* USI register map */ + + size_t mode; /* current USI SW_CONF mode index */ + bool clkreq_on; /* always provide clock to IP */ + + /* System Register */ + struct regmap *sysreg; /* System Register map */ + unsigned int sw_conf; /* SW_CONF register offset in sysreg */ + + const struct exynos_usi_variant *data; +}; + +struct exynos_usi_mode { + const char *name; /* mode name */ + unsigned int val; /* mode register value */ +}; + +static const struct exynos_usi_mode exynos_usi_modes[] = { + [USI_V2_NONE] = { .name = "none", .val = USI_V2_SW_CONF_NONE }, + [USI_V2_UART] = { .name = "uart", .val = USI_V2_SW_CONF_UART }, + [USI_V2_SPI] = { .name = "spi", .val = USI_V2_SW_CONF_SPI }, + [USI_V2_I2C] = { .name = "i2c", .val = USI_V2_SW_CONF_I2C }, +}; + +static const struct exynos_usi_variant exynos850_usi_data = { + .ver = USI_VER2, + .sw_conf_mask = USI_V2_SW_CONF_MASK, + .min_mode = USI_V2_NONE, + .max_mode = USI_V2_I2C, +}; + +static const struct udevice_id exynos_usi_ids[] = { + { + .compatible = "samsung,exynos850-usi", + .data = (ulong)&exynos850_usi_data, + }, + { } /* sentinel */ +}; + +/** + * exynos_usi_set_sw_conf - Set USI block configuration mode + * @dev: Driver object + * + * Select underlying serial protocol (UART/SPI/I2C) in USI IP-core as specified + * in @usi.mode. + * + * Return: 0 on success, or negative error code on failure. + */ +static int exynos_usi_set_sw_conf(struct udevice *dev) +{ + struct exynos_usi *usi = dev_get_priv(dev); + size_t mode = usi->mode; + unsigned int val; + int ret; + + if (mode < usi->data->min_mode || mode > usi->data->max_mode) + return -EINVAL; + + val = exynos_usi_modes[mode].val; + ret = regmap_update_bits(usi->sysreg, usi->sw_conf, + usi->data->sw_conf_mask, val); + if (ret) + return ret; + + dev_dbg(dev, "protocol: %s\n", exynos_usi_modes[mode].name); + + return 0; +} + +/** + * exynos_usi_enable - Initialize USI block + * @usi: USI driver object + * + * USI IP-core start state is "reset" (on startup and after CPU resume). This + * routine enables the USI block by clearing the reset flag. It also configures + * HWACG behavior (needed e.g. for UART Rx). It should be performed before + * underlying protocol becomes functional. + */ +static void exynos_usi_enable(const struct exynos_usi *usi) +{ + u32 val; + + /* Enable USI block */ + val = readl(usi->regs + USI_CON); + val &= ~USI_CON_RESET; + writel(val, usi->regs + USI_CON); + udelay(1); + + /* Continuously provide the clock to USI IP w/o gating */ + if (usi->clkreq_on) { + val = readl(usi->regs + USI_OPTION); + val &= ~USI_OPTION_CLKSTOP_ON; + val |= USI_OPTION_CLKREQ_ON; + writel(val, usi->regs + USI_OPTION); + } +} + +static int exynos_usi_configure(struct udevice *dev) +{ + struct exynos_usi *usi = dev_get_priv(dev); + int ret; + + ret = exynos_usi_set_sw_conf(dev); + if (ret) + return ret; + + if (usi->data->ver == USI_VER2) + exynos_usi_enable(usi); + + return 0; +} + +static int exynos_usi_of_to_plat(struct udevice *dev) +{ + struct exynos_usi *usi = dev_get_priv(dev); + ofnode node = dev_ofnode(dev); + int ret; + u32 mode; + + usi->data = (struct exynos_usi_variant *)dev_get_driver_data(dev); + if (usi->data->ver == USI_VER2) { + usi->regs = dev_read_addr_ptr(dev); + if (!usi->regs) + return -ENODEV; + } + + ret = ofnode_read_u32(node, "samsung,mode", &mode); + if (ret) + return ret; + if (mode < usi->data->min_mode || mode > usi->data->max_mode) + return -EINVAL; + usi->mode = mode; + + usi->sysreg = syscon_regmap_lookup_by_phandle(dev, "samsung,sysreg"); + if (IS_ERR(usi->sysreg)) + return PTR_ERR(usi->sysreg); + + ret = ofnode_read_u32_index(node, "samsung,sysreg", 1, &usi->sw_conf); + if (ret) + return ret; + + usi->clkreq_on = ofnode_read_bool(node, "samsung,clkreq-on"); + + return 0; +} + +static int exynos_usi_probe(struct udevice *dev) +{ + return exynos_usi_configure(dev); +} + +U_BOOT_DRIVER(exynos_usi) = { + .name = "exynos-usi", + .id = UCLASS_MISC, + .of_match = exynos_usi_ids, + .of_to_plat = exynos_usi_of_to_plat, + .probe = exynos_usi_probe, + .priv_auto = sizeof(struct exynos_usi), +}; From patchwork Thu Jan 11 03:09:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 761781 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp2198486wrz; Wed, 10 Jan 2024 19:10:33 -0800 (PST) X-Google-Smtp-Source: AGHT+IFPTcjhEIuqbixntEqm8qy/CWyDgg1SjS1UQnEakBwRz69be9fUhXgj3XwOAprzbLrxCA0d X-Received: by 2002:a5d:6092:0:b0:336:7f6b:190c with SMTP id w18-20020a5d6092000000b003367f6b190cmr127069wrt.205.1704942633688; Wed, 10 Jan 2024 19:10:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704942633; cv=none; d=google.com; s=arc-20160816; b=0ZpWaAFvujRYAs5SRYnzQyhtoEyiCokMrzX4u6YlqAGJmOP+E4fmxiIKizcjXxempL DJ4S4q1mWiKa/T7mJtXB0tNmO0WsLfJsz8uML6W3cwLEv7VEaAPtau8+maXYL/ArvgWi mX+r8PAL95VZnZXOknaspJaUvoGipy2OW0G/2qp43TdSqvP+SwwdMnvdT8mxBSFiv4qe Q84217PmuMcvdrAU3xFNFfbPUywfD6S5JEl1tei2HE3saNYOvj/cx/07Ogi2S4DT96i2 Egh8y24dB4dZwirI+yXPm5Z1ANkkNLYb3eH9fS58p+djQgKnP+7DQhmkElLAOLZSox4W /9Zw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=4Rb3vWqeE5FdFhswjFxTMx7BEcFmSARX6ONpf5W+V3I=; fh=PzVE172kMYfD8vsZrdrkQaWk4G6SF+wa//e7xu1cQV0=; b=C4Pb4WPbWQxMhi1U8CzOdtdBv31j/izCkCRieVpwHARUHK+B2YNVh5PLApS13lOC9L c5d6wMqXxEi3DbZvnPPkLcXh87qu9anPpIaaFiItinGCKBka4XqvFAtrU12Uj9qAvLN2 Lj2Sct3LEIaF2XURXF6sX4ORoNLPvbbgNJugudZQF6+lFsiycxTWPAOBL1jMnTS+Hd4m OV6NLxQURMlpARqUbAJ9RYnV3L1jHjM2kwVf1T0YLqOvOrnZbbIEaQCCoSsdBVGFYgHj 5b1MvTKaxRRiz7TTB8o3IujJdpW4UGmRyCfWh2QQqAvsGFzVvS99eCs8Wxe9IeqXYS8k wQyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hmXZ5O7d; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id c11-20020adfef4b000000b00337650349ffsi4958wrp.878.2024.01.10.19.10.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 19:10:33 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hmXZ5O7d; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A740487B0C; Thu, 11 Jan 2024 04:09:28 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="hmXZ5O7d"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id EC5D987AEB; Thu, 11 Jan 2024 04:09:24 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mail-oi1-x22a.google.com (mail-oi1-x22a.google.com [IPv6:2607:f8b0:4864:20::22a]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id C1F4287A97 for ; Thu, 11 Jan 2024 04:09:17 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=semen.protsenko@linaro.org Received: by mail-oi1-x22a.google.com with SMTP id 5614622812f47-3bbbf5a59b7so4373262b6e.3 for ; Wed, 10 Jan 2024 19:09:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704942556; x=1705547356; darn=lists.denx.de; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4Rb3vWqeE5FdFhswjFxTMx7BEcFmSARX6ONpf5W+V3I=; b=hmXZ5O7dixMqi5A6posnzw31r7wEK56m24Uu5+4bdASsYLYJ0KdcXBA5W3/RWiXu1d nx8bAJ+iqw5ljUpsYFTS4XvrtVeXpBae2uq7/3EFLLANhR8noRqnOMzMi7RJCvWSBQcP PGJJej92EUtwCmT4sVJaXRQHof2wI9ziAPPckUD918XjGmtAzZL1ZXDZLfxXCZE4fLWg 9iDCe6MNugGbfzvg+ByyHJ4lOPkSFmrj6AI1o+2MbRG1JsME47l5710k6Cv8gFpnsODR psWBzCYs06grACam6pOkunXAwQAkJsE7cpbhFvJ7bXORjGf0Xu6Xl6+G5dxeV6xiyP10 JP6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704942556; x=1705547356; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4Rb3vWqeE5FdFhswjFxTMx7BEcFmSARX6ONpf5W+V3I=; b=fihK0dPheUm/7i7gtRxGcPrHGHWtRj1Tj0U+lkLShOUbWofkjz3X8VIl4P15AwQ7W0 ZMyjICtmFHUHeIs8jQQzdUE6J71xZCJ3dAWntvxuSmpwAsTKgvE7Q86hWklE9h/Yrf0A uwxx4zMhqscPJ4ui5cXyazDBQ9C5iWrvPVAugL09pqjnKYz9YRqs+ip+OTCBXK0W/BJy 0Zt8SOopBDQ5D6IR88BhucZc+pLH0wOzg5O4l4f964njQRwKxLabIFT7BcWF7HEPTk/H dgOWKyxqEPhg0b/0bE0Gl4SRUaq/xuTpB0M4Zxlfa6ymVQh5Ph5E5CflSG6nYg9gsr+B PD5Q== X-Gm-Message-State: AOJu0YzDiKv6/U3MTh7KCtKN/00WLzCXY7TyuJ6EWXp7ozXVo7bQHCtC no/4eFbW5Lu+OUPf8vS3CZfm95eQbTjMiQ== X-Received: by 2002:a05:6808:13d4:b0:3bd:3b75:b68c with SMTP id d20-20020a05680813d400b003bd3b75b68cmr837657oiw.13.1704942556465; Wed, 10 Jan 2024 19:09:16 -0800 (PST) Received: from localhost ([136.62.192.75]) by smtp.gmail.com with ESMTPSA id k1-20020a05680808c100b003bd40e302c7sm19314oij.51.2024.01.10.19.09.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 19:09:15 -0800 (PST) From: Sam Protsenko To: Minkyu Kang , Tom Rini , Lukasz Majewski , Sean Anderson Cc: Simon Glass , Chanho Park , Heinrich Schuchardt , u-boot@lists.denx.de Subject: [PATCH v2 05/13] soc: samsung: Add Exynos PMU driver Date: Wed, 10 Jan 2024 21:09:01 -0600 Message-Id: <20240111030909.27373-6-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240111030909.27373-1-semen.protsenko@linaro.org> References: <20240111030909.27373-1-semen.protsenko@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add basic Power Management Unit (PMU) driver for Exynos SoCs. For now it's only capable of changing UART path in PMU, which is needed for E850-96 board. The driver's structure resembles the exynos-pmu driver from Linux kernel, and although it's very basic and slim at the moment, it can be easily extended in future if the need arises. UCLASS_NOP is used, as there are no benefits in using more elaborate classes like UCLASS_MISC in this case. The DM_FLAG_PROBE_AFTER_BIND flag is added in bind function, as the probe function must be always called for this driver. Signed-off-by: Sam Protsenko Reviewed-by: Chanho Park --- Changes in v2: - Added R-b tag drivers/soc/samsung/Kconfig | 10 +++ drivers/soc/samsung/Makefile | 1 + drivers/soc/samsung/exynos-pmu.c | 102 +++++++++++++++++++++++++++++++ 3 files changed, 113 insertions(+) create mode 100644 drivers/soc/samsung/exynos-pmu.c diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig index ffb87fe79316..737b7ca8cd19 100644 --- a/drivers/soc/samsung/Kconfig +++ b/drivers/soc/samsung/Kconfig @@ -5,6 +5,16 @@ menuconfig SOC_SAMSUNG if SOC_SAMSUNG +config EXYNOS_PMU + bool "Exynos PMU controller driver" + depends on ARCH_EXYNOS + select REGMAP + select SYSCON + help + Enable support for system controller configuration driver. It allows + one to configure system controller registers (e.g. some register in + PMU syscon) by providing register's offset, mask and value. + config EXYNOS_USI bool "Exynos USI (Universal Serial Interface) driver" depends on ARCH_EXYNOS diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile index 833ac073fbfa..0eb3ed8353b0 100644 --- a/drivers/soc/samsung/Makefile +++ b/drivers/soc/samsung/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ +obj-$(CONFIG_EXYNOS_PMU) += exynos-pmu.o obj-$(CONFIG_EXYNOS_USI) += exynos-usi.o diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c new file mode 100644 index 000000000000..233ad4a908f5 --- /dev/null +++ b/drivers/soc/samsung/exynos-pmu.c @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Linaro Ltd. + * Author: Sam Protsenko + * + * Exynos PMU (Power Management Unit) driver. + */ + +#include +#include +#include +#include +#include +#include + +#define EXYNOS850_UART_IO_SHARE_CTRL 0x0760 +#define SEL_RXD_AP_UART_SHIFT 16 +#define SEL_RXD_AP_UART_MASK GENMASK(17, 16) +#define SEL_TXD_GPIO_1_SHIFT 20 +#define SEL_TXD_GPIO_1_MASK GENMASK(21, 20) +#define RXD_GPIO_1 0x3 +#define TXD_AP_UART 0x0 + +struct exynos_pmu { + struct udevice *dev; + const struct exynos_pmu_data *pmu_data; + struct regmap *regmap; +}; + +struct exynos_pmu_data { + int (*pmu_init)(struct exynos_pmu *priv); +}; + +static int exynos850_pmu_init(struct exynos_pmu *priv) +{ + ofnode node; + bool uart_debug_1; + unsigned int offset, mask, value; + + node = dev_ofnode(priv->dev); + uart_debug_1 = ofnode_read_bool(node, "samsung,uart-debug-1"); + if (!uart_debug_1) + return 0; + + /* + * If uart1_pins are used for serial, AP UART lines have to be muxed + * in PMU block to UART_DEBUG_1 path (GPIO_1). By default (reset value) + * UART_DEBUG_0 path (uart0_pins) is connected to AP UART lines. + */ + offset = EXYNOS850_UART_IO_SHARE_CTRL; + mask = SEL_RXD_AP_UART_MASK | SEL_TXD_GPIO_1_MASK; + value = RXD_GPIO_1 << SEL_RXD_AP_UART_SHIFT | + TXD_AP_UART << SEL_TXD_GPIO_1_SHIFT; + return regmap_update_bits(priv->regmap, offset, mask, value); +} + +static const struct exynos_pmu_data exynos850_pmu_data = { + .pmu_init = exynos850_pmu_init, +}; + +static int exynos_pmu_bind(struct udevice *dev) +{ + dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND); + return 0; +} + +static int exynos_pmu_probe(struct udevice *dev) +{ + ofnode node; + struct exynos_pmu *priv; + + priv = dev_get_priv(dev); + priv->dev = dev; + + node = dev_ofnode(dev); + priv->regmap = syscon_node_to_regmap(node); + if (IS_ERR(priv->regmap)) + return PTR_ERR(priv->regmap); + + priv->pmu_data = (struct exynos_pmu_data *)dev_get_driver_data(dev); + if (priv->pmu_data && priv->pmu_data->pmu_init) + return priv->pmu_data->pmu_init(priv); + + return 0; +} + +static const struct udevice_id exynos_pmu_ids[] = { + { + .compatible = "samsung,exynos850-pmu", + .data = (ulong)&exynos850_pmu_data + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(exynos_pmu) = { + .name = "exynos-pmu", + .id = UCLASS_NOP, + .of_match = exynos_pmu_ids, + .bind = exynos_pmu_bind, + .probe = exynos_pmu_probe, + .priv_auto = sizeof(struct exynos_pmu), +}; From patchwork Thu Jan 11 03:09:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 761783 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp2198584wrz; Wed, 10 Jan 2024 19:10:55 -0800 (PST) X-Google-Smtp-Source: AGHT+IFTDT0pWn6uSFPqKc1R5Gl0IG0Q9jjhgkExya4ENyPfAG7kxa696KymXtH4oedUpnC/wog/ X-Received: by 2002:a05:600c:3644:b0:40e:423a:54e8 with SMTP id y4-20020a05600c364400b0040e423a54e8mr1854wmq.56.1704942654936; Wed, 10 Jan 2024 19:10:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704942654; cv=none; d=google.com; s=arc-20160816; b=ufSrf/t1wbdARorGQYFjQZKvqQNGR04rnE3CERNXdT+gw3+JjHZHsidEEnN4w8W4ti 5GOH0nI7qtrmtnkdhUdDonW+VSE9ru74du8cqP6bBZFhlDGnNr/Up/DcuwuQqT6qCoIO sea2WTH8yJ0LgDoMLMKVIayibcrl/KHOr4VDU/CiSAxwk6tsjZksioJ85KKyvW4wmcml zZ88IhUTWn1bguCpODagLk8Vf2CVwY8chMyo8wbT7b9bUZ+0vZICnpeu/835MFOx31gm FBPQ6C6o4GPM+AKX54wZ5JRnQcSYJTYJ5lvnC44UFn2Tm41TZeqYAsvdlqruTwi1dcwN fQ+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=FZamB8HQFE3xnEU3Kog2EvJx83VWjNRAeNl6NTTGjZQ=; fh=PzVE172kMYfD8vsZrdrkQaWk4G6SF+wa//e7xu1cQV0=; b=F0saskg2bj/+rfiNgFgjISFh5jwZo5a4eZjCWZz1xxkuy0Ggmt66Ub8Q2oOefvFCJ/ bc6bDp5FVXYayr73yohTcqLzxiH5KLxhWZtrkuR1FXGE+TAxYHk22gpv+y1vLP3j/SFE LoeAEnnKjqxdn4D91PuYfpV1kjmmM1uXPkhxOFNph2tbu7W18Xj+ZT8Kqxh7UkVgs4de UtSoitBNPY8poJjfqDC+Uij3MQaMoMo+mjSG2lhk3E7K9Z7cGCBisyO/8I6UqMJ2Qt97 rDJQp7nk0oa4WHbItyL7xEBQubVzUm/dRT4p/bDlbsr7LJjgjJuXno6rdkLQn09bRkWP LQKg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=svLcMEU9; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id n12-20020a5d4c4c000000b0033635e89878si5089wrt.881.2024.01.10.19.10.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 19:10:54 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=svLcMEU9; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5643387A36; Thu, 11 Jan 2024 04:09:31 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="svLcMEU9"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 361738792C; Thu, 11 Jan 2024 04:09:28 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mail-ot1-x32a.google.com (mail-ot1-x32a.google.com [IPv6:2607:f8b0:4864:20::32a]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id AA20287ADC for ; Thu, 11 Jan 2024 04:09:18 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=semen.protsenko@linaro.org Received: by mail-ot1-x32a.google.com with SMTP id 46e09a7af769-6dde00025faso1794422a34.3 for ; Wed, 10 Jan 2024 19:09:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704942557; x=1705547357; darn=lists.denx.de; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FZamB8HQFE3xnEU3Kog2EvJx83VWjNRAeNl6NTTGjZQ=; b=svLcMEU96uDWY5OFf4iBa9hfMJUvHOu08EFI8rQV9eZaxUJIPPC9lylJ2CCZBHmnXv qvmTy5XntQ9XllOKNbXqJu76EjoeY51YV+aHXgutx6ZGQVvr3lVDy/TvMkTTTIexnS1u XmXEHx7Qfy3p8w4mO6zJa83lewhxcrkiiDNaamyNoQW2qpRs2eAU5A/oUe5pof0gHGh9 /wlzOHbioIhnqRpf7gTYewwdI+944BQyqqB+Bmm6iFAf8lwwBqQNhrv5kwiYsodFC0mV 2byVpm//WDCTJb4cMYzJHNvkqNWX+gNDO0BvO1ULcvOfsDBOFiYDzeEt6Kwc/ygHjfdv Pb5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704942557; x=1705547357; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FZamB8HQFE3xnEU3Kog2EvJx83VWjNRAeNl6NTTGjZQ=; b=mAPgFOwghkJbdF09JkUXwDnUsReU1rjH2U78j3D0aqSirKaBx5cYTZ+PF88ix7TgtS GGFlgyoVJKf7B6fq2EFvUh0p2nEflIx8GafLB5L7u77ZSEQkRhJwSE3qRuuSMytNhKgb T+c95G/W0V5DXUFdsUWCgJmAkywRc3BUzPRZNHbN7aH/iswVrj2Ft6Dj9c1FjMWnw2tV omIOhPVkF5pTjYZjmiELxT6MMn61nZMJSttSWVG9z9Q4RCnr7LISWRbFRbohFgzqYLrp UlifNgXDp5dtRXPCVNyybjmXpISg+CQr0chj2HSTH+E9J5uUScROeGRH5KfLJzbs7Mnv VhgA== X-Gm-Message-State: AOJu0YyKAQhKGZOWzfI7ZzrQoBhOCmH/CpQNO79GMCoZWpb54Rt33lk+ /UK+XObOuPBwPTo9YUBL2sqI90AAaMzxNA== X-Received: by 2002:a9d:6301:0:b0:6dd:dda6:67b3 with SMTP id q1-20020a9d6301000000b006dddda667b3mr621811otk.67.1704942557342; Wed, 10 Jan 2024 19:09:17 -0800 (PST) Received: from localhost ([136.62.192.75]) by smtp.gmail.com with ESMTPSA id w10-20020a4aa44a000000b00598a2ef41ddsm11493ool.44.2024.01.10.19.09.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 19:09:16 -0800 (PST) From: Sam Protsenko To: Minkyu Kang , Tom Rini , Lukasz Majewski , Sean Anderson Cc: Simon Glass , Chanho Park , Heinrich Schuchardt , u-boot@lists.denx.de Subject: [PATCH v2 06/13] clk: exynos: Move pll code into clk-exynos7420 Date: Wed, 10 Jan 2024 21:09:02 -0600 Message-Id: <20240111030909.27373-7-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240111030909.27373-1-semen.protsenko@linaro.org> References: <20240111030909.27373-1-semen.protsenko@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean PLL utilities code is only used by clk-exynos7420 driver at the moment. Move it into clk-exynos7420 to make clk-pll.c file available for CCF PLL clocks implementation, which is coming in the next patches. Signed-off-by: Sam Protsenko Reviewed-by: Chanho Park --- Changes in v2: - Added R-b tag drivers/clk/exynos/Makefile | 1 - drivers/clk/exynos/clk-exynos7420.c | 25 +++++++++++++++++++++- drivers/clk/exynos/clk-pll.c | 32 ----------------------------- drivers/clk/exynos/clk-pll.h | 13 ------------ 4 files changed, 24 insertions(+), 47 deletions(-) delete mode 100644 drivers/clk/exynos/clk-pll.c delete mode 100644 drivers/clk/exynos/clk-pll.h diff --git a/drivers/clk/exynos/Makefile b/drivers/clk/exynos/Makefile index c9f29c873e9b..7faf238571ef 100644 --- a/drivers/clk/exynos/Makefile +++ b/drivers/clk/exynos/Makefile @@ -3,5 +3,4 @@ # Copyright (C) 2016 Samsung Electronics # Thomas Abraham -obj-y += clk-pll.o obj-$(CONFIG_CLK_EXYNOS7420) += clk-exynos7420.o diff --git a/drivers/clk/exynos/clk-exynos7420.c b/drivers/clk/exynos/clk-exynos7420.c index 7d869eb02b8e..9caa932e12fb 100644 --- a/drivers/clk/exynos/clk-exynos7420.c +++ b/drivers/clk/exynos/clk-exynos7420.c @@ -10,8 +10,15 @@ #include #include #include +#include #include -#include "clk-pll.h" + +#define PLL145X_MDIV_SHIFT 16 +#define PLL145X_MDIV_MASK 0x3ff +#define PLL145X_PDIV_SHIFT 8 +#define PLL145X_PDIV_MASK 0x3f +#define PLL145X_SDIV_SHIFT 0 +#define PLL145X_SDIV_MASK 0x7 #define DIVIDER(reg, shift, mask) \ (((readl(reg) >> shift) & mask) + 1) @@ -64,6 +71,22 @@ struct exynos7420_clk_top0_priv { unsigned long sclk_uart2; }; +static unsigned long pll145x_get_rate(unsigned int *con1, + unsigned long fin_freq) +{ + unsigned long pll_con1 = readl(con1); + unsigned long mdiv, sdiv, pdiv; + u64 fvco = fin_freq; + + mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK; + pdiv = (pll_con1 >> PLL145X_PDIV_SHIFT) & PLL145X_PDIV_MASK; + sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK; + + fvco *= mdiv; + do_div(fvco, (pdiv << sdiv)); + return (unsigned long)fvco; +} + static ulong exynos7420_topc_get_rate(struct clk *clk) { struct exynos7420_clk_topc_priv *priv = dev_get_priv(clk->dev); diff --git a/drivers/clk/exynos/clk-pll.c b/drivers/clk/exynos/clk-pll.c deleted file mode 100644 index 407fc71d415b..000000000000 --- a/drivers/clk/exynos/clk-pll.c +++ /dev/null @@ -1,32 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Exynos PLL helper functions for clock drivers. - * Copyright (C) 2016 Samsung Electronics - * Thomas Abraham - */ - -#include -#include -#include - -#define PLL145X_MDIV_SHIFT 16 -#define PLL145X_MDIV_MASK 0x3ff -#define PLL145X_PDIV_SHIFT 8 -#define PLL145X_PDIV_MASK 0x3f -#define PLL145X_SDIV_SHIFT 0 -#define PLL145X_SDIV_MASK 0x7 - -unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq) -{ - unsigned long pll_con1 = readl(con1); - unsigned long mdiv, sdiv, pdiv; - uint64_t fvco = fin_freq; - - mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK; - pdiv = (pll_con1 >> PLL145X_PDIV_SHIFT) & PLL145X_PDIV_MASK; - sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK; - - fvco *= mdiv; - do_div(fvco, (pdiv << sdiv)); - return (unsigned long)fvco; -} diff --git a/drivers/clk/exynos/clk-pll.h b/drivers/clk/exynos/clk-pll.h deleted file mode 100644 index 7b7af5e67612..000000000000 --- a/drivers/clk/exynos/clk-pll.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Exynos PLL helper functions for clock drivers. - * Copyright (C) 2016 Samsung Electronics - * Thomas Abraham - */ - -#ifndef __EXYNOS_CLK_PLL_H -#define __EXYNOS_CLK_PLL_H - -unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq); - -#endif /* __EXYNOS_CLK_PLL_H */ From patchwork Thu Jan 11 03:09:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 761782 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp2198536wrz; Wed, 10 Jan 2024 19:10:44 -0800 (PST) X-Google-Smtp-Source: AGHT+IEZwuY8FD0n1zIaA3PZxqPnj4bXcw+5chmHAmRChymVwGvEd6eUnKlYMJ3hvCExNqYmEmid X-Received: by 2002:adf:f609:0:b0:337:61aa:9682 with SMTP id t9-20020adff609000000b0033761aa9682mr199012wrp.110.1704942644135; Wed, 10 Jan 2024 19:10:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704942644; cv=none; d=google.com; s=arc-20160816; b=HeolsmSYPuLFxxzPtdvt0NXUvLim+tYUO1aeBuOypei84Rm7pn+OG/y/kbroDvIjNu CYvd3VNWtd9PWr/SJEbk8H/1HWG9sLxKQT0BABkW05XI/L0Ph/wXp4tigKYUk4hLRi31 Q8ryBJ5wBzi/WaiGbltmQ0c4iWhk1/I3ahsV5jQ+eNU1SfDetGP8oM1ZeiSydJgc1BwS mWlsTCDoP5ELISn17sOXyUKiOdDuzyqIG34dttmYaHwUsC4qm1gLUjTY/5O1hXBKWJ9F fQ35EXi9ZKq8KYYIJV3TsA2LUzjFyKIgZR23oPw2ebdXtZPqNMwU8KhWSCkd+r7s2Nyk xKZw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=pWCOtSiZiCsY82ekLLkAxSvnzb2DCAEccueMHBBUVHs=; fh=PzVE172kMYfD8vsZrdrkQaWk4G6SF+wa//e7xu1cQV0=; b=mxbk3YgMTlhamc5ApunvZNRgC+ZjeScleueTfRXCqOz5KecrkbHocLTeYXXvp5BY+y TMKwKoreyhRvmSKXXACGeZpf9q/T3diLb8WdKt+gxowSL50WL7XB4H6NA2I7IKeLQU4g nZ+PCCDMe7wA/9Cm20t7Cxi3TtW9I9o6xZIEF87gzzMiLOpJR4BQwG0KEEJBUd1EZ13n HNhMnJwh3Grcfll5AJpPV8dXrGnvJ6bjoGunADtXayi+R7+6Q+J5RhaB+OyNrCalLgcW LGhe9PBC6tMgAJdP4H7uf4yOfUpWlPPipCUVq3BPl6gBO5qkRgQlb9VI3YqyheD+s350 3nXw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RDxs6Rqu; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id v15-20020a5d43cf000000b0033638cd5eb2si4241wrr.954.2024.01.10.19.10.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 19:10:44 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RDxs6Rqu; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 7EB9687AEC; Thu, 11 Jan 2024 04:09:30 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="RDxs6Rqu"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id D30E38792C; Thu, 11 Jan 2024 04:09:27 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mail-oa1-x36.google.com (mail-oa1-x36.google.com [IPv6:2001:4860:4864:20::36]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 317D68791E for ; Thu, 11 Jan 2024 04:09:20 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=semen.protsenko@linaro.org Received: by mail-oa1-x36.google.com with SMTP id 586e51a60fabf-2045bedb806so4035931fac.3 for ; Wed, 10 Jan 2024 19:09:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704942558; x=1705547358; darn=lists.denx.de; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pWCOtSiZiCsY82ekLLkAxSvnzb2DCAEccueMHBBUVHs=; b=RDxs6RquNAA5Hy70UOcJRTYaEjvTfnxNbShE/wZ6b3cD3gSfQ4ngFiMp0eDPc99RFH Esgo5fYkNTSTpxYNw4bGLdEXX4ajsHRAL59RzIfFOrtNwtoqTvPlYN79Onh5rGBYIN07 D2CW3dMc38OGUi/A/7TwT23sNI/3PcvYoPEE2q6HLqLWpu6l+PUnugbUrCp6gNhIkWBA tih09zUAP6tW1tQq5VzDYtf8LwO5o6PK53KDYmx/QMznDKxZqiFBYIJ8WgRo43NPMFs3 lGDpoUiOdK8hkNOOR2Il+Nqr+ZJxfc4AhpPHwT8PfXfAvXuMZjz31878/1Ds0EvVATLt 8Cpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704942558; x=1705547358; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pWCOtSiZiCsY82ekLLkAxSvnzb2DCAEccueMHBBUVHs=; b=QElnXN2qcd4mBuLVThlcOpRcHGYtBtVq05NODg6Tbtr2HndO40uDkl4OKnRUElx9e8 wZdsuwrp52yuii5ylEP/MW6n0sdNk4xDka88W+wasAEYFr6HaeaRTEnWke+IlrTHRob9 s+s6Gw3KIMr1kXzxIH4v8ZroMkT9mjBVZw/Rrjh1NhWUg96eoZ3jPsADE57pzjdtXgbg 9fzAyxS0BJFA3E/QWLoC24J4wA4kGssMZQ89k4f5jF0xr8wZvMGZgq+ShiFa5G0XFw4/ VklSA0BEnGQgmWwYHhfYDpFsSU9ZfQ4ocqlxI6SHBafKwen26z1AfO/Vks7Ys5wzYq8d 7+ig== X-Gm-Message-State: AOJu0Yy7neiM1r/e0xbZCvmS06LJze1a4AIedjCVdRsnKgtfeIqJ9VPG 14Rk6SJDAiT46bfRA9YqIwvkEd5GRMDQxA== X-Received: by 2002:a05:6870:1707:b0:206:7e46:f18b with SMTP id h7-20020a056870170700b002067e46f18bmr691571oae.28.1704942558312; Wed, 10 Jan 2024 19:09:18 -0800 (PST) Received: from localhost ([136.62.192.75]) by smtp.gmail.com with ESMTPSA id l21-20020a9d7355000000b006dc375b57d4sm2697otk.65.2024.01.10.19.09.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 19:09:17 -0800 (PST) From: Sam Protsenko To: Minkyu Kang , Tom Rini , Lukasz Majewski , Sean Anderson Cc: Simon Glass , Chanho Park , Heinrich Schuchardt , u-boot@lists.denx.de Subject: [PATCH v2 07/13] clk: exynos: Add Samsung clock framework Date: Wed, 10 Jan 2024 21:09:03 -0600 Message-Id: <20240111030909.27373-8-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240111030909.27373-1-semen.protsenko@linaro.org> References: <20240111030909.27373-1-semen.protsenko@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Heavily based on Linux kernel Samsung clock framework, with some changes to accommodate the differences in U-Boot CCF implementation. It's also quite minimal as compared to the Linux version. Signed-off-by: Sam Protsenko Reviewed-by: Chanho Park --- Changes in v2: - Corrected Thomas Abraham's e-mail - Added R-b tag drivers/clk/exynos/Makefile | 9 +- drivers/clk/exynos/clk-pll.c | 167 +++++++++++++++++++++++++ drivers/clk/exynos/clk-pll.h | 23 ++++ drivers/clk/exynos/clk.c | 121 +++++++++++++++++++ drivers/clk/exynos/clk.h | 228 +++++++++++++++++++++++++++++++++++ 5 files changed, 546 insertions(+), 2 deletions(-) create mode 100644 drivers/clk/exynos/clk-pll.c create mode 100644 drivers/clk/exynos/clk-pll.h create mode 100644 drivers/clk/exynos/clk.c create mode 100644 drivers/clk/exynos/clk.h diff --git a/drivers/clk/exynos/Makefile b/drivers/clk/exynos/Makefile index 7faf238571ef..04c5b9a39e16 100644 --- a/drivers/clk/exynos/Makefile +++ b/drivers/clk/exynos/Makefile @@ -1,6 +1,11 @@ # SPDX-License-Identifier: GPL-2.0+ # # Copyright (C) 2016 Samsung Electronics -# Thomas Abraham +# Copyright (C) 2023 Linaro Ltd. +# +# Authors: +# Thomas Abraham +# Sam Protsenko -obj-$(CONFIG_CLK_EXYNOS7420) += clk-exynos7420.o +obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-pll.o +obj-$(CONFIG_CLK_EXYNOS7420) += clk-exynos7420.o diff --git a/drivers/clk/exynos/clk-pll.c b/drivers/clk/exynos/clk-pll.c new file mode 100644 index 000000000000..4aacbc26b25d --- /dev/null +++ b/drivers/clk/exynos/clk-pll.c @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Samsung Electronics + * Copyright (C) 2023 Linaro Ltd. + * + * Authors: + * Thomas Abraham + * Sam Protsenko + * + * This file contains the utility functions to register the pll clocks. + */ + +#include +#include +#include +#include +#include +#include +#include "clk.h" + +#define UBOOT_DM_CLK_SAMSUNG_PLL0822X "samsung_clk_pll0822x" +#define UBOOT_DM_CLK_SAMSUNG_PLL0831X "samsung_clk_pll0831x" + +struct samsung_clk_pll { + struct clk clk; + void __iomem *con_reg; + enum samsung_pll_type type; +}; + +#define to_clk_pll(_clk) container_of(_clk, struct samsung_clk_pll, clk) + +/* + * PLL0822x Clock Type + */ + +#define PLL0822X_MDIV_MASK 0x3ff +#define PLL0822X_PDIV_MASK 0x3f +#define PLL0822X_SDIV_MASK 0x7 +#define PLL0822X_MDIV_SHIFT 16 +#define PLL0822X_PDIV_SHIFT 8 +#define PLL0822X_SDIV_SHIFT 0 + +static unsigned long samsung_pll0822x_recalc_rate(struct clk *clk) +{ + struct samsung_clk_pll *pll = to_clk_pll(clk); + u32 mdiv, pdiv, sdiv, pll_con3; + u64 fvco = clk_get_parent_rate(clk); + + pll_con3 = readl_relaxed(pll->con_reg); + mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK; + pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK; + sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK; + + fvco *= mdiv; + do_div(fvco, (pdiv << sdiv)); + return (unsigned long)fvco; +} + +static const struct clk_ops samsung_pll0822x_clk_min_ops = { + .get_rate = samsung_pll0822x_recalc_rate, +}; + +/* + * PLL0831x Clock Type + */ + +#define PLL0831X_KDIV_MASK 0xffff +#define PLL0831X_MDIV_MASK 0x1ff +#define PLL0831X_PDIV_MASK 0x3f +#define PLL0831X_SDIV_MASK 0x7 +#define PLL0831X_MDIV_SHIFT 16 +#define PLL0831X_PDIV_SHIFT 8 +#define PLL0831X_SDIV_SHIFT 0 +#define PLL0831X_KDIV_SHIFT 0 + +static unsigned long samsung_pll0831x_recalc_rate(struct clk *clk) +{ + struct samsung_clk_pll *pll = to_clk_pll(clk); + u32 mdiv, pdiv, sdiv, pll_con3, pll_con5; + s16 kdiv; + u64 fvco = clk_get_parent_rate(clk); + + pll_con3 = readl_relaxed(pll->con_reg); + pll_con5 = readl_relaxed(pll->con_reg + 8); + mdiv = (pll_con3 >> PLL0831X_MDIV_SHIFT) & PLL0831X_MDIV_MASK; + pdiv = (pll_con3 >> PLL0831X_PDIV_SHIFT) & PLL0831X_PDIV_MASK; + sdiv = (pll_con3 >> PLL0831X_SDIV_SHIFT) & PLL0831X_SDIV_MASK; + kdiv = (s16)((pll_con5 >> PLL0831X_KDIV_SHIFT) & PLL0831X_KDIV_MASK); + + fvco *= (mdiv << 16) + kdiv; + do_div(fvco, (pdiv << sdiv)); + fvco >>= 16; + + return (unsigned long)fvco; +} + +static const struct clk_ops samsung_pll0831x_clk_min_ops = { + .get_rate = samsung_pll0831x_recalc_rate, +}; + +static struct clk *_samsung_clk_register_pll(void __iomem *base, + const struct samsung_pll_clock *pll_clk) +{ + struct samsung_clk_pll *pll; + struct clk *clk; + const char *drv_name; + int ret; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + pll->con_reg = base + pll_clk->con_offset; + pll->type = pll_clk->type; + clk = &pll->clk; + clk->flags = pll_clk->flags; + + switch (pll_clk->type) { + case pll_0822x: + drv_name = UBOOT_DM_CLK_SAMSUNG_PLL0822X; + break; + case pll_0831x: + drv_name = UBOOT_DM_CLK_SAMSUNG_PLL0831X; + break; + default: + kfree(pll); + return ERR_PTR(-ENODEV); + } + + ret = clk_register(clk, drv_name, pll_clk->name, pll_clk->parent_name); + if (ret) { + kfree(pll); + return ERR_PTR(ret); + } + + return clk; +} + +void samsung_clk_register_pll(void __iomem *base, + const struct samsung_pll_clock *clk_list, + unsigned int nr_clk) +{ + unsigned int cnt; + + for (cnt = 0; cnt < nr_clk; cnt++) { + struct clk *clk; + const struct samsung_pll_clock *pll_clk; + + pll_clk = &clk_list[cnt]; + clk = _samsung_clk_register_pll(base, pll_clk); + clk_dm(pll_clk->id, clk); + } +} + +U_BOOT_DRIVER(samsung_pll0822x_clk) = { + .name = UBOOT_DM_CLK_SAMSUNG_PLL0822X, + .id = UCLASS_CLK, + .ops = &samsung_pll0822x_clk_min_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DRIVER(samsung_pll0831x_clk) = { + .name = UBOOT_DM_CLK_SAMSUNG_PLL0831X, + .id = UCLASS_CLK, + .ops = &samsung_pll0831x_clk_min_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/exynos/clk-pll.h b/drivers/clk/exynos/clk-pll.h new file mode 100644 index 000000000000..bd79309fa1cf --- /dev/null +++ b/drivers/clk/exynos/clk-pll.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Samsung Electronics + * Copyright (C) 2023 Linaro Ltd. + * + * Authors: + * Thomas Abraham + * Sam Protsenko + * + * Common Clock Framework support for all PLL's in Samsung platforms. + */ + +#ifndef __EXYNOS_CLK_PLL_H +#define __EXYNOS_CLK_PLL_H + +#include + +enum samsung_pll_type { + pll_0822x, + pll_0831x, +}; + +#endif /* __EXYNOS_CLK_PLL_H */ diff --git a/drivers/clk/exynos/clk.c b/drivers/clk/exynos/clk.c new file mode 100644 index 000000000000..430767f072d8 --- /dev/null +++ b/drivers/clk/exynos/clk.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Linaro Ltd. + * Sam Protsenko + * + * This file includes utility functions to register clocks to common + * clock framework for Samsung platforms. + */ + +#include +#include "clk.h" + +void samsung_clk_register_mux(void __iomem *base, + const struct samsung_mux_clock *clk_list, + unsigned int nr_clk) +{ + unsigned int cnt; + + for (cnt = 0; cnt < nr_clk; cnt++) { + struct clk *clk; + const struct samsung_mux_clock *m; + + m = &clk_list[cnt]; + clk = clk_register_mux(NULL, m->name, m->parent_names, + m->num_parents, m->flags, base + m->offset, m->shift, + m->width, m->mux_flags); + clk_dm(m->id, clk); + } +} + +void samsung_clk_register_div(void __iomem *base, + const struct samsung_div_clock *clk_list, + unsigned int nr_clk) +{ + unsigned int cnt; + + for (cnt = 0; cnt < nr_clk; cnt++) { + struct clk *clk; + const struct samsung_div_clock *d; + + d = &clk_list[cnt]; + clk = clk_register_divider(NULL, d->name, d->parent_name, + d->flags, base + d->offset, d->shift, + d->width, d->div_flags); + clk_dm(d->id, clk); + } +} + +void samsung_clk_register_gate(void __iomem *base, + const struct samsung_gate_clock *clk_list, + unsigned int nr_clk) +{ + unsigned int cnt; + + for (cnt = 0; cnt < nr_clk; cnt++) { + struct clk *clk; + const struct samsung_gate_clock *g; + + g = &clk_list[cnt]; + clk = clk_register_gate(NULL, g->name, g->parent_name, + g->flags, base + g->offset, g->bit_idx, + g->gate_flags, NULL); + clk_dm(g->id, clk); + } +} + +typedef void (*samsung_clk_register_fn)(void __iomem *base, + const void *clk_list, + unsigned int nr_clk); + +static const samsung_clk_register_fn samsung_clk_register_fns[] = { + [S_CLK_MUX] = (samsung_clk_register_fn)samsung_clk_register_mux, + [S_CLK_DIV] = (samsung_clk_register_fn)samsung_clk_register_div, + [S_CLK_GATE] = (samsung_clk_register_fn)samsung_clk_register_gate, + [S_CLK_PLL] = (samsung_clk_register_fn)samsung_clk_register_pll, +}; + +/** + * samsung_cmu_register_clocks() - Register provided clock groups + * @base: Base address of CMU registers + * @clk_groups: list of clock groups + * @nr_groups: count of clock groups in @clk_groups + * + * Having the array of clock groups @clk_groups makes it possible to keep a + * correct clocks registration order. + */ +void samsung_cmu_register_clocks(void __iomem *base, + const struct samsung_clk_group *clk_groups, + unsigned int nr_groups) +{ + unsigned int i; + + for (i = 0; i < nr_groups; i++) { + const struct samsung_clk_group *g = &clk_groups[i]; + + samsung_clk_register_fns[g->type](base, g->clk_list, g->nr_clk); + } +} + +/** + * samsung_cmu_register_one - Register all CMU clocks + * @dev: CMU device + * @clk_groups: list of CMU clock groups + * @nr_groups: count of CMU clock groups in @clk_groups + * + * Return: 0 on success or negative value on error. + */ +int samsung_cmu_register_one(struct udevice *dev, + const struct samsung_clk_group *clk_groups, + unsigned int nr_groups) +{ + void __iomem *base; + + base = dev_read_addr_ptr(dev); + if (!base) + return -EINVAL; + + samsung_cmu_register_clocks(base, clk_groups, nr_groups); + + return 0; +} diff --git a/drivers/clk/exynos/clk.h b/drivers/clk/exynos/clk.h new file mode 100644 index 000000000000..91a51b877a63 --- /dev/null +++ b/drivers/clk/exynos/clk.h @@ -0,0 +1,228 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023 Linaro Ltd. + * Sam Protsenko + * + * Common Clock Framework support for all Samsung platforms. + */ + +#ifndef __EXYNOS_CLK_H +#define __EXYNOS_CLK_H + +#include +#include +#include "clk-pll.h" + +/** + * struct samsung_mux_clock - information about mux clock + * @id: platform specific id of the clock + * @name: name of this mux clock + * @parent_names: array of pointer to parent clock names + * @num_parents: number of parents listed in @parent_names + * @flags: optional flags for basic clock + * @offset: offset of the register for configuring the mux + * @shift: starting bit location of the mux control bit-field in @reg + * @width: width of the mux control bit-field in @reg + * @mux_flags: flags for mux-type clock + */ +struct samsung_mux_clock { + unsigned int id; + const char *name; + const char * const *parent_names; + u8 num_parents; + unsigned long flags; + unsigned long offset; + u8 shift; + u8 width; + u8 mux_flags; +}; + +#define PNAME(x) static const char * const x[] + +#define __MUX(_id, cname, pnames, o, s, w, f, mf) \ + { \ + .id = _id, \ + .name = cname, \ + .parent_names = pnames, \ + .num_parents = ARRAY_SIZE(pnames), \ + .flags = (f) | CLK_SET_RATE_NO_REPARENT, \ + .offset = o, \ + .shift = s, \ + .width = w, \ + .mux_flags = mf, \ + } + +#define MUX(_id, cname, pnames, o, s, w) \ + __MUX(_id, cname, pnames, o, s, w, 0, 0) + +#define MUX_F(_id, cname, pnames, o, s, w, f, mf) \ + __MUX(_id, cname, pnames, o, s, w, f, mf) + +/** + * struct samsung_div_clock - information about div clock + * @id: platform specific id of the clock + * @name: name of this div clock + * @parent_name: name of the parent clock + * @flags: optional flags for basic clock + * @offset: offset of the register for configuring the div + * @shift: starting bit location of the div control bit-field in @reg + * @width: width of the bitfield + * @div_flags: flags for div-type clock + */ +struct samsung_div_clock { + unsigned int id; + const char *name; + const char *parent_name; + unsigned long flags; + unsigned long offset; + u8 shift; + u8 width; + u8 div_flags; +}; + +#define __DIV(_id, cname, pname, o, s, w, f, df) \ + { \ + .id = _id, \ + .name = cname, \ + .parent_name = pname, \ + .flags = f, \ + .offset = o, \ + .shift = s, \ + .width = w, \ + .div_flags = df, \ + } + +#define DIV(_id, cname, pname, o, s, w) \ + __DIV(_id, cname, pname, o, s, w, 0, 0) + +#define DIV_F(_id, cname, pname, o, s, w, f, df) \ + __DIV(_id, cname, pname, o, s, w, f, df) + +/** + * struct samsung_gate_clock - information about gate clock + * @id: platform specific id of the clock + * @name: name of this gate clock + * @parent_name: name of the parent clock + * @flags: optional flags for basic clock + * @offset: offset of the register for configuring the gate + * @bit_idx: bit index of the gate control bit-field in @reg + * @gate_flags: flags for gate-type clock + */ +struct samsung_gate_clock { + unsigned int id; + const char *name; + const char *parent_name; + unsigned long flags; + unsigned long offset; + u8 bit_idx; + u8 gate_flags; +}; + +#define __GATE(_id, cname, pname, o, b, f, gf) \ + { \ + .id = _id, \ + .name = cname, \ + .parent_name = pname, \ + .flags = f, \ + .offset = o, \ + .bit_idx = b, \ + .gate_flags = gf, \ + } + +#define GATE(_id, cname, pname, o, b, f, gf) \ + __GATE(_id, cname, pname, o, b, f, gf) + +/** + * struct samsung_pll_clock - information about pll clock + * @id: platform specific id of the clock + * @name: name of this pll clock + * @parent_name: name of the parent clock + * @flags: optional flags for basic clock + * @con_offset: offset of the register for configuring the PLL + * @type: type of PLL to be registered + */ +struct samsung_pll_clock { + unsigned int id; + const char *name; + const char *parent_name; + unsigned long flags; + int con_offset; + enum samsung_pll_type type; +}; + +#define PLL(_typ, _id, _name, _pname, _con) \ + { \ + .id = _id, \ + .name = _name, \ + .parent_name = _pname, \ + .flags = CLK_GET_RATE_NOCACHE, \ + .con_offset = _con, \ + .type = _typ, \ + } + +enum samsung_clock_type { + S_CLK_MUX, + S_CLK_DIV, + S_CLK_GATE, + S_CLK_PLL, +}; + +/** + * struct samsung_clock_group - contains a list of clocks of one type + * @type: type of clocks this structure contains + * @clk_list: list of clocks + * @nr_clk: count of clocks in @clk_list + */ +struct samsung_clk_group { + enum samsung_clock_type type; + const void *clk_list; + unsigned int nr_clk; +}; + +void samsung_clk_register_mux(void __iomem *base, + const struct samsung_mux_clock *clk_list, + unsigned int nr_clk); +void samsung_clk_register_div(void __iomem *base, + const struct samsung_div_clock *clk_list, + unsigned int nr_clk); +void samsung_clk_register_gate(void __iomem *base, + const struct samsung_gate_clock *clk_list, + unsigned int nr_clk); +void samsung_clk_register_pll(void __iomem *base, + const struct samsung_pll_clock *clk_list, + unsigned int nr_clk); + +void samsung_cmu_register_clocks(void __iomem *base, + const struct samsung_clk_group *clk_groups, + unsigned int nr_groups); +int samsung_cmu_register_one(struct udevice *dev, + const struct samsung_clk_group *clk_groups, + unsigned int nr_groups); + +/** + * samsung_register_cmu - Register CMU clocks ensuring parent CMU is present + * @dev: CMU device + * @clk_groups: list of CMU clock groups + * @parent_drv: name of parent CMU driver + * + * Register provided CMU clocks, but make sure CMU_TOP driver is instantiated + * first. + * + * Return: 0 on success or negative value on error. + */ +#define samsung_register_cmu(dev, clk_groups, parent_drv) \ +({ \ + struct udevice *__parent; \ + int __ret; \ + \ + __ret = uclass_get_device_by_driver(UCLASS_CLK, \ + DM_DRIVER_GET(parent_drv), &__parent); \ + if (__ret || !__parent) \ + __ret = -ENOENT; \ + else \ + __ret = samsung_cmu_register_one(dev, clk_groups, \ + ARRAY_SIZE(clk_groups)); \ + __ret; \ +}) + +#endif /* __EXYNOS_CLK_H */ From patchwork Thu Jan 11 03:09:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 761784 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp2198650wrz; Wed, 10 Jan 2024 19:11:08 -0800 (PST) X-Google-Smtp-Source: AGHT+IGon5bVoaW90TXHAKO/jvVDKH8bjgmuYzpn7IwajiX0NwY8Qjv42/TPEyPNE/XunB6i8RGS X-Received: by 2002:a05:600c:4690:b0:40e:44ac:e7ed with SMTP id p16-20020a05600c469000b0040e44ace7edmr3192wmo.25.1704942668027; Wed, 10 Jan 2024 19:11:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704942668; cv=none; d=google.com; s=arc-20160816; b=FD+4+/M/rYNS4K4GnyI84buBKPZ/qSDwqEXCN0Kf4CJErZe2q7FebCkj85FkFN6p3s fyqKxsvqwzqzv+96ib6TYrO7gYBd2geoj+eXAsrJn32jdHp1jV01vRt67eft+PbB6E0k N/z0Q/9Ba1uVQquSKmg1pETOEPyM/PQav0BjcblqolqFAFHtrPxS5BcKLrY709Vv1HX2 QFz90MnUihg33i1ja66omlolMjWL2ACnTYnyHxVkfaWnyBeycu6mbUvOExdRONmsCnUc HBCyYHVrtoA3q6D6xFgqcOOjd++CrY5YotsLdsxkV/n9IDHKEVeFFd1K3WGDKsD0Qx+e JBmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=3Ex6pMMHhqGEAwaom06S0ZoW3U+HE+HFGWqoIxAKOh4=; fh=PzVE172kMYfD8vsZrdrkQaWk4G6SF+wa//e7xu1cQV0=; b=c26Jo+MczOzw7qKvX6cWJPEYchIH/Cc+fuKB8AtLs/Eiectyd4/ETpwXjVY+MDTch6 u7Tn2e89FAroc2JFBkPBgrR6iL0Ml0L05BTESveshR7KgpkM9ejJdg4j0F/PBpYEDw9B IuSLEX0YrB3DaQkWF8QHTGh9ERDHCDcVXvktzK3I4HHMWON7LpCMXVtguXlBaGcNDGcJ PzLtmzNh3g+Zuq54TraOQ2ev905l4uEKvmEHXSKEglPvRtEwt8Yc/bzuKco2X5PUrvJx GxK+TTg+nbW7g9upWtMFcFISk6VLnpDh/VTANg50vRbneLXH1DjGrUNUcRIdfWO0pb0U Ndwg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=R8ZMKdI9; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id j6-20020a05600c190600b0040d5aef840esi78211wmq.77.2024.01.10.19.11.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 19:11:08 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=R8ZMKdI9; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 14DD887AFB; Thu, 11 Jan 2024 04:09:32 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="R8ZMKdI9"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id D9D4687B18; Thu, 11 Jan 2024 04:09:28 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mail-oi1-x22b.google.com (mail-oi1-x22b.google.com [IPv6:2607:f8b0:4864:20::22b]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id B907687A4B for ; Thu, 11 Jan 2024 04:09:20 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=semen.protsenko@linaro.org Received: by mail-oi1-x22b.google.com with SMTP id 5614622812f47-3bb9b28acb4so3879754b6e.2 for ; Wed, 10 Jan 2024 19:09:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704942559; x=1705547359; darn=lists.denx.de; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3Ex6pMMHhqGEAwaom06S0ZoW3U+HE+HFGWqoIxAKOh4=; b=R8ZMKdI93ZOOSPpYlA0C1uhMilK9u4HXwe5KUZlujowGY6Ms6zAbfj4Qf52SELcvb+ NhT2V75+cZs8a304LoI2TMym+q0FOiVeLqMyUBg/HYSMI71yH8chQgzaelq34yZ78JC/ hXQfxN4U/gC6ut9/Ogkoo/WRCUz0Lmh8BpFO3x7avpdzqfeDRUkfENz76css/81yjlfx HVC9rpUYsitxA4mn4iGNib8DCKJQSZ4skaR+eF7cdd7efT9cqPVPCu5+X9qqQW3bEA0+ Jo7Gpb1hN2gWPR+vjRS6pNtO2QZ8qwQ0AbFOWx3FxoE1Yc+91vXXy1DdA5gBXb2LTdvi EsgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704942559; x=1705547359; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3Ex6pMMHhqGEAwaom06S0ZoW3U+HE+HFGWqoIxAKOh4=; b=Rz7a4G+94t07yKqsaiMd01TqQlR84IgQBnfQ6m3FZ59poDuWU+WBtZrINoexOPNwm1 VSD4AZ1WZ/NKVndAJ/kMtCaqoyAxdayyP/smCrYYCrjbZJoxc2dgsMsuxaxyd9Rhfja5 vNmLGECbSz51qAH8ZtSaLQ/75eVulsX0CYVnbPjzv95ZdazkY/+dMZKLGYDXgJleEo5g cSMXj73be8cbJLmCzbVbxHjtPeiKFGcU9qiSMOzaj1rkIaRNzH5rTq10/GPf7ppAnBgJ iD5J4i/7OK1YCJP90d2G+eSBQ5jrj7zUk3dfwiJRc8ZjztmG9n/2c9yMNbnuKZqv0I17 L9Tw== X-Gm-Message-State: AOJu0YxRQ8xjVxra9EVvBbP+XOFTw3gVFezsvidd8lz9xxkEvm3N/YeY jIJna47YOY/CCs63dNTg5EWY2ibvg6YXIQ== X-Received: by 2002:a05:6808:6501:b0:3b8:60b8:4263 with SMTP id fm1-20020a056808650100b003b860b84263mr837384oib.31.1704942559413; Wed, 10 Jan 2024 19:09:19 -0800 (PST) Received: from localhost ([136.62.192.75]) by smtp.gmail.com with ESMTPSA id bg42-20020a05680817aa00b003bc3d7d3723sm22362oib.11.2024.01.10.19.09.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 19:09:18 -0800 (PST) From: Sam Protsenko To: Minkyu Kang , Tom Rini , Lukasz Majewski , Sean Anderson Cc: Simon Glass , Chanho Park , Heinrich Schuchardt , u-boot@lists.denx.de Subject: [PATCH v2 08/13] clk: exynos: Add Exynos850 clock driver Date: Wed, 10 Jan 2024 21:09:04 -0600 Message-Id: <20240111030909.27373-9-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240111030909.27373-1-semen.protsenko@linaro.org> References: <20240111030909.27373-1-semen.protsenko@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Heavily influenced by its Linux kernel counterpart. It's implemented on top of recently added Samsung CCF clock framework API. For now only UART leaf clocks are implemented, along with all preceding clocks in CMU_TOP and CMU_PERI. The UART baud clock is required in the serial driver, to get its rate for the consequent baud rate calculation. Signed-off-by: Sam Protsenko Reviewed-by: Chanho Park --- Changes in v2: - Added R-b tag drivers/clk/exynos/Kconfig | 7 ++ drivers/clk/exynos/Makefile | 1 + drivers/clk/exynos/clk-exynos850.c | 189 +++++++++++++++++++++++++++++ 3 files changed, 197 insertions(+) create mode 100644 drivers/clk/exynos/clk-exynos850.c diff --git a/drivers/clk/exynos/Kconfig b/drivers/clk/exynos/Kconfig index eb0efa97d15c..85ce9d6e2418 100644 --- a/drivers/clk/exynos/Kconfig +++ b/drivers/clk/exynos/Kconfig @@ -15,4 +15,11 @@ config CLK_EXYNOS7420 This enables common clock driver support for platforms based on Samsung Exynos7420 SoC. +config CLK_EXYNOS850 + bool "Clock driver for Samsung's Exynos850 SoC" + select CLK_CCF + help + This enables common clock driver support for platforms based + on Samsung Exynos850 SoC. + endmenu diff --git a/drivers/clk/exynos/Makefile b/drivers/clk/exynos/Makefile index 04c5b9a39e16..734100e2bff3 100644 --- a/drivers/clk/exynos/Makefile +++ b/drivers/clk/exynos/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-pll.o obj-$(CONFIG_CLK_EXYNOS7420) += clk-exynos7420.o +obj-$(CONFIG_CLK_EXYNOS850) += clk-exynos850.o diff --git a/drivers/clk/exynos/clk-exynos850.c b/drivers/clk/exynos/clk-exynos850.c new file mode 100644 index 000000000000..cf94a3e1b646 --- /dev/null +++ b/drivers/clk/exynos/clk-exynos850.c @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Samsung Exynos850 clock driver. + * Copyright (c) 2023 Linaro Ltd. + * Author: Sam Protsenko + */ + +#include +#include +#include +#include "clk.h" + +/* ---- CMU_TOP ------------------------------------------------------------- */ + +/* Register Offset definitions for CMU_TOP (0x120e0000) */ +#define PLL_CON0_PLL_MMC 0x0100 +#define PLL_CON3_PLL_MMC 0x010c +#define PLL_CON0_PLL_SHARED0 0x0140 +#define PLL_CON3_PLL_SHARED0 0x014c +#define PLL_CON0_PLL_SHARED1 0x0180 +#define PLL_CON3_PLL_SHARED1 0x018c +#define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070 +#define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074 +#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078 +#define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c +#define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880 +#define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884 +#define CLK_CON_DIV_PLL_SHARED0_DIV2 0x188c +#define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1890 +#define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1894 +#define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1898 +#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c +#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0 +#define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080 +#define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084 +#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088 + +static const struct samsung_pll_clock top_pure_pll_clks[] = { + PLL(pll_0822x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "clock-oscclk", + PLL_CON3_PLL_SHARED0), + PLL(pll_0822x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "clock-oscclk", + PLL_CON3_PLL_SHARED1), + PLL(pll_0831x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "clock-oscclk", + PLL_CON3_PLL_MMC), +}; + +/* List of parent clocks for Muxes in CMU_TOP */ +PNAME(mout_shared0_pll_p) = { "clock-oscclk", "fout_shared0_pll" }; +PNAME(mout_shared1_pll_p) = { "clock-oscclk", "fout_shared1_pll" }; +PNAME(mout_mmc_pll_p) = { "clock-oscclk", "fout_mmc_pll" }; +/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */ +PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" }; +PNAME(mout_peri_uart_p) = { "clock-oscclk", "dout_shared0_div4", + "dout_shared1_div4", "clock-oscclk" }; +PNAME(mout_peri_ip_p) = { "clock-oscclk", "dout_shared0_div4", + "dout_shared1_div4", "clock-oscclk" }; + +static const struct samsung_mux_clock top_pure_mux_clks[] = { + MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p, + PLL_CON0_PLL_SHARED0, 4, 1), + MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p, + PLL_CON0_PLL_SHARED1, 4, 1), + MUX(CLK_MOUT_MMC_PLL, "mout_mmc_pll", mout_mmc_pll_p, + PLL_CON0_PLL_MMC, 4, 1), +}; + +static const struct samsung_mux_clock top_peri_mux_clks[] = { + MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p, + CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1), + MUX(CLK_MOUT_PERI_UART, "mout_peri_uart", mout_peri_uart_p, + CLK_CON_MUX_MUX_CLKCMU_PERI_UART, 0, 2), + MUX(CLK_MOUT_PERI_IP, "mout_peri_ip", mout_peri_ip_p, + CLK_CON_MUX_MUX_CLKCMU_PERI_IP, 0, 2), +}; + +static const struct samsung_div_clock top_pure_div_clks[] = { + DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll", + CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), + DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll", + CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), + DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll", + CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), + DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll", + CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), + DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2", + CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), + DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2", + CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), +}; + +static const struct samsung_div_clock top_peri_div_clks[] = { + DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus", + CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4), + DIV(CLK_DOUT_PERI_UART, "dout_peri_uart", "gout_peri_uart", + CLK_CON_DIV_CLKCMU_PERI_UART, 0, 4), + DIV(CLK_DOUT_PERI_IP, "dout_peri_ip", "gout_peri_ip", + CLK_CON_DIV_CLKCMU_PERI_IP, 0, 4), +}; + +static const struct samsung_gate_clock top_peri_gate_clks[] = { + GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus", + CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0), + GATE(CLK_GOUT_PERI_UART, "gout_peri_uart", "mout_peri_uart", + CLK_CON_GAT_GATE_CLKCMU_PERI_UART, 21, 0, 0), + GATE(CLK_GOUT_PERI_IP, "gout_peri_ip", "mout_peri_ip", + CLK_CON_GAT_GATE_CLKCMU_PERI_IP, 21, 0, 0), +}; + +static const struct samsung_clk_group top_cmu_clks[] = { + /* CMU_TOP_PURECLKCOMP */ + { S_CLK_PLL, top_pure_pll_clks, ARRAY_SIZE(top_pure_pll_clks) }, + { S_CLK_MUX, top_pure_mux_clks, ARRAY_SIZE(top_pure_mux_clks) }, + { S_CLK_DIV, top_pure_div_clks, ARRAY_SIZE(top_pure_div_clks) }, + + /* CMU_TOP clocks for CMU_PERI */ + { S_CLK_MUX, top_peri_mux_clks, ARRAY_SIZE(top_peri_mux_clks) }, + { S_CLK_GATE, top_peri_gate_clks, ARRAY_SIZE(top_peri_gate_clks) }, + { S_CLK_DIV, top_peri_div_clks, ARRAY_SIZE(top_peri_div_clks) }, +}; + +static int exynos850_cmu_top_probe(struct udevice *dev) +{ + return samsung_cmu_register_one(dev, top_cmu_clks, + ARRAY_SIZE(top_cmu_clks)); +} + +static const struct udevice_id exynos850_cmu_top_ids[] = { + { .compatible = "samsung,exynos850-cmu-top" }, + { } +}; + +U_BOOT_DRIVER(exynos850_cmu_top) = { + .name = "exynos850-cmu-top", + .id = UCLASS_CLK, + .of_match = exynos850_cmu_top_ids, + .ops = &ccf_clk_ops, + .probe = exynos850_cmu_top_probe, + .flags = DM_FLAG_PRE_RELOC, +}; + +/* ---- CMU_PERI ------------------------------------------------------------ */ + +/* Register Offset definitions for CMU_PERI (0x10030000) */ +#define PLL_CON0_MUX_CLKCMU_PERI_BUS_USER 0x0600 +#define PLL_CON0_MUX_CLKCMU_PERI_UART_USER 0x0630 +#define CLK_CON_GAT_GOUT_PERI_UART_IPCLK 0x20a8 +#define CLK_CON_GAT_GOUT_PERI_UART_PCLK 0x20ac + +/* List of parent clocks for Muxes in CMU_PERI */ +PNAME(mout_peri_bus_user_p) = { "clock-oscclk", "dout_peri_bus" }; +PNAME(mout_peri_uart_user_p) = { "clock-oscclk", "dout_peri_uart" }; + +static const struct samsung_mux_clock peri_mux_clks[] = { + MUX(CLK_MOUT_PERI_BUS_USER, "mout_peri_bus_user", mout_peri_bus_user_p, + PLL_CON0_MUX_CLKCMU_PERI_BUS_USER, 4, 1), + MUX(CLK_MOUT_PERI_UART_USER, "mout_peri_uart_user", + mout_peri_uart_user_p, PLL_CON0_MUX_CLKCMU_PERI_UART_USER, 4, 1), +}; + +static const struct samsung_gate_clock peri_gate_clks[] = { + GATE(CLK_GOUT_UART_IPCLK, "gout_uart_ipclk", "mout_peri_uart_user", + CLK_CON_GAT_GOUT_PERI_UART_IPCLK, 21, 0, 0), + GATE(CLK_GOUT_UART_PCLK, "gout_uart_pclk", "mout_peri_bus_user", + CLK_CON_GAT_GOUT_PERI_UART_PCLK, 21, 0, 0), +}; + +static const struct samsung_clk_group peri_cmu_clks[] = { + { S_CLK_MUX, peri_mux_clks, ARRAY_SIZE(peri_mux_clks) }, + { S_CLK_GATE, peri_gate_clks, ARRAY_SIZE(peri_gate_clks) }, +}; + +static int exynos850_cmu_peri_probe(struct udevice *dev) +{ + return samsung_register_cmu(dev, peri_cmu_clks, exynos850_cmu_top); +} + +static const struct udevice_id exynos850_cmu_peri_ids[] = { + { .compatible = "samsung,exynos850-cmu-peri" }, + { } +}; + +U_BOOT_DRIVER(exynos850_cmu_peri) = { + .name = "exynos850-cmu-peri", + .id = UCLASS_CLK, + .of_match = exynos850_cmu_peri_ids, + .ops = &ccf_clk_ops, + .probe = exynos850_cmu_peri_probe, + .flags = DM_FLAG_PRE_RELOC, +}; From patchwork Thu Jan 11 03:09:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 761785 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp2198703wrz; Wed, 10 Jan 2024 19:11:20 -0800 (PST) X-Google-Smtp-Source: AGHT+IEXoOaB4z4mOMwjEOoB+6vs6hXjBLI6l2t57QVZT5xSxzhfpFwQwRA4ez6aItFED6CmT8ZN X-Received: by 2002:a05:600c:4ecf:b0:40d:3b88:4516 with SMTP id g15-20020a05600c4ecf00b0040d3b884516mr188930wmq.95.1704942680428; Wed, 10 Jan 2024 19:11:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704942680; cv=none; d=google.com; s=arc-20160816; b=x5zmk6m0BQb/t0cNUJQK6jj+TC5myxpre+6Fv+PTuOKY6VUw6BCtw+NqU2RDiL7PZG K+SjZQuDrretbFex7R+Fy/sASJqP9LSUdz8a+Uj8/+MYe61HBeMNuk1LbN0RVnBehTl2 mcm8zCCOIKzelq+QEC44p2Ipz6GTZ5VvDCC/u0WLPqrDdwEVdPbzeL/luSDYoaC6Pz0t ehmu9WoAzBv/5QSqbsbbFU+DzCUdNJ14M8XoUQ6t5kkaryN47lIElqSisEEsJf1uRJo+ cs7S8RoxM9YtVHW5YxQUsSDCWWxN3M5kAzovAH0EJqVmkFHfUB3FEytTojRDpAKJPRWS axPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=MG4e0ucyozZyaMKAPmykBi+fgVMgXa+3BtZ/TcSt97o=; fh=PzVE172kMYfD8vsZrdrkQaWk4G6SF+wa//e7xu1cQV0=; b=Fra3YIFWHERv6LC/RIkLM1qtmSdVpsXXuoo1O5iX9SDZZp4GkWZWiomKAQxeyJeCOo pzGlcNYwM40BEKx0xBnewLVzlYSg08iWyB1EQblwwkUR5DFuVyOwrxK14JiKWKlbVxCO roF2LiEIKpDTwhr6gei/RvJET1r5DEQRFcAP9CksXeaWsTG7gynhRUkUj72gQvZD7/qE z7SmNGcxGIAXYeLIWyCYiQrk+iCc4htBKEGEprMNo6CITz6g/VHWsQB5D2VqsNIBAzDI MxD9lch8e/baXHrPwLQAU2R7QV/Z0W6LddkbEiA9WRtQ9yBD45i5jMmM93t+1AiQO4k5 BiDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pBwI2MVU; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id b20-20020a05600c4e1400b0040e4b343e1esi79313wmq.4.2024.01.10.19.11.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 19:11:20 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pBwI2MVU; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id F41EF87B04; Thu, 11 Jan 2024 04:09:32 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="pBwI2MVU"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id F2E6787613; Thu, 11 Jan 2024 04:09:30 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mail-oa1-x35.google.com (mail-oa1-x35.google.com [IPv6:2001:4860:4864:20::35]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 257FE87AC9 for ; Thu, 11 Jan 2024 04:09:22 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=semen.protsenko@linaro.org Received: by mail-oa1-x35.google.com with SMTP id 586e51a60fabf-20451bc39b1so3073977fac.1 for ; Wed, 10 Jan 2024 19:09:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704942560; x=1705547360; darn=lists.denx.de; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MG4e0ucyozZyaMKAPmykBi+fgVMgXa+3BtZ/TcSt97o=; b=pBwI2MVUIs3jPVT+p3+Lbnm8poJxEthOnsCMmjTZpAMaSN0wBlcYJdOZdVHhRGH0GU 3xpFDm8N+unc9vGMTALlE9469z3a5qqRdlzjMW3l1qtVfziqu6BEjFHWl1/vXvEZ4BvV tpyWFQH2CzqbTq49sZUhPJzohuzZhSZOCy7BO4TQK8ZpqX/chrJMBHiltJd0NFQqCr2C VU94L5wbxf+waBUOTNvcQHrJ+nIlnPqE0HcaUxaNWbj7Xql/BpL84aKLEvBSQyUTdx/6 mivjNYMVZf2PRTycQsZq+bnDO+EiSqaIMoMGBCHWD2ToVc11asod1SVTHokm6c80WeGP K4sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704942560; x=1705547360; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MG4e0ucyozZyaMKAPmykBi+fgVMgXa+3BtZ/TcSt97o=; b=Ss/yC1myNIdNqO4lpAdHw/hIxD3HB6uNDnBg3l7pEcrkp/tUQLLrYyZcK/V39o5AlI yR8SMUsKJphQM/hSDvfgH0xnrk0+u1EJLfLbHp7qmqseDkfeFGhu6zI16KtmLF0fruil nQn8baec2gzwd+bBIbw2uGRcVGL3wyVoXLkqrwAewW5VxAi4uKrMJ9qbJGeRS/vmoDI3 Muq43367pnFAuhi7lkWgN0ySE6ncuLgu2Qf2L/Hy3GMpOFwsAswEJFIt/H16zi/Woegb nsjzGGL551fL7T6sEFGW9VLkZXmI8jIdG/KxF+9jl6g77uw++IQMumK/VyOzao3KWVjf 9OCQ== X-Gm-Message-State: AOJu0YyqgY+UiNT/sBBP2bIcnS8SVlqxFiOU6Cr58pdQyhZwm9xwhQ7U ovay+C+Mf+j2U6yInrGzoJz49mabemWbrA== X-Received: by 2002:a05:6871:7586:b0:204:5026:c9f5 with SMTP id nz6-20020a056871758600b002045026c9f5mr632816oac.91.1704942560267; Wed, 10 Jan 2024 19:09:20 -0800 (PST) Received: from localhost ([136.62.192.75]) by smtp.gmail.com with ESMTPSA id pk3-20020a0568704c0300b00206892f8a80sm4662oab.48.2024.01.10.19.09.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 19:09:19 -0800 (PST) From: Sam Protsenko To: Minkyu Kang , Tom Rini , Lukasz Majewski , Sean Anderson Cc: Simon Glass , Chanho Park , Heinrich Schuchardt , u-boot@lists.denx.de Subject: [PATCH v2 09/13] pinctrl: exynos: Add pinctrl support for Exynos850 Date: Wed, 10 Jan 2024 21:09:05 -0600 Message-Id: <20240111030909.27373-10-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240111030909.27373-1-semen.protsenko@linaro.org> References: <20240111030909.27373-1-semen.protsenko@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add pinctrl support for Exynos850 SoC. It was mostly extracted from corresponding Linux kernel code [1]. Power down modes and external interrupt data were removed while converting the code for U-Boot, but everything else was kept almost unchanged. [1] drivers/pinctrl/samsung/pinctrl-exynos-arm64.c Signed-off-by: Sam Protsenko Reviewed-by: Chanho Park --- Changes in v2: - Fixed driver description in the comment - Added R-b tag drivers/pinctrl/exynos/Kconfig | 8 ++ drivers/pinctrl/exynos/Makefile | 1 + drivers/pinctrl/exynos/pinctrl-exynos850.c | 125 +++++++++++++++++++++ 3 files changed, 134 insertions(+) create mode 100644 drivers/pinctrl/exynos/pinctrl-exynos850.c diff --git a/drivers/pinctrl/exynos/Kconfig b/drivers/pinctrl/exynos/Kconfig index a60f49869b45..1b7fb62bc4ba 100644 --- a/drivers/pinctrl/exynos/Kconfig +++ b/drivers/pinctrl/exynos/Kconfig @@ -16,3 +16,11 @@ config PINCTRL_EXYNOS78x0 help Support pin multiplexing and pin configuration control on Samsung's Exynos78x0 SoC. + +config PINCTRL_EXYNOS850 + bool "Samsung Exynos850 pinctrl driver" + depends on ARCH_EXYNOS && PINCTRL_FULL + select PINCTRL_EXYNOS + help + Support pin multiplexing and pin configuration control on + Samsung's Exynos850 SoC. diff --git a/drivers/pinctrl/exynos/Makefile b/drivers/pinctrl/exynos/Makefile index 07db970ca942..3abe1226eb74 100644 --- a/drivers/pinctrl/exynos/Makefile +++ b/drivers/pinctrl/exynos/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o obj-$(CONFIG_PINCTRL_EXYNOS7420) += pinctrl-exynos7420.o obj-$(CONFIG_PINCTRL_EXYNOS78x0) += pinctrl-exynos78x0.o +obj-$(CONFIG_PINCTRL_EXYNOS850) += pinctrl-exynos850.o diff --git a/drivers/pinctrl/exynos/pinctrl-exynos850.c b/drivers/pinctrl/exynos/pinctrl-exynos850.c new file mode 100644 index 000000000000..3ec2636e0d87 --- /dev/null +++ b/drivers/pinctrl/exynos/pinctrl-exynos850.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Linaro Ltd. + * Author: Sam Protsenko + * + * Exynos850 pinctrl driver. + */ + +#include +#include +#include "pinctrl-exynos.h" + +#define EXYNOS850_PIN_BANK(pins, reg, id) \ + { \ + .type = &exynos850_bank_type, \ + .offset = reg, \ + .nr_pins = pins, \ + .name = id \ + } + +/* CON, DAT, PUD, DRV */ +static const struct samsung_pin_bank_type exynos850_bank_type = { + .fld_width = { 4, 1, 4, 4, }, + .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, +}; + +static const struct pinctrl_ops exynos850_pinctrl_ops = { + .set_state = exynos_pinctrl_set_state +}; + +/* pin banks of exynos850 pin-controller 0 (ALIVE) */ +static const struct samsung_pin_bank_data exynos850_pin_banks0[] = { + EXYNOS850_PIN_BANK(8, 0x000, "gpa0"), + EXYNOS850_PIN_BANK(8, 0x020, "gpa1"), + EXYNOS850_PIN_BANK(8, 0x040, "gpa2"), + EXYNOS850_PIN_BANK(8, 0x060, "gpa3"), + EXYNOS850_PIN_BANK(4, 0x080, "gpa4"), + EXYNOS850_PIN_BANK(3, 0x0a0, "gpq0"), +}; + +/* pin banks of exynos850 pin-controller 1 (CMGP) */ +static const struct samsung_pin_bank_data exynos850_pin_banks1[] = { + EXYNOS850_PIN_BANK(1, 0x000, "gpm0"), + EXYNOS850_PIN_BANK(1, 0x020, "gpm1"), + EXYNOS850_PIN_BANK(1, 0x040, "gpm2"), + EXYNOS850_PIN_BANK(1, 0x060, "gpm3"), + EXYNOS850_PIN_BANK(1, 0x080, "gpm4"), + EXYNOS850_PIN_BANK(1, 0x0a0, "gpm5"), + EXYNOS850_PIN_BANK(1, 0x0c0, "gpm6"), + EXYNOS850_PIN_BANK(1, 0x0e0, "gpm7"), +}; + +/* pin banks of exynos850 pin-controller 2 (AUD) */ +static const struct samsung_pin_bank_data exynos850_pin_banks2[] = { + EXYNOS850_PIN_BANK(5, 0x000, "gpb0"), + EXYNOS850_PIN_BANK(5, 0x020, "gpb1"), +}; + +/* pin banks of exynos850 pin-controller 3 (HSI) */ +static const struct samsung_pin_bank_data exynos850_pin_banks3[] = { + EXYNOS850_PIN_BANK(6, 0x000, "gpf2"), +}; + +/* pin banks of exynos850 pin-controller 4 (CORE) */ +static const struct samsung_pin_bank_data exynos850_pin_banks4[] = { + EXYNOS850_PIN_BANK(4, 0x000, "gpf0"), + EXYNOS850_PIN_BANK(8, 0x020, "gpf1"), +}; + +/* pin banks of exynos850 pin-controller 5 (PERI) */ +static const struct samsung_pin_bank_data exynos850_pin_banks5[] = { + EXYNOS850_PIN_BANK(2, 0x000, "gpg0"), + EXYNOS850_PIN_BANK(6, 0x020, "gpp0"), + EXYNOS850_PIN_BANK(4, 0x040, "gpp1"), + EXYNOS850_PIN_BANK(4, 0x060, "gpp2"), + EXYNOS850_PIN_BANK(8, 0x080, "gpg1"), + EXYNOS850_PIN_BANK(8, 0x0a0, "gpg2"), + EXYNOS850_PIN_BANK(1, 0x0c0, "gpg3"), + EXYNOS850_PIN_BANK(3, 0x0e0, "gpc0"), + EXYNOS850_PIN_BANK(6, 0x100, "gpc1"), +}; + +static const struct samsung_pin_ctrl exynos850_pin_ctrl[] = { + { + /* pin-controller instance 0 ALIVE data */ + .pin_banks = exynos850_pin_banks0, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks0), + }, { + /* pin-controller instance 1 CMGP data */ + .pin_banks = exynos850_pin_banks1, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks1), + }, { + /* pin-controller instance 2 AUD data */ + .pin_banks = exynos850_pin_banks2, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks2), + }, { + /* pin-controller instance 3 HSI data */ + .pin_banks = exynos850_pin_banks3, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks3), + }, { + /* pin-controller instance 4 CORE data */ + .pin_banks = exynos850_pin_banks4, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks4), + }, { + /* pin-controller instance 5 PERI data */ + .pin_banks = exynos850_pin_banks5, + .nr_banks = ARRAY_SIZE(exynos850_pin_banks5), + }, + {/* list terminator */} +}; + +static const struct udevice_id exynos850_pinctrl_ids[] = { + { .compatible = "samsung,exynos850-pinctrl", + .data = (ulong)exynos850_pin_ctrl }, + { } +}; + +U_BOOT_DRIVER(pinctrl_exynos850) = { + .name = "pinctrl_exynos850", + .id = UCLASS_PINCTRL, + .of_match = exynos850_pinctrl_ids, + .priv_auto = sizeof(struct exynos_pinctrl_priv), + .ops = &exynos850_pinctrl_ops, + .probe = exynos_pinctrl_probe, +}; From patchwork Thu Jan 11 03:09:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 761786 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp2198762wrz; Wed, 10 Jan 2024 19:11:31 -0800 (PST) X-Google-Smtp-Source: AGHT+IG4YxQNSQbq67iyiyPKYzheo06MO8qY0Fjm5vxk2BbmJK+6TBdFKny2jL6mPeCG5Y1TvRT+ X-Received: by 2002:adf:e450:0:b0:337:39c7:2a3 with SMTP id t16-20020adfe450000000b0033739c702a3mr192950wrm.129.1704942691170; Wed, 10 Jan 2024 19:11:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704942691; cv=none; d=google.com; s=arc-20160816; b=wPuMVlTibnYnz2cLpSycCRzPTUDKYiErToWy9GdF25ytjKlnD90yzAYnN2sMxkJlwl 83uvWQPpYRNpwLC1r7q/vGCmK8YVE7PitF6g0dlfbDwgjmYvj71F4Z3vfZwDmSriVA8Y dr1ZUijmj5xmRk4C0OZ7DR0axTzdvjQSyRd30gHd5FilX8t/jtQgKal8NaRKUrZWFd94 DjIgm2GZBJuEFEMFHCoiThj29FMkXOPZnYA3xzhjRoXSUNPrTWJpetYnE2dbE8QA/bdc sWRe+f7WFJhgkWPMnAmW4FhLjM5417JWKTcgMd8/AJ6dRxg//TTx+84/wA3uSAea5Vvz 6Lhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=04HwiPFawIqbCII2LGetu6SD9m4mjbVpnnuIHfkRq3I=; fh=PzVE172kMYfD8vsZrdrkQaWk4G6SF+wa//e7xu1cQV0=; b=dQpsfiOEhXpxfiB+8rrk9gNCRKuzKjIBUd24W+/JhT3BF9p3n3/wCDqDOa2Mgtxtvi +yUMwLGuGSk5/30qUR2KbDAtgSwlXakS9zTq7u3fE+StFP5Pn1qqe3656JjaPjSSMD1U 50/l9ICELLxBP5r0agIX4H1n0xXUa8YlTEZAo3peukni6Gz5kyMDl4NKiPfj4x/AsupD RVyfOdT42WiaXumUWFRgtL6EyYK6lNnQWABXnfCuaCN+b3btdp/UR93nu74yOxckCiPJ zqzMdY47xiLmfyzJTCLd2iBsQLip7huNqV6Cyr4d8AJOubNBuPpw8DotTh4lxmzoI2zV fH/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iQCcye+L; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id u1-20020adfa181000000b003374e5434f6si5438wru.894.2024.01.10.19.11.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 19:11:31 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iQCcye+L; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A015187A97; Thu, 11 Jan 2024 04:09:35 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="iQCcye+L"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 987B087B12; Thu, 11 Jan 2024 04:09:32 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mail-oa1-x2b.google.com (mail-oa1-x2b.google.com [IPv6:2001:4860:4864:20::2b]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id AAD9A87B04 for ; Thu, 11 Jan 2024 04:09:22 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=semen.protsenko@linaro.org Received: by mail-oa1-x2b.google.com with SMTP id 586e51a60fabf-203fed05a31so3078132fac.0 for ; Wed, 10 Jan 2024 19:09:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704942561; x=1705547361; darn=lists.denx.de; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=04HwiPFawIqbCII2LGetu6SD9m4mjbVpnnuIHfkRq3I=; b=iQCcye+LzXq6c/6IynFqxkX+35FiSDgtDfMHTeRAR/CBteCTmjndFRP69grcptaKVb Q+n3oWAo3cqZPt0GRkQqQ/PloLqJwDmDsWaaF8e1lSvr9gLpnLcHDXY85M+kWODRf5ml tzX7Yh28cBliLFTLdSknB8qIJQs/T/VPopsfrEqrpAHouZpZ2aMt/mcQ8yNHJBwRcl7d wAByIJMHmKKoPkZ8WvCWC2JNZVEJHJWM2+Nu1JGvGQ6Ug6X74UJSDMSx16k1Fq7VnnHf Zr0Z6hTs12+LZQen3Nmh8eus0UKpfnKvoUk6cU5r79knlPsWTPv8URiSGKnJoUeJN0Ud Qwjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704942561; x=1705547361; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=04HwiPFawIqbCII2LGetu6SD9m4mjbVpnnuIHfkRq3I=; b=d4f8BC8rdbESBf5KRPVJRZ/mSX9WITF7YZo9QJKGhmEzxeqfWNNi1zdY5aaIrvw3ND Pbxvdd01X4lqE60F8mn6Xlw7m8PXv2nxLrRFNhBrHCucNWiwb7ZRt9u+zRNsr+zDESS4 XhqN+i3SCPzj1mkEVDdfEWinoErhZrPnJ98Nh0qC6AaeQhd5R2WovngKT9Fi1iwZj2F7 wDs55LUZw3isbjiu0JKRhGolO8VMc+lgqXgTHh1eW7Jo57t7U7GTkElN1hcNR1phC9UE jX1vTkxv6yDzodK2atMkSW2N1KddDPU3E90pW82f8yeNFY6UfetiEAiOBQu49ljkzRYL 94kA== X-Gm-Message-State: AOJu0Yx8/6DqGNIj9A0E2EUlo2p9FyAGOFPJj0+9U1BaOA1XD9sJrN/A q+Pm4wtvCGAuJobjSBX69OXwj7mG+jtMvg== X-Received: by 2002:a05:6870:ac8c:b0:206:848d:a3e7 with SMTP id ns12-20020a056870ac8c00b00206848da3e7mr680290oab.53.1704942561315; Wed, 10 Jan 2024 19:09:21 -0800 (PST) Received: from localhost ([136.62.192.75]) by smtp.gmail.com with ESMTPSA id mm4-20020a056871728400b002059d4b979bsm8019oac.25.2024.01.10.19.09.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 19:09:20 -0800 (PST) From: Sam Protsenko To: Minkyu Kang , Tom Rini , Lukasz Majewski , Sean Anderson Cc: Simon Glass , Chanho Park , Heinrich Schuchardt , u-boot@lists.denx.de Subject: [PATCH v2 10/13] serial: s5p: Add Exynos850 compatible Date: Wed, 10 Jan 2024 21:09:06 -0600 Message-Id: <20240111030909.27373-11-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240111030909.27373-1-semen.protsenko@linaro.org> References: <20240111030909.27373-1-semen.protsenko@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Enable serial support for Exynos850 SoC by adding the corresponding compatible string. No additional changes needed, the driver works as is on Exynos850. Related USI and PMU configuration is enabled in separate drivers. The only other dependencies are clock and pinctrl drivers, which are already enabled too. Signed-off-by: Sam Protsenko --- Changes in v2: - (none) drivers/serial/serial_s5p.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c index 7d04dcff54fc..801b7645afa4 100644 --- a/drivers/serial/serial_s5p.c +++ b/drivers/serial/serial_s5p.c @@ -257,6 +257,7 @@ static const struct dm_serial_ops s5p_serial_ops = { static const struct udevice_id s5p_serial_ids[] = { { .compatible = "samsung,exynos4210-uart", .data = PORT_S5P }, + { .compatible = "samsung,exynos850-uart", .data = PORT_S5P }, { .compatible = "apple,s5l-uart", .data = PORT_S5L }, { } }; From patchwork Thu Jan 11 03:09:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 761788 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp2198860wrz; Wed, 10 Jan 2024 19:11:53 -0800 (PST) X-Google-Smtp-Source: AGHT+IHrJE3vvGHt0ANTQoFof6aX1rvSdFoeXxtTAIj40/JqAZRI5HthkduZ6aJEhmDPiIgyq4EE X-Received: by 2002:adf:f0cc:0:b0:336:835e:7e06 with SMTP id x12-20020adff0cc000000b00336835e7e06mr200554wro.9.1704942713033; Wed, 10 Jan 2024 19:11:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704942713; cv=none; d=google.com; s=arc-20160816; b=SLGkBmzaozzSxv3vngIP4Voh8sBdmMOqWvK7pX42/aDRaOfh2+cQf3WV7ZVUJDApyq m8ECTHZ12PhwgSSXPK9O5sslyjQSSwdwGzAXla7nogJUqUb4FmMdZX7xFwC4exXc8ztI OC3MABfc42AH+ddwg6DYUnqKgoqetGf6/sL+SKDqGlp4h2Yn4nGLUKfIK67PmJ770EpM EloUaXaD6zgomglUneMs/Ki4K2hnmU3vnNcI6iUkw1pCiQR5odJq21q48YGvzKquAwcW nBu14ez0/qG7zBETj+iinDz32XYV/8FVIR5a1ilsblpOEMA1gDfzbUPJegwBLoYL+bSx FA1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=+Lb7nfTrnMk79YIj0fD79ZuXIH7gSXGq4RJBnrduuTQ=; fh=PzVE172kMYfD8vsZrdrkQaWk4G6SF+wa//e7xu1cQV0=; b=kbbZpbpRfF0N4pJaKT+fNgdX+Hr9rX7i9Vb3V6/BPO+spJICqJfQv0NgCUTzFHmpP+ U8Sn5Bhs9V4GiPFX0Z77ISAQAJ0yPeDVkdM0XUdUVsz/RiZtnIrqagfxulCtA/gLpv+P wTFm2n28y3QOrrjByC+4X4eEnWxKyoc26fsejC/35+tNZsp4xa8EW3Hds0KC+uVRw9SS EUWZlGRUzWqUcdzNBUk1sTbvj70FrPz+7rBhmF/DG3gKSzsz2V24FHz9V6kv9wILKHgx Jz5sd5yOuNDh86m1M39JUhjj4swuNY+w5K+lTvnXdzw/7Az2nGaDptn4iRTzTyrbCBH+ 80/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=W0VouxU6; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id c14-20020a5d414e000000b0033684327428si13634wrq.123.2024.01.10.19.11.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 19:11:53 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=W0VouxU6; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E631287A7F; Thu, 11 Jan 2024 04:09:40 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="W0VouxU6"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 24BF987613; Thu, 11 Jan 2024 04:09:39 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mail-ot1-x32d.google.com (mail-ot1-x32d.google.com [IPv6:2607:f8b0:4864:20::32d]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id E811887A80 for ; Thu, 11 Jan 2024 04:09:23 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=semen.protsenko@linaro.org Received: by mail-ot1-x32d.google.com with SMTP id 46e09a7af769-6ddeb09bc68so905624a34.1 for ; Wed, 10 Jan 2024 19:09:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704942562; x=1705547362; darn=lists.denx.de; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+Lb7nfTrnMk79YIj0fD79ZuXIH7gSXGq4RJBnrduuTQ=; b=W0VouxU6PN3gr9N/V5JhdVmJTI6ObYM+CeJKqEXBApWqU9tiUcLhNYK0VWo5PO/uk1 BVQW7LARvqrhLvYNj0C9VWZWyqCPq36JDQMmyX2GiW48UUYYCXHL+tBbetfqzINhr5K+ W5qlUb0+Whn0wfjRNLBuqugZgeJD/Ntr4LM+4O56rOh6pzog6eHdMjUCyOFtRzbM36JX FqKanAXbEJulGkogHLQ0bfehhWcIMb6d6BRPwJP1kJ5aytiRgJq2ph5H/yvY2cafReQz i6nffyVYWA44ky7DBmNYpiZoQo5rTuyjzupOJsY5/1c+2HeKxnc5+bFIRufo9muMMBc3 wCZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704942562; x=1705547362; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+Lb7nfTrnMk79YIj0fD79ZuXIH7gSXGq4RJBnrduuTQ=; b=ZA2rxsyWxH8AmVt8INiPQ1smr7Zq80RLQjOHCb3zP3QL5QT91Ft12zYSfUjsHTXoi+ Jf9FxfWUobK2oZ78DxvWo2JnnKYo0b4OBrIZDSjwl2VO7dxaccHbjvGyrzPs+nfugFFB KcPLtGfKIpVNlvDz9ory06N06KxwaP/RjujY144GUfOdqG1vIcbRs5uBp2eo7CWiXT6E VuSO5sfAQaGjoUbSkOtsp4o+rNFnHKAL18/5AizgmjRC34KgY+LadqqZw+ECv+8B3m8x wEbEZSef2HDuWHT9S8P8edR4C+kOWyblNLkje32Z81BkEgi/gcDXLJvCRCXTLh6Kl2O4 3dYQ== X-Gm-Message-State: AOJu0YziOyhnXEnlWQoLgmygQNiyMQFu+P6XGkcsabYUBQcd1wleHi9X h8gJkiiG6gqHhEGxLXcvSvPUAdgNFl3AQQ== X-Received: by 2002:a05:6830:1548:b0:6dd:df24:3fb3 with SMTP id l8-20020a056830154800b006dddf243fb3mr37441otp.27.1704942562440; Wed, 10 Jan 2024 19:09:22 -0800 (PST) Received: from localhost ([136.62.192.75]) by smtp.gmail.com with ESMTPSA id 127-20020a4a0685000000b005944c7f6bb6sm12508ooj.29.2024.01.10.19.09.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 19:09:21 -0800 (PST) From: Sam Protsenko To: Minkyu Kang , Tom Rini , Lukasz Majewski , Sean Anderson Cc: Simon Glass , Chanho Park , Heinrich Schuchardt , u-boot@lists.denx.de Subject: [PATCH v2 11/13] arm: exynos: Add Exynos850 SoC support Date: Wed, 10 Jan 2024 21:09:07 -0600 Message-Id: <20240111030909.27373-12-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240111030909.27373-1-semen.protsenko@linaro.org> References: <20240111030909.27373-1-semen.protsenko@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Samsung Exynos850 is ARMv8-based mobile-oriented SoC. It features Cortex-A55 CPU (8 cores) and it's built using 8nm process. Add Exynos850 support by enabling next features: * Import Exynos850 SoC dtsi files from Linux kernel * Add Exynos850 MMU memory map * Introduce ARCH_EXYNOS9 platform config option Signed-off-by: Sam Protsenko --- Changes in v2: - (none) arch/arm/dts/exynos-pinctrl.h | 79 +++ arch/arm/dts/exynos850-pinctrl.dtsi | 663 +++++++++++++++++++++++ arch/arm/dts/exynos850.dtsi | 809 ++++++++++++++++++++++++++++ arch/arm/mach-exynos/Kconfig | 9 + arch/arm/mach-exynos/mmu-arm64.c | 34 ++ 5 files changed, 1594 insertions(+) create mode 100644 arch/arm/dts/exynos-pinctrl.h create mode 100644 arch/arm/dts/exynos850-pinctrl.dtsi create mode 100644 arch/arm/dts/exynos850.dtsi diff --git a/arch/arm/dts/exynos-pinctrl.h b/arch/arm/dts/exynos-pinctrl.h new file mode 100644 index 000000000000..7dd94a9b3652 --- /dev/null +++ b/arch/arm/dts/exynos-pinctrl.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Samsung Exynos DTS pinctrl constants + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Copyright (c) 2022 Linaro Ltd + * Author: Krzysztof Kozlowski + */ + +#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__ +#define __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__ + +#define EXYNOS_PIN_PULL_NONE 0 +#define EXYNOS_PIN_PULL_DOWN 1 +#define EXYNOS_PIN_PULL_UP 3 + +/* Pin function in power down mode */ +#define EXYNOS_PIN_PDN_OUT0 0 +#define EXYNOS_PIN_PDN_OUT1 1 +#define EXYNOS_PIN_PDN_INPUT 2 +#define EXYNOS_PIN_PDN_PREV 3 + +/* + * Drive strengths for Exynos5410, Exynos542x, Exynos5800, Exynos7885, Exynos850 + * (except GPIO_HSI block), ExynosAutov9 (FSI0, PERIC1) + */ +#define EXYNOS5420_PIN_DRV_LV1 0 +#define EXYNOS5420_PIN_DRV_LV2 1 +#define EXYNOS5420_PIN_DRV_LV3 2 +#define EXYNOS5420_PIN_DRV_LV4 3 + +/* Drive strengths for Exynos5433 */ +#define EXYNOS5433_PIN_DRV_FAST_SR1 0 +#define EXYNOS5433_PIN_DRV_FAST_SR2 1 +#define EXYNOS5433_PIN_DRV_FAST_SR3 2 +#define EXYNOS5433_PIN_DRV_FAST_SR4 3 +#define EXYNOS5433_PIN_DRV_FAST_SR5 4 +#define EXYNOS5433_PIN_DRV_FAST_SR6 5 +#define EXYNOS5433_PIN_DRV_SLOW_SR1 8 +#define EXYNOS5433_PIN_DRV_SLOW_SR2 9 +#define EXYNOS5433_PIN_DRV_SLOW_SR3 0xa +#define EXYNOS5433_PIN_DRV_SLOW_SR4 0xb +#define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc +#define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf + +/* Drive strengths for Exynos7 (except FSYS1) */ +#define EXYNOS7_PIN_DRV_LV1 0 +#define EXYNOS7_PIN_DRV_LV2 2 +#define EXYNOS7_PIN_DRV_LV3 1 +#define EXYNOS7_PIN_DRV_LV4 3 + +/* Drive strengths for Exynos7 FSYS1 block */ +#define EXYNOS7_FSYS1_PIN_DRV_LV1 0 +#define EXYNOS7_FSYS1_PIN_DRV_LV2 4 +#define EXYNOS7_FSYS1_PIN_DRV_LV3 2 +#define EXYNOS7_FSYS1_PIN_DRV_LV4 6 +#define EXYNOS7_FSYS1_PIN_DRV_LV5 1 +#define EXYNOS7_FSYS1_PIN_DRV_LV6 5 + +/* Drive strengths for Exynos850 GPIO_HSI block */ +#define EXYNOS850_HSI_PIN_DRV_LV1 0 /* 1x */ +#define EXYNOS850_HSI_PIN_DRV_LV1_5 1 /* 1.5x */ +#define EXYNOS850_HSI_PIN_DRV_LV2 2 /* 2x */ +#define EXYNOS850_HSI_PIN_DRV_LV2_5 3 /* 2.5x */ +#define EXYNOS850_HSI_PIN_DRV_LV3 4 /* 3x */ +#define EXYNOS850_HSI_PIN_DRV_LV4 5 /* 4x */ + +#define EXYNOS_PIN_FUNC_INPUT 0 +#define EXYNOS_PIN_FUNC_OUTPUT 1 +#define EXYNOS_PIN_FUNC_2 2 +#define EXYNOS_PIN_FUNC_3 3 +#define EXYNOS_PIN_FUNC_4 4 +#define EXYNOS_PIN_FUNC_5 5 +#define EXYNOS_PIN_FUNC_6 6 +#define EXYNOS_PIN_FUNC_EINT 0xf +#define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT + +#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_PINCTRL_H__ */ diff --git a/arch/arm/dts/exynos850-pinctrl.dtsi b/arch/arm/dts/exynos850-pinctrl.dtsi new file mode 100644 index 000000000000..424bc80bde68 --- /dev/null +++ b/arch/arm/dts/exynos850-pinctrl.dtsi @@ -0,0 +1,663 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos850 SoC pin-mux and pin-config device tree source + * + * Copyright (C) 2017 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Samsung's Exynos850 SoC pin-mux and pin-config options are listed as device + * tree nodes in this file. + */ + +#include +#include "exynos-pinctrl.h" + +&pinctrl_alive { + gpa0: gpa0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa1: gpa1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa2: gpa2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa3: gpa3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + ; + }; + + gpa4: gpa4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + gpq0: gpq0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + /* I2C5 (also called CAM_PMIC_I2C in TRM) */ + i2c5_pins: i2c5-pins { + samsung,pins = "gpa3-5", "gpa3-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* I2C6 (also called MOTOR_I2C in TRM) */ + i2c6_pins: i2c6-pins { + samsung,pins = "gpa3-7", "gpa4-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* USI: UART_DEBUG_0 pins */ + uart0_pins: uart0-pins { + samsung,pins = "gpq0-0", "gpq0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI: UART_DEBUG_1 pins */ + uart1_pins: uart1-pins { + samsung,pins = "gpa3-7", "gpa4-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +&pinctrl_cmgp { + gpm0: gpm0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm1: gpm1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm2: gpm2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm3: gpm3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm4: gpm4-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm5: gpm5-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm6: gpm6-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + gpm7: gpm7-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + /* USI_CMGP0: HSI2C function */ + hsi2c3_pins: hsi2c3-pins { + samsung,pins = "gpm0-0", "gpm1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* USI_CMGP0: UART function (4 pins, Auto Flow Control) */ + uart1_single_pins: uart1-single-pins { + samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI_CMGP0: UART function (2 pins, Non-Auto Flow Control) */ + uart1_dual_pins: uart1-dual-pins { + samsung,pins = "gpm0-0", "gpm1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI_CMGP0: SPI function */ + spi1_pins: spi1-pins { + samsung,pins = "gpm0-0", "gpm1-0", "gpm2-0", "gpm3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* USI_CMGP1: HSI2C function */ + hsi2c4_pins: hsi2c4-pins { + samsung,pins = "gpm4-0", "gpm5-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* USI_CMGP1: UART function (4 pins, Auto Flow Control) */ + uart2_single_pins: uart2-single-pins { + samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI_CMGP1: UART function (2 pins, Non-Auto Flow Control) */ + uart2_dual_pins: uart2-dual-pins { + samsung,pins = "gpm4-0", "gpm5-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + /* USI_CMGP1: SPI function */ + spi2_pins: spi2-pins { + samsung,pins = "gpm4-0", "gpm5-0", "gpm6-0", "gpm7-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_aud { + gpb0: gpb0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb1: gpb1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + aud_codec_mclk_pins: aud-codec-mclk-pins { + samsung,pins = "gpb0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_codec_mclk_idle_pins: aud-codec-mclk-idle-pins { + samsung,pins = "gpb0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_i2s0_pins: aud-i2s0-pins { + samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_i2s0_idle_pins: aud-i2s0-idle-pins { + samsung,pins = "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_i2s1_pins: aud-i2s1-pins { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_i2s1_idle_pins: aud-i2s1-idle-pins { + samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_fm_pins: aud-fm-pins { + samsung,pins = "gpb1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + aud_fm_idle_pins: aud-fm-idle-pins { + samsung,pins = "gpb1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +&pinctrl_hsi { + gpf2: gpf2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd2_clk_pins: sd2-clk-pins { + samsung,pins = "gpf2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_cmd_pins: sd2-cmd-pins { + samsung,pins = "gpf2-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus1_pins: sd2-bus1-pins { + samsung,pins = "gpf2-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_bus4_pins: sd2-bus4-pins { + samsung,pins = "gpf2-3", "gpf2-4", "gpf2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd2_pdn_pins: sd2-pdn-pins { + samsung,pins = "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", + "gpf2-4", "gpf2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +&pinctrl_core { + gpf0: gpf0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd0_clk_pins: sd0-clk-pins { + samsung,pins = "gpf0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_cmd_pins: sd0-cmd-pins { + samsung,pins = "gpf0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_rdqs_pins: sd0-rdqs-pins { + samsung,pins = "gpf0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_nreset_pins: sd0-nreset-pins { + samsung,pins = "gpf0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus1_pins: sd0-bus1-pins { + samsung,pins = "gpf1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus4_pins: sd0-bus4-pins { + samsung,pins = "gpf1-1", "gpf1-2", "gpf1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sd0_bus8_pins: sd0-bus8-pins { + samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_peri { + gpc0: gpc0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg0: gpg0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg1: gpg1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg2: gpg2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpg3: gpg3-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp0: gpp0-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + gpp1: gpp1-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpp2: gpp2-gpio-bank { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sensor_mclk0_in_pins: sensor-mclk0-in-pins { + samsung,pins = "gpc0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk0_out_pins: sensor-mclk0-out-pins { + samsung,pins = "gpc0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk0_fn_pins: sensor-mclk0-fn-pins { + samsung,pins = "gpc0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk1_in_pins: sensor-mclk1-in-pins { + samsung,pins = "gpc0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk1_out_pins: sensor-mclk1-out-pins { + samsung,pins = "gpc0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk1_fn_pins: sensor-mclk1-fn-pins { + samsung,pins = "gpc0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk2_in_pins: sensor-mclk2-in-pins { + samsung,pins = "gpc0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk2_out_pins: sensor-mclk2-out-pins { + samsung,pins = "gpc0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sensor_mclk2_fn_pins: sensor-mclk2-fn-pins { + samsung,pins = "gpc0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* USI: HSI2C0 */ + hsi2c0_pins: hsi2c0-pins { + samsung,pins = "gpc1-0", "gpc1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* USI: HSI2C1 */ + hsi2c1_pins: hsi2c1-pins { + samsung,pins = "gpc1-2", "gpc1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* USI: HSI2C2 */ + hsi2c2_pins: hsi2c2-pins { + samsung,pins = "gpc1-4", "gpc1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + /* USI: SPI */ + spi0_pins: spi0-pins { + samsung,pins = "gpp2-0", "gpp2-1", "gpp2-2", "gpp2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c0_pins: i2c0-pins { + samsung,pins = "gpp0-0", "gpp0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c1_pins: i2c1-pins { + samsung,pins = "gpp0-2", "gpp0-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c2_pins: i2c2-pins { + samsung,pins = "gpp0-4", "gpp0-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c3_pins: i2c3-pins { + samsung,pins = "gpp1-0", "gpp1-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + i2c4_pins: i2c4-pins { + samsung,pins = "gpp1-2", "gpp1-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + xclkout_pins: xclkout-pins { + samsung,pins = "gpq0-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; diff --git a/arch/arm/dts/exynos850.dtsi b/arch/arm/dts/exynos850.dtsi new file mode 100644 index 000000000000..53104e65b9c6 --- /dev/null +++ b/arch/arm/dts/exynos850.dtsi @@ -0,0 +1,809 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung Exynos850 SoC device tree source + * + * Copyright (C) 2018 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Samsung Exynos850 SoC device nodes are listed in this file. + * Exynos850 based board files can include this file and provide + * values for board specific bindings. + */ + +#include +#include +#include + +/ { + /* Also known under engineering name Exynos3830 */ + compatible = "samsung,exynos850"; + #address-cells = <2>; + #size-cells = <1>; + + interrupt-parent = <&gic>; + + aliases { + pinctrl0 = &pinctrl_alive; + pinctrl1 = &pinctrl_cmgp; + pinctrl2 = &pinctrl_aud; + pinctrl3 = &pinctrl_hsi; + pinctrl4 = &pinctrl_core; + pinctrl5 = &pinctrl_peri; + }; + + arm-pmu { + compatible = "arm,cortex-a55-pmu"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, + <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + }; + + /* Main system clock (XTCXO); external, must be 26 MHz */ + oscclk: clock-oscclk { + compatible = "fixed-clock"; + clock-output-names = "oscclk"; + #clock-cells = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x1>; + enable-method = "psci"; + }; + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x2>; + enable-method = "psci"; + }; + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x3>; + enable-method = "psci"; + }; + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + }; + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x101>; + enable-method = "psci"; + }; + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x102>; + enable-method = "psci"; + }; + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x103>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + /* Hypervisor Virtual Timer interrupt is not wired to GIC */ + interrupts = + , + , + , + ; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x0 0x20000000>; + + chipid@10000000 { + compatible = "samsung,exynos850-chipid"; + reg = <0x10000000 0x100>; + }; + + timer@10040000 { + compatible = "samsung,exynos850-mct", + "samsung,exynos4210-mct"; + reg = <0x10040000 0x800>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&oscclk>, <&cmu_peri CLK_GOUT_MCT_PCLK>; + clock-names = "fin_pll", "mct"; + }; + + gic: interrupt-controller@12a01000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + reg = <0x12a01000 0x1000>, + <0x12a02000 0x2000>, + <0x12a04000 0x2000>, + <0x12a06000 0x2000>; + interrupt-controller; + interrupts = ; + }; + + pmu_system_controller: system-controller@11860000 { + compatible = "samsung,exynos850-pmu", "syscon"; + reg = <0x11860000 0x10000>; + + reboot: syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pmu_system_controller>; + offset = <0x3a00>; /* SYSTEM_CONFIGURATION */ + mask = <0x2>; /* SWRESET_SYSTEM */ + value = <0x2>; /* reset value */ + }; + }; + + watchdog_cl0: watchdog@10050000 { + compatible = "samsung,exynos850-wdt"; + reg = <0x10050000 0x100>; + interrupts = ; + clocks = <&cmu_peri CLK_GOUT_WDT0_PCLK>, <&oscclk>; + clock-names = "watchdog", "watchdog_src"; + samsung,syscon-phandle = <&pmu_system_controller>; + samsung,cluster-index = <0>; + status = "disabled"; + }; + + watchdog_cl1: watchdog@10060000 { + compatible = "samsung,exynos850-wdt"; + reg = <0x10060000 0x100>; + interrupts = ; + clocks = <&cmu_peri CLK_GOUT_WDT1_PCLK>, <&oscclk>; + clock-names = "watchdog", "watchdog_src"; + samsung,syscon-phandle = <&pmu_system_controller>; + samsung,cluster-index = <1>; + status = "disabled"; + }; + + cmu_peri: clock-controller@10030000 { + compatible = "samsung,exynos850-cmu-peri"; + reg = <0x10030000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>, + <&cmu_top CLK_DOUT_PERI_UART>, + <&cmu_top CLK_DOUT_PERI_IP>; + clock-names = "oscclk", "dout_peri_bus", + "dout_peri_uart", "dout_peri_ip"; + }; + + cmu_g3d: clock-controller@11400000 { + compatible = "samsung,exynos850-cmu-g3d"; + reg = <0x11400000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_G3D_SWITCH>; + clock-names = "oscclk", "dout_g3d_switch"; + }; + + cmu_apm: clock-controller@11800000 { + compatible = "samsung,exynos850-cmu-apm"; + reg = <0x11800000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_CLKCMU_APM_BUS>; + clock-names = "oscclk", "dout_clkcmu_apm_bus"; + }; + + cmu_cmgp: clock-controller@11c00000 { + compatible = "samsung,exynos850-cmu-cmgp"; + reg = <0x11c00000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_apm CLK_GOUT_CLKCMU_CMGP_BUS>; + clock-names = "oscclk", "gout_clkcmu_cmgp_bus"; + }; + + cmu_core: clock-controller@12000000 { + compatible = "samsung,exynos850-cmu-core"; + reg = <0x12000000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_CORE_BUS>, + <&cmu_top CLK_DOUT_CORE_CCI>, + <&cmu_top CLK_DOUT_CORE_MMC_EMBD>, + <&cmu_top CLK_DOUT_CORE_SSS>; + clock-names = "oscclk", "dout_core_bus", + "dout_core_cci", "dout_core_mmc_embd", + "dout_core_sss"; + }; + + cmu_top: clock-controller@120e0000 { + compatible = "samsung,exynos850-cmu-top"; + reg = <0x120e0000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>; + clock-names = "oscclk"; + }; + + cmu_mfcmscl: clock-controller@12c00000 { + compatible = "samsung,exynos850-cmu-mfcmscl"; + reg = <0x12c00000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_MFCMSCL_MFC>, + <&cmu_top CLK_DOUT_MFCMSCL_M2M>, + <&cmu_top CLK_DOUT_MFCMSCL_MCSC>, + <&cmu_top CLK_DOUT_MFCMSCL_JPEG>; + clock-names = "oscclk", "dout_mfcmscl_mfc", + "dout_mfcmscl_m2m", "dout_mfcmscl_mcsc", + "dout_mfcmscl_jpeg"; + }; + + cmu_dpu: clock-controller@13000000 { + compatible = "samsung,exynos850-cmu-dpu"; + reg = <0x13000000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_DPU>; + clock-names = "oscclk", "dout_dpu"; + }; + + cmu_hsi: clock-controller@13400000 { + compatible = "samsung,exynos850-cmu-hsi"; + reg = <0x13400000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_HSI_BUS>, + <&cmu_top CLK_DOUT_HSI_MMC_CARD>, + <&cmu_top CLK_DOUT_HSI_USB20DRD>; + clock-names = "oscclk", "dout_hsi_bus", + "dout_hsi_mmc_card", "dout_hsi_usb20drd"; + }; + + cmu_is: clock-controller@14500000 { + compatible = "samsung,exynos850-cmu-is"; + reg = <0x14500000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_IS_BUS>, + <&cmu_top CLK_DOUT_IS_ITP>, + <&cmu_top CLK_DOUT_IS_VRA>, + <&cmu_top CLK_DOUT_IS_GDC>; + clock-names = "oscclk", "dout_is_bus", "dout_is_itp", + "dout_is_vra", "dout_is_gdc"; + }; + + cmu_aud: clock-controller@14a00000 { + compatible = "samsung,exynos850-cmu-aud"; + reg = <0x14a00000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_AUD>; + clock-names = "oscclk", "dout_aud"; + }; + + pinctrl_alive: pinctrl@11850000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x11850000 0x1000>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos850-wakeup-eint"; + }; + }; + + pinctrl_cmgp: pinctrl@11c30000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x11c30000 0x1000>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos850-wakeup-eint"; + }; + }; + + pinctrl_core: pinctrl@12070000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x12070000 0x1000>; + interrupts = ; + }; + + pinctrl_hsi: pinctrl@13430000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x13430000 0x1000>; + interrupts = ; + }; + + pinctrl_peri: pinctrl@139b0000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x139b0000 0x1000>; + interrupts = ; + }; + + pinctrl_aud: pinctrl@14a60000 { + compatible = "samsung,exynos850-pinctrl"; + reg = <0x14a60000 0x1000>; + }; + + rtc: rtc@11a30000 { + compatible = "samsung,s3c6410-rtc"; + reg = <0x11a30000 0x100>; + interrupts = , + ; + clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>; + clock-names = "rtc"; + status = "disabled"; + }; + + mmc_0: mmc@12100000 { + compatible = "samsung,exynos7-dw-mshc-smu"; + reg = <0x12100000 0x2000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu_core CLK_GOUT_MMC_EMBD_ACLK>, + <&cmu_core CLK_GOUT_MMC_EMBD_SDCLKIN>; + clock-names = "biu", "ciu"; + fifo-depth = <0x40>; + status = "disabled"; + }; + + i2c_0: i2c@13830000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13830000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clocks = <&cmu_peri CLK_GOUT_I2C0_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + i2c_1: i2c@13840000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13840000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clocks = <&cmu_peri CLK_GOUT_I2C1_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + i2c_2: i2c@13850000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13850000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + clocks = <&cmu_peri CLK_GOUT_I2C2_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + i2c_3: i2c@13860000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13860000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clocks = <&cmu_peri CLK_GOUT_I2C3_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + i2c_4: i2c@13870000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13870000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + clocks = <&cmu_peri CLK_GOUT_I2C4_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + /* I2C_5 (also called CAM_PMIC_I2C in TRM) */ + i2c_5: i2c@13880000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13880000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins>; + clocks = <&cmu_peri CLK_GOUT_I2C5_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + /* I2C_6 (also called MOTOR_I2C in TRM) */ + i2c_6: i2c@13890000 { + compatible = "samsung,s3c2440-i2c"; + reg = <0x13890000 0x100>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins>; + clocks = <&cmu_peri CLK_GOUT_I2C6_PCLK>; + clock-names = "i2c"; + status = "disabled"; + }; + + sysmmu_mfcmscl: sysmmu@12c50000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12c50000 0x9000>; + interrupts = ; + clock-names = "sysmmu"; + clocks = <&cmu_mfcmscl CLK_GOUT_MFCMSCL_SYSMMU_CLK>; + #iommu-cells = <0>; + }; + + sysmmu_dpu: sysmmu@130c0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x130c0000 0x9000>; + interrupts = ; + clock-names = "sysmmu"; + clocks = <&cmu_dpu CLK_GOUT_DPU_SMMU_CLK>; + #iommu-cells = <0>; + }; + + sysmmu_is0: sysmmu@14550000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14550000 0x9000>; + interrupts = ; + clock-names = "sysmmu"; + clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS0_CLK>; + #iommu-cells = <0>; + }; + + sysmmu_is1: sysmmu@14570000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14570000 0x9000>; + interrupts = ; + clock-names = "sysmmu"; + clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS1_CLK>; + #iommu-cells = <0>; + }; + + sysmmu_aud: sysmmu@14850000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x14850000 0x9000>; + interrupts = ; + clock-names = "sysmmu"; + clocks = <&cmu_aud CLK_GOUT_AUD_SYSMMU_CLK>; + #iommu-cells = <0>; + }; + + sysreg_peri: syscon@10020000 { + compatible = "samsung,exynos850-peri-sysreg", + "samsung,exynos850-sysreg", "syscon"; + reg = <0x10020000 0x10000>; + clocks = <&cmu_peri CLK_GOUT_SYSREG_PERI_PCLK>; + }; + + sysreg_cmgp: syscon@11c20000 { + compatible = "samsung,exynos850-cmgp-sysreg", + "samsung,exynos850-sysreg", "syscon"; + reg = <0x11c20000 0x10000>; + clocks = <&cmu_cmgp CLK_GOUT_SYSREG_CMGP_PCLK>; + }; + + usbdrd: usb@13600000 { + compatible = "samsung,exynos850-dwusb3"; + ranges = <0x0 0x13600000 0x10000>; + clocks = <&cmu_hsi CLK_GOUT_USB_BUS_EARLY_CLK>, + <&cmu_hsi CLK_GOUT_USB_REF_CLK>; + clock-names = "bus_early", "ref"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + usbdrd_dwc3: usb@0 { + compatible = "snps,dwc3"; + reg = <0x0 0x10000>; + interrupts = ; + phys = <&usbdrd_phy 0>; + phy-names = "usb2-phy"; + }; + }; + + usbdrd_phy: phy@135d0000 { + compatible = "samsung,exynos850-usbdrd-phy"; + reg = <0x135d0000 0x100>; + clocks = <&cmu_hsi CLK_GOUT_USB_PHY_ACLK>, + <&cmu_hsi CLK_GOUT_USB_PHY_REF_CLK>; + clock-names = "phy", "ref"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <1>; + status = "disabled"; + }; + + usi_uart: usi@138200c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x138200c0 0x20>; + samsung,sysreg = <&sysreg_peri 0x1010>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peri CLK_GOUT_UART_PCLK>, + <&cmu_peri CLK_GOUT_UART_IPCLK>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + serial_0: serial@13820000 { + compatible = "samsung,exynos850-uart"; + reg = <0x13820000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + clocks = <&cmu_peri CLK_GOUT_UART_PCLK>, + <&cmu_peri CLK_GOUT_UART_IPCLK>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + }; + + usi_hsi2c_0: usi@138a00c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x138a00c0 0x20>; + samsung,sysreg = <&sysreg_peri 0x1020>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peri CLK_GOUT_HSI2C0_PCLK>, + <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_0: i2c@138a0000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x138a0000 0xc0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c0_pins>; + clocks = <&cmu_peri CLK_GOUT_HSI2C0_IPCLK>, + <&cmu_peri CLK_GOUT_HSI2C0_PCLK>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + }; + + usi_hsi2c_1: usi@138b00c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x138b00c0 0x20>; + samsung,sysreg = <&sysreg_peri 0x1030>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peri CLK_GOUT_HSI2C1_PCLK>, + <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_1: i2c@138b0000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x138b0000 0xc0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c1_pins>; + clocks = <&cmu_peri CLK_GOUT_HSI2C1_IPCLK>, + <&cmu_peri CLK_GOUT_HSI2C1_PCLK>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + }; + + usi_hsi2c_2: usi@138c00c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x138c00c0 0x20>; + samsung,sysreg = <&sysreg_peri 0x1040>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peri CLK_GOUT_HSI2C2_PCLK>, + <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_2: i2c@138c0000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x138c0000 0xc0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c2_pins>; + clocks = <&cmu_peri CLK_GOUT_HSI2C2_IPCLK>, + <&cmu_peri CLK_GOUT_HSI2C2_PCLK>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + }; + + usi_spi_0: usi@139400c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x139400c0 0x20>; + samsung,sysreg = <&sysreg_peri 0x1050>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>, + <&cmu_peri CLK_GOUT_SPI0_IPCLK>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + }; + + usi_cmgp0: usi@11d000c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x11d000c0 0x20>; + samsung,sysreg = <&sysreg_cmgp 0x2000>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_3: i2c@11d00000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x11d00000 0xc0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c3_pins>; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + + serial_1: serial@11d00000 { + compatible = "samsung,exynos850-uart"; + reg = <0x11d00000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_single_pins>; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + }; + + usi_cmgp1: usi@11d200c0 { + compatible = "samsung,exynos850-usi"; + reg = <0x11d200c0 0x20>; + samsung,sysreg = <&sysreg_cmgp 0x2010>; + samsung,mode = ; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; + clock-names = "pclk", "ipclk"; + status = "disabled"; + + hsi2c_4: i2c@11d20000 { + compatible = "samsung,exynosautov9-hsi2c"; + reg = <0x11d20000 0xc0>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hsi2c4_pins>; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>; + clock-names = "hsi2c", "hsi2c_pclk"; + status = "disabled"; + }; + + serial_2: serial@11d20000 { + compatible = "samsung,exynos850-uart"; + reg = <0x11d20000 0xc0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_single_pins>; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + }; + }; +}; + +#include "exynos850-pinctrl.dtsi" diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 8f3aee052c8a..45fc6bb024b0 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -58,6 +58,15 @@ config ARCH_EXYNOS7 Cortex-A53 CPU (and some in a big.LITTLE configuration). There are multiple SoCs in this family including Exynos7420. +config ARCH_EXYNOS9 + bool "Exynos9 SoC family" + select ARM64 + select BLK + select DM_MMC + help + Samsung Exynos9 SoC family are based on ARMv8 Cortex CPU. There are + multiple SoCs in this family including Exynos850. + endchoice if ARCH_EXYNOS4 diff --git a/arch/arm/mach-exynos/mmu-arm64.c b/arch/arm/mach-exynos/mmu-arm64.c index 8d8c64e8f8fa..30e522804fbf 100644 --- a/arch/arm/mach-exynos/mmu-arm64.c +++ b/arch/arm/mach-exynos/mmu-arm64.c @@ -6,6 +6,7 @@ #include #include +#include #if IS_ENABLED(CONFIG_EXYNOS7420) @@ -95,4 +96,37 @@ static struct mm_region exynos7880_mem_map[] = { }; struct mm_region *mem_map = exynos7880_mem_map; + +#elif IS_ENABLED(CONFIG_EXYNOS850) + +static struct mm_region exynos850_mem_map[] = { + { + /* Peripheral block */ + .virt = 0x10000000UL, + .phys = 0x10000000UL, + .size = SZ_256M, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* DDR, 32-bit area */ + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = SZ_2G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* DDR, 64-bit area */ + .virt = 0x880000000UL, + .phys = 0x880000000UL, + .size = SZ_2G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* List terminator */ + } +}; + +struct mm_region *mem_map = exynos850_mem_map; + #endif From patchwork Thu Jan 11 03:09:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 761789 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp2198939wrz; Wed, 10 Jan 2024 19:12:08 -0800 (PST) X-Google-Smtp-Source: AGHT+IHChGhIYTwx5gEtWRlHqzX3MIYATZLc5AO3Ti5A2k80RUFxJgc4tcz68jGKRadShZEffgmB X-Received: by 2002:a05:600c:3506:b0:40e:485c:ae84 with SMTP id h6-20020a05600c350600b0040e485cae84mr3064wmq.9.1704942728458; Wed, 10 Jan 2024 19:12:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704942728; cv=none; d=google.com; s=arc-20160816; b=f3Ci6C+g8we895vIEQX1JoVN7JmarsugdWPgBnMkK2jIqgnV0ttY72ZpG9h2/ZDXAE aiO/jT6jUawZvywql9IFQdCmx8UUWf+XaHcJeKKMDIxG+g4954A39FtijLJjuHakTuJI BcfXv9/bdXD3u8JiBvocEO8/BjKZT5rHnD6elaj+i+82S2WPhingDNR0HSU4JEGYl34k d1dEYNbUFOt+jGgiNaaZ4CtGCqTea98A4qXrBoegOb5olFEzDqHGDRN2H/kut3V1per2 tlSRF1W2QQ1jdHaW2NdLP/Ke9yZPZwg5I3/Ab14yk7SJIN9rsOBdG8Q2oc+UQSzmPvaH 178A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=wQdIBijoLbVOUSmNfjg4hizsNKbfzuaifjOH6eQhFXc=; fh=PzVE172kMYfD8vsZrdrkQaWk4G6SF+wa//e7xu1cQV0=; b=G/hCBiCQ7eVjiennDkVNN23/zs5xNJWOfcKpwJmeL9xunpph7im+cdFAolByk28ooS N8PUAA6UkeQushBo7TwinC60W4r93LyEEpfpWAB6w0zwH0Pc13LWWADe+aisb1trpkET +FJtyV97vprpSGpwuPocNySNB2qj9/jnKk2KmpeSxIVvNZCCJ1ML7Gxnn95dzxlmOoAP h/IMMj1ri2TtjFctw3loekh4Jf+rikVHB8uiJkmu5AeezWt5sgCHkW9of2IxGfmOWh+D xofRW5D6RT3/TZpb/dqhaimCxtyiQLxtPAoYsaM+UdBDw/vj7w1c51h+vmrcQkKE8vG0 qLIw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YwCARoYT; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id t10-20020a05600c198a00b0040d8e907793si1416618wmq.140.2024.01.10.19.12.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 19:12:08 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YwCARoYT; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 8741687AAB; Thu, 11 Jan 2024 04:09:42 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="YwCARoYT"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 8519887613; Thu, 11 Jan 2024 04:09:39 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mail-oa1-x33.google.com (mail-oa1-x33.google.com [IPv6:2001:4860:4864:20::33]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id AD9AE87B1D for ; Thu, 11 Jan 2024 04:09:27 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=semen.protsenko@linaro.org Received: by mail-oa1-x33.google.com with SMTP id 586e51a60fabf-203ae9903a6so2556022fac.0 for ; Wed, 10 Jan 2024 19:09:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704942563; x=1705547363; darn=lists.denx.de; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wQdIBijoLbVOUSmNfjg4hizsNKbfzuaifjOH6eQhFXc=; b=YwCARoYTrAT6luIRNSTqWmPyWJ7vH/C3xcGsNQfumdGHU7srP2HP+cCzEK0pzyzKBQ 5G0HJphn62g0XoxMsqwkKg4/oZSqCr7piLeqyL0OeB0+abEhsg3YEk555CoTQCAfuzLc o0qSkQNnwKn5O3p2+MKKH/7nOULMFveYDjWCDJyimXD+JUo7z6ME5Yn2MsgZA7BP/8YQ kRlt6zq65xtpaX+ngUwfkkBM8cZVrp53VlAvjjTP0Ey8BpZ1EUlNgzyBRbQ/whf61f0o +RRjRzoVJaDgWkTUFcWNUABGzSt//7SVj6L28Ww2rwxDl7Khv0pjScHwQ7nv5TpWqMfs A9Ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704942563; x=1705547363; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wQdIBijoLbVOUSmNfjg4hizsNKbfzuaifjOH6eQhFXc=; b=EB9261wK97G8kRd1ikHnUbyEN3lze8pWP8g4dDBkYzM+kGditZ8PQpLPfEt9aKUI1W tO82sIj3PUJN6XNU3KHDUcMIphRYOUBLboHBLdajeWKxG6PeDV4UBYdIQqmy5pVCNzIz RXJUrF1BlAkHnxn0ZwHZhe+wqQI8H3y7WN8wxTt7VwkxkchDnkHkhkM+I4v4Ut/N1xBi kwaNrBsbpgMWr509gQKhiwztUF6SA73mbyqW72UKD4qo1ZhLvs1CqDi8cW/TvwjQnw4/ fRZ5jV5RdpZafhQwAvocB/ccpNGIdHhGBcOdVblA+Zyj1/8ZCHOHPvug84XVqL8DqwHl m/bA== X-Gm-Message-State: AOJu0YwsivShlnZKYN+lm2+N/FpkWOxSN1UAFKhb4/B7wanFYJRd8JRa g+tgz7sRHmLj+VTfiNfWZEQPqIYDk/v4TA== X-Received: by 2002:a05:6870:8a0d:b0:206:8307:9411 with SMTP id p13-20020a0568708a0d00b0020683079411mr583720oaq.19.1704942563549; Wed, 10 Jan 2024 19:09:23 -0800 (PST) Received: from localhost ([136.62.192.75]) by smtp.gmail.com with ESMTPSA id sk16-20020a056871801000b002064e3ae6e7sm13779oab.0.2024.01.10.19.09.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 19:09:22 -0800 (PST) From: Sam Protsenko To: Minkyu Kang , Tom Rini , Lukasz Majewski , Sean Anderson Cc: Simon Glass , Chanho Park , Heinrich Schuchardt , u-boot@lists.denx.de Subject: [PATCH v2 12/13] board: samsung: Add support for E850-96 board Date: Wed, 10 Jan 2024 21:09:08 -0600 Message-Id: <20240111030909.27373-13-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240111030909.27373-1-semen.protsenko@linaro.org> References: <20240111030909.27373-1-semen.protsenko@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add support for WinLink E850-96 board [1]. It's based on Exynos850 SoC and follows 96boards specification, so it's compatible with 96boards mezzanine boards [2]. This patch enables next features: * Serial console * USI * PMU (muxing AP UART path) * Pinctrl * Clocks * Timer (ARMv8 architected) * Reset control It's quite a minimal enablement. Features like MMC, USB and Ethernet will be enabled later. The rationale for config values is as follows: * TEXT_BASE = 0xf8800000 That's where BL2 loads the U-Boot payload, so TEXT_BASE must be exactly this value. Overall the memory map is designed in a way to keep the bootloader in the upper 128 MiB area of RAM, which is 0xf8000000..0xffffffff. That includes bootloader's code, stack, data, heap, MMU tables, etc. All the memory below that 128 MiB chunk can be used for storing boot images (0x80000000..0xf8000000). * CUSTOM_SYS_INIT_SP_ADDR = 0xf8c00000 Just 4 MiB above the TEXT_BASE address, to leave enough space for U-Boot code and stack itself (grows downwards). * SYS_LOAD_ADDR = 0x80000000 The beginning of RAM. That's where Linux kernel image must be loaded. * SYS_MALLOC_LEN = 0x81f000 8 MiB for malloc() + ENV_SIZE (128 KiB) * SYS_MALLOC_F_LEN = 0x4000 Increase malloc() pool size available before relocation from 8 KiB (default) to 16 KiB. Otherwise "alloc space exhausted" message appears in U-Boot log during board_init_f() stage. There are next reasons for doing so: 1. Having "bootph-all" flags in some dts nodes leads to binding those during pre-relocation stage, and binding (DM) uses dynamic memory allocation 2. clk-exynos850 driver uses CCF clocks, which in turn use dynamic memory allocation Device tree file was imported from Linux kernel. All nodes and boot phase flags added in exynos850-e850-96-u-boot.dtsi are only needed to enable serial console: * oscclk -> cmu_top -> cmu_peri: generate UART/USI clocks * pinctrl_alive and uart1_pins: needed to mux UART pins * pmu_system_controller: configures AP UART path to uart1_pins * usi_uart: configures USI block to operate as a UART protocol * serial_0: enables serial console (UART) [1] https://www.96boards.org/product/e850-96b/ [2] https://www.96boards.org/products/mezzanine/ Signed-off-by: Sam Protsenko --- Changes in v2: - (none) arch/arm/dts/Makefile | 1 + arch/arm/dts/exynos850-e850-96-u-boot.dtsi | 37 + arch/arm/dts/exynos850-e850-96.dts | 273 ++++ arch/arm/mach-exynos/Kconfig | 19 +- board/samsung/e850-96/Kconfig | 16 + board/samsung/e850-96/MAINTAINERS | 9 + board/samsung/e850-96/Makefile | 6 + board/samsung/e850-96/e850-96.c | 22 + configs/e850-96_defconfig | 21 + doc/board/samsung/e850-96.rst | 87 ++ .../img/exynos850-boot-architecture.svg | 1283 +++++++++++++++++ doc/board/samsung/index.rst | 1 + include/configs/e850-96.h | 12 + 13 files changed, 1786 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/exynos850-e850-96-u-boot.dtsi create mode 100644 arch/arm/dts/exynos850-e850-96.dts create mode 100644 board/samsung/e850-96/Kconfig create mode 100644 board/samsung/e850-96/MAINTAINERS create mode 100644 board/samsung/e850-96/Makefile create mode 100644 board/samsung/e850-96/e850-96.c create mode 100644 configs/e850-96_defconfig create mode 100644 doc/board/samsung/e850-96.rst create mode 100644 doc/board/samsung/img/exynos850-boot-architecture.svg create mode 100644 include/configs/e850-96.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 773c2546131c..84b8203e0f6a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -31,6 +31,7 @@ dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb dtb-$(CONFIG_TARGET_A5Y17LTE) += exynos78x0-axy17lte.dtb dtb-$(CONFIG_TARGET_A3Y17LTE) += exynos78x0-axy17lte.dtb dtb-$(CONFIG_TARGET_A7Y17LTE) += exynos78x0-axy17lte.dtb +dtb-$(CONFIG_TARGET_E850_96) += exynos850-e850-96.dtb dtb-$(CONFIG_ARCH_APPLE) += \ t8103-j274.dtb \ diff --git a/arch/arm/dts/exynos850-e850-96-u-boot.dtsi b/arch/arm/dts/exynos850-e850-96-u-boot.dtsi new file mode 100644 index 000000000000..7ad11e9faab2 --- /dev/null +++ b/arch/arm/dts/exynos850-e850-96-u-boot.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Linaro Ltd. + */ + +&cmu_top { + bootph-all; +}; + +&cmu_peri { + bootph-all; +}; + +&oscclk { + bootph-all; +}; + +&pinctrl_alive { + bootph-all; +}; + +&pmu_system_controller { + bootph-all; + samsung,uart-debug-1; +}; + +&serial_0 { + bootph-all; +}; + +&uart1_pins { + bootph-all; +}; + +&usi_uart { + bootph-all; +}; diff --git a/arch/arm/dts/exynos850-e850-96.dts b/arch/arm/dts/exynos850-e850-96.dts new file mode 100644 index 000000000000..f074df8982b3 --- /dev/null +++ b/arch/arm/dts/exynos850-e850-96.dts @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * WinLink E850-96 board device tree source + * + * Copyright (C) 2018 Samsung Electronics Co., Ltd. + * Copyright (C) 2021 Linaro Ltd. + * + * Device tree source file for WinLink's E850-96 board which is based on + * Samsung Exynos850 SoC. + */ + +/dts-v1/; + +#include "exynos850.dtsi" +#include +#include +#include + +/ { + model = "WinLink E850-96 board"; + compatible = "winlink,e850-96", "samsung,exynos850"; + + aliases { + mmc0 = &mmc_0; + serial0 = &serial_0; + }; + + chosen { + stdout-path = &serial_0; + }; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + vbus-supply = <®_usb_host_vbus>; + id-gpios = <&gpa0 0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <µ_usb_det_pins>; + + port { + usb_dr_connector: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; + }; + + /* + * RAM: 4 GiB (eMCP): + * - 2 GiB at 0x80000000 + * - 2 GiB at 0x880000000 + * + * 0xbab00000..0xbfffffff: secure memory (85 MiB). + */ + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x3ab00000>, + <0x0 0xc0000000 0x40000000>, + <0x8 0x80000000 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&key_voldown_pins &key_volup_pins>; + + volume-down-key { + label = "Volume Down"; + linux,code = ; + gpios = <&gpa1 0 GPIO_ACTIVE_LOW>; + }; + + volume-up-key { + label = "Volume Up"; + linux,code = ; + gpios = <&gpa0 7 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + /* HEART_BEAT_LED */ + user_led1: led-1 { + label = "yellow:user1"; + gpios = <&gpg2 2 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_HEARTBEAT; + linux,default-trigger = "heartbeat"; + }; + + /* eMMC_LED */ + user_led2: led-2 { + label = "yellow:user2"; + gpios = <&gpg2 3 GPIO_ACTIVE_HIGH>; + color = ; + linux,default-trigger = "mmc0"; + }; + + /* SD_LED */ + user_led3: led-3 { + label = "white:user3"; + gpios = <&gpg2 4 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_SD; + linux,default-trigger = "mmc2"; + }; + + /* WIFI_LED */ + wlan_active_led: led-4 { + label = "yellow:wlan"; + gpios = <&gpg2 6 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_WLAN; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + /* BLUETOOTH_LED */ + bt_active_led: led-5 { + label = "blue:bt"; + gpios = <&gpg2 7 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_BLUETOOTH; + linux,default-trigger = "hci0-power"; + default-state = "off"; + }; + }; + + /* TODO: Remove this once PMIC is implemented */ + reg_dummy: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "dummy_reg"; + }; + + reg_usb_host_vbus: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "usb_host_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpa3 5 GPIO_ACTIVE_LOW>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <1>; + ranges; + + ramoops@f0000000 { + compatible = "ramoops"; + reg = <0x0 0xf0000000 0x200000>; + record-size = <0x20000>; + console-size = <0x20000>; + ftrace-size = <0x100000>; + pmsg-size = <0x20000>; + }; + }; + + /* + * RTC clock (XrtcXTI); external, must be 32.768 kHz. + * + * TODO: Remove this once RTC clock is implemented properly as part of + * PMIC driver. + */ + rtcclk: clock-rtcclk { + compatible = "fixed-clock"; + clock-output-names = "rtcclk"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; +}; + +&cmu_hsi { + clocks = <&oscclk>, <&rtcclk>, + <&cmu_top CLK_DOUT_HSI_BUS>, + <&cmu_top CLK_DOUT_HSI_MMC_CARD>, + <&cmu_top CLK_DOUT_HSI_USB20DRD>; + clock-names = "oscclk", "rtcclk", "dout_hsi_bus", + "dout_hsi_mmc_card", "dout_hsi_usb20drd"; +}; + +&mmc_0 { + status = "okay"; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-highspeed; + non-removable; + mmc-hs400-enhanced-strobe; + card-detect-delay = <200>; + clock-frequency = <800000000>; + bus-width = <8>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <2 4>; + samsung,dw-mshc-hs400-timing = <0 2>; + + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk_pins &sd0_cmd_pins &sd0_rdqs_pins &sd0_nreset_pins + &sd0_bus1_pins &sd0_bus4_pins &sd0_bus8_pins>; +}; + +&oscclk { + clock-frequency = <26000000>; +}; + +&pinctrl_alive { + key_voldown_pins: key-voldown-pins { + samsung,pins = "gpa1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + key_volup_pins: key-volup-pins { + samsung,pins = "gpa0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + micro_usb_det_pins: micro-usb-det-pins { + samsung,pins = "gpa0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; +}; + +&rtc { + status = "okay"; + clocks = <&cmu_apm CLK_GOUT_RTC_PCLK>, <&rtcclk>; + clock-names = "rtc", "rtc_src"; +}; + +&serial_0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&usbdrd { + status = "okay"; + vdd10-supply = <®_dummy>; + vdd33-supply = <®_dummy>; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "host"; + + port { + usb1_drd_sw: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; + }; +}; + +&usbdrd_phy { + status = "okay"; +}; + +&usi_uart { + samsung,clkreq-on; /* needed for UART mode */ + status = "okay"; +}; + +&watchdog_cl0 { + status = "okay"; +}; + +&watchdog_cl1 { + status = "okay"; +}; diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 45fc6bb024b0..af00ee1db07a 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -2,7 +2,7 @@ if ARCH_EXYNOS config BOARD_COMMON def_bool y - depends on !TARGET_SMDKV310 && !TARGET_ARNDALE + depends on !TARGET_SMDKV310 && !TARGET_ARNDALE && !TARGET_E850_96 config SPI_BOOTING bool @@ -237,6 +237,22 @@ config TARGET_A3Y17LTE endchoice endif +if ARCH_EXYNOS9 + +choice + prompt "EXYNOS9 board select" + +config TARGET_E850_96 + bool "WinLink E850-96 board" + select ARM64 + select CLK_EXYNOS + select OF_CONTROL + select PINCTRL + select PINCTRL_EXYNOS850 + +endchoice +endif + config SYS_SOC default "exynos" @@ -261,5 +277,6 @@ source "board/samsung/smdk5250/Kconfig" source "board/samsung/smdk5420/Kconfig" source "board/samsung/espresso7420/Kconfig" source "board/samsung/axy17lte/Kconfig" +source "board/samsung/e850-96/Kconfig" endif diff --git a/board/samsung/e850-96/Kconfig b/board/samsung/e850-96/Kconfig new file mode 100644 index 000000000000..f891a906959b --- /dev/null +++ b/board/samsung/e850-96/Kconfig @@ -0,0 +1,16 @@ +if TARGET_E850_96 + +config EXYNOS850 + bool "Exynos850 SoC support" + default y + +config SYS_BOARD + default "e850-96" + +config SYS_VENDOR + default "samsung" + +config SYS_CONFIG_NAME + default "e850-96" + +endif diff --git a/board/samsung/e850-96/MAINTAINERS b/board/samsung/e850-96/MAINTAINERS new file mode 100644 index 000000000000..e8b9365eea85 --- /dev/null +++ b/board/samsung/e850-96/MAINTAINERS @@ -0,0 +1,9 @@ +WINLINK E850-96 BOARD +M: Sam Protsenko +S: Maintained +F: arch/arm/dts/exynos850-e850-96-u-boot.dtsi +F: arch/arm/dts/exynos850-e850-96.dts +F: board/samsung/e850-96/ +F: configs/e850-96_defconfig +F: doc/board/samsung/e850-96.rst +F: include/configs/e850-96.h diff --git a/board/samsung/e850-96/Makefile b/board/samsung/e850-96/Makefile new file mode 100644 index 000000000000..301c22337119 --- /dev/null +++ b/board/samsung/e850-96/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2020, Linaro Limited +# Sam Protsenko + +obj-y := e850-96.o diff --git a/board/samsung/e850-96/e850-96.c b/board/samsung/e850-96/e850-96.c new file mode 100644 index 000000000000..a00d81b5d4c3 --- /dev/null +++ b/board/samsung/e850-96/e850-96.c @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020, Linaro Limited + * Sam Protsenko + */ + +#include + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +int board_init(void) +{ + return 0; +} diff --git a/configs/e850-96_defconfig b/configs/e850-96_defconfig new file mode 100644 index 000000000000..bb41635ff784 --- /dev/null +++ b/configs/e850-96_defconfig @@ -0,0 +1,21 @@ +CONFIG_ARM=y +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_EXYNOS=y +CONFIG_TEXT_BASE=0xf8800000 +CONFIG_SYS_MALLOC_LEN=0x81f000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_ARCH_EXYNOS9=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xf8c00000 +CONFIG_DEFAULT_DEVICE_TREE="exynos850-e850-96" +CONFIG_SYS_LOAD_ADDR=0x80000000 +# CONFIG_AUTOBOOT is not set +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_NET is not set +CONFIG_CLK_EXYNOS850=y +# CONFIG_MMC is not set +CONFIG_SOC_SAMSUNG=y +CONFIG_EXYNOS_PMU=y +CONFIG_EXYNOS_USI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_SYSCON=y diff --git a/doc/board/samsung/e850-96.rst b/doc/board/samsung/e850-96.rst new file mode 100644 index 000000000000..0cb95473e536 --- /dev/null +++ b/doc/board/samsung/e850-96.rst @@ -0,0 +1,87 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Sam Protsenko + +WinLink E850-96 board +===================== + +Overview +-------- + +WinLink's E850-96 board [1]_ is based on Samsung Exynos850 SoC and follows +96Boards Consumer Edition specification [2]_. That makes it possible to use +96Boards mezzanine boards [3]_ along with it. It's an open-hardware board and +the hardware design files [4]_ were published, along with the supported +software [5]_ and related documentation. + +U-Boot can be used on E850-96 instead of the original Samsung LittleKernel based +bootloader [6]_. Because FWBL1 [7]_ doesn't verify bootloader's signature, there +is no need to sign a U-Boot binary. That means U-Boot binary can be flashed into +``bootloader`` partition (instead of LittleKernel bootloader) and it will just +work. + +Because BL2 bootloader already sets up DRAM and runs the final bootloader +(U-Boot) from DRAM, there is no need in U-Boot SPL. It's enough to have only +U-Boot proper (``u-boot.bin``). + +Boot Flow +--------- + +The boot path for Exynos850 is shown on the figure below. + +.. image:: img/exynos850-boot-architecture.svg + :alt: Exynos850 SoC boot flow + +Legend: + +* ``BL0``: Boot ROM code +* ``BL1``: Software part of Boot ROM +* ``EPBL``: Exynos Primary Boot Loader +* ``BL2``: Initializes CMU and DRAM and runs the final bootloader +* ``Bootloader``: Final bootloader (e.g. U-Boot); also called BL33 in terms of + ARM boot flow +* ``EL3_MON``: EL3 monitor (trusted firmware, handles SMC calls); also called + BL31 in terms of ARM boot flow +* ``LDFW``: Loadable Firmware + +Build Procedure +--------------- + +.. warning:: + At the moment both eMMC and USB features are not enabled in U-Boot. Flashing + U-Boot binary **WILL** effectively brick your board. The ``dltool`` [8]_ can + be used then to perform USB boot and flash LittleKernel bootloader binary [7]_ + to unbrick and revive the board. Flashing U-Boot binary might be helpful for + developers or anybody who want to check current state of U-Boot enablement on + E850-96 (which is mostly serial console and related blocks). + +Build U-Boot binary from source code (using AArch64 baremetal GCC toolchain): + +.. prompt:: bash $ + + export PATH=/bin:$PATH + export CROSS_COMPILE= + make e850-96_defconfig + make + +Boot E850-96 board into fastboot mode as described in board software doc [9]_, +and flash U-Boot binary into ``bootloader`` eMMC partition: + +.. prompt:: bash $ + + fastboot flash bootloader u-boot.bin + fastboot reboot + +U-Boot will boot up to the shell. + +References +---------- + +.. [1] https://www.96boards.org/product/e850-96b/ +.. [2] https://www.96boards.org/products/ce/ +.. [3] https://www.96boards.org/products/mezzanine/ +.. [4] https://www.96boards.org/documentation/consumer/e850-96b/hardware-docs/ +.. [5] https://gitlab.com/Linaro/96boards/e850-96/ +.. [6] https://gitlab.com/Linaro/96boards/e850-96/lk +.. [7] https://gitlab.com/Linaro/96boards/e850-96/images +.. [8] https://gitlab.com/Linaro/96boards/e850-96/tools/dltool +.. [9] https://gitlab.com/Linaro/96boards/e850-96/doc diff --git a/doc/board/samsung/img/exynos850-boot-architecture.svg b/doc/board/samsung/img/exynos850-boot-architecture.svg new file mode 100644 index 000000000000..c6e850407b4a --- /dev/null +++ b/doc/board/samsung/img/exynos850-boot-architecture.svg @@ -0,0 +1,1283 @@ + + + + + + + + + + + + + + + Secure World + + + + Secure World + + + + + + + + + + + + + + + Non-Secure World + + + + Non-SecureWorld + + + + + + + + + +Booting Period + + + + Booting Period + + + + + + + + + + + BL0 + + + + BL0 + + + + + + + + + + + BL1 + + + + BL1 + + + + + + + + + + + + + EPBL + + + + EPBL + + + + + + + + + + + + + BL2 + + + + BL2 + + + + + + + + + + + + + Bootloader + + + + Bootloader + + + + + + + + + + + + + EL3_MON + + + + EL3_MON + + + + + + + + + + + Linux + + + + Linux + + + + + + + + + + Android + + + + + Android + + + + + + + + + Secure App + + + + Secure App + + + + + + + + + + + Secure OS + + + + Secure OS + + + + + + + + + LDFW + + + + LDFW + + + + + + + + + + iROM + + + + + iROM + + + + + + + + + + iRAM + + + + + iRAM + + + + + + + + + + DRAM + + + + + DRAM + + + + + + + + + + + + EL0 + + + + EL0 + + + + + + + + + EL1 + + + + EL1 + + + + + + + + + EL3 + + + + EL3 + + + + + + + Text is not SVG - cannot display + + + diff --git a/doc/board/samsung/index.rst b/doc/board/samsung/index.rst index 971805e20169..a1c9636b0507 100644 --- a/doc/board/samsung/index.rst +++ b/doc/board/samsung/index.rst @@ -7,3 +7,4 @@ Samsung :maxdepth: 2 axy17lte + e850-96 diff --git a/include/configs/e850-96.h b/include/configs/e850-96.h new file mode 100644 index 000000000000..4607b3089b21 --- /dev/null +++ b/include/configs/e850-96.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020, Linaro Limited + * Sam Protsenko + * + * Configuration for E850-96 board. + */ + +#ifndef __E850_96_H +#define __E850_96_H + +#endif /* __E850_96_H */ From patchwork Thu Jan 11 03:09:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Protsenko X-Patchwork-Id: 761787 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp2198813wrz; Wed, 10 Jan 2024 19:11:42 -0800 (PST) X-Google-Smtp-Source: AGHT+IHJK/lr18tSoX5RinfOtNdLjvT/ab8qmsTx8yZGp3yNfJtb3nY4vGbee3cRTKlzHIB1g6Tj X-Received: by 2002:a05:600c:4e8a:b0:40e:5aa4:44f9 with SMTP id f10-20020a05600c4e8a00b0040e5aa444f9mr4034wmq.10.1704942702225; Wed, 10 Jan 2024 19:11:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704942702; cv=none; d=google.com; s=arc-20160816; b=XInM9wBoO+XGooFeJxPjQ6CtATRLv9N5+VlbpQLLUL2B5+1D6jNEqdawz13JIlzOYQ UGZIArpG+U16Y9/81ypaQsC6bMM71WlHkzKU++wzouLF8gqsItSsbQK4YZFeQ5VXFUdp F9qobYn7cihRgKOrekJ9cpG2Td15mmHmZvaVMlZFYXrcayt8qAOKv19v6U8Ye7CjLqV4 e7TCQ6yaITKfAI51njwpW6rleMirkXoVQPmsdCrYJcKuFSck7nVv6NSzbHBXGfRoI7id RL40rH+k4tfIzJCQmdH1NV9qIIOWEzavMsmH1ATAna3pj79AdeA9mHacthTvlY+7xmkU iCcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=jCR2s6dv9TcN0rCDDRwOvshFyB9yr+laMEwcE42IykI=; fh=PzVE172kMYfD8vsZrdrkQaWk4G6SF+wa//e7xu1cQV0=; b=lIKJxaj+FXropsGDveUZSAkZHzY0HtA+aCI/1vgacOTU9hyqh7kFPMr8biyaXskJDK LYE1ULHvwkLzS0e5G5O/0ClBi362UMlNMpRyM8H7EFqHJfe7reuZiz7ZFM+vraZa9oY9 nPlSKfr92JGoSkz+0ISgkZ1Q+Wcr+3WeiWWiwQSwJM9oWueMShqv3lcZGTC+MbMkNo3e E6Mv1231w3VCdzAAnp6IOVuqyl8ox81HpH6oaPCCdHYm/u6/Kbh24O/XwM9P1JNrY5EJ xxBW03/Ggv+W+cxmyC+XANfZKEMd+lkndTQXOhLqfRVnhW/0JMc61BlHn7PJOMHRfEkP vyIQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="BNt/4ZqL"; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from phobos.denx.de (phobos.denx.de. [85.214.62.61]) by mx.google.com with ESMTPS id q14-20020adfab0e000000b003371c4ea2f6si5845wrc.844.2024.01.10.19.11.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 19:11:42 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) client-ip=85.214.62.61; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="BNt/4ZqL"; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.62.61 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 4D2FB87A82; Thu, 11 Jan 2024 04:09:38 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=linaro.org header.i=@linaro.org header.b="BNt/4ZqL"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 0962287A7F; Thu, 11 Jan 2024 04:09:37 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.2 Received: from mail-ot1-x334.google.com (mail-ot1-x334.google.com [IPv6:2607:f8b0:4864:20::334]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id ADA3B87B1E for ; Thu, 11 Jan 2024 04:09:27 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=semen.protsenko@linaro.org Received: by mail-ot1-x334.google.com with SMTP id 46e09a7af769-6de424cef01so469249a34.2 for ; Wed, 10 Jan 2024 19:09:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704942564; x=1705547364; darn=lists.denx.de; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jCR2s6dv9TcN0rCDDRwOvshFyB9yr+laMEwcE42IykI=; b=BNt/4ZqLPWXxchOuDlTU8Cq2H5MeCQoymUktOo/HmnW9WUKCfg/HTjKv9kJPFH/5TN 0iCCzbqUCGBioCetuQx9tpsj1ghfx5ABsV1sFlrr9FSkhD8mC4Uw2lb7M8JTShI5BRj2 zcqsGFnfVo473RyZ/aOlXD1yRDo973MpzrUNij5uVsoi8x1friz83A0kK+xlu99QY+Mq bh6UDz1b43GG9w0+SW4OMaa3vFbAOIQSNQj6J5OUvzEHqh2hD0ZguZ8aIs24hmleyrE9 ikBuoFVAYREXfNZDDI5IyrtdTlyzDD8b0+TajuSO8AdLjCzP31zgGyi+3gCoDIvxtbEu cchg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704942564; x=1705547364; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jCR2s6dv9TcN0rCDDRwOvshFyB9yr+laMEwcE42IykI=; b=MhvHMZ4DhWNBd+jy/vT9hR7kwlZV8JnV+Lgwl0Pt3dw2GWzyeKg2Oy0IKhbHeToR/9 jzX7Nk1V1QZKtOb5lFYcxdhRkfHy9F/dZjrs/n3+eJNu9omIIpJmMZqyQL5ndT10f5AV AldjmeDJ+YpWltZ3baeh5u5VHciNMr7SoQs39+Jupb4B8+p4v6R8L1XSUPxNwHxEtAJt 9heoRxaY1hPEmrDYaJc0GPifjK8aKZq9DvCgiE577aoJJzJcK+NgUWjzSCcJ5gVrGEAg KUz528z/d6k9qViZCPg+420t0ic76Oe5gQgZfTDqEnIYrRtaFwAUDXCdk9XVd++tr1lx fQUQ== X-Gm-Message-State: AOJu0YzOz6LrlHVyhWe4f8aYF+YR/5hyGciqxkPilQYbHM4iCG0TGpWi EGaWbWVBw7pfY6kIi/cxRxayB6Elf6L9yw== X-Received: by 2002:a05:6830:144b:b0:6dc:5d73:d744 with SMTP id w11-20020a056830144b00b006dc5d73d744mr580071otp.23.1704942564418; Wed, 10 Jan 2024 19:09:24 -0800 (PST) Received: from localhost ([136.62.192.75]) by smtp.gmail.com with ESMTPSA id l23-20020a05683016d700b006dc8ce3b8b6sm2841otr.69.2024.01.10.19.09.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 19:09:24 -0800 (PST) From: Sam Protsenko To: Minkyu Kang , Tom Rini , Lukasz Majewski , Sean Anderson Cc: Simon Glass , Chanho Park , Heinrich Schuchardt , u-boot@lists.denx.de Subject: [PATCH v2 13/13] MAINTAINERS: Add new Samsung subsystems Date: Wed, 10 Jan 2024 21:09:09 -0600 Message-Id: <20240111030909.27373-14-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240111030909.27373-1-semen.protsenko@linaro.org> References: <20240111030909.27373-1-semen.protsenko@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add next Samsung subsystems with Sam Protsenko as a maintainer: - Samsung CCF Clock Framework - Exynos850 SoC Support - Samsung SoC Drivers Signed-off-by: Sam Protsenko --- Changes in v2: - (none) MAINTAINERS | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4fec063a242f..33e96cd4231f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -563,6 +563,31 @@ F: arch/arm/mach-exynos/ F: arch/arm/mach-s5pc1xx/ F: arch/arm/cpu/armv7/s5p-common/ +ARM SAMSUNG CLOCK +M: Sam Protsenko +S: Maintained +F: drivers/clk/exynos/clk-pll.c +F: drivers/clk/exynos/clk-pll.h +F: drivers/clk/exynos/clk.c +F: drivers/clk/exynos/clk.h + +ARM SAMSUNG EXYNOS850 SOC +M: Sam Protsenko +S: Maintained +F: arch/arm/dts/exynos850-pinctrl.dtsi +F: arch/arm/dts/exynos850.dtsi +F: doc/device-tree-bindings/clock/samsung,exynos850-clock.yaml +F: drivers/clk/exynos/clk-exynos850.c +F: drivers/pinctrl/exynos/pinctrl-exynos850.c +F: include/dt-bindings/clock/exynos850.h + +ARM SAMSUNG SOC DRIVERS +M: Sam Protsenko +S: Maintained +F: doc/device-tree-bindings/soc/samsung/* +F: drivers/soc/samsung/* +F: include/dt-bindings/soc/samsung,*.h + ARM SANCLOUD M: Paul Barker R: Marc Murphy