From patchwork Wed Jan 10 11:20:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 761555 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 725F84776F; Wed, 10 Jan 2024 11:21:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ereBSzNk" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 40A8oMxM005978; Wed, 10 Jan 2024 11:21:23 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=0tgyZq56LbgeyLFmlrLBCFlUmFvbEsQ/fInNhqR0U8w=; b=er eBSzNkf7G8o3TkYX5F+4IcxujDmcvxlVE9sFKhD1o/WbAOC7IvZgUZH2LDcnL8En RqnPSCvRDwuOAp5oouv52Nwathf3JBCmTQ3twHX5nl6OCvy7n4uui5idTEDVzqsE dGxsdK5bcZSSmx0zp3TYbsFeFkjhQC0zQIVyHf6iWw18i2IX+v6GmBn/v7+EX3jZ +qB0IBYT+aze+eFWOpF4M8G5jbmhYi9oCVIaNJIHKdFiarxVm7JulzyId3XRuY98 y6i+K93lrGp1iFWSYCbA8c2MsJV/6ho2DxTTITS+OMOmz+mVhga+BNcGidRvzyGe 13MwKPAa1tj+sJmv8TlQ== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3vh85t2cqy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 10 Jan 2024 11:21:22 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 40ABLLxs026578 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 10 Jan 2024 11:21:21 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 10 Jan 2024 03:21:16 -0800 From: Luo Jie To: , , , , CC: , , , , , , , , , , Subject: [PATCH 1/6] arm64: dts: qcom: ipq9574: Add PPE device tree node Date: Wed, 10 Jan 2024 19:20:54 +0800 Message-ID: <20240110112059.2498-2-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240110112059.2498-1-quic_luoj@quicinc.com> References: <20240110112059.2498-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: _Wp0J2wSiZfHeZTx6zxGf0qmZxNgMmhN X-Proofpoint-GUID: _Wp0J2wSiZfHeZTx6zxGf0qmZxNgMmhN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 bulkscore=0 malwarescore=0 suspectscore=0 mlxlogscore=999 clxscore=1015 priorityscore=1501 adultscore=0 impostorscore=0 phishscore=0 spamscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2401100092 The PPE device tree node includes the PPE initialization configurations and UNIPHY instance configuration. Ther are 3 UNIPHYs(PCS) on the platform ipq9574, which register the clock provider to output the clock for PPE port to work on the different link speed. Signed-off-by: Luo Jie --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 730 +++++++++++++++++++++++++- 1 file changed, 724 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 810cda4a850f..5fa241e27c8b 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -775,16 +775,734 @@ nsscc: nsscc@39b00000 { <&bias_pll_nss_noc_clk>, <&bias_pll_ubi_nc_clk>, <&gcc_gpll0_out_aux>, - <0>, - <0>, - <0>, - <0>, - <0>, - <0>, + <&uniphys 0>, + <&uniphys 1>, + <&uniphys 2>, + <&uniphys 3>, + <&uniphys 4>, + <&uniphys 5>, <&xo_board_clk>; #clock-cells = <1>; #reset-cells = <1>; }; + + qcom_ppe: qcom-ppe@3a000000 { + compatible = "qcom,ipq9574-ppe"; + reg = <0x3a000000 0xb00000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "okay"; + + clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>, + <&gcc GCC_CMN_12GPLL_SYS_CLK>, + <&gcc GCC_UNIPHY0_SYS_CLK>, + <&gcc GCC_UNIPHY1_SYS_CLK>, + <&gcc GCC_UNIPHY2_SYS_CLK>, + <&gcc GCC_UNIPHY0_AHB_CLK>, + <&gcc GCC_UNIPHY1_AHB_CLK>, + <&gcc GCC_UNIPHY2_AHB_CLK>, + <&gcc GCC_NSSCC_CLK>, + <&gcc GCC_NSSNOC_NSSCC_CLK>, + <&gcc GCC_NSSNOC_SNOC_CLK>, + <&gcc GCC_NSSNOC_SNOC_1_CLK>, + <&nsscc NSS_CC_PPE_SWITCH_CLK>, + <&nsscc NSS_CC_PPE_SWITCH_CFG_CLK>, + <&nsscc NSS_CC_NSSNOC_PPE_CLK>, + <&nsscc NSS_CC_NSSNOC_PPE_CFG_CLK>, + <&nsscc NSS_CC_PPE_EDMA_CLK>, + <&nsscc NSS_CC_PPE_EDMA_CFG_CLK>, + <&nsscc NSS_CC_PPE_SWITCH_IPE_CLK>, + <&nsscc NSS_CC_PPE_SWITCH_BTQ_CLK>, + <&nsscc NSS_CC_PORT1_MAC_CLK>, + <&nsscc NSS_CC_PORT2_MAC_CLK>, + <&nsscc NSS_CC_PORT3_MAC_CLK>, + <&nsscc NSS_CC_PORT4_MAC_CLK>, + <&nsscc NSS_CC_PORT5_MAC_CLK>, + <&nsscc NSS_CC_PORT6_MAC_CLK>, + <&nsscc NSS_CC_PORT1_RX_CLK>, + <&nsscc NSS_CC_PORT1_TX_CLK>, + <&nsscc NSS_CC_PORT2_RX_CLK>, + <&nsscc NSS_CC_PORT2_TX_CLK>, + <&nsscc NSS_CC_PORT3_RX_CLK>, + <&nsscc NSS_CC_PORT3_TX_CLK>, + <&nsscc NSS_CC_PORT4_RX_CLK>, + <&nsscc NSS_CC_PORT4_TX_CLK>, + <&nsscc NSS_CC_PORT5_RX_CLK>, + <&nsscc NSS_CC_PORT5_TX_CLK>, + <&nsscc NSS_CC_PORT6_RX_CLK>, + <&nsscc NSS_CC_PORT6_TX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT1_RX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT1_TX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT2_RX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT2_TX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT3_RX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT3_TX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT4_RX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT4_TX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT5_RX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT5_TX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT6_RX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT6_TX_CLK>, + <&nsscc NSS_CC_PORT5_RX_CLK_SRC>, + <&nsscc NSS_CC_PORT5_TX_CLK_SRC>; + clock-names = "cmn_ahb", + "cmn_sys", + "uniphy0_sys", + "uniphy1_sys", + "uniphy2_sys", + "uniphy0_ahb", + "uniphy1_ahb", + "uniphy2_ahb", + "gcc_nsscc", + "gcc_nssnoc_nsscc", + "gcc_nssnoc_snoc", + "gcc_nssnoc_snoc_1", + "nss_ppe", + "nss_ppe_cfg", + "nssnoc_ppe", + "nssnoc_ppe_cfg", + "nss_edma", + "nss_edma_cfg", + "nss_ppe_ipe", + "nss_ppe_btq", + "port1_mac", + "port2_mac", + "port3_mac", + "port4_mac", + "port5_mac", + "port6_mac", + "nss_port1_rx", + "nss_port1_tx", + "nss_port2_rx", + "nss_port2_tx", + "nss_port3_rx", + "nss_port3_tx", + "nss_port4_rx", + "nss_port4_tx", + "nss_port5_rx", + "nss_port5_tx", + "nss_port6_rx", + "nss_port6_tx", + "uniphy_port1_rx", + "uniphy_port1_tx", + "uniphy_port2_rx", + "uniphy_port2_tx", + "uniphy_port3_rx", + "uniphy_port3_tx", + "uniphy_port4_rx", + "uniphy_port4_tx", + "uniphy_port5_rx", + "uniphy_port5_tx", + "uniphy_port6_rx", + "uniphy_port6_tx", + "nss_port5_rx_clk_src", + "nss_port5_tx_clk_src"; + + resets = <&nsscc PPE_FULL_RESET>, + <&gcc GCC_UNIPHY0_SYS_RESET>, + <&gcc GCC_UNIPHY1_SYS_RESET>, + <&gcc GCC_UNIPHY2_SYS_RESET>, + <&gcc GCC_UNIPHY0_AHB_RESET>, + <&gcc GCC_UNIPHY1_AHB_RESET>, + <&gcc GCC_UNIPHY2_AHB_RESET>, + <&gcc GCC_UNIPHY0_XPCS_RESET>, + <&gcc GCC_UNIPHY1_XPCS_RESET>, + <&gcc GCC_UNIPHY2_XPCS_RESET>, + <&nsscc UNIPHY0_SOFT_RESET>, + <&nsscc UNIPHY_PORT5_ARES>, + <&nsscc UNIPHY_PORT6_ARES>, + <&nsscc UNIPHY_PORT1_ARES>, + <&nsscc UNIPHY_PORT2_ARES>, + <&nsscc UNIPHY_PORT3_ARES>, + <&nsscc UNIPHY_PORT4_ARES>, + <&nsscc NSSPORT1_RESET>, + <&nsscc NSSPORT2_RESET>, + <&nsscc NSSPORT3_RESET>, + <&nsscc NSSPORT4_RESET>, + <&nsscc NSSPORT5_RESET>, + <&nsscc NSSPORT6_RESET>, + <&nsscc PORT1_MAC_ARES>, + <&nsscc PORT2_MAC_ARES>, + <&nsscc PORT3_MAC_ARES>, + <&nsscc PORT4_MAC_ARES>, + <&nsscc PORT5_MAC_ARES>, + <&nsscc PORT6_MAC_ARES>; + reset-names = "ppe", + "uniphy0_sys", + "uniphy1_sys", + "uniphy2_sys", + "uniphy0_ahb", + "uniphy1_ahb", + "uniphy2_ahb", + "uniphy0_xpcs", + "uniphy1_xpcs", + "uniphy2_xpcs", + "uniphy0_soft", + "uniphy1_soft", + "uniphy2_soft", + "uniphy0_port1_dis", + "uniphy0_port2_dis", + "uniphy0_port3_dis", + "uniphy0_port4_dis", + "nss_port1", + "nss_port2", + "nss_port3", + "nss_port4", + "nss_port5", + "nss_port6", + "nss_port1_mac", + "nss_port2_mac", + "nss_port3_mac", + "nss_port4_mac", + "nss_port5_mac", + "nss_port6_mac"; + + uniphys: qcom-uniphy@7a00000 { + reg = <0x7a00000 0x10000>, + <0x7a10000 0x10000>, + <0x7a20000 0x10000>; + #clock-cells = <0x1>; + clock-output-names = "uniphy0_gcc_rx_clk", + "uniphy0_gcc_tx_clk", + "uniphy1_gcc_rx_clk", + "uniphy1_gcc_tx_clk", + "uniphy2_gcc_rx_clk", + "uniphy2_gcc_tx_clk"; + }; + + tdm-config { + /* + * qcom,tdm-bm-config = ; + */ + qcom,tdm-bm-config = <1 0 0 0 0>, + <1 1 0 0 0>, + <1 0 5 0 0>, + <1 1 5 0 0>, + <1 0 6 0 0>, + <1 1 6 0 0>, + <1 0 1 0 0>, + <1 1 1 0 0>, + <1 0 0 0 0>, + <1 1 0 0 0>, + <1 0 5 0 0>, + <1 1 5 0 0>, + <1 0 6 0 0>, + <1 1 6 0 0>, + <1 0 7 0 0>, + <1 1 7 0 0>, + <1 0 0 0 0>, + <1 1 0 0 0>, + <1 0 1 0 0>, + <1 1 1 0 0>, + <1 0 5 0 0>, + <1 1 5 0 0>, + <1 0 6 0 0>, + <1 1 6 0 0>, + <1 0 2 0 0>, + <1 1 2 0 0>, + <1 0 0 0 0>, + <1 1 0 0 0>, + <1 0 5 0 0>, + <1 1 5 0 0>, + <1 0 6 0 0>, + <1 1 6 0 0>, + <1 0 1 0 0>, + <1 1 1 0 0>, + <1 0 3 0 0>, + <1 1 3 0 0>, + <1 0 0 0 0>, + <1 1 0 0 0>, + <1 0 5 0 0>, + <1 1 5 0 0>, + <1 0 6 0 0>, + <1 1 6 0 0>, + <1 0 7 0 0>, + <1 1 7 0 0>, + <1 0 0 0 0>, + <1 1 0 0 0>, + <1 0 1 0 0>, + <1 1 1 0 0>, + <1 0 5 0 0>, + <1 1 5 0 0>, + <1 0 6 0 0>, + <1 1 6 0 0>, + <1 0 4 0 0>, + <1 1 4 0 0>, + <1 0 0 0 0>, + <1 1 0 0 0>, + <1 0 5 0 0>, + <1 1 5 0 0>, + <1 0 6 0 0>, + <1 1 6 0 0>, + <1 0 1 0 0>, + <1 1 1 0 0>, + <1 0 0 0 0>, + <1 1 0 0 0>, + <1 0 5 0 0>, + <1 1 5 0 0>, + <1 0 6 0 0>, + <1 1 6 0 0>, + <1 0 2 0 0>, + <1 1 2 0 0>, + <1 0 0 0 0>, + <1 1 0 0 0>, + <1 0 7 0 0>, + <1 1 7 0 0>, + <1 0 5 0 0>, + <1 1 5 0 0>, + <1 0 6 0 0>, + <1 1 6 0 0>, + <1 0 1 0 0>, + <1 1 1 0 0>, + <1 0 0 0 0>, + <1 1 0 0 0>, + <1 0 5 0 0>, + <1 1 5 0 0>, + <1 0 6 0 0>, + <1 1 6 0 0>, + <1 0 3 0 0>, + <1 1 3 0 0>, + <1 0 1 0 0>, + <1 1 1 0 0>, + <1 0 0 0 0>, + <1 1 0 0 0>, + <1 0 5 0 0>, + <1 1 5 0 0>, + <1 0 6 0 0>, + <1 1 6 0 0>, + <1 0 4 0 0>, + <1 1 4 0 0>, + <1 0 7 0 0>, + <1 1 7 0 0>; + + /* + * qcom,tdm-port-scheduler-config = ; + */ + qcom,tdm-port-scheduler-config = <0x98 6 0 1 1>, + <0x94 5 6 1 3>, + <0x86 0 5 1 4>, + <0x8C 1 6 1 0>, + <0x1C 7 5 1 1>, + <0x98 2 6 1 0>, + <0x1C 5 7 1 1>, + <0x34 3 6 1 0>, + <0x8C 4 5 1 1>, + <0x98 2 6 1 0>, + <0x8C 5 4 1 1>, + <0xA8 0 6 1 2>, + <0x98 5 1 1 0>, + <0x98 6 5 1 2>, + <0x89 1 6 1 4>, + <0xA4 3 0 1 1>, + <0x8C 5 6 1 4>, + <0xA8 0 2 1 1>, + <0x98 6 5 1 0>, + <0xC4 4 3 1 1>, + <0x94 6 5 1 0>, + <0x1C 7 6 1 1>, + <0x98 2 5 1 0>, + <0x1C 6 7 1 1>, + <0x1C 5 6 1 0>, + <0x94 3 5 1 1>, + <0x8C 4 6 1 0>, + <0x94 1 5 1 3>, + <0x94 6 1 1 0>, + <0xD0 3 5 1 2>, + <0x98 6 0 1 1>, + <0x94 5 6 1 3>, + <0x94 1 5 1 0>, + <0x98 2 6 1 1>, + <0x8C 4 5 1 0>, + <0x1C 7 6 1 1>, + <0x8C 0 5 1 4>, + <0x89 1 6 1 2>, + <0x98 5 0 1 1>, + <0x94 6 5 1 3>, + <0x92 0 6 1 2>, + <0x98 1 5 1 0>, + <0x98 6 2 1 1>, + <0xD0 0 5 1 3>, + <0x94 6 0 1 1>, + <0x8C 5 6 1 4>, + <0x8C 1 5 1 0>, + <0x1C 6 7 1 1>, + <0x1C 5 6 1 0>, + <0xB0 2 3 1 1>, + <0xC4 4 5 1 0>, + <0x8C 6 4 1 1>, + <0xA4 3 6 1 0>, + <0x1C 5 7 1 1>, + <0x4C 0 5 1 4>, + <0x8C 6 0 1 1>, + <0x34 7 6 1 3>, + <0x94 5 0 1 1>, + <0x98 6 5 1 2>; + }; + + buffer-management-config { + /* qcom,group-config = ; */ + qcom,group-config = <0 1550>; + /* + * qcom,port-config = ; + */ + qcom,port-config = <0 0 0 100 1146 7 8 0 1>, + <0 1 0 100 250 4 36 0 1>, + <0 2 0 100 250 4 36 0 1>, + <0 3 0 100 250 4 36 0 1>, + <0 4 0 100 250 4 36 0 1>, + <0 5 0 100 250 4 36 0 1>, + <0 6 0 100 250 4 36 0 1>, + <0 7 0 100 250 4 36 0 1>, + <0 8 0 128 250 4 36 0 1>, + <0 9 0 128 250 4 36 0 1>, + <0 10 0 128 250 4 36 0 1>, + <0 11 0 128 250 4 36 0 1>, + <0 12 0 128 250 4 36 0 1>, + <0 13 0 128 250 4 36 0 1>, + <0 14 0 40 250 4 36 0 1>; + }; + + queue-management-config { + /* + * qcom,group-config = ; + */ + qcom,group-config = <0 2000 0 0 0>; + /* + * qcom,queue-config = ; + */ + qcom,queue-config = <0 256 0 0 400 4 36 1>, + <256 44 0 0 250 0 36 0>; + }; + + port-scheduler-resource { + port0 { + port-id = <0>; + qcom,ucast-queue = <0 63>; + qcom,mcast-queue = <256 263>; + qcom,l0sp = <0 0>; + qcom,l0cdrr = <0 7>; + qcom,l0edrr = <0 7>; + qcom,l1cdrr = <0 0>; + qcom,l1edrr = <0 0>; + }; + + port1 { + port-id = <1>; + qcom,ucast-queue = <204 211>; + qcom,mcast-queue = <272 275>; + qcom,l0sp = <51 52>; + qcom,l0cdrr = <108 115>; + qcom,l0edrr = <108 115>; + qcom,l1cdrr = <23 24>; + qcom,l1edrr = <23 24>; + }; + + port2 { + port-id = <2>; + qcom,ucast-queue = <212 219>; + qcom,mcast-queue = <276 279>; + qcom,l0sp = <53 54>; + qcom,l0cdrr = <116 123>; + qcom,l0edrr = <116 123>; + qcom,l1cdrr = <25 26>; + qcom,l1edrr = <25 26>; + }; + + port3 { + port-id = <3>; + qcom,ucast-queue = <220 227>; + qcom,mcast-queue = <280 283>; + qcom,l0sp = <55 56>; + qcom,l0cdrr = <124 131>; + qcom,l0edrr = <124 131>; + qcom,l1cdrr = <27 28>; + qcom,l1edrr = <27 28>; + }; + + port4 { + port-id = <4>; + qcom,ucast-queue = <228 235>; + qcom,mcast-queue = <284 287>; + qcom,l0sp = <57 58>; + qcom,l0cdrr = <132 139>; + qcom,l0edrr = <132 139>; + qcom,l1cdrr = <29 30>; + qcom,l1edrr = <29 30>; + }; + + port5 { + port-id = <5>; + qcom,ucast-queue = <236 243>; + qcom,mcast-queue = <288 291>; + qcom,l0sp = <59 60>; + qcom,l0cdrr = <140 147>; + qcom,l0edrr = <140 147>; + qcom,l1cdrr = <31 32>; + qcom,l1edrr = <31 32>; + }; + + port6 { + port-id = <6>; + qcom,ucast-queue = <244 251>; + qcom,mcast-queue = <292 295>; + qcom,l0sp = <61 62>; + qcom,l0cdrr = <148 155>; + qcom,l0edrr = <148 155>; + qcom,l1cdrr = <33 34>; + qcom,l1edrr = <33 34>; + }; + + port7 { + port-id = <7>; + qcom,ucast-queue = <252 255>; + qcom,mcast-queue = <296 299>; + qcom,l0sp = <63 63>; + qcom,l0cdrr = <156 159>; + qcom,l0edrr = <156 159>; + qcom,l1cdrr = <35 35>; + qcom,l1edrr = <35 35>; + }; + }; + + port-scheduler-config { + port0 { + port-id = <0>; + l1scheduler { + group0 { + /* flow ID from L0 SP */ + qcom,flow = <0>; + /* sp cpri cdrr epri edrr */ + qcom,scheduler-config = <0 0 0 0 0>; + }; + }; + + l0scheduler { + group0 { + /* unicast queue */ + qcom,ucast-queue = <0>; + qcom,ucast-loop-priority = <8>; + /* multicast queue */ + qcom,mcast-queue = <256>; + /* sp cpri cdrr epri edrr */ + qcom,scheduler-config = <0 0 0 0 0>; + }; + + group1 { + qcom,ucast-queue = <8>; + qcom,ucast-loop-priority = <8>; + qcom,mcast-queue = <257>; + qcom,scheduler-config = <0 0 0 0 0>; + }; + + group2 { + qcom,ucast-queue = <16>; + qcom,ucast-loop-priority = <8>; + qcom,mcast-queue = <258>; + qcom,scheduler-config = <0 0 0 0 0>; + }; + + group3 { + qcom,ucast-queue = <24>; + qcom,ucast-loop-priority = <8>; + qcom,mcast-queue = <259>; + qcom,scheduler-config = <0 0 0 0 0>; + }; + + group4 { + qcom,ucast-queue = <32>; + qcom,ucast-loop-priority = <8>; + qcom,mcast-queue = <260>; + qcom,scheduler-config = <0 0 0 0 0>; + }; + + group5 { + qcom,ucast-queue = <40>; + qcom,ucast-loop-priority = <8>; + qcom,mcast-queue = <261>; + qcom,scheduler-config = <0 0 0 0 0>; + }; + + group6 { + qcom,ucast-queue = <48>; + qcom,ucast-loop-priority = <8>; + qcom,mcast-queue = <262>; + qcom,scheduler-config = <0 0 0 0 0>; + }; + + group7 { + qcom,ucast-queue = <56>; + qcom,ucast-loop-priority = <8>; + qcom,mcast-queue = <263>; + qcom,scheduler-config = <0 0 0 0 0>; + }; + }; + }; + + port1 { + port-id = <1>; + l1scheduler { + group0 { + qcom,flow = <51>; + qcom,flow-loop-priority = <2>; + qcom,scheduler-config = <1 0 23 0 23>; + }; + }; + + l0scheduler { + group0 { + qcom,ucast-queue = <204>; + qcom,ucast-loop-priority = <8>; + /* max priority per SP */ + qcom,drr-max-priority = <4>; + qcom,mcast-queue = <272>; + qcom,mcast-loop-priority = <4>; + qcom,scheduler-config = <51 0 108 0 108>; + }; + }; + }; + + port2 { + port-id = <2>; + l1scheduler { + group0 { + qcom,flow = <53>; + qcom,flow-loop-priority = <2>; + qcom,scheduler-config = <2 0 25 0 25>; + }; + }; + + l0scheduler { + group0 { + qcom,ucast-queue = <212>; + qcom,ucast-loop-priority = <8>; + /* max priority per SP */ + qcom,drr-max-priority = <4>; + qcom,mcast-queue = <276>; + qcom,mcast-loop-priority = <4>; + qcom,scheduler-config = <53 0 116 0 116>; + }; + }; + }; + + port3 { + port-id = <3>; + l1scheduler { + group0 { + qcom,flow = <55>; + qcom,flow-loop-priority = <2>; + qcom,scheduler-config = <3 0 27 0 27>; + }; + }; + + l0scheduler { + group0 { + qcom,ucast-queue = <220>; + qcom,ucast-loop-priority = <8>; + /* max priority per SP */ + qcom,drr-max-priority = <4>; + qcom,mcast-queue = <280>; + qcom,mcast-loop-priority = <4>; + qcom,scheduler-config = <55 0 124 0 124>; + }; + }; + }; + + port4 { + port-id = <4>; + l1scheduler { + group0 { + qcom,flow = <57>; + qcom,flow-loop-priority = <2>; + qcom,scheduler-config = <4 0 29 0 29>; + }; + }; + + l0scheduler { + group0 { + qcom,ucast-queue = <228>; + qcom,ucast-loop-priority = <8>; + /* max priority per SP */ + qcom,drr-max-priority = <4>; + qcom,mcast-queue = <284>; + qcom,mcast-loop-priority = <4>; + qcom,scheduler-config = <57 0 132 0 132>; + }; + }; + }; + + port5 { + port-id = <5>; + l1scheduler { + group0 { + qcom,flow = <59>; + qcom,flow-loop-priority = <2>; + qcom,scheduler-config = <5 0 31 0 31>; + }; + }; + + l0scheduler { + group0 { + qcom,ucast-queue = <236>; + qcom,ucast-loop-priority = <8>; + /* max priority per SP */ + qcom,drr-max-priority = <4>; + qcom,mcast-queue = <288>; + qcom,mcast-loop-priority = <4>; + qcom,scheduler-config = <59 0 140 0 140>; + }; + }; + }; + + port6 { + port-id = <6>; + l1scheduler { + group0 { + qcom,flow = <61>; + qcom,flow-loop-priority = <2>; + qcom,scheduler-config = <6 0 33 0 33>; + }; + }; + + l0scheduler { + group0 { + qcom,ucast-queue = <244>; + qcom,ucast-loop-priority = <8>; + /* max priority per SP */ + qcom,drr-max-priority = <4>; + qcom,mcast-queue = <292>; + qcom,mcast-loop-priority = <4>; + qcom,scheduler-config = <61 0 148 0 148>; + }; + }; + }; + + port7 { + port-id = <7>; + l1scheduler { + group0 { + qcom,flow = <63>; + qcom,scheduler-config = <7 0 35 0 35>; + }; + }; + + l0scheduler { + group0 { + qcom,ucast-queue = <252>; + qcom,ucast-loop-priority = <4>; + qcom,mcast-queue = <296>; + qcom,mcast-loop-priority = <4>; + qcom,scheduler-config = <63 0 156 0 156>; + }; + }; + }; + }; + }; }; thermal-zones { From patchwork Wed Jan 10 11:20:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 761914 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 82C6E481A8; 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Wed, 10 Jan 2024 11:21:26 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 40ABLPhF026852 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 10 Jan 2024 11:21:25 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 10 Jan 2024 03:21:21 -0800 From: Luo Jie To: , , , , CC: , , , , , , , , , , Subject: [PATCH 2/6] arm64: dts: qcom: ipq5332: Add PPE device tree node Date: Wed, 10 Jan 2024 19:20:55 +0800 Message-ID: <20240110112059.2498-3-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240110112059.2498-1-quic_luoj@quicinc.com> References: <20240110112059.2498-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: IWYwjtTgFyNSeAEuggMRF5OFQzY7Sed4 X-Proofpoint-GUID: IWYwjtTgFyNSeAEuggMRF5OFQzY7Sed4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 mlxlogscore=921 impostorscore=0 phishscore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 spamscore=0 priorityscore=1501 adultscore=1 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2401100092 The PPE device tree node includes the PPE initialization configurations and the UNIPHY(PCS) instance configurations. There are two UNIPHYs in ipq5332 platform, which provide the root clock to the PPE port to work on the different link speed. Signed-off-by: Luo Jie --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 370 +++++++++++++++++++++++++- 1 file changed, 366 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index a1504f6c40c1..bc89480820cb 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -7,6 +7,7 @@ #include #include +#include #include / { @@ -492,15 +493,376 @@ nsscc: clock-controller@39b00000{ clocks = <&cmn_pll_nss_200m_clk>, <&cmn_pll_nss_300m_clk>, <&gcc GPLL0_OUT_AUX>, - <0>, - <0>, - <0>, - <0>, + <&uniphys 0>, + <&uniphys 1>, + <&uniphys 2>, + <&uniphys 3>, <&xo_board>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; }; + + qcom_ppe: qcom-ppe@3a000000 { + compatible = "qcom,ipq5332-ppe"; + reg = <0x3a000000 0xb00000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "okay"; + + clocks = <&gcc GCC_CMN_12GPLL_AHB_CLK>, + <&gcc GCC_CMN_12GPLL_SYS_CLK>, + <&gcc GCC_UNIPHY0_SYS_CLK>, + <&gcc GCC_UNIPHY1_SYS_CLK>, + <&gcc GCC_UNIPHY0_AHB_CLK>, + <&gcc GCC_UNIPHY1_AHB_CLK>, + <&gcc GCC_NSSCC_CLK>, + <&gcc GCC_NSSNOC_SNOC_CLK>, + <&gcc GCC_NSSNOC_SNOC_1_CLK>, + <&gcc GCC_IM_SLEEP_CLK>, + <&nsscc NSS_CC_PPE_SWITCH_CLK>, + <&nsscc NSS_CC_PPE_SWITCH_CFG_CLK>, + <&nsscc NSS_CC_NSSNOC_PPE_CLK>, + <&nsscc NSS_CC_NSSNOC_PPE_CFG_CLK>, + <&nsscc NSS_CC_PPE_EDMA_CLK>, + <&nsscc NSS_CC_PPE_EDMA_CFG_CLK>, + <&nsscc NSS_CC_PPE_SWITCH_IPE_CLK>, + <&nsscc NSS_CC_PPE_SWITCH_BTQ_CLK>, + <&nsscc NSS_CC_PORT1_MAC_CLK>, + <&nsscc NSS_CC_PORT2_MAC_CLK>, + <&nsscc NSS_CC_PORT1_RX_CLK>, + <&nsscc NSS_CC_PORT1_TX_CLK>, + <&nsscc NSS_CC_PORT2_RX_CLK>, + <&nsscc NSS_CC_PORT2_TX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT1_RX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT1_TX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT2_RX_CLK>, + <&nsscc NSS_CC_UNIPHY_PORT2_TX_CLK>; + clock-names = "cmn_ahb", + "cmn_sys", + "uniphy0_sys", + "uniphy1_sys", + "uniphy0_ahb", + "uniphy1_ahb", + "gcc_nsscc", + "gcc_nssnoc_snoc", + "gcc_nssnoc_snoc_1", + "gcc_im_sleep", + "nss_ppe", + "nss_ppe_cfg", + "nssnoc_ppe", + "nssnoc_ppe_cfg", + "nss_edma", + "nss_edma_cfg", + "nss_ppe_ipe", + "nss_ppe_btq", + "port1_mac", + "port2_mac", + "nss_port1_rx", + "nss_port1_tx", + "nss_port2_rx", + "nss_port2_tx", + "uniphy_port1_rx", + "uniphy_port1_tx", + "uniphy_port2_rx", + "uniphy_port2_tx"; + + resets = <&nsscc NSS_CC_PPE_BCR>, + <&gcc GCC_UNIPHY0_SYS_CLK_ARES>, + <&gcc GCC_UNIPHY1_SYS_CLK_ARES>, + <&gcc GCC_UNIPHY0_AHB_CLK_ARES>, + <&gcc GCC_UNIPHY1_AHB_CLK_ARES>, + <&gcc GCC_UNIPHY0_XPCS_ARES>, + <&gcc GCC_UNIPHY1_XPCS_ARES>, + <&gcc GCC_UNIPHY0_BCR>, + <&gcc GCC_UNIPHY1_BCR>, + <&nsscc NSS_CC_UNIPHY_PORT1_RX_CLK_ARES>, + <&nsscc NSS_CC_UNIPHY_PORT1_TX_CLK_ARES>, + <&nsscc NSS_CC_UNIPHY_PORT2_RX_CLK_ARES>, + <&nsscc NSS_CC_UNIPHY_PORT2_TX_CLK_ARES>, + <&nsscc NSS_CC_PORT1_RX_CLK_ARES>, + <&nsscc NSS_CC_PORT1_TX_CLK_ARES>, + <&nsscc NSS_CC_PORT2_RX_CLK_ARES>, + <&nsscc NSS_CC_PORT2_TX_CLK_ARES>, + <&nsscc NSS_CC_PORT1_MAC_CLK_ARES>, + <&nsscc NSS_CC_PORT2_MAC_CLK_ARES>; + reset-names = "ppe", + "uniphy0_sys", + "uniphy1_sys", + "uniphy0_ahb", + "uniphy1_ahb", + "uniphy0_xpcs", + "uniphy1_xpcs", + "uniphy0_soft", + "uniphy1_soft", + "uniphy_port1_rx", + "uniphy_port1_tx", + "uniphy_port2_rx", + "uniphy_port2_tx", + "nss_port1_rx", + "nss_port1_tx", + "nss_port2_rx", + "nss_port2_tx", + "nss_port1_mac", + "nss_port2_mac"; + + uniphys: qcom-uniphy@7a00000 { + reg = <0x7a00000 0x10000>, + <0x7a10000 0x10000>; + #clock-cells = <0x1>; + clock-output-names = "uniphy0_gcc_rx_clk", + "uniphy0_gcc_tx_clk", + "uniphy1_gcc_rx_clk", + "uniphy1_gcc_tx_clk"; + }; + + tdm-config { + /* + * qcom,tdm-bm-config = + * ; + */ + qcom,tdm-bm-config = <1 0 2 0 0>, + <1 1 0 0 0>, + <1 0 1 0 0>, + <1 1 1 0 0>, + <1 0 2 0 0>, + <1 1 2 0 0>, + <1 0 0 0 0>, + <1 1 0 0 0>, + <1 0 2 0 0>, + <1 1 1 0 0>, + <1 0 1 0 0>, + <1 1 2 0 0>, + <1 0 0 0 0>, + <1 1 0 0 0>, + <1 0 1 0 0>, + <1 1 1 0 0>, + <1 0 2 0 0>, + <1 1 2 0 0>, + <1 0 1 0 0>, + <1 1 0 0 0>, + <1 0 2 0 0>, + <1 1 1 0 0>, + <1 0 0 0 0>, + <1 1 2 0 0>, + <1 0 2 0 0>, + <1 1 0 0 0>, + <1 0 1 0 0>, + <1 1 1 0 0>, + <1 0 0 0 0>, + <1 1 2 0 0>, + <1 0 1 0 0>, + <0 0 0 0 0>; + + /* + * qcom,tdm-port-scheduler-config = + * ; + */ + qcom,tdm-port-scheduler-config = <0x0 2 0 0 0>, + <0x0 1 2 0 0>, + <0x0 0 1 0 0>, + <0x0 0 2 0 0>, + <0x0 1 0 0 0>, + <0x0 2 1 0 0>, + <0x0 0 2 0 0>, + <0x0 0 1 0 0>, + <0x0 0 2 0 0>, + <0x0 0 1 0 0>; + }; + + buffer-management-config { + /* qcom,group-config = ; */ + qcom,group-config = <0 240>; + /* + * qcom,port-config = + * ; + */ + qcom,port-config = <0 0 12 40 30 7 5 20 1>, + <0 1 12 40 30 7 5 20 1>, + <0 2 12 40 30 7 5 20 1>, + <0 3 12 40 30 7 5 20 1>, + <0 4 12 40 30 7 5 20 1>, + <0 5 12 40 30 7 5 20 1>, + <0 6 12 40 30 7 5 20 1>, + <0 7 12 40 30 7 5 20 1>, + <0 8 12 128 48 7 5 20 1>, + <0 9 12 128 48 7 5 20 1>; + }; + + queue-management-config { + /* + * qcom,group-config = + * ; + */ + qcom,group-config = <0 500 0 0 0>; + /* + * qcom,queue-config = + * ; + */ + qcom,queue-config = <0 256 0 0 50 5 18 1>, + <256 44 0 0 50 0 18 0>; + }; + + port-scheduler-resource { + port0 { + port-id = <0>; + qcom,ucast-queue = <0 63>; + qcom,mcast-queue = <256 263>; + qcom,l0sp = <0 0>; + qcom,l0cdrr = <0 7>; + qcom,l0edrr = <0 7>; + qcom,l1cdrr = <0 0>; + qcom,l1edrr = <0 0>; + }; + + port1 { + port-id = <1>; + qcom,ucast-queue = <204 211>; + qcom,mcast-queue = <272 275>; + qcom,l0sp = <51 52>; + qcom,l0cdrr = <108 115>; + qcom,l0edrr = <108 115>; + qcom,l1cdrr = <23 24>; + qcom,l1edrr = <23 24>; + }; + + port2 { + port-id = <2>; + qcom,ucast-queue = <212 219>; + qcom,mcast-queue = <276 279>; + qcom,l0sp = <53 54>; + qcom,l0cdrr = <116 123>; + qcom,l0edrr = <116 123>; + qcom,l1cdrr = <25 26>; + qcom,l1edrr = <25 26>; + }; + }; + + port-scheduler-config { + port0 { + port-id = <0>; + l1scheduler { + group0 { + /* flow ID from L0 SP */ + qcom,flow = <0>; + /* sp cpri cdrr epri edrr */ + qcom,scheduler-config = <0 0 0 0 0>; + }; + }; + + l0scheduler { + group0 { + /* unicast queue */ + qcom,ucast-queue = <0>; + qcom,ucast-loop-priority = <8>; + /* multicast queue */ + qcom,mcast-queue = <256>; + /* sp cpri cdrr epri edrr */ + qcom,scheduler-config = <0 0 0 0 0>; + }; + + group1 { + qcom,ucast-queue = <8>; + qcom,ucast-loop-priority = <8>; + qcom,mcast-queue = <257>; + qcom,scheduler-config = <0 0 0 0 0>; + }; + + group2 { + qcom,ucast-queue = <16>; + qcom,ucast-loop-priority = <8>; + qcom,mcast-queue = <258>; + qcom,scheduler-config = <0 0 0 0 0>; + }; + + group3 { + qcom,ucast-queue = <24>; + qcom,ucast-loop-priority = <8>; + qcom,mcast-queue = <259>; + qcom,scheduler-config = <0 0 0 0 0>; + }; + + group4 { + qcom,ucast-queue = <32>; + qcom,ucast-loop-priority = <8>; + qcom,mcast-queue = <260>; + qcom,scheduler-config = <0 0 0 0 0>; + }; + + group5 { + qcom,ucast-queue = <40>; + qcom,ucast-loop-priority = <8>; + qcom,mcast-queue = <261>; + qcom,scheduler-config = <0 0 0 0 0>; + }; + + group6 { + qcom,ucast-queue = <48>; + qcom,ucast-loop-priority = <8>; + qcom,mcast-queue = <262>; + qcom,scheduler-config = <0 0 0 0 0>; + }; + + group7 { + qcom,ucast-queue = <56>; + qcom,ucast-loop-priority = <8>; + qcom,mcast-queue = <263>; + qcom,scheduler-config = <0 0 0 0 0>; + }; + }; + }; + + port1 { + port-id = <1>; + l1scheduler { + group0 { + qcom,flow = <51>; + qcom,flow-loop-priority = <2>; + qcom,scheduler-config = <1 0 23 0 23>; + }; + }; + + l0scheduler { + group0 { + qcom,ucast-queue = <204>; + qcom,ucast-loop-priority = <8>; + /* max priority per SP */ + qcom,drr-max-priority = <4>; + qcom,mcast-queue = <272>; + qcom,mcast-loop-priority = <4>; + qcom,scheduler-config = <51 0 108 0 108>; + }; + }; + }; + + port2 { + port-id = <2>; + l1scheduler { + group0 { + qcom,flow = <53>; + qcom,flow-loop-priority = <2>; + qcom,scheduler-config = <2 0 25 0 25>; + }; + }; + + l0scheduler { + group0 { + qcom,ucast-queue = <212>; + qcom,ucast-loop-priority = <8>; + /* max priority per SP */ + qcom,drr-max-priority = <4>; + qcom,mcast-queue = <276>; + qcom,mcast-loop-priority = <4>; + qcom,scheduler-config = <53 0 116 0 116>; + }; + }; + }; + }; + }; }; timer { From patchwork Wed Jan 10 11:20:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 761554 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 17F74482DD; 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Signed-off-by: Luo Jie --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 44 +++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index bc89480820cb..e6c780e69d6e 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -214,6 +214,38 @@ serial_0_pins: serial0-state { drive-strength = <8>; bias-pull-up; }; + + mdio0_pins: mdio0-state { + mux_0 { + pins = "gpio25"; + function = "mdc0"; + drive-strength = <8>; + bias-disable; + }; + + mux_1 { + pins = "gpio26"; + function = "mdio0"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + mdio1_pins: mdio1-state { + mux_0 { + pins = "gpio27"; + function = "mdc1"; + drive-strength = <8>; + bias-disable; + }; + + mux_1 { + pins = "gpio28"; + function = "mdio1"; + drive-strength = <8>; + bias-pull-up; + }; + }; }; gcc: clock-controller@1800000 { @@ -863,6 +895,18 @@ group0 { }; }; }; + + mdio: mdio@90000 { + compatible = "qcom,ipq4019-mdio"; + reg = <0x90000 0x64>; + pinctrl-0 = <&mdio1_pins &mdio0_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_MDIO_AHB_CLK>; + clock-names = "gcc_mdio_ahb_clk"; + status = "disabled"; + }; }; timer { From patchwork Wed Jan 10 11:20:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 761913 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 251B6487AC; Wed, 10 Jan 2024 11:21:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="CjalYQod" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 40A8dkpL020117; Wed, 10 Jan 2024 11:21:34 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=QrQjWGCp/5SioZxztmEdNb7eZ3tjnjFQYAo0wxrKtZ4=; b=Cj alYQod7s/wzBSLzFZSCM7dQ5bqNd7Wy76LD9xCmoou8oCaLlSoWYo/rTtAvbs2yy HoOUVY6al4EDq7WgQ3QtvenK5Y9I9QW++DJ7eamwt21GJ8Qz/4DR//8THqxaNbFM u4gR5wzhsZ8AT8jOXD+mLGOq+1QCUBL9L9UCa16PoHzc++EQ5Rnjrgz++O0U7OFp HEJ8T9z3rQ0bDP49Lmsv1G13SJ7KWZG9RtmN0thTO3l54cogMCZWbhX2FNsQFE77 PnHja7pIZ7J7fsyLpohHOt7ZPuaDD3HL17EAyvCiHd7QD+i0KigXr7yDgF4HEEBn jB6HJy1uaNX5j1JXP18Q== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3vh9evt7f6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 10 Jan 2024 11:21:34 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 40ABLXaG020731 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 10 Jan 2024 11:21:33 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 10 Jan 2024 03:21:29 -0800 From: Luo Jie To: , , , , CC: , , , , , , , , , , Subject: [PATCH 4/6] arm64: dts: qcom: ipq9574: Add MDIO device tree Date: Wed, 10 Jan 2024 19:20:57 +0800 Message-ID: <20240110112059.2498-5-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240110112059.2498-1-quic_luoj@quicinc.com> References: <20240110112059.2498-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 7fQkWV0YLXV0Xd4R2DlNcNyZXtmpoG_m X-Proofpoint-ORIG-GUID: 7fQkWV0YLXV0Xd4R2DlNcNyZXtmpoG_m X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 bulkscore=0 mlxlogscore=849 lowpriorityscore=0 mlxscore=0 priorityscore=1501 adultscore=0 suspectscore=0 clxscore=1015 spamscore=0 phishscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2401100092 Add MDIO device tree of ipq9574. Signed-off-by: Luo Jie --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 28 +++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 5fa241e27c8b..cf21ce9bf756 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -316,6 +316,22 @@ uart2_pins: uart2-state { drive-strength = <8>; bias-disable; }; + + mdio_pins: mdio-state { + mux_0 { + pins = "gpio38"; + function = "mdc"; + drive-strength = <8>; + bias-disable; + }; + + mux_1 { + pins = "gpio39"; + function = "mdio"; + drive-strength = <8>; + bias-pull-up; + }; + }; }; gcc: clock-controller@1800000 { @@ -1503,6 +1519,18 @@ group0 { }; }; }; + + mdio: mdio@90000 { + compatible = "qcom,ipq4019-mdio"; + reg = <0x90000 0x64>; + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_MDIO_AHB_CLK>; + clock-names = "gcc_mdio_ahb_clk"; + status = "disabled"; + }; }; thermal-zones { From patchwork Wed Jan 10 11:20:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 761553 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5B8F495CA; Wed, 10 Jan 2024 11:21:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="DihKeHFo" Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 40AAGBdw008594; Wed, 10 Jan 2024 11:21:38 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=d37+e83tZwogOPVrwPm8SdeiQJvavFXD5ROs6vq+SHY=; b=Di hKeHFodxIwRnYIVjmdcl+H9hIxLqKcwGOeVKglNQ7F0WHzU9n6nwh41kclwO27pz gSLn0z1vsGPHx34QjUfywhGCcA1I8pS3hBhy0PlAtbISlY5BRAY8wl21LP0aHUBK BUTEsYOakDDqsuZNE6fxzMfrCXQubzkNAi+67/eeXd+/S+k0f67r1fTdj9SpXVks +4lQWOvgwC+t/N2MB8oQNsXoaOeOT1ODLWmDJ4hnuPWl9a9K5XPqAguJI8VHzSId uERvfPIGbMYYqw48UbydEWvOCe54RJcCakYxCQBMEVAWPDwVUawHln1nd52zaf22 0odaI9uwlaJKdicp8Wog== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3vhnbnrms5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 10 Jan 2024 11:21:38 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 40ABLbix020799 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 10 Jan 2024 11:21:37 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 10 Jan 2024 03:21:33 -0800 From: Luo Jie To: , , , , CC: , , , , , , , , , , Subject: [PATCH 5/6] arm64: dts: qcom: ipq5332: Add RDP441 board device tree Date: Wed, 10 Jan 2024 19:20:58 +0800 Message-ID: <20240110112059.2498-6-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240110112059.2498-1-quic_luoj@quicinc.com> References: <20240110112059.2498-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: sAbTDsgBYlvv8YlsnNYBgKDcn9gvsDMC X-Proofpoint-GUID: sAbTDsgBYlvv8YlsnNYBgKDcn9gvsDMC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 phishscore=0 spamscore=0 clxscore=1015 priorityscore=1501 mlxlogscore=902 suspectscore=0 adultscore=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2401100092 From: Lei Wei RDP441 board has onboard QCA8386 switch and 10G SFP port. Signed-off-by: Lei Wei Signed-off-by: Luo Jie --- arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 51 +++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts index 846413817e9a..d51968e9d601 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts @@ -12,6 +12,15 @@ / { model = "Qualcomm Technologies, Inc. IPQ5332 MI01.2"; compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332"; + + soc@0 { + sfp1: sfp-1 { + compatible = "sff,sfp"; + i2c-bus = <&blsp1_i2c1>; + los-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&tlmm 24 GPIO_ACTIVE_HIGH>; + }; + }; }; &blsp1_i2c1 { @@ -63,3 +72,45 @@ data-pins { }; }; }; + +&qcom_ppe { + qcom,port_phyinfo { + ppe_port0: port@0 { + port_id = <1>; + phy-mode = "2500base-x"; + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + ppe_port1: port@1 { + port_id = <2>; + phy-mode = "10gbase-r"; + sfp = <&sfp1>; + managed = "in-band-status"; + }; + }; +}; + +&mdio { + status = "okay"; + reset-gpios = <&tlmm 51 GPIO_ACTIVE_LOW>; + + phy0: ethernet-phy@0 { + reg = <1>; + }; + + phy1: ethernet-phy@1 { + reg = <2>; + }; + + phy2: ethernet-phy@2 { + reg = <3>; + }; + + phy3: ethernet-phy@3 { + reg = <4>; + }; +}; From patchwork Wed Jan 10 11:20:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 761912 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E870A495E7; Wed, 10 Jan 2024 11:21:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="hT9KKwT9" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 40AAhJw3012648; Wed, 10 Jan 2024 11:21:42 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=6qhSHiLUEMIZqqtuODQqyRrpU7sCEv0dSwFH8nc3DCI=; b=hT 9KKwT9DPdfM7be2i14T7ztFnEkJ2MW4h1SM62f88qcOFKE7XhHlAi/v90vdrTy2n k63LPf1eKqnVeC+sYOmLG+3POihMsJTK3XG8scdQG2v7A76mNCug425EgCPmdUSh Jrr8si0/r1nhANSnHKC2fX4jCNxjKaqJmuJpe0GLASqOtycnSfaW75QCEVkPco2F 03CifEsKIAw6xu6mXTyA2qJulHVAIXUvwvKIQ4vrLKnnYHHRtqGzgbA5iarcMBpc VycNRpO3bB82DltiQBgP7+aXtsxkTUWfgt0VdryyjfioIe9oljsARmImQ8Sprfdm Pv2y5Y5jysarn2dgXIWg== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3vhsqyr335-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 10 Jan 2024 11:21:42 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 40ABLfCT027571 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 10 Jan 2024 11:21:41 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 10 Jan 2024 03:21:37 -0800 From: Luo Jie To: , , , , CC: , , , , , , , , , , Subject: [PATCH 6/6] arm64: dts: qcom: ipq9574: Add RDP433 board device tree Date: Wed, 10 Jan 2024 19:20:59 +0800 Message-ID: <20240110112059.2498-7-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20240110112059.2498-1-quic_luoj@quicinc.com> References: <20240110112059.2498-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: qRHlwPZ5X9hJR7qrkypKZKW6oTvYbnEO X-Proofpoint-ORIG-GUID: qRHlwPZ5X9hJR7qrkypKZKW6oTvYbnEO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 phishscore=0 adultscore=0 mlxlogscore=857 spamscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2401100092 From: Lei Wei RDP433 board has four QCA8075 PHYs and two Aquantia 10G PHY onboard. Signed-off-by: Lei Wei Signed-off-by: Luo Jie --- arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 66 +++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts index 1bb8d96c9a82..298c0853b4d2 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts +++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts @@ -60,3 +60,69 @@ rclk-pins { }; }; }; + +&qcom_ppe { + qcom,port_phyinfo { + ppe_port0: port@0 { + port_id = <1>; + phy-mode = "qsgmii"; + phy-handle = <&phy0>; + }; + ppe_port1: port@1 { + port_id = <2>; + phy-mode = "qsgmii"; + phy-handle = <&phy1>; + }; + ppe_port2: port@2 { + port_id = <3>; + phy-mode = "qsgmii"; + phy-handle = <&phy2>; + }; + ppe_port3: port@3 { + port_id = <4>; + phy-mode = "qsgmii"; + phy-handle = <&phy3>; + }; + ppe_port4: port@4 { + port_id = <5>; + phy-mode = "usxgmii"; + phy-handle = <&phy4>; + }; + ppe_port5: port@5 { + port_id = <6>; + phy-mode = "usxgmii"; + phy-handle = <&phy5>; + }; + }; +}; + +&mdio { + reset-gpios = <&tlmm 60 GPIO_ACTIVE_LOW>; + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <16>; + }; + + phy1: ethernet-phy@1 { + reg = <17>; + }; + + phy2: ethernet-phy@2 { + reg = <18>; + }; + + phy3: ethernet-phy@3 { + reg = <19>; + }; + + phy4: ethernet-phy@4 { + compatible ="ethernet-phy-ieee802.3-c45"; + reg = <8>; + }; + + phy5: ethernet-phy@5 { + compatible ="ethernet-phy-ieee802.3-c45"; + reg = <0>; + }; +};