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[176.184.32.47]) by smtp.gmail.com with ESMTPSA id i12-20020adff30c000000b00336b8461a5esm2980486wro.88.2024.01.09.10.09.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 09 Jan 2024 10:09:39 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Leif Lindholm , Radoslaw Biernacki , Kevin Wolf , Markus Armbruster , "Edgar E. Iglesias" , Igor Mitsyanko , Rob Herring , Alistair Francis , Peter Maydell , Marcin Juszkiewicz , =?utf-8?q?Philippe_Math?= =?utf-8?q?ieu-Daud=C3=A9?= Subject: [PATCH v2 01/14] target/arm/cpu: Simplify checking A64_MTE bit in FEATURE_ID register Date: Tue, 9 Jan 2024 19:09:16 +0100 Message-ID: <20240109180930.90793-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240109180930.90793-1-philmd@linaro.org> References: <20240109180930.90793-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org cpu_isar_feature(aa64_mte, cpu) is testing a AArch64-only ID register. The ARM_FEATURE_AARCH64 check is redundant. Signed-off-by: Philippe Mathieu-Daudé --- target/arm/cpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1c8b787482..c828b333c9 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1690,8 +1690,7 @@ void arm_cpu_post_init(Object *obj) } #ifndef CONFIG_USER_ONLY - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && - cpu_isar_feature(aa64_mte, cpu)) { + if (cpu_isar_feature(aa64_mte, cpu)) { object_property_add_link(obj, "tag-memory", TYPE_MEMORY_REGION, (Object **)&cpu->tag_memory, From patchwork Tue Jan 9 18:09:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 761057 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp1495088wrz; Tue, 9 Jan 2024 10:10:49 -0800 (PST) X-Google-Smtp-Source: AGHT+IEOLmoY/GmGl4Qxxg+d4+pDjhgsz+jnEU/ci/IijEcc7XTSFAhLoXdeNAMdT1jZKDfKnTzD X-Received: by 2002:a05:620a:1132:b0:783:29d0:f755 with SMTP id p18-20020a05620a113200b0078329d0f755mr2037756qkk.61.1704823849643; Tue, 09 Jan 2024 10:10:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704823849; cv=none; d=google.com; s=arc-20160816; b=gway182GhCj/FxmXpiCVzNwz/jUX85S9vMldjKiQlFm7tiDzmYTFNaSFz7lR/83k4n qy8EULLFBo0fD5bpCbsV5sQ/5xMRWujzeAqhslSyIkGjfFd/lc98e9YoiFC0YdHOQW66 /vtKc+OiR8erWZMEy/T9VH218HZld5Zcfy88Hngrd+71Dv7eHNMGqr0CbTFQ9nPS/vk2 tdX2H2gUE9EVfcF1NQqvVpzgACZHou1/+BUwwQEiAmxgxaTS1DlyxY8nn3gX6nSsWXSI MCF4ftQKy5emSQbwwmFzLP4gbb+QZmT80IyizWHPGu4BeWu0Afep1t0Q346Mzt5X/T3b ia7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=W5YYwF8QpDX8Jtsvrc0+qop9CxJbiTqbmmnqrqDqyeI=; fh=v69mdd+nxs/0WeTIWzLZOPCx0ynE2o0vtvId2fSwkBY=; b=QjJwpBfgsiB9Z22jIoby8N4NCsVLOQk++KjRHT48lNUxuuMbDlHRWhnZI5S3daPB4K 90+P54lHAc6HJrMSHWVhtctEieD19i1KlVZhjCQA7Vtx9UvdBBrTvX8lzt511O+9gd56 ddhzjmdAys7w+bGSFBta22C5WkoPkr6l3tmnYe4U2VH1EpqKsaGQrJxSc2y7LAHoCH4q Yp9TkI1kIebOCQVIZ03OsZB3DzsYgJRVxRW2Aqy7OMcQeHQgpDVT/NmFjHrw8kNVsdl8 Nzky0itVyd7ooeB7dzKG74qx2KAv2PYT8zmKHIIR68BPYWoasWwPZVI5RwuMIIvRqidO RKuQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zc3HwQdS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.32.47]) by smtp.gmail.com with ESMTPSA id x6-20020a5d54c6000000b0033674734a58sm3001364wrv.79.2024.01.09.10.09.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 09 Jan 2024 10:09:45 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Leif Lindholm , Radoslaw Biernacki , Kevin Wolf , Markus Armbruster , "Edgar E. Iglesias" , Igor Mitsyanko , Rob Herring , Alistair Francis , Peter Maydell , Marcin Juszkiewicz , =?utf-8?q?Philippe_Math?= =?utf-8?q?ieu-Daud=C3=A9?= Subject: [PATCH v2 02/14] hw/arm/armv7m: Introduce cpudev variable in armv7m_realize() Date: Tue, 9 Jan 2024 19:09:17 +0100 Message-ID: <20240109180930.90793-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240109180930.90793-1-philmd@linaro.org> References: <20240109180930.90793-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We are going to cast s->cpu as DeviceState multiple times. Add a local 'cpudev' variable to simplify code review, having a single DEVICE(s->cpu) conversion. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/armv7m.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 50c6c6b1f5..d239468558 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -277,6 +277,7 @@ static void armv7m_realize(DeviceState *dev, Error **errp) { ARMv7MState *s = ARMV7M(dev); SysBusDevice *sbd; + DeviceState *cpudev; Error *err = NULL; int i; @@ -299,6 +300,7 @@ static void armv7m_realize(DeviceState *dev, Error **errp) error_propagate(errp, err); return; } + cpudev = DEVICE(s->cpu); object_property_set_link(OBJECT(s->cpu), "memory", OBJECT(&s->container), &error_abort); @@ -356,7 +358,7 @@ static void armv7m_realize(DeviceState *dev, Error **errp) s->cpu->env.nvic = &s->nvic; s->nvic.cpu = s->cpu; - if (!qdev_realize(DEVICE(s->cpu), NULL, errp)) { + if (!qdev_realize(cpudev, NULL, errp)) { return; } @@ -426,8 +428,7 @@ static void armv7m_realize(DeviceState *dev, Error **errp) /* Wire the NVIC up to the CPU */ sbd = SYS_BUS_DEVICE(&s->nvic); - sysbus_connect_irq(sbd, 0, - qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ)); + sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); memory_region_add_subregion(&s->container, 0xe000e000, sysbus_mmio_get_region(sbd, 0)); From patchwork Tue Jan 9 18:09:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 761067 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp1496212wrz; Tue, 9 Jan 2024 10:13:02 -0800 (PST) X-Google-Smtp-Source: AGHT+IFgWo7vaGPxVZ7zANmHQo7ZgB+vwBPOXPoa/EW3SGG4mGvdybxHreZ4KzrIJIlJteOfAWrX X-Received: by 2002:a05:6808:1644:b0:3bb:f5a8:9798 with SMTP id az4-20020a056808164400b003bbf5a89798mr6731976oib.24.1704823982445; Tue, 09 Jan 2024 10:13:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704823982; cv=none; d=google.com; s=arc-20160816; b=qJK6Ig6c+ta9QF2fWipevwOS1XrYaDWwUbYkakM3ZwxcwILRC/97I7rUT/7X3TLq4x qPLDSwM4SfwCB/bsNMK2GihJPP0r7Mh8yDQSHDwGcMs4gcAY8f78pia0Q7O1mNDOTBEq BRq80uB/Iu/eekKenFCu/fgcoSnTtbEsO/k1A9BstD8kIJgpWSCTz1K2KUwqpig0nPh4 kpwCDBcE1frtDvGUvjzgfa6n9jWv1c9LfObPsBhJ/e2uL7sO77N6UJUXGXE6G8hAc10P uLelmHZDe+p1klCS4yu4hqUFaroGNMIdM8hbeEkdzHGIlu3Q4dmHZeXNIItrE+/MK+U3 hFCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=mdirajlt6qC945MCVDYIpUTSXSVbweTZjiyf2mppVOc=; fh=v69mdd+nxs/0WeTIWzLZOPCx0ynE2o0vtvId2fSwkBY=; b=WMz4fR6zeGMS2iESAXbd1SMkY5epeusOs98vXHR6FYYh6Hs1YL/Vgd4ntqyHPplV7F phzQTNtruqP8hLtzvhXgyVkbD+xjMJYBf1b+bpZ1vJ5mGkDhM2Rlo5QRvYhoLfXyUViQ awP5IAc8i4rAlE4TN/TpMae4KP5QBZ38ZF63VvcZLKkR0H8xUgbfmjXBA236r7avccIM VxG5JRIfvnMlmd+DHZrSEJcOHlEJhC4xu/vXSTeGDOTZ+2HvRXyNfZ1WKene7CWqj4o5 cZDv9tpz63r/KU/Cf0QGynIWAgIhxzVVdYlHLerjY3o2rfubFK4vAVVCAdD5UE7LM9se PlsQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=n03HaZy8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.32.47]) by smtp.gmail.com with ESMTPSA id c2-20020a056000104200b0033642a9a1eesm2995571wrx.21.2024.01.09.10.09.50 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 09 Jan 2024 10:09:52 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Leif Lindholm , Radoslaw Biernacki , Kevin Wolf , Markus Armbruster , "Edgar E. Iglesias" , Igor Mitsyanko , Rob Herring , Alistair Francis , Peter Maydell , Marcin Juszkiewicz , =?utf-8?q?Philippe_Math?= =?utf-8?q?ieu-Daud=C3=A9?= Subject: [PATCH v2 03/14] hw/arm/armv7m: Ensure requested CPU type implements ARM_FEATURE_M Date: Tue, 9 Jan 2024 19:09:18 +0100 Message-ID: <20240109180930.90793-4-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240109180930.90793-1-philmd@linaro.org> References: <20240109180930.90793-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org ARMV7M container can only accept M-profile CPU types. Check requested type is valid once to allow further simplifications. Suggested-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/armv7m.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index d239468558..8900730e53 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -300,6 +300,10 @@ static void armv7m_realize(DeviceState *dev, Error **errp) error_propagate(errp, err); return; } + if (!arm_feature(&s->cpu->env, ARM_FEATURE_M)) { + error_setg(errp, "armv7m: CPU must be of Cortex-M family"); + return; + } cpudev = DEVICE(s->cpu); object_property_set_link(OBJECT(s->cpu), "memory", OBJECT(&s->container), From patchwork Tue Jan 9 18:09:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 761058 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp1495307wrz; Tue, 9 Jan 2024 10:11:14 -0800 (PST) X-Google-Smtp-Source: AGHT+IGbZhGj/X/nBIng8r57V9EesNj+rMNV9dQjg+j8HwZVHtqnvVlP8zu1t2/9YfKmhAUdYhxL X-Received: by 2002:a05:6808:199a:b0:3bd:437e:853f with SMTP id bj26-20020a056808199a00b003bd437e853fmr533476oib.95.1704823874450; Tue, 09 Jan 2024 10:11:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704823874; cv=none; d=google.com; s=arc-20160816; b=RRfL6f2ditNFdpiE+0r/rO27oW+ljn4PfIM4FtOolJ9aPkPHh7AlB0XT3HuLS+nEJf vZ36jR3Eaq0MdtxHhIhDUJiyxHZHdh+fHlwLbxmDM0c9bkQFeIVKSq77ZpvqyQ3qv+5O qiwp86VXrvjZ+x1/fMr1xS77wDbpI2yhFezukB01dhYL4Hw6nUiZPRnYlwtB+C/HKuPt HrIj4Snx6OMwSfMfvNHTiC7alSY0Rf0HWiigP8GVevSKFEy3eaURn7VQBelTM6pFCM6r psUaaBTtY7WhWlKS8mL2XYDM6wRncys7/1p5fB0vhlxkCagIhyVbl0KcO7/rqrkCn4v1 Nlgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=znfL4d0kUd7PQLWgd/IbU4xVCADxWCmjPBLUUJRZlJU=; fh=v69mdd+nxs/0WeTIWzLZOPCx0ynE2o0vtvId2fSwkBY=; b=ZT8i20xzjOxvdTDzz1j2Q9ueUGrcsKJ0yDd4Y6G2Lq9n7oicSKnQs3GIizX43DMcx+ e9PqSt5JUfGn3zqTcq5hDpy7NE0qB9hQbbr0JkIxfJBr54WZVllKcLrbCE6j4mAxKHDz W1IaGB03o+eKE83Fo75geNEkM+j1ZW/a7BZ6xpZ0krHKqPUlRSU3T3+5fjfnlg89G44G AE4r2rkcikkrJQ8tuRczk4Azo53oj0nWPqyPvV6mwPGOVd6bokx9qFdU1dQm7d6b+omL p0IcMsyfsKnrVi/5VbA1dA/NN+05HYGhdeHTUjBp91M1jZEOUiWBwNHgiqNxp3Krw6om 7liA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=F+I7cVJ8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.32.47]) by smtp.gmail.com with ESMTPSA id r14-20020a5d494e000000b003364a0e6983sm2975178wrs.62.2024.01.09.10.09.57 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 09 Jan 2024 10:09:58 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Leif Lindholm , Radoslaw Biernacki , Kevin Wolf , Markus Armbruster , "Edgar E. Iglesias" , Igor Mitsyanko , Rob Herring , Alistair Francis , Peter Maydell , Marcin Juszkiewicz , =?utf-8?q?Philippe_Math?= =?utf-8?q?ieu-Daud=C3=A9?= Subject: [PATCH v2 04/14] hw/arm/armv7m: Move code setting 'start-powered-off' property around Date: Tue, 9 Jan 2024 19:09:19 +0100 Message-ID: <20240109180930.90793-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240109180930.90793-1-philmd@linaro.org> References: <20240109180930.90793-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reorganize a bit by first setting properties which are not dependent of CPU features (and can not fail). Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/armv7m.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 8900730e53..b752049add 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -308,6 +308,7 @@ static void armv7m_realize(DeviceState *dev, Error **errp) object_property_set_link(OBJECT(s->cpu), "memory", OBJECT(&s->container), &error_abort); + qdev_prop_set_bit(cpudev, "start-powered-off", s->start_powered_off); if (object_property_find(OBJECT(s->cpu), "idau")) { object_property_set_link(OBJECT(s->cpu), "idau", s->idau, &error_abort); @@ -334,7 +335,6 @@ static void armv7m_realize(DeviceState *dev, Error **errp) return; } } - qdev_prop_set_bit(DEVICE(s->cpu), "start-powered-off", s->start_powered_off); /* * Real M-profile hardware can be configured with a different number of From patchwork Tue Jan 9 18:09:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 761059 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp1495426wrz; Tue, 9 Jan 2024 10:11:27 -0800 (PST) X-Google-Smtp-Source: AGHT+IFRfS5xGVSgL9GOike8GpwkJIXWrA7f5oWzON6jNweERKYmnu7J4GJhQ8npQPgaRdWSrwy4 X-Received: by 2002:ac8:5fd1:0:b0:429:8e28:8f1c with SMTP id k17-20020ac85fd1000000b004298e288f1cmr5104483qta.47.1704823887290; Tue, 09 Jan 2024 10:11:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704823887; cv=none; d=google.com; s=arc-20160816; b=ti/H8+yAkRRe+U7YGRjbWZ2AKcqDUygpgfmfw/G04fjfmO0GKGfUY68q3vHLUFgnHQ ezO87oDqzIed/uwFF79BdxvwgjvYLLBZnH4mB56yFibcmE5PrieZCKvGhwxGS02J1+Ji LzsZcvpcEoPMecxQVff3lSAbp1HQlV3S9oh+8YYEFTl4wMb6nr4XApW0WO5ctEGgX9UL UhMDkk2h/tW2ql2wRGdxeii1iyiOnY+a/5p8Ms7uWqA7fBMNsWH/jIgc1qzJ/8ju2+rj K3IijmomcpYxs93d8dBJEnH3Cr3dpxd/CVSrKyFMKUXXcI/eeRalNdSPaBJkBY/U78IT SgBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=fOLjDR/IKNF0Xh0mudwkf1U6/g8RGHkdFKaUB2oy+80=; fh=v69mdd+nxs/0WeTIWzLZOPCx0ynE2o0vtvId2fSwkBY=; b=bpr+DVfRIK+eEdw7KXCW8ZZpLBBGqrzDpsSZspiM1/p30VU70MPgA389D+CV8oGgL1 kRnvOFdrssWiX1dWdipHNS4Ps9fLYOPeu5lyXiN8hg/se4RXVukcgXImPlnsibR2qhS8 5KuHMm133bSDRRiWq87/oDMBB2JYjcvaS2x1oc9jNmPIXHoLbbUCe5Zl4Jd38r4R2x0h WiMPAWaVevTvpXfOg2mDocyWb6l38EfWdyjdjdGQWYjxlo2xjSjCL4LXN7LyvEXYkGuE pjM3NCKErzEfDWVvYPDu3xSDUyXZ/zmvgxLrC9zazYa7qxFvctw/0tPA7SlkDYBfnD+o jdrA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BaTqlScV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.32.47]) by smtp.gmail.com with ESMTPSA id n25-20020a05600c3b9900b0040e527602c8sm2101803wms.9.2024.01.09.10.10.03 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 09 Jan 2024 10:10:05 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Leif Lindholm , Radoslaw Biernacki , Kevin Wolf , Markus Armbruster , "Edgar E. Iglesias" , Igor Mitsyanko , Rob Herring , Alistair Francis , Peter Maydell , Marcin Juszkiewicz , =?utf-8?q?Philippe_Math?= =?utf-8?q?ieu-Daud=C3=A9?= Subject: [PATCH v2 05/14] hw/arm/armv7m: Always set 'init-nsvtor' property for Cortex-M CPUs Date: Tue, 9 Jan 2024 19:09:20 +0100 Message-ID: <20240109180930.90793-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240109180930.90793-1-philmd@linaro.org> References: <20240109180930.90793-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org All CPUs implementing ARM_FEATURE_M have the 'init-nsvtor' property. Since setting the property can not fail, replace object_property_set_uint(..., "init-nsvtor", ..., &error_abort); by: qdev_prop_set_uint32(..., "init-nsvtor", ...). which is a one-to-one replacement. Suggested-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/armv7m.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index b752049add..530729f42e 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -309,6 +309,8 @@ static void armv7m_realize(DeviceState *dev, Error **errp) object_property_set_link(OBJECT(s->cpu), "memory", OBJECT(&s->container), &error_abort); qdev_prop_set_bit(cpudev, "start-powered-off", s->start_powered_off); + qdev_prop_set_uint32(cpudev, "init-nsvtor", s->init_nsvtor); + if (object_property_find(OBJECT(s->cpu), "idau")) { object_property_set_link(OBJECT(s->cpu), "idau", s->idau, &error_abort); @@ -319,12 +321,6 @@ static void armv7m_realize(DeviceState *dev, Error **errp) return; } } - if (object_property_find(OBJECT(s->cpu), "init-nsvtor")) { - if (!object_property_set_uint(OBJECT(s->cpu), "init-nsvtor", - s->init_nsvtor, errp)) { - return; - } - } if (object_property_find(OBJECT(s->cpu), "vfp")) { if (!object_property_set_bool(OBJECT(s->cpu), "vfp", s->vfp, errp)) { return; From patchwork Tue Jan 9 18:09:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 761061 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp1495443wrz; Tue, 9 Jan 2024 10:11:29 -0800 (PST) X-Google-Smtp-Source: AGHT+IFYfUUlZnepCpY60Q6n5VFw6eBrW3ntIKJqMwQqfCTm0Fc/9JqPX0ndanNFchXp73NsYNn0 X-Received: by 2002:a05:6214:248c:b0:67a:a58f:e364 with SMTP id gi12-20020a056214248c00b0067aa58fe364mr7911218qvb.31.1704823888854; Tue, 09 Jan 2024 10:11:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704823888; cv=none; d=google.com; s=arc-20160816; b=t7imi798mLvFc7r80AdzD2WTjWu7KFubHAu25UuHV7KfjwhBf5otKVFPqKaFcDNISV s3a7kxyyVY+GXWpfM0FgTvucan9L8unEj9OtmRgwnWhcLuPUVUXxksLH7inzt4lCcPjr Ucj50ZWQmh5xtI7WmkglI6E+EugLUfhKBufU62xqLcxcCyluTwuuN2qMfIEd38gMRUiF iu0CAn7MzbRLqRQhK3fwi97rQDjwmEREmO0gPcFTWr8cliK6sIF+kmzjujNigC8fUGIM 7pSqClENJBQ5zcGn2haYX4SkoiZ1BlClBhyC5rr0iCNMll2goOARWQY8cb8qcl295kka jc1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=+Lqyw2xeJxP0nadk2efU9Sx5aGl4DyqfaFeDtt0siLg=; fh=v69mdd+nxs/0WeTIWzLZOPCx0ynE2o0vtvId2fSwkBY=; b=fZjKIu1LY6eKd1Wp1XtIzDUo2+BMgO4+EltLJ1YW+7Cg8Fdl16qKli0ZsSQWvpA4Dh T+ISOzjyKzA1xU/dEWLiFonnKKlSirya7VuYlt03TK+wyDUF9hgFDSRh+BzTMo7Ko42Z 92u208B0ZdTRy68z4mKRlSdB80Ok8F+zgNFPE17N8SRbHYKj4UXd+GK1OeWjeOG9wYQE QuWf/FDjFQKNAev7jPThDo7Blc858tUBc+FZbEgp/fPPoF4VjMa1CXyW1jrJK/CEuR9S uBcC7Pqqh9sw2dgvi9q4GzWwIx3jacCBdrneWiGCN+6nKn7RtVXXCGJYFHLMcvxtilos 2xLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EerEEoYu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.32.47]) by smtp.gmail.com with ESMTPSA id gw24-20020a05600c851800b0040d3276ba19sm4549145wmb.25.2024.01.09.10.10.09 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 09 Jan 2024 10:10:11 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Leif Lindholm , Radoslaw Biernacki , Kevin Wolf , Markus Armbruster , "Edgar E. Iglesias" , Igor Mitsyanko , Rob Herring , Alistair Francis , Peter Maydell , Marcin Juszkiewicz , =?utf-8?q?Philippe_Math?= =?utf-8?q?ieu-Daud=C3=A9?= Subject: [PATCH v2 06/14] hw/arm: Prefer arm_feature(M_SECURITY) over object_property_find() Date: Tue, 9 Jan 2024 19:09:21 +0100 Message-ID: <20240109180930.90793-7-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240109180930.90793-1-philmd@linaro.org> References: <20240109180930.90793-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Both "idau" and "init-svtor" properties are added to ARMCPU when the ARM_FEATURE_M_SECURITY feature is available. Rather than checking whether the QOM properties are present, directly check the feature. Since we are sure the "init-svtor" is present, the object_property_set_uint() can't fail. Instead of using &error_abort, replace: object_property_set_uint(OBJECT(s->cpu), "init-svtor", s->init_svtor, &error_abort); by: qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor); which is a one-to-one replacement. Suggested-by: Markus Armbruster Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/armv7m.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 530729f42e..8350267d96 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -311,16 +311,11 @@ static void armv7m_realize(DeviceState *dev, Error **errp) qdev_prop_set_bit(cpudev, "start-powered-off", s->start_powered_off); qdev_prop_set_uint32(cpudev, "init-nsvtor", s->init_nsvtor); - if (object_property_find(OBJECT(s->cpu), "idau")) { + if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY)) { + qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor); object_property_set_link(OBJECT(s->cpu), "idau", s->idau, &error_abort); } - if (object_property_find(OBJECT(s->cpu), "init-svtor")) { - if (!object_property_set_uint(OBJECT(s->cpu), "init-svtor", - s->init_svtor, errp)) { - return; - } - } if (object_property_find(OBJECT(s->cpu), "vfp")) { if (!object_property_set_bool(OBJECT(s->cpu), "vfp", s->vfp, errp)) { return; From patchwork Tue Jan 9 18:09:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 761063 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp1495596wrz; Tue, 9 Jan 2024 10:11:47 -0800 (PST) X-Google-Smtp-Source: AGHT+IGmzsgPapArrIDAlcIFB5eTmj4dygJ4sdgy5DXHn5W08wR5u/WQhh3IK0PBG8RgaCwp1rq5 X-Received: by 2002:a05:6214:76f:b0:67a:2061:d4dd with SMTP id f15-20020a056214076f00b0067a2061d4ddmr6547297qvz.50.1704823907051; Tue, 09 Jan 2024 10:11:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704823907; cv=none; d=google.com; s=arc-20160816; b=NWH2TxdvpVIFqCjybPet4bVCHE76M02KiSDNbfr1g+/FVp/aoDkl7+p77O8M7Anwti ybpMWiM/e2ZOy+/i7sj+ckbxgbPmeI/A2Zs0XHZoSkGAkwbKb03ZYvrm93rvy0oE0pNv SV82uX31vDUEmkMurFEh2Izn85WGRIxQnL5iJN/i+LFSX9XbMP5XfPZOMZdTpJAAdt5p +LYyULsKbNIVx7GIGQAVlYfifM2+5fuF+iukjstFLV9CHK91TMmHaZbGlEWfMKnS08KH Ff60XkdduK0O4a9x20Qxb+VO/zJBlwqpHOxZOTeOCX5IfXoG68HK0Y07A/Ug8YFvdQyP oiBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=5n6b/Kfb2q1nuszk7kQnrf8+ZzcUeVpd0islGk5jF8M=; fh=v69mdd+nxs/0WeTIWzLZOPCx0ynE2o0vtvId2fSwkBY=; b=CuQ+z9GBVe8GehrL8dbXRysslO/4UK8dMKaF9NxGh8h+7m31WElKCOKFnBleOLnmcz BDcFxNutC1Ol5yHtKTTjTW6u7ZSjwwiCUtt2GagC6Nvlb2hnkJX42PToiJTROQz4Ckg5 m9EULwELc4pKS+B2PW37rSMXJT8VQbxBjSjz8WXdiVDZMcokmwbMYFPnoFqktKagXRvI R8xYz7k5e6abLbqRseQaMjvHxbeLzOa4yFRuKW4CDTH62gj9VeH4aMyki97NQ4dXddGR VvPgibD2vyBdAqD3AckVjyumxC4AWoEjkCs8rU0WwoGefupkcSY2qOf9N7xi8uwin6ED LXmA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cE5mV5dX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.32.47]) by smtp.gmail.com with ESMTPSA id i1-20020a05600c354100b0040d5a5c523csm15647125wmq.1.2024.01.09.10.10.16 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 09 Jan 2024 10:10:17 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Leif Lindholm , Radoslaw Biernacki , Kevin Wolf , Markus Armbruster , "Edgar E. Iglesias" , Igor Mitsyanko , Rob Herring , Alistair Francis , Peter Maydell , Marcin Juszkiewicz , =?utf-8?q?Philippe_Math?= =?utf-8?q?ieu-Daud=C3=A9?= Subject: [PATCH v2 07/14] hw/arm: Prefer arm_feature(THUMB_DSP) over object_property_find(dsp) Date: Tue, 9 Jan 2024 19:09:22 +0100 Message-ID: <20240109180930.90793-8-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240109180930.90793-1-philmd@linaro.org> References: <20240109180930.90793-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The "dsp" property is added to ARMCPU when the ARM_FEATURE_THUMB_DSP feature is available. Rather than checking whether the QOM property is present, directly check the feature. Suggested-by: Markus Armbruster Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/armv7m.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 8350267d96..0a7ad2b762 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -321,7 +321,7 @@ static void armv7m_realize(DeviceState *dev, Error **errp) return; } } - if (object_property_find(OBJECT(s->cpu), "dsp")) { + if (arm_feature(&s->cpu->env, ARM_FEATURE_THUMB_DSP)) { if (!object_property_set_bool(OBJECT(s->cpu), "dsp", s->dsp, errp)) { return; } From patchwork Tue Jan 9 18:09:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 761062 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp1495456wrz; Tue, 9 Jan 2024 10:11:30 -0800 (PST) X-Google-Smtp-Source: AGHT+IFWH0RTTqFXY+18Dd07P+TnuNXgrcTDxtEY1Ljr0o9Y1fel498dph6kNFkloOJs8PPpgbmY X-Received: by 2002:a0c:e84d:0:b0:680:f847:e6a9 with SMTP id l13-20020a0ce84d000000b00680f847e6a9mr5875856qvo.27.1704823890044; Tue, 09 Jan 2024 10:11:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704823890; cv=none; d=google.com; s=arc-20160816; b=WnuL6Kn3YhZDAqi78n6Bb+c8PIjcTAR1yEvQmg2Ruk0oBtQ7k5d+j/UcLQai4kwNIF /i/jbPJYXFixIc7Oak6IznizOlOu7SwMBem7T4OLu4nYt+/y1SD/FBI+gbX0tMdaI7Oh uyo0+AfogztWEeyoeAvw0XJ2/oVUipDQxut46dYlId8fLvQT5NaOVThItylrMQErIvjw suvXmFf3ax89n9TN2vBWL28pdB04OcJoO7YwFlN4eJ45pjh+SP3+hSPBWBSwMbd3qep8 yVXYktv0b6MKAMCyivJhsj02b9U8suDgO3v+/Hz9xswoGYHO+8Hvea8PBmVWoqeHJyDT 7Akg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=4lFs+peHffZXBVVkShWxuZ7VjcO+rV+nUwkZ0/LL7Zg=; fh=v69mdd+nxs/0WeTIWzLZOPCx0ynE2o0vtvId2fSwkBY=; b=tF3N4Ytitb+EkdivN+tBS/rHCto98j62Wl6DsAYAbPFdXEvquAQTjprpy6jx9FsWA0 z8LE9Rs8GhB2Q8qONFV287lMJvd0hd7NO+HlRv+t2/KA1ctdizfIRVBdIwmKn5HHbltl 4D+0+1OJP807VrFLUSff+x4WgxkwxeEnz/3hB2Py3/I6gLVIXCherusD0BC/4/U0gRCw VkRVEEn+sy15NEbgwLIA/5QOFmXUs5MlE97TnNuRSh9cw5ggXlrbg+hl7DCwGbLG6O9R 2QEqXLy/ZicK7Wtu52WfzstDpFtl+SVHebQtNWn3ZUYnqBIAV++Z+7ueJnce2Z8h3pNK CY9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GBnNFNk2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.32.47]) by smtp.gmail.com with ESMTPSA id je4-20020a05600c1f8400b0040e38b7cfdasm15763276wmb.4.2024.01.09.10.10.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 09 Jan 2024 10:10:24 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Leif Lindholm , Radoslaw Biernacki , Kevin Wolf , Markus Armbruster , "Edgar E. Iglesias" , Igor Mitsyanko , Rob Herring , Alistair Francis , Peter Maydell , Marcin Juszkiewicz , =?utf-8?q?Philippe_Math?= =?utf-8?q?ieu-Daud=C3=A9?= Subject: [PATCH v2 08/14] hw/arm: Prefer arm_feature(V7) over object_property_find(pmsav7-dregion) Date: Tue, 9 Jan 2024 19:09:23 +0100 Message-ID: <20240109180930.90793-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240109180930.90793-1-philmd@linaro.org> References: <20240109180930.90793-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The "pmsav7-dregion" property is added to ARMCPU when the ARM_FEATURE_V7 feature is available. Rather than checking whether the QOM property is present, directly check the feature. Suggested-by: Markus Armbruster Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/armv7m.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 0a7ad2b762..7f15318ae3 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -338,8 +338,8 @@ static void armv7m_realize(DeviceState *dev, Error **errp) "mpu-ns-regions and mpu-s-regions properties must have the same value"); return; } - if (s->mpu_ns_regions != UINT_MAX && - object_property_find(OBJECT(s->cpu), "pmsav7-dregion")) { + if (s->mpu_ns_regions != UINT_MAX && arm_feature(&s->cpu->env, + ARM_FEATURE_V7)) { if (!object_property_set_uint(OBJECT(s->cpu), "pmsav7-dregion", s->mpu_ns_regions, errp)) { return; From patchwork Tue Jan 9 18:09:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 761064 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp1495957wrz; Tue, 9 Jan 2024 10:12:27 -0800 (PST) X-Google-Smtp-Source: AGHT+IGl7I+85jwMMtV4Cpyu4VV1MBj58QE4L3aiEhsn3N56tY3Ghn+TgGaNWpfIPseAan5K1155 X-Received: by 2002:ae9:c308:0:b0:783:825:3bea with SMTP id n8-20020ae9c308000000b0078308253beamr5781592qkg.76.1704823946808; Tue, 09 Jan 2024 10:12:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704823946; cv=none; d=google.com; s=arc-20160816; b=FIcD9j5zAO8wgp9zptHHAT+bSU2Pxj9VdVtPQqp4/BkiFBXq1ZKrYwOZuufPJHM08u ykHDtzan/E70TOup8TBeT4HCa/PmLBhh93j7+ou/sEO+RtwlxjiY9yO2wVhkfgUTpo/t YRqFLqm8GVFt9iaEwybRp2NxBqskRwLBxPgC1KbFcUrjg9G/YaLovsz1a5enHQUa2d9n W/vexbOX14kDYQfY5hUZ6PKVEimamfVZHJ1jRWDvQsk8l1Q95o5gkEVvFnTlTrs/CHL8 e9IrIJ5qOcPEA8WVq1VSk3980YkEpSazZefgqmJjk9qRtSX/XO84zuTedtLtpQU5S6rC 0ZaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Fs9yHmgYAN3jLkfd5xrkR/STV7YHc6sb5NlHxAOGVok=; fh=v69mdd+nxs/0WeTIWzLZOPCx0ynE2o0vtvId2fSwkBY=; b=AzL1MSk4RMVoENoN4MTpYxpyxQdRawLIL4djUO617N1XQO/4tFscLpHgYqpZA3xOLj Oob5U48rYrDwPOFnPYsip5PzsvAq7PA1+/DY45JKm+/5ew8ilbHOYgFAzkoDlc+2uRvn 8lndzai9sdCfh17a9rnBQy6nOcxBk2ErHWX9+hdczl6KG4G3YbSuQwtbcFC6FzS1ya6B fL9j7gGEbl8tr2dFmmNvPG9GB33QqzQUbs0NAceACa7xMACfHAl87JqF4qRe+QaFa0Ma 3Ds1aF8mSc0eA0YKc7cWbPEFw0cFPbCdfDWhGCrzX6Sa8hIiItCKtFk3ZtiJ319FhsUV oyoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TfNtrFZw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.32.47]) by smtp.gmail.com with ESMTPSA id f16-20020adffcd0000000b003373ef060d5sm2990432wrs.113.2024.01.09.10.10.29 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 09 Jan 2024 10:10:31 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Leif Lindholm , Radoslaw Biernacki , Kevin Wolf , Markus Armbruster , "Edgar E. Iglesias" , Igor Mitsyanko , Rob Herring , Alistair Francis , Peter Maydell , Marcin Juszkiewicz , =?utf-8?q?Philippe_Math?= =?utf-8?q?ieu-Daud=C3=A9?= Subject: [PATCH v2 09/14] hw/arm: Prefer arm_feature(EL3) over object_property_find(has_el3) Date: Tue, 9 Jan 2024 19:09:24 +0100 Message-ID: <20240109180930.90793-10-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240109180930.90793-1-philmd@linaro.org> References: <20240109180930.90793-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The "has_el3" property is added to ARMCPU when the ARM_FEATURE_EL3 feature is available. Rather than checking whether the QOM property is present, directly check the feature. Suggested-by: Markus Armbruster Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/exynos4210.c | 4 ++-- hw/arm/integratorcp.c | 5 ++--- hw/arm/realview.c | 2 +- hw/arm/versatilepb.c | 5 ++--- hw/arm/xilinx_zynq.c | 2 +- hw/cpu/a15mpcore.c | 11 +++++++---- hw/cpu/a9mpcore.c | 6 +++--- 7 files changed, 18 insertions(+), 17 deletions(-) diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index de39fb0ece..5efaa538cd 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -554,14 +554,14 @@ static void exynos4210_realize(DeviceState *socdev, Error **errp) for (n = 0; n < EXYNOS4210_NCPUS; n++) { Object *cpuobj = object_new(ARM_CPU_TYPE_NAME("cortex-a9")); + s->cpu[n] = ARM_CPU(cpuobj); /* By default A9 CPUs have EL3 enabled. This board does not currently * support EL3 so the CPU EL3 property is disabled before realization. */ - if (object_property_find(cpuobj, "has_el3")) { + if (arm_feature(&s->cpu[n]->env, ARM_FEATURE_EL3)) { object_property_set_bool(cpuobj, "has_el3", false, &error_fatal); } - s->cpu[n] = ARM_CPU(cpuobj); object_property_set_int(cpuobj, "mp-affinity", exynos4210_calc_affinity(n), &error_abort); object_property_set_int(cpuobj, "reset-cbar", diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c index 1830e1d785..7685527eb2 100644 --- a/hw/arm/integratorcp.c +++ b/hw/arm/integratorcp.c @@ -596,19 +596,18 @@ static void integratorcp_init(MachineState *machine) int i; cpuobj = object_new(machine->cpu_type); + cpu = ARM_CPU(cpuobj); /* By default ARM1176 CPUs have EL3 enabled. This board does not * currently support EL3 so the CPU EL3 property is disabled before * realization. */ - if (object_property_find(cpuobj, "has_el3")) { + if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { object_property_set_bool(cpuobj, "has_el3", false, &error_fatal); } qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); - cpu = ARM_CPU(cpuobj); - /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */ /* ??? RAM should repeat to fill physical memory space. */ /* SDRAM at address zero*/ diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 132217b2ed..433fe72ced 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -123,7 +123,7 @@ static void realview_init(MachineState *machine, * does not currently support EL3 so the CPU EL3 property is disabled * before realization. */ - if (object_property_find(cpuobj, "has_el3")) { + if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { object_property_set_bool(cpuobj, "has_el3", false, &error_fatal); } diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index 4b2257787b..1969bb4608 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -208,19 +208,18 @@ static void versatile_init(MachineState *machine, int board_id) } cpuobj = object_new(machine->cpu_type); + cpu = ARM_CPU(cpuobj); /* By default ARM1176 CPUs have EL3 enabled. This board does not * currently support EL3 so the CPU EL3 property is disabled before * realization. */ - if (object_property_find(cpuobj, "has_el3")) { + if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { object_property_set_bool(cpuobj, "has_el3", false, &error_fatal); } qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); - cpu = ARM_CPU(cpuobj); - /* ??? RAM should repeat to fill physical memory space. */ /* SDRAM at address zero. */ memory_region_add_subregion(sysmem, 0, machine->ram); diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index dbb9793aa1..33e57dceef 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -198,7 +198,7 @@ static void zynq_init(MachineState *machine) * currently support EL3 so the CPU EL3 property is disabled before * realization. */ - if (object_property_find(OBJECT(cpu), "has_el3")) { + if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { object_property_set_bool(OBJECT(cpu), "has_el3", false, &error_fatal); } diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index bfd8aa5644..cebfe142cf 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -53,7 +53,6 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp) DeviceState *gicdev; SysBusDevice *busdev; int i; - bool has_el3; bool has_el2 = false; Object *cpuobj; @@ -62,13 +61,17 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp) qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); if (!kvm_irqchip_in_kernel()) { + CPUState *cpu; + /* Make the GIC's TZ support match the CPUs. We assume that * either all the CPUs have TZ, or none do. */ - cpuobj = OBJECT(qemu_get_cpu(0)); - has_el3 = object_property_find(cpuobj, "has_el3") && + cpu = qemu_get_cpu(0); + cpuobj = OBJECT(cpu); + if (arm_feature(cpu_env(cpu), ARM_FEATURE_EL3)) { object_property_get_bool(cpuobj, "has_el3", &error_abort); - qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); + qdev_prop_set_bit(gicdev, "has-security-extensions", true); + } /* Similarly for virtualization support */ has_el2 = object_property_find(cpuobj, "has_el2") && object_property_get_bool(cpuobj, "has_el2", &error_abort); diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index d03f57e579..9355e8443b 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -52,7 +52,6 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp) SysBusDevice *scubusdev, *gicbusdev, *gtimerbusdev, *mptimerbusdev, *wdtbusdev; int i; - bool has_el3; CPUState *cpu0; Object *cpuobj; @@ -81,9 +80,10 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp) /* Make the GIC's TZ support match the CPUs. We assume that * either all the CPUs have TZ, or none do. */ - has_el3 = object_property_find(cpuobj, "has_el3") && + if (arm_feature(cpu_env(cpu0), ARM_FEATURE_EL3)) { object_property_get_bool(cpuobj, "has_el3", &error_abort); - qdev_prop_set_bit(gicdev, "has-security-extensions", has_el3); + qdev_prop_set_bit(gicdev, "has-security-extensions", true); + } if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { return; From patchwork Tue Jan 9 18:09:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 761069 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp1496229wrz; Tue, 9 Jan 2024 10:13:04 -0800 (PST) X-Google-Smtp-Source: AGHT+IEN3x6xzhMBakhJQezk2Wj4sMwHQAoreQzkK35HFChE91kaKROw2j9obpL/FT6f46hHzZm3 X-Received: by 2002:a05:620a:2287:b0:783:3443:7f55 with SMTP id o7-20020a05620a228700b0078334437f55mr121658qkh.122.1704823983801; Tue, 09 Jan 2024 10:13:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704823983; cv=none; d=google.com; s=arc-20160816; b=GzexPwrqEOI2w9+zc6/rPt7Y21a4f08JNBgASzwf9JPpNy62LQKapCtIGLE/dXX4vU KdbZ8/P/N7z8mKlI/iH4b5QWA7yNpYlT/RuZd5ISQrbRHbe/Sm8p/al1Lj4iSRQGUGxF jARGR4vXXTVZkIT52owZWix9X1SeELTvV1lY/EWup7PRMgeMPP9XpCVTLVSekEl6cqTF 8zZKtdMSnGTl/PuXFesF8b5mm22KgDU3AG34MkU94hwRY7IFvLCSOJDi9q3OTWzsHXGu EpiGKwz5BomweF1Wh6bB78c/N32FPjl0UVP618ddIf70AhBZqSLbuYCzIEIFTnkWQMo9 k0Kw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ZzKRv8rSt0g4enhYH8TEbkEK8L7Z/ollqT46K3u21b8=; fh=v69mdd+nxs/0WeTIWzLZOPCx0ynE2o0vtvId2fSwkBY=; b=rYaJDg6kV7R5T+B6GcLZPRMkT2W2Oemn5aH3XnqJPK15maSh0JJ8L4OsmEClCbbHa6 Vnmn2fvUPbrmYz+5sBZXY6yvGDlhOL4/2/FjYJ6YHcrjzGExIXmVUKExzUGuJ0dA4le1 vgwWmF/GhJ15BZlcPiPhFOrE2WnL3ra8LoTuRq/oh++1bWKW91Zbud6POHL5O8yfSV+R 9R/8rOtyegxhAB4qJauOHSxFQKqwaqDFrZ9q+HofZDEpMfMlOJkmM7UrhY1BKGCM+W4u d0QVU6SqLPoJ+g9omMTH4IramJirjm3l0CEB9pUuFFbApL0PLbURJ2BZEOM/yavjegB3 56zQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=v8HxgRQN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.32.47]) by smtp.gmail.com with ESMTPSA id t6-20020a05600c198600b0040e4a7a7ca3sm4385674wmq.43.2024.01.09.10.10.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 09 Jan 2024 10:10:37 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Leif Lindholm , Radoslaw Biernacki , Kevin Wolf , Markus Armbruster , "Edgar E. Iglesias" , Igor Mitsyanko , Rob Herring , Alistair Francis , Peter Maydell , Marcin Juszkiewicz , =?utf-8?q?Philippe_Math?= =?utf-8?q?ieu-Daud=C3=A9?= Subject: [PATCH v2 10/14] hw/arm: Prefer arm_feature(EL2) over object_property_find(has_el2) Date: Tue, 9 Jan 2024 19:09:25 +0100 Message-ID: <20240109180930.90793-11-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240109180930.90793-1-philmd@linaro.org> References: <20240109180930.90793-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The "has_el2" property is added to ARMCPU when the ARM_FEATURE_EL2 feature is available. Rather than checking whether the QOM property is present, directly check the feature. Suggested-by: Markus Armbruster Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/vexpress.c | 3 ++- hw/arm/virt.c | 2 +- hw/cpu/a15mpcore.c | 6 ++++-- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index fd981f4c33..753a645c05 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -218,12 +218,13 @@ static void init_cpus(MachineState *ms, const char *cpu_type, /* Create the actual CPUs */ for (n = 0; n < smp_cpus; n++) { Object *cpuobj = object_new(cpu_type); + ARMCPU *cpu = ARM_CPU(cpuobj); if (!secure) { object_property_set_bool(cpuobj, "has_el3", false, NULL); } if (!virt) { - if (object_property_find(cpuobj, "has_el2")) { + if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { object_property_set_bool(cpuobj, "has_el2", false, NULL); } } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 2793121cb4..35eb01a3dc 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2146,7 +2146,7 @@ static void machvirt_init(MachineState *machine) object_property_set_bool(cpuobj, "has_el3", false, NULL); } - if (!vms->virt && object_property_find(cpuobj, "has_el2")) { + if (!vms->virt && arm_feature(cpu_env(cs), ARM_FEATURE_EL2)) { object_property_set_bool(cpuobj, "has_el2", false, NULL); } diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index cebfe142cf..1fa079b3b8 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -73,9 +73,11 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp) qdev_prop_set_bit(gicdev, "has-security-extensions", true); } /* Similarly for virtualization support */ - has_el2 = object_property_find(cpuobj, "has_el2") && + has_el2 = arm_feature(cpu_env(cpu), ARM_FEATURE_EL2); + if (has_el2) { object_property_get_bool(cpuobj, "has_el2", &error_abort); - qdev_prop_set_bit(gicdev, "has-virtualization-extensions", has_el2); + qdev_prop_set_bit(gicdev, "has-virtualization-extensions", true); + } } if (!sysbus_realize(SYS_BUS_DEVICE(&s->gic), errp)) { From patchwork Tue Jan 9 18:09:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 761066 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp1496205wrz; Tue, 9 Jan 2024 10:13:02 -0800 (PST) X-Google-Smtp-Source: AGHT+IGlMXjAevfd+Abf0+qg9ybp/fEjhmXJYEAVpyhHKu5AfwuGiWASlgjjGSfEN5mwH3HOKNAf X-Received: by 2002:a05:6214:1bc7:b0:67f:31aa:284b with SMTP id m7-20020a0562141bc700b0067f31aa284bmr8302043qvc.1.1704823981602; Tue, 09 Jan 2024 10:13:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704823981; cv=none; d=google.com; s=arc-20160816; b=xMN1RutjfX+L2vOIzt4lYtdbV0rml7qmgUdDU0PkmAuYVybbNydAi7QOVwZJMTI/TQ Kn5vTtvsYJI9EmFOPS0EAdUHiFjomxj+DG5V2SREnaBhrh1r++gVbALgzE/abzwWerQM muqgGk3b9ZuE2h0lq502yvJmrO6V0m1HWcPGGrSf0GFtLeS0AklJYRDXLNdhMB2MhmCC 7oXQvo73R8Mq0TqZudvs05gT+a0f03qy3PER5ZmLnzoDy3eBqPzXeXpLOe1AxM+NLKYW EQ3hiPWQppEYYUC699oqRSrGEK9NRjBgJmDJAl3Iejx9x/lhjyRHYgA5/rtTwIh/Td6B 6VIA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=rKXURkFhsCy0V0ubg/nJYR4pTGn8xQxbtylatTgX1X4=; fh=v69mdd+nxs/0WeTIWzLZOPCx0ynE2o0vtvId2fSwkBY=; b=NZcTQ951ikJ9dgghQtHQ5jZjMJ0yimsJU7CelOuH2TIAMuwUiRsefNQamHW/7IrBEr 7V0GD9JwTFH8XXFAwLWon1oNjSqnoYqwI6rAYCFc2VdPaoHacqN7rqUm4hFu1+SQH2gz w2DssuL89qHShcPOtF0FHBYTr5kycroLngAvcoWbjHizgzBKgqNCTd4GB2sHxapcUcqu wCD7j/+KEJJMmzVKHYpwCjZEB0E94QgfDreggenHylF4dIYt835h7RmKl8463VkxLe7n ayXwRERx2b4ZR7pRc9ky57ryiCymEGGdff+3teOItZVVUxGkROp7X1m/oRELj9zLbE/f L30Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="jyKL/Emk"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.32.47]) by smtp.gmail.com with ESMTPSA id p11-20020a5d59ab000000b00336ebf93416sm3047825wrr.17.2024.01.09.10.10.42 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 09 Jan 2024 10:10:44 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Leif Lindholm , Radoslaw Biernacki , Kevin Wolf , Markus Armbruster , "Edgar E. Iglesias" , Igor Mitsyanko , Rob Herring , Alistair Francis , Peter Maydell , Marcin Juszkiewicz , =?utf-8?q?Philippe_Math?= =?utf-8?q?ieu-Daud=C3=A9?= Subject: [PATCH v2 11/14] hw/arm: Prefer arm_feature(CBAR*) over object_property_find(reset-cbar) Date: Tue, 9 Jan 2024 19:09:26 +0100 Message-ID: <20240109180930.90793-12-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240109180930.90793-1-philmd@linaro.org> References: <20240109180930.90793-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The "reset-cbar" property is added to ARMCPU when the ARM_FEATURE_CBAR[_RO] features are available. Rather than checking whether the QOM property is present, directly check the features. Suggested-by: Markus Armbruster Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/highbank.c | 3 ++- hw/arm/sbsa-ref.c | 3 ++- hw/arm/vexpress.c | 3 ++- hw/arm/virt.c | 3 ++- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index c21e18d08f..b06a727c06 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -211,7 +211,8 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id) object_property_set_int(cpuobj, "psci-conduit", QEMU_PSCI_CONDUIT_SMC, &error_abort); - if (object_property_find(cpuobj, "reset-cbar")) { + if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || + arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { object_property_set_int(cpuobj, "reset-cbar", MPCORE_PERIPHBASE, &error_abort); } diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 477dca0637..c073c462c7 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -770,7 +770,8 @@ static void sbsa_ref_init(MachineState *machine) numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj), &error_fatal); - if (object_property_find(cpuobj, "reset-cbar")) { + if (arm_feature(cpu_env(cs), ARM_FEATURE_CBAR) || + arm_feature(cpu_env(cs), ARM_FEATURE_CBAR_RO)) { object_property_set_int(cpuobj, "reset-cbar", sbsa_ref_memmap[SBSA_CPUPERIPHS].base, &error_abort); diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 753a645c05..ea3c76f3e1 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -229,7 +229,8 @@ static void init_cpus(MachineState *ms, const char *cpu_type, } } - if (object_property_find(cpuobj, "reset-cbar")) { + if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || + arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { object_property_set_int(cpuobj, "reset-cbar", periphbase, &error_abort); } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 35eb01a3dc..7e7350fec2 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2168,7 +2168,8 @@ static void machvirt_init(MachineState *machine) object_property_set_bool(cpuobj, "lpa2", false, NULL); } - if (object_property_find(cpuobj, "reset-cbar")) { + if (arm_feature(cpu_env(cs), ARM_FEATURE_CBAR) || + arm_feature(cpu_env(cs), ARM_FEATURE_CBAR_RO)) { object_property_set_int(cpuobj, "reset-cbar", vms->memmap[VIRT_CPUPERIPHS].base, &error_abort); From patchwork Tue Jan 9 18:09:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 761060 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp1495444wrz; Tue, 9 Jan 2024 10:11:29 -0800 (PST) X-Google-Smtp-Source: AGHT+IFw2YZzKR4iZraanNcj4lHOqFcDvPj6Ytku6tZUtpDYKp0dSa7Uh368wslzjZiaKj5mIkCJ X-Received: by 2002:ae9:e90f:0:b0:783:2be5:eb92 with SMTP id x15-20020ae9e90f000000b007832be5eb92mr1477980qkf.53.1704823888880; Tue, 09 Jan 2024 10:11:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704823888; cv=none; d=google.com; s=arc-20160816; b=sflcET1Ei+mnpAweD/1DPOfovu4QKvzUxHymbSBZOJH/mZQnzBnbayvGm8/STDIK+Q Af6tEVrDjR8iFoWoUYL/Nz0molBnojJSf/9px0Vfegy/byjLoeNnlWFtaNqjk5q5af2Y TPcqjwyUnmZNoVQ0Nyz5jigB1tjuZ0/a662Ji6dXqQbGuXOJsoGP1e8quzoLNWThNmkb htenWrXLJE/wD/TyEK2DeoFoxOTivLxg/GGV/2J+52hs5i/V6Prvm6KwU3eadNmJyQLU xVy4mcg2TZvf/50rgQU6pvWaMgsCK3Qi8OD9/49wAC7NEdHhEdBd6XeJY0WKIhQbCudt cdcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=6/Hk2SmJl7pABngKVtRs+8Jo9OKAAK/e6Yxa8zZeHcw=; fh=v69mdd+nxs/0WeTIWzLZOPCx0ynE2o0vtvId2fSwkBY=; b=OfcIhCMi+QmSFhA8FQnSBG3yqjl0w6IjiyUO2b/1fTFI23dELWXgjZU9HgPIF9XnEs 5COtfBG/vQYF3DI+Od0FF9VkM3EU19dO2rWZ0F6d5xndWOYSIaO/ftwxVyUkUT002aNg ONOo4KvbV1DgjJ8uLB5H77/9f59hQPE7ytGpzR7SCQl7vRTDiYx+2HvEFHqZyM77bB77 Ow7etzpgNGyILapD4EHEQl/F5CI8kwtw1SG2w0B0eGYlGdMUaj/ivG7RWNQTjrevfToH I7ACWHP1ezcUaWp3WN5k1nJ8OZnnenfREeoqVzNknsgDSjK8LHttpp7ZA/l/KhTTz0f0 TFyQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=i2fOY1kt; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.32.47]) by smtp.gmail.com with ESMTPSA id l8-20020adfe9c8000000b003365951cef9sm2990208wrn.55.2024.01.09.10.10.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 09 Jan 2024 10:10:50 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Leif Lindholm , Radoslaw Biernacki , Kevin Wolf , Markus Armbruster , "Edgar E. Iglesias" , Igor Mitsyanko , Rob Herring , Alistair Francis , Peter Maydell , Marcin Juszkiewicz , =?utf-8?q?Philippe_Math?= =?utf-8?q?ieu-Daud=C3=A9?= Subject: [PATCH v2 12/14] hw/arm: Prefer arm_feature(PMU) over object_property_find(pmu) Date: Tue, 9 Jan 2024 19:09:27 +0100 Message-ID: <20240109180930.90793-13-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240109180930.90793-1-philmd@linaro.org> References: <20240109180930.90793-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The "pmu" property is added to ARMCPU when the ARM_FEATURE_PMU feature is available. Rather than checking whether the QOM property is present, directly check the feature. Suggested-by: Markus Armbruster Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 7e7350fec2..6d1cb24a6e 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2160,7 +2160,7 @@ static void machvirt_init(MachineState *machine) object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL); } - if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) { + if (arm_feature(cpu_env(cs), ARM_FEATURE_PMU) && vmc->no_pmu) { object_property_set_bool(cpuobj, "pmu", false, NULL); } From patchwork Tue Jan 9 18:09:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 761068 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp1496221wrz; Tue, 9 Jan 2024 10:13:03 -0800 (PST) X-Google-Smtp-Source: AGHT+IGHHy7MJRs3FfMps5wmhl7RhhLSUkBE3DbmsQIViwdW1oK32A+KJGVK6fzAUU9OZe01KQNP X-Received: by 2002:a05:622a:1a82:b0:429:8a55:9d72 with SMTP id s2-20020a05622a1a8200b004298a559d72mr6010605qtc.81.1704823983036; Tue, 09 Jan 2024 10:13:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704823983; cv=none; d=google.com; s=arc-20160816; b=d6v4ToiLDWshSP3V2DNVnyXtl+WGTSv4vQzS9dK0UXmc/LuEJk3HpyBKrtYLsiqzEc /5m9Ak59wGVHf6mip1DsVyHBhUrn/hIbtFJZBxI96dlrdQvBga/vJaf8+N2Hkb9CBQEF h4+z6reC4z2E5Ulm3QCxOzC9UPAjUzJBo/hzVZ9+V8ITKkLsGTLrnvrqPs/LtNedfwRI EUZc7+KicxNVtQt1z7muF5UhMjPL60UkSB7SNu+wTHgPZ/mFHb7+Ml7r3nwlrpGAD9b1 Fae8JADNNRFdxB5ruGaTEDgCzVSwjgyoFemFOL0lpnLrVQ3lAo4tz/JyotdvLHGCCRqJ rC+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=TTZBSvKw8jVi+klzEjHlnxZcbayvqCJEGNzo5jVRjUI=; fh=v69mdd+nxs/0WeTIWzLZOPCx0ynE2o0vtvId2fSwkBY=; b=HQs+TI3GHaqLTHxUAt2mJJj9MII85cLucnq5byhaqDFnY6ryUxwulc9mi6Pl2e29ym SzliS77rCgJEXnXmchVhCWtfK8mg5kEC81qW9dShfUv09yBfvL8Fqg5lpYGw8BPdpTGI Bni8zR4NOmzpK6PzjaoAJy6QWNaeareuCeICt1WasO+GbqoLTb/Q+8jc3G/2SNmwhGPx aIkbek+b7aF+BYPHtuC6RdS8O+u1sXc2jKOK0O2yIxCp6V5tC7aJRpsLVvWtRXLLlGBD p+T2aOOyH9QfylzvfL9dbjOzqgmx/yIEhgqFabqGT5PJyd81x/THSbSQJumrQ4Sv8h7d MzRA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CDLUhKRA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.32.47]) by smtp.gmail.com with ESMTPSA id p4-20020a5d6384000000b0033760ad2eabsm2966695wru.69.2024.01.09.10.10.55 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 09 Jan 2024 10:10:56 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Leif Lindholm , Radoslaw Biernacki , Kevin Wolf , Markus Armbruster , "Edgar E. Iglesias" , Igor Mitsyanko , Rob Herring , Alistair Francis , Peter Maydell , Marcin Juszkiewicz , =?utf-8?q?Philippe_Math?= =?utf-8?q?ieu-Daud=C3=A9?= Subject: [PATCH v2 13/14] hw/arm: Prefer cpu_isar_feature(aa64_mte) over property_find(tag-memory) Date: Tue, 9 Jan 2024 19:09:28 +0100 Message-ID: <20240109180930.90793-14-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240109180930.90793-1-philmd@linaro.org> References: <20240109180930.90793-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The "tag-memory" property is added to ARMCPU when the A64_MTE bit is set in the feature ID register. Rather than checking whether the QOM property is present, directly check the feature bit. Suggested-by: Markus Armbruster Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/virt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 6d1cb24a6e..2ce4a18d73 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2189,7 +2189,7 @@ static void machvirt_init(MachineState *machine) * The property exists only if MemTag is supported. * If it is, we must allocate the ram to back that up. */ - if (!object_property_find(cpuobj, "tag-memory")) { + if (!cpu_isar_feature(aa64_mte, ARM_CPU(cs))) { error_report("MTE requested, but not supported " "by the guest CPU"); exit(1); From patchwork Tue Jan 9 18:09:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 761065 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e02:0:b0:337:62d3:c6d5 with SMTP id h2csp1495958wrz; Tue, 9 Jan 2024 10:12:27 -0800 (PST) X-Google-Smtp-Source: AGHT+IHTBXkoW0UvvRDDk3+AkD9C+xngviv0YPYeXnL+glAaB2XGA+JePKQ0oTOoTP8fb6KOU3j4 X-Received: by 2002:a05:620a:1792:b0:783:3159:c7a4 with SMTP id ay18-20020a05620a179200b007833159c7a4mr898089qkb.59.1704823947170; Tue, 09 Jan 2024 10:12:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1704823947; cv=none; d=google.com; s=arc-20160816; b=Ch3lsvUciXIwcM1tMQPdapEbDeN4rdcRIC0aXBNDBwLQZ4kFKuWBB3QYe+6tAuDhkr /313Ki6/urBBcyaScJ3J/ELh2QgrG9UAcKaAT8yi56D2EfqqVzxaAy6PzGFaiqWsjTsj PMc0TuVWKPQhHeJyyU6QGlByKJiIzvM29AvhOylsWtWOqCw+GppTxK/lYBl6ZcsgykM3 1scqWcmL8Krby7F2LJkMRN5AW9HUmWAiuXiuddtAyrbWujjE1F8ZTHF1lKIowwabC3Fw FJ8RUzprRu5/ow/U98oQBPib9JoXuwJSgXj0yICIcRcbc+fTogC8R92VspsJUeU5UPuQ mluQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ZHN1WAhVwI6VDlIQMYmKaw16w5C6ru8lwNtKGuzaAIs=; fh=v69mdd+nxs/0WeTIWzLZOPCx0ynE2o0vtvId2fSwkBY=; b=GasZQOIRsITOZL4dBmatPYPvoTZjEbHx8fxI6EiuC8TYDksH/80V0utIyNi531YUYg Wv1eaEfpJUKKUtyNRhQlOSfxMIhcGOkJJzju+I9Q8uJSW/eo38iuKKmyyTTmMP/xrkym hmzsqs2ydy67QZtoVilHWn7BJZAYr7ywGsGIyVEkwoSc77r/SHxzgtBYtdVr0p5Pr6/v 7VGEJec5rUMcjNxc4XH9nXjItkVT9mVOGZiTIOrsh6U57C+IbawZNb4AfKWGDb2NXTAQ jKjcNVLBGLQ/akTF4u0C+wRCbUJ2GiiZyas2Q+4Yz4aj5/oX+LIJHT1QSFfr9hoA2/kM mVvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QyDFv6mb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.32.47]) by smtp.gmail.com with ESMTPSA id i6-20020adfe486000000b003368d2e729bsm2988794wrm.43.2024.01.09.10.11.01 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 09 Jan 2024 10:11:02 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Leif Lindholm , Radoslaw Biernacki , Kevin Wolf , Markus Armbruster , "Edgar E. Iglesias" , Igor Mitsyanko , Rob Herring , Alistair Francis , Peter Maydell , Marcin Juszkiewicz , =?utf-8?q?Philippe_Math?= =?utf-8?q?ieu-Daud=C3=A9?= Subject: [PATCH v2 14/14] hw/arm: Prefer arm_feature(GENERIC_TMR) over 'kvm-no-adjvtime' property Date: Tue, 9 Jan 2024 19:09:29 +0100 Message-ID: <20240109180930.90793-15-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240109180930.90793-1-philmd@linaro.org> References: <20240109180930.90793-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org First, the "kvm-no-adjvtime" and "kvm-steal-time" are only available when KVM is available, so guard this block within a 'kvm_enabled()' check. Since the "kvm-steal-time" property is always available under KVM, directly set it. Then, the "kvm-no-adjvtime" property is added to ARMCPU when the ARM_FEATURE_GENERIC_TIMER feature is available. Rather than checking whether the QOM property is present, directly check the feature. Finally, since we are sure the properties are available, we can use &error_abort instead of NULL error. Replace: object_property_set_bool(..., PROPERTY, ..., &error_abort); by: qdev_prop_set_bit(..., PROPERTY, ...); which is a one-to-one replacement. Suggested-by: Markus Armbruster Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/virt.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 2ce4a18d73..6ac8fb19d2 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2150,14 +2150,13 @@ static void machvirt_init(MachineState *machine) object_property_set_bool(cpuobj, "has_el2", false, NULL); } - if (vmc->kvm_no_adjvtime && - object_property_find(cpuobj, "kvm-no-adjvtime")) { - object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL); - } - - if (vmc->no_kvm_steal_time && - object_property_find(cpuobj, "kvm-steal-time")) { - object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL); + if (kvm_enabled()) { + if (arm_feature(cpu_env(cs), ARM_FEATURE_GENERIC_TIMER)) { + qdev_prop_set_bit(DEVICE(cs), "kvm-no-adjvtime", + vmc->kvm_no_adjvtime); + } + qdev_prop_set_bit(DEVICE(cs), "kvm-steal-time", + !vmc->no_kvm_steal_time); } if (arm_feature(cpu_env(cs), ARM_FEATURE_PMU) && vmc->no_pmu) {