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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB75.mail.protection.outlook.com (10.167.242.168) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7181.13 via Frontend Transport; Mon, 8 Jan 2024 15:39:34 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Mon, 8 Jan 2024 09:39:32 -0600 From: Michal Simek To: , , , CC: Conor Dooley , Krzysztof Kozlowski , Rob Herring , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM/ZYNQ ARCHITECTURE" Subject: [PATCH 01/14] arm64: xilinx: Move address/size-cells to proper locations Date: Mon, 8 Jan 2024 16:39:12 +0100 Message-ID: <18339ffa3d8c3bf284d9c53ce950beea76516408.1704728353.git.michal.simek@amd.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; 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Changes are related to qspi, spi, nand, i2c and ethernet address cells make -j8 W=1 dtbs Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts | 6 ++++++ arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts | 2 ++ arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts | 2 ++ .../boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 4 ++++ .../boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 8 ++++++++ .../boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts | 2 ++ .../boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts | 2 ++ arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 2 ++ arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 6 ++++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 4 ++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 6 ++++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 6 ++++++ arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts | 2 ++ arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 14 -------------- 15 files changed, 56 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts index 51622896b1b1..5442edede687 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts @@ -129,6 +129,8 @@ mux { }; &qspi { /* MIO 0-5 - U143 */ + #address-cells = <1>; + #size-cells = <0>; status = "okay"; spi_flash: flash@0 { /* MT25QU512A */ compatible = "jedec,spi-nor"; /* 64MB */ @@ -240,6 +242,8 @@ &sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A */ }; &spi1 { /* MIO6, 9-11 */ + #address-cells = <1>; + #size-cells = <0>; status = "okay"; label = "TPM"; num-cs = <1>; @@ -251,6 +255,8 @@ tpm@0 { /* slm9670 - U144 */ }; &i2c1 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; bootph-all; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts index 04079d1704f1..cbaf6303a17c 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dts @@ -38,6 +38,8 @@ &dcc { }; &qspi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts index 3dec57cf18be..18187b6df3d8 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dts @@ -39,6 +39,8 @@ &dcc { }; &qspi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts index 73491626e01e..986efae8847a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -118,6 +118,8 @@ &gpu { }; &i2c1 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio"; @@ -353,6 +355,8 @@ &psgtr { }; &qspi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts index f767708fb50d..7599a12b64a5 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts @@ -109,6 +109,8 @@ &gpio { }; &i2c0 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio"; @@ -132,6 +134,8 @@ rtc@68 { }; &nand0 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nand0_default>; @@ -444,6 +448,8 @@ &rtc { }; &spi0 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; num-cs = <1>; pinctrl-names = "default"; @@ -464,6 +470,8 @@ partition@0 { }; &spi1 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; num-cs = <1>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts index f553b317e6b2..17e8a7c3701a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts @@ -103,6 +103,8 @@ &gpio { /* just eeprom here */ &i2c0 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts index 6ec1d9813973..5ad533cf86ea 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts @@ -171,6 +171,8 @@ &i2c1 { }; &qspi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index 52f998c22538..b4456e5b5058 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -176,6 +176,8 @@ &gpu { }; &i2c1 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1_default>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 84952c14f021..55a8d3e9d44f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -228,6 +228,8 @@ &gpu { }; &i2c0 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio"; @@ -492,6 +494,8 @@ max20751@73 { /* u96 */ }; &i2c1 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio"; @@ -951,6 +955,8 @@ &psgtr { }; &qspi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index 5084ddcee00f..59a919368094 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -135,6 +135,8 @@ &gpu { }; &i2c1 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio"; @@ -438,6 +440,8 @@ &psgtr { }; &qspi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts index b273bd1d920a..4fe60f22c852 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -140,6 +140,8 @@ &gpu { }; &i2c1 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio"; @@ -450,6 +452,8 @@ &psgtr { }; &qspi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 50c384aa253e..afc5571bf72b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -240,6 +240,8 @@ &gpu { }; &i2c0 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio"; @@ -503,6 +505,8 @@ max20751@73 { /* u96 */ }; &i2c1 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio"; @@ -958,6 +962,8 @@ &psgtr { }; &qspi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index 617cb0405a7d..e3e0377d543e 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -200,6 +200,8 @@ &gpu { }; &i2c0 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio"; @@ -380,6 +382,8 @@ i2c@3 { }; &i2c1 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; clock-frequency = <400000>; pinctrl-names = "default", "gpio"; @@ -788,6 +792,8 @@ &psgtr { }; &qspi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */ diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts index c406017b0348..7386ffb7daeb 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu1275-revA.dts @@ -43,6 +43,8 @@ &gpio { }; &qspi { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index ea1a9ba16246..a9a23cf50196 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -571,8 +571,6 @@ nand0: nand-controller@ff100000 { clock-names = "controller", "bus"; interrupt-parent = <&gic>; interrupts = ; - #address-cells = <1>; - #size-cells = <0>; iommus = <&smmu 0x872>; power-domains = <&zynqmp_firmware PD_NAND>; }; @@ -653,8 +651,6 @@ i2c0: i2c@ff020000 { interrupts = ; clock-frequency = <400000>; reg = <0x0 0xff020000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; power-domains = <&zynqmp_firmware PD_I2C_0>; }; @@ -665,8 +661,6 @@ i2c1: i2c@ff030000 { interrupts = ; clock-frequency = <400000>; reg = <0x0 0xff030000 0x0 0x1000>; - #address-cells = <1>; - #size-cells = <0>; power-domains = <&zynqmp_firmware PD_I2C_1>; }; @@ -718,8 +712,6 @@ qspi: spi@ff0f0000 { num-cs = <1>; reg = <0x0 0xff0f0000 0x0 0x1000>, <0x0 0xc0000000 0x0 0x8000000>; - #address-cells = <1>; - #size-cells = <0>; iommus = <&smmu 0x873>; power-domains = <&zynqmp_firmware PD_QSPI>; }; @@ -819,8 +811,6 @@ spi0: spi@ff040000 { interrupts = ; reg = <0x0 0xff040000 0x0 0x1000>; clock-names = "ref_clk", "pclk"; - #address-cells = <1>; - #size-cells = <0>; power-domains = <&zynqmp_firmware PD_SPI_0>; }; @@ -831,8 +821,6 @@ spi1: spi@ff050000 { interrupts = ; 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Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB74.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6807 From: Ilias Apalodimas Since the zynqmp boards can run upstream OP-TEE, and having the DT node present doesn't cause any side effects add it in case someone tries to load OP-TEE. Signed-off-by: Ilias Apalodimas Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index a9a23cf50196..f72fb4ea3e11 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -180,6 +180,11 @@ psci { }; firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; #power-domain-cells = <1>; From patchwork Mon Jan 8 15:39:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 760860 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2065.outbound.protection.outlook.com [40.107.244.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2602451C2E; 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Mon, 8 Jan 2024 09:40:12 -0600 From: Michal Simek To: , , , CC: Conor Dooley , Krzysztof Kozlowski , Rob Herring , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM/ZYNQ ARCHITECTURE" Subject: [PATCH 05/14] arm64: zynqmp: Setup default si570 frequency to 156.25MHz Date: Mon, 8 Jan 2024 16:39:16 +0100 Message-ID: <65a53776cbc5e4586f58da57a4b99e4d5c6c26a7.1704728353.git.michal.simek@amd.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1784; i=michal.simek@amd.com; h=from:subject:message-id; bh=lmMa2YMYHaVedg3PyHU2y16J4g30BLTDhNIOobPXwf0=; b=owGbwMvMwCR4yjP1tKYXjyLjabUkhtQ54urZH5dfM3v48UCO/8WMN0VdTXv4MudsL7EU5qz+s I9T7C9PRywLgyATg6yYIou0zZUzeytnTBG+eFgOZg4rE8gQBi5OAZhI2h+GBdMfnGQJTM/e+vRf 4cUCybiUfwqzzBnmqQad/39liymTtPaVyKsXn3BdqZZuBwA= X-Developer-Key: i=michal.simek@amd.com; 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Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB78.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7951 All si570 mgt chips have factory default 156.25MHz but DT changed it to 148.5MHz. After tracking it is pretty much c&p fault taken from Zynq zc702/zc706 boards where 148.5MHz was setup as default because it was requirement for AD7511 chip available on these boards. ZynqMP board don't contain this chip that's why factory default frequency can be used. Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 55a8d3e9d44f..3b929c0eedcd 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -607,7 +607,7 @@ si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; - clock-frequency = <148500000>; + clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index afc5571bf72b..03955aa708d4 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -609,7 +609,7 @@ si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ reg = <0x5d>; temperature-stability = <50>; /* copy from zc702 */ factory-fout = <156250000>; - clock-frequency = <148500000>; + clock-frequency = <156250000>; clock-output-names = "si570_mgt"; }; }; From patchwork Mon Jan 8 15:39:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 760859 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2073.outbound.protection.outlook.com [40.107.243.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2913452F6B; Mon, 8 Jan 2024 15:40:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="vX3Jwset" ARC-Seal: i=1; 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Signed-off-by: Thippeswamy Havalige Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index c41c935f92b1..f1b0d4a15e76 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -690,7 +690,7 @@ pcie: pcie@fd0e0000 { msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, - <0x80 0x00000000 0x0 0x1000000>; + <0x80 0x00000000 0x0 0x10000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */ <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ From patchwork Mon Jan 8 15:39:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 760858 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2061.outbound.protection.outlook.com [40.107.243.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DF314C624; 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It helps in making automated flow easier by fetching the 64bit address directly from DT. Value should be automatically copied to the U-Boot 'scriptaddr' variable. When it is defined, bootscr-ram-offset property should be ignored. Actually only one of them should be present in the DT." Address is generic for all zynqmp boards because all of them have DDR starting from 0. Custom boards should revisit the location and aligned it based on their needs. Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index f1b0d4a15e76..a1a9c8fd6038 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -24,6 +24,13 @@ / { #address-cells = <2>; #size-cells = <2>; + options { + u-boot { + compatible = "u-boot,config"; + bootscr-address = /bits/ 64 <0x20000000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; From patchwork Mon Jan 8 15:39:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 760857 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2049.outbound.protection.outlook.com [40.107.223.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C485252F7C; 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Mon, 8 Jan 2024 09:41:17 -0600 From: Michal Simek To: , , , CC: Tejas Bhumkar , Conor Dooley , Krzysztof Kozlowski , Rob Herring , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM/ZYNQ ARCHITECTURE" Subject: [PATCH 11/14] arm64: zynqmp: Disable Tri-state for MIO38 Pin Date: Mon, 8 Jan 2024 16:39:22 +0100 Message-ID: <9f8a0687be407a8ffad610087074e94ebc4f5982.1704728353.git.michal.simek@amd.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2951; i=michal.simek@amd.com; h=from:subject:message-id; bh=NAm3bgwC4tjFVVxRsOzvkT6TFE+17ZLOoBpu26K7LlA=; b=owGbwMvMwCR4yjP1tKYXjyLjabUkhtQ54po3RX4WfJKYceim7neB/MyZG6+f6zrm/oh/wg8nJ Y70Fz0fOmJZGASZGGTFFFmkba6c2Vs5Y4rwxcNyMHNYmUCGMHBxCsBEXtQyLJgzV2fZYesnwSd3 aZ7U3mF8rS3jySuGOZxmU3dPvGRW9yzDznmGiE56TeW6pQA= X-Developer-Key: i=michal.simek@amd.com; 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Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB73.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5809 From: Tejas Bhumkar gpio38 is used in SOM's kv260 to reset the Ethernet PHY. At present, HW reset is not working properly as Tri-state  is enabled for MIO38, causing inappropriate PHY register reads. Disabled Tri-state for MIO38 to make HW reset work. Tri-state disable : ZynqMP> md 0xFF180208 2 ff180208: 00bfe7a3 00000540 Tri-state enable : ZynqMP> md 0xFF180208 2 ff180208: 00bfe7e3 00000540 Signed-off-by: Tejas Bhumkar Signed-off-by: Michal Simek --- .../boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 25 +++++++++++++++++++ .../boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 25 +++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index b7b94254cc09..585b5845a1f4 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -169,6 +169,25 @@ phy0: ethernet-phy@1 { &pinctrl0 { status = "okay"; + pinctrl_gpio0_default: gpio0-default { + conf { + groups = "gpio0_38_grp"; + bias-pull-up; + power-source = ; + }; + + mux { + groups = "gpio0_38_grp"; + function = "gpio0"; + }; + + conf-tx { + pins = "MIO38"; + bias-disable; + output-enable; + }; + }; + pinctrl_uart1_default: uart1-default { conf { groups = "uart1_9_grp"; @@ -324,6 +343,12 @@ mux { }; }; +&gpio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; +}; + &uart1 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index 1446c2b19de7..037f0941ba0b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -152,6 +152,25 @@ phy0: ethernet-phy@1 { &pinctrl0 { status = "okay"; + pinctrl_gpio0_default: gpio0-default { + conf { + groups = "gpio0_38_grp"; + bias-pull-up; + power-source = ; + }; + + mux { + groups = "gpio0_38_grp"; + function = "gpio0"; + }; + + conf-tx { + pins = "MIO38"; + bias-disable; + output-enable; + }; + }; + pinctrl_uart1_default: uart1-default { conf { groups = "uart1_9_grp"; @@ -307,6 +326,12 @@ mux { }; }; +&gpio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; +}; 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That's why rename the gpio suffix to gpio-grp to avoid name collision. Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts | 4 ++-- arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts | 4 ++-- arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts | 2 +- arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts | 4 ++-- arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts | 4 ++-- 11 files changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index 585b5845a1f4..d7535a77b45e 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -227,7 +227,7 @@ mux { }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { conf { groups = "gpio0_24_grp", "gpio0_25_grp"; slew-rate = ; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index 037f0941ba0b..9e5853206eeb 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -210,7 +210,7 @@ mux { }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { conf { groups = "gpio0_24_grp", "gpio0_25_grp"; slew-rate = ; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts index 986efae8847a..2a671816015d 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts @@ -150,7 +150,7 @@ conf { }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_36_grp", "gpio0_37_grp"; function = "gpio0"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts index 7599a12b64a5..54a32a705390 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts @@ -223,7 +223,7 @@ conf { }; }; - pinctrl_i2c0_gpio: i2c0-gpio { + pinctrl_i2c0_gpio: i2c0-gpio-grp { mux { groups = "gpio0_6_grp", "gpio0_7_grp"; function = "gpio0"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts index b1857e17ab7e..53aa3dca1dca 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts @@ -125,7 +125,7 @@ conf { }; }; - pinctrl_i2c0_gpio: i2c0-gpio { + pinctrl_i2c0_gpio: i2c0-gpio-grp { mux { groups = "gpio0_74_grp", "gpio0_75_grp"; function = "gpio0"; @@ -152,7 +152,7 @@ conf { }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_76_grp", "gpio0_77_grp"; function = "gpio0"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts index b4456e5b5058..528b5beb4dee 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts @@ -277,7 +277,7 @@ conf { }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_4_grp", "gpio0_5_grp"; function = "gpio0"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts index 3b929c0eedcd..2ec0e2d1c869 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts @@ -693,7 +693,7 @@ conf { }; }; - pinctrl_i2c0_gpio: i2c0-gpio { + pinctrl_i2c0_gpio: i2c0-gpio-grp { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; @@ -720,7 +720,7 @@ conf { }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts index 59a919368094..a3d9f1b2713c 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts @@ -274,7 +274,7 @@ conf { }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts index 4fe60f22c852..ba8708b88e67 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts @@ -286,7 +286,7 @@ conf { }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts index 03955aa708d4..700f5b5f171e 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts @@ -704,7 +704,7 @@ conf { }; }; - pinctrl_i2c0_gpio: i2c0-gpio { + pinctrl_i2c0_gpio: i2c0-gpio-grp { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; @@ -731,7 +731,7 @@ conf { }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts index e3e0377d543e..920eb16cebf2 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dts @@ -593,7 +593,7 @@ conf { }; }; - pinctrl_i2c0_gpio: i2c0-gpio { + pinctrl_i2c0_gpio: i2c0-gpio-grp { mux { groups = "gpio0_14_grp", "gpio0_15_grp"; function = "gpio0"; @@ -620,7 +620,7 @@ conf { }; }; - pinctrl_i2c1_gpio: i2c1-gpio { + pinctrl_i2c1_gpio: i2c1-gpio-grp { mux { groups = "gpio0_16_grp", "gpio0_17_grp"; function = "gpio0"; From patchwork Mon Jan 8 15:39:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 760855 Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2084.outbound.protection.outlook.com [40.107.102.84]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD16E54FA2; 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With also describing kv260 assigned clock rates with assigned clocks. Also add missing status property to standard dwc3 core. Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 14 ++++++++++++-- .../boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 1 + arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 ++++++-- 3 files changed, 19 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index ca1248784f59..dd4569e7bd95 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -238,12 +238,22 @@ &uart1 { assigned-clocks = <&zynqmp_clk UART1_REF>; }; -&dwc3_0 { +&usb0 { clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; + assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; }; -&dwc3_1 { +&dwc3_0 { + clocks = <&zynqmp_clk USB3_DUAL_REF>; +}; + +&usb1 { clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; + assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; +}; + +&dwc3_1 { + clocks = <&zynqmp_clk USB3_DUAL_REF>; }; &watchdog0 { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index 9e5853206eeb..a7b8fffad499 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -94,6 +94,7 @@ &usb0 { pinctrl-0 = <&pinctrl_usb0_default>; phy-names = "usb3-phy"; phys = <&psgtr 2 PHY_TYPE_USB3 0 1>; + assigned-clock-rates = <250000000>, <20000000>; }; &dwc3_0 { diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 631484e17ab0..133b464baa9a 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -913,6 +913,7 @@ usb0: usb@ff9d0000 { status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; + clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_0>; resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, @@ -923,13 +924,14 @@ usb0: usb@ff9d0000 { dwc3_0: usb@fe200000 { compatible = "snps,dwc3"; + status = "disabled"; reg = <0x0 0xfe200000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "host", "peripheral", "otg"; interrupts = , , ; - clock-names = "bus_early", "ref"; + clock-names = "ref"; /* iommus = <&smmu 0x860>; */ snps,quirk-frame-length-adjustment = <0x20>; snps,resume-hs-terminations; @@ -943,6 +945,7 @@ usb1: usb@ff9e0000 { status = "disabled"; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; + clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_1>; resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, @@ -952,13 +955,14 @@ usb1: usb@ff9e0000 { dwc3_1: usb@fe300000 { compatible = "snps,dwc3"; + status = "disabled"; reg = <0x0 0xfe300000 0x0 0x40000>; interrupt-parent = <&gic>; interrupt-names = "host", "peripheral", "otg"; interrupts = , , ; - clock-names = "bus_early", "ref"; + clock-names = "ref"; /* iommus = <&smmu 0x861>; */ snps,quirk-frame-length-adjustment = <0x20>; snps,resume-hs-terminations;