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Signed-off-by: Tomer Maimon --- arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi index 868454ae6bde..f72c5a03d04c 100644 --- a/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi +++ b/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi @@ -93,8 +93,8 @@ gcr: gcr@800000 { reg = <0x800000 0x1000>; }; - rst: rst@801000 { - compatible = "nuvoton,npcm750-rst", "syscon", "simple-mfd"; + clk_rst: syscon@801000 { + compatible = "nuvoton,npcm750-clk-rst", "syscon", "simple-mfd"; reg = <0x801000 0x6C>; }; }; From patchwork Mon Jan 8 13:54:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomer Maimon X-Patchwork-Id: 760871 Received: from APC01-TYZ-obe.outbound.protection.outlook.com (mail-tyzapc01rlnn2050.outbound.protection.outlook.com [40.95.110.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 394314777C; 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Helo=[NTHCCAS01.nuvoton.com] X-MS-Exchange-CrossTenant-AuthSource: HK2PEPF00006FB5.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SEYPR03MB7968 A nuvoton,*-clk-rst node is present in nuvoton-common-npcm7xx.dtsi and will be added to nuvoton-common-npcm8xx.dtsi. It is necessary for the NPCM7xx and NPCM8xx clock and reset drivers, and may later be used to retrieve SoC model and version information. This patch adds a binding to describe this node. Signed-off-by: Tomer Maimon --- .../soc/nuvoton/nuvoton,npcm-clk-rst.yaml | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/nuvoton/nuvoton,npcm-clk-rst.yaml diff --git a/Documentation/devicetree/bindings/soc/nuvoton/nuvoton,npcm-clk-rst.yaml b/Documentation/devicetree/bindings/soc/nuvoton/nuvoton,npcm-clk-rst.yaml new file mode 100644 index 000000000000..dfec64a8eb26 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/nuvoton/nuvoton,npcm-clk-rst.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/nuvoton/nuvoton,npcm-clk-rst.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Clock and reset registers block in Nuvoton SoCs + +maintainers: + - Tomer Maimon + +description: + The clock and reset registers are a registers block in Nuvoton SoCs that + handle both reset and clock functionality. + +properties: + compatible: + items: + - enum: + - nuvoton,npcm750-clk-rst + - nuvoton,npcm845-clk-rst + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: + type: object + +examples: + - | + clk_rst: syscon@801000 { + compatible = "nuvoton,npcm750-clk-rst", "syscon", "simple-mfd"; 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Signed-off-by: Tomer Maimon --- arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi index 9c4df91031e7..7d5956e2c9f3 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi @@ -22,6 +22,11 @@ gcr: system-controller@f0800000 { reg = <0x0 0xf0800000 0x0 0x1000>; }; + clk_rst: syscon@f0801000 { + compatible = "nuvoton,npcm845-clk-rst", "syscon", "simple-mfd"; + reg = <0x0 0xf0801000 0x0 0xC4>; + }; + gic: interrupt-controller@dfff9000 { compatible = "arm,gic-400"; reg = <0x0 0xdfff9000 0x0 0x1000>, From patchwork Mon Jan 8 13:54:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomer Maimon X-Patchwork-Id: 760842 Received: from APC01-TYZ-obe.outbound.protection.outlook.com (mail-tyzapc01rlnn2045.outbound.protection.outlook.com [40.95.110.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 479F855C2C; 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Signed-off-by: Tomer Maimon --- .../bindings/clock/nuvoton,npcm845-clk.yaml | 22 +++++++++---------- 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml b/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml index 0b642bfce292..c6bf05c163b4 100644 --- a/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml +++ b/Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml @@ -18,8 +18,9 @@ properties: enum: - nuvoton,npcm845-clk - reg: - maxItems: 1 + nuvoton,sysclk: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to access clock registers. clocks: items: @@ -37,7 +38,7 @@ properties: required: - compatible - - reg + - nuvoton,sysclk - clocks - clock-names - '#clock-cells' @@ -52,14 +53,11 @@ examples: clock-frequency = <25000000>; }; - ahb { - #address-cells = <2>; - #size-cells = <2>; - - clock-controller@f0801000 { - compatible = "nuvoton,npcm845-clk"; - reg = <0x0 0xf0801000 0x0 0x1000>; - #clock-cells = <1>; - }; + clk: clock-controller { + compatible = "nuvoton,npcm845-clk"; + nuvoton,sysclk = <&clk_rst>; + #clock-cells = <1>; + clocks = <&refclk>; + clock-names = "refclk"; }; ... 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Signed-off-by: Tomer Maimon --- arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi index 7d5956e2c9f3..5cc0efdbb3c7 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi @@ -59,10 +59,10 @@ rstc: reset-controller@f0801000 { nuvoton,sysgcr = <&gcr>; }; - clk: clock-controller@f0801000 { + clk: clock-controller { compatible = "nuvoton,npcm845-clk"; #clock-cells = <1>; - reg = <0x0 0xf0801000 0x0 0x1000>; + nuvoton,sysclk = <&clk_rst>; clocks = <&refclk>; clock-names = "refclk"; };