From patchwork Wed Jan 3 13:28:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Emil Renner Berthing X-Patchwork-Id: 760016 Received: from smtp-relay-internal-0.canonical.com (smtp-relay-internal-0.canonical.com [185.125.188.122]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2032199B6 for ; Wed, 3 Jan 2024 13:29:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=canonical.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=canonical.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=canonical.com header.i=@canonical.com header.b="d8rJTwWn" Received: from mail-lf1-f72.google.com (mail-lf1-f72.google.com [209.85.167.72]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-0.canonical.com (Postfix) with ESMTPS id 94D233F5AE for ; Wed, 3 Jan 2024 13:28:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1704288535; bh=lN7QxaajzrvpBlbQTOF6hDrc4xdY0uP48KXpLPsfjdI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=d8rJTwWnugK0HtX+81ezQm5wyZtG4DKe8txySdojq1A6IDR5UxvpEUtleE5vvgcDX uc6PJYa+3uFNyMvT950pW3vEmuVb7BMBZ2++2dOe0fZwNwPkTQxIe92OcFXssMtmvr o7AWL35LxGubMj8lr+VWXwlKJ6j+6zv4WlmS7ApjVH41hoAxSdxbPmWuSxgetOY0yb fv+WwhvTopuDIRaGJYCPsqtLLmkk6aggQb5YrgHJtWHuIQUNVgzrJXT+fZgRFb8nx5 vKml89wUJYrKE/iidU8eQPh4t7XiP0Dc2QjeD7Vs/D5fLnFsA0L7UpDqqqxt4auwP6 c2mBjezXTc2sw== Received: by mail-lf1-f72.google.com with SMTP id 2adb3069b0e04-50e5aa11579so8157500e87.1 for ; Wed, 03 Jan 2024 05:28:55 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704288535; x=1704893335; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lN7QxaajzrvpBlbQTOF6hDrc4xdY0uP48KXpLPsfjdI=; b=pXpyxa/BHr/gdIi8YnNoDMyDiSUDJVWV/dBitXi2deEvIqs52yf/Bm1gQRTiuHEND5 bT2B44mpbYZ+X/YIXRT70fyYBXQml91kjW7iCbdAbsMeXnBGwbOwHh8a/ZHSwJBTUYgT 0zVDTpYJg4b2NjV+DKEYJ3W0AFwE6D4WkgTSupAK/UbKuuCrcUpgJKPhCbNX65fdAt/y e+VAh6nQhhPlkFh3iOV7RjBKDmYLlbI9CvtFg8Mpq4kbmOrmvlpuef0d+Cze6yPfhsok eKWntEmr7ytW/G7J90hXD6YxpkWqAaYI7PEed7sIlywSAwKGXrsSWYdQcV6diSNrTadE 0Nbg== X-Gm-Message-State: AOJu0Yye0GyZp6ZGjwTj6kHLwlGWYvQN7dX21KoH07EgcyA1y8EUag/H Vyk9/q9dboCLMu9GCOEaBty3NJyxaVeiMZlRKhJ+ONEHNKsIUSyzVy2bNDqdffo96c0GveLVQtt 2sLdOPfwyhcQX2uyY7jKQhwC7kYrSM7oJg1k2+MsWUXsAgA== X-Received: by 2002:a05:6512:3e10:b0:50e:815f:50d1 with SMTP id i16-20020a0565123e1000b0050e815f50d1mr5797345lfv.105.1704288534874; Wed, 03 Jan 2024 05:28:54 -0800 (PST) X-Google-Smtp-Source: AGHT+IEt1Eu/ihnqJcTy9xJ3HzcwJWfnNjjiBgAIOs526DjSHN+s/rQtmU3iRfzWNow4FzuYEHUttA== X-Received: by 2002:a05:6512:3e10:b0:50e:815f:50d1 with SMTP id i16-20020a0565123e1000b0050e815f50d1mr5797342lfv.105.1704288534499; Wed, 03 Jan 2024 05:28:54 -0800 (PST) Received: from stitch.. ([2a01:4262:1ab:c:5af0:999b:bb78:7614]) by smtp.gmail.com with ESMTPSA id eu18-20020a170907299200b00a26e53be089sm9549873ejc.44.2024.01.03.05.28.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 05:28:54 -0800 (PST) From: Emil Renner Berthing To: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Guo Ren , Fu Wei , Paul Walmsley , Palmer Dabbelt , Drew Fustini Subject: [PATCH v2 1/8] dt-bindings: pinctrl: Add thead,th1520-pinctrl bindings Date: Wed, 3 Jan 2024 14:28:38 +0100 Message-ID: <20240103132852.298964-2-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103132852.298964-1-emil.renner.berthing@canonical.com> References: <20240103132852.298964-1-emil.renner.berthing@canonical.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add bindings for the pin controllers on the T-Head TH1520 RISC-V SoC. Signed-off-by: Emil Renner Berthing --- .../pinctrl/thead,th1520-pinctrl.yaml | 372 ++++++++++++++++++ 1 file changed, 372 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml new file mode 100644 index 000000000000..d3ad7a7cfdd1 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml @@ -0,0 +1,372 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/thead,th1520-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-Head TH1520 SoC pin controller + +maintainers: + - Emil Renner Berthing + +description: | + Pinmux and pinconf controller in the T-Head TH1520 RISC-V SoC. + + The TH1520 has 3 groups of pads each controlled from different memory ranges. + Confusingly the memory ranges are named + PADCTRL_AOSYS -> PAD Group 1 + PADCTRL1_APSYS -> PAD Group 2 + PADCTRL0_APSYS -> PAD Group 3 + + Each pad can be muxed individually to up to 6 different functions. For most + pads only a few of those 6 configurations are valid though, and a few pads in + group 1 does not support muxing at all. + + Pinconf is fairly regular except for a few pads in group 1 that either can't + be configured or has some special functions. The rest have configurable drive + strength, input enable, schmitt trigger, slew rate, pull-up and pull-down in + addition to a special strong pull up. + + Certain pads in group 1 can be muxed to AUDIO_PA0 - AUDIO_PA30 functions and + are then meant to be used by the audio co-processor. Each such pad can then + be further muxed to either audio GPIO or one of 4 functions such as UART, I2C + and I2S. If the audio pad is muxed to one of the 4 functions then pinconf is + also configured in different registers. All of this is done from a different + AUDIO_IOCTRL memory range and is left to the audio co-processor for now. + +properties: + compatible: + enum: + - thead,th1520-group1-pinctrl + - thead,th1520-group2-pinctrl + - thead,th1520-group3-pinctrl + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +patternProperties: + '-[0-9]+$': + type: object + + additionalProperties: false + + patternProperties: + '-pins$': + type: object + $ref: /schemas/pinctrl/pincfg-node.yaml + + additionalProperties: false + + description: + A pinctrl node should contain at least one subnode describing one + or more pads and their associated pinmux and pinconf settings. + + properties: + pins: + $ref: /schemas/pinctrl/pinmux-node.yaml#/properties/pins + description: List of pads that properties in the node apply to. + + function: + $ref: /schemas/pinctrl/pinmux-node.yaml#/properties/function + enum: [ gpio, pwm, uart, ir, i2c, spi, qspi, sdio, audio, i2s, + gmac0, gmac1, dpu0, dpu1, isp, hdmi, bootsel, debug, + clock, jtag, iso7816, efuse, reset ] + description: The mux function to select for the given pins. + + bias-disable: true + + bias-pull-up: + oneOf: + - type: boolean + description: Enable the regular 48kOhm pull-up + - enum: [ 2100, 48000 ] + description: Enable the strong 2.1kOhm pull-up or regular 48kOhm pull-up + + bias-pull-down: + oneOf: + - type: boolean + - const: 44000 + description: Enable the regular 44kOhm pull-down + + drive-strength: + enum: [ 1, 2, 3, 5, 7, 8, 10, 12, 13, 15, 16, 18, 20, 21, 23, 25 ] + description: Drive strength in mA + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + slew-rate: + maximum: 1 + + required: + - pins + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + - if: + properties: + compatible: + const: thead,th1520-group1-pinctrl + then: + patternProperties: + '-[0-9]+$': + patternProperties: + '-pins$': + properties: + pins: + items: + enum: + - OSC_CLK_IN + - OSC_CLK_OUT + - SYS_RST_N + - RTC_CLK_IN + - RTC_CLK_OUT + - TEST_MODE + - DEBUG_MODE + - POR_SEL + - I2C_AON_SCL + - I2C_AON_SDA + - CPU_JTG_TCLK + - CPU_JTG_TMS + - CPU_JTG_TDI + - CPU_JTG_TDO + - CPU_JTG_TRST + - AOGPIO_7 + - AOGPIO_8 + - AOGPIO_9 + - AOGPIO_10 + - AOGPIO_11 + - AOGPIO_12 + - AOGPIO_13 + - AOGPIO_14 + - AOGPIO_15 + - AUDIO_PA0 + - AUDIO_PA1 + - AUDIO_PA2 + - AUDIO_PA3 + - AUDIO_PA4 + - AUDIO_PA5 + - AUDIO_PA6 + - AUDIO_PA7 + - AUDIO_PA8 + - AUDIO_PA9 + - AUDIO_PA10 + - AUDIO_PA11 + - AUDIO_PA12 + - AUDIO_PA13 + - AUDIO_PA14 + - AUDIO_PA15 + - AUDIO_PA16 + - AUDIO_PA17 + - AUDIO_PA27 + - AUDIO_PA28 + - AUDIO_PA29 + - AUDIO_PA30 + - if: + properties: + compatible: + const: thead,th1520-group2-pinctrl + then: + patternProperties: + '-[0-9]+$': + patternProperties: + '-pins$': + properties: + pins: + items: + enum: + - QSPI1_SCLK + - QSPI1_CSN0 + - QSPI1_D0_MOSI + - QSPI1_D1_MISO + - QSPI1_D2_WP + - QSPI1_D3_HOLD + - I2C0_SCL + - I2C0_SDA + - I2C1_SCL + - I2C1_SDA + - UART1_TXD + - UART1_RXD + - UART4_TXD + - UART4_RXD + - UART4_CTSN + - UART4_RTSN + - UART3_TXD + - UART3_RXD + - GPIO0_18 + - GPIO0_19 + - GPIO0_20 + - GPIO0_21 + - GPIO0_22 + - GPIO0_23 + - GPIO0_24 + - GPIO0_25 + - GPIO0_26 + - GPIO0_27 + - GPIO0_28 + - GPIO0_29 + - GPIO0_30 + - GPIO0_31 + - GPIO1_0 + - GPIO1_1 + - GPIO1_2 + - GPIO1_3 + - GPIO1_4 + - GPIO1_5 + - GPIO1_6 + - GPIO1_7 + - GPIO1_8 + - GPIO1_9 + - GPIO1_10 + - GPIO1_11 + - GPIO1_12 + - GPIO1_13 + - GPIO1_14 + - GPIO1_15 + - GPIO1_16 + - CLK_OUT_0 + - CLK_OUT_1 + - CLK_OUT_2 + - CLK_OUT_3 + - GPIO1_21 + - GPIO1_22 + - GPIO1_23 + - GPIO1_24 + - GPIO1_25 + - GPIO1_26 + - GPIO1_27 + - GPIO1_28 + - GPIO1_29 + - GPIO1_30 + - if: + properties: + compatible: + const: thead,th1520-group3-pinctrl + then: + patternProperties: + '-[0-9]+$': + patternProperties: + '-pins$': + properties: + pins: + items: + enum: + - UART0_TXD + - UART0_RXD + - QSPI0_SCLK + - QSPI0_CSN0 + - QSPI0_CSN1 + - QSPI0_D0_MOSI + - QSPI0_D1_MISO + - QSPI0_D2_WP + - QSPI1_D3_HOLD + - I2C2_SCL + - I2C2_SDA + - I2C3_SCL + - I2C3_SDA + - GPIO2_13 + - SPI_SCLK + - SPI_CSN + - SPI_MOSI + - SPI_MISO + - GPIO2_18 + - GPIO2_19 + - GPIO2_20 + - GPIO2_21 + - GPIO2_22 + - GPIO2_23 + - GPIO2_24 + - GPIO2_25 + - SDIO0_WPRTN + - SDIO0_DETN + - SDIO1_WPRTN + - SDIO1_DETN + - GPIO2_30 + - GPIO2_31 + - GPIO3_0 + - GPIO3_1 + - GPIO3_2 + - GPIO3_3 + - HDMI_SCL + - HDMI_SDA + - HDMI_CEC + - GMAC0_TX_CLK + - GMAC0_RX_CLK + - GMAC0_TXEN + - GMAC0_TXD0 + - GMAC0_TXD1 + - GMAC0_TXD2 + - GMAC0_TXD3 + - GMAC0_RXDV + - GMAC0_RXD0 + - GMAC0_RXD1 + - GMAC0_RXD2 + - GMAC0_RXD3 + - GMAC0_MDC + - GMAC0_MDIO + - GMAC0_COL + - GMAC0_CRS + +examples: + - | + padctrl0_apsys: pinctrl@ec007000 { + compatible = "thead,th1520-group3-pinctrl"; + reg = <0xec007000 0x1000>; + clocks = <&apb_clk>; + + uart0_pins: uart0-0 { + tx-pins { + pins = "UART0_TXD"; + function = "uart"; + bias-disable; + drive-strength = <3>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + + rx-pins { + pins = "UART0_RXD"; + function = "uart"; + bias-disable; + drive-strength = <1>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; + }; + + padctrl1_apsys: pinctrl@e7f3c000 { + compatible = "thead,th1520-group2-pinctrl"; + reg = <0xe7f3c000 0x1000>; + clocks = <&apb_clk>; + + i2c5_pins: i2c5-0 { + i2c-pins { + pins = "QSPI1_CSN0", /* I2C5_SCL */ + "QSPI1_D0_MOSI"; /* I2C5_SDA */ + function = "i2c"; + bias-pull-up = <2100>; + drive-strength = <7>; + input-enable; + input-schmitt-enable; + slew-rate = <0>; + }; + }; + }; From patchwork Wed Jan 3 13:28:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Emil Renner Berthing X-Patchwork-Id: 760015 Received: from smtp-relay-internal-1.canonical.com (smtp-relay-internal-1.canonical.com [185.125.188.123]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CD7D1A27E for ; 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([2a01:4262:1ab:c:5af0:999b:bb78:7614]) by smtp.gmail.com with ESMTPSA id eu18-20020a170907299200b00a26e53be089sm9549873ejc.44.2024.01.03.05.28.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 05:28:56 -0800 (PST) From: Emil Renner Berthing To: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Guo Ren , Fu Wei , Paul Walmsley , Palmer Dabbelt , Drew Fustini Subject: [PATCH v2 4/8] riscv: dts: thead: Add TH1520 GPIO ranges Date: Wed, 3 Jan 2024 14:28:41 +0100 Message-ID: <20240103132852.298964-5-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103132852.298964-1-emil.renner.berthing@canonical.com> References: <20240103132852.298964-1-emil.renner.berthing@canonical.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add gpio-ranges properties to the TH1520 device tree, so user space can change basic pinconf settings for GPIOs and are not allowed to use pads already used by other functions. Adjust number of GPIOs available for the different controllers. Signed-off-by: Emil Renner Berthing --- arch/riscv/boot/dts/thead/th1520.dtsi | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index e65a306ff575..5eb841ba5124 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -223,6 +223,7 @@ portc: gpio-controller@0 { gpio-controller; #gpio-cells = <2>; ngpios = <32>; + gpio-ranges = <&padctrl0_apsys 0 0 32>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; @@ -240,7 +241,8 @@ portd: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; - ngpios = <32>; + ngpios = <23>; + gpio-ranges = <&padctrl0_apsys 0 32 23>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; @@ -265,6 +267,7 @@ porta: gpio-controller@0 { gpio-controller; #gpio-cells = <2>; ngpios = <32>; + gpio-ranges = <&padctrl1_apsys 0 0 32>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; @@ -282,7 +285,8 @@ portb: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; - ngpios = <32>; + ngpios = <31>; + gpio-ranges = <&padctrl1_apsys 0 32 31>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; @@ -424,7 +428,8 @@ porte: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; - ngpios = <32>; + ngpios = <16>; + gpio-ranges = <&padctrl_aosys 0 9 16>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; @@ -448,7 +453,8 @@ portf: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; - ngpios = <32>; + ngpios = <23>; + gpio-ranges = <&padctrl_aosys 0 25 22>, <&padctrl_aosys 22 7 1>; reg = <0>; interrupt-controller; #interrupt-cells = <2>; From patchwork Wed Jan 3 13:28:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Emil Renner Berthing X-Patchwork-Id: 760014 Received: from smtp-relay-internal-0.canonical.com (smtp-relay-internal-0.canonical.com [185.125.188.122]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0E0471A289 for ; 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([2a01:4262:1ab:c:5af0:999b:bb78:7614]) by smtp.gmail.com with ESMTPSA id eu18-20020a170907299200b00a26e53be089sm9549873ejc.44.2024.01.03.05.28.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 05:28:58 -0800 (PST) From: Emil Renner Berthing To: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Guo Ren , Fu Wei , Paul Walmsley , Palmer Dabbelt , Drew Fustini Subject: [PATCH v2 6/8] riscv: dts: thead: Add Lichee Pi 4M GPIO line names Date: Wed, 3 Jan 2024 14:28:43 +0100 Message-ID: <20240103132852.298964-7-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103132852.298964-1-emil.renner.berthing@canonical.com> References: <20240103132852.298964-1-emil.renner.berthing@canonical.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add names for the GPIO00-GPIO14 lines of the SO-DIMM module. Signed-off-by: Emil Renner Berthing --- .../dts/thead/th1520-lichee-module-4a.dtsi | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index 9865925be372..f674e5acd0f9 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -37,6 +37,45 @@ &uart_sclk { clock-frequency = <100000000>; }; +&aogpio { + gpio-line-names = "", "", "", + "GPIO00", + "GPIO04"; +}; + &dmac0 { status = "okay"; }; + +&gpio0 { + gpio-line-names = "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", + "GPIO07", + "GPIO08", + "", + "GPIO01", + "GPIO02"; +}; + +&gpio1 { + gpio-line-names = "", "", "", + "GPIO11", + "GPIO12", + "GPIO13", + "GPIO14", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", + "GPIO06"; +}; + +&gpio2 { + gpio-line-names = "GPIO03", + "GPIO05"; +}; + +&gpio3 { + gpio-line-names = "", "", + "GPIO09", + "GPIO10"; +}; From patchwork Wed Jan 3 13:28:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Emil Renner Berthing X-Patchwork-Id: 760013 Received: from smtp-relay-internal-0.canonical.com (smtp-relay-internal-0.canonical.com [185.125.188.122]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BCA41BDD9 for ; Wed, 3 Jan 2024 13:29:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=canonical.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=canonical.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=canonical.com header.i=@canonical.com header.b="KQ50OvmX" Received: from mail-lf1-f70.google.com (mail-lf1-f70.google.com [209.85.167.70]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp-relay-internal-0.canonical.com (Postfix) with ESMTPS id 013653F5B7 for ; Wed, 3 Jan 2024 13:29:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=canonical.com; s=20210705; t=1704288552; bh=j8polI0w/bjJ8tZqB1jGYw0XXYsOmvLZx8MNesRoCUY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KQ50OvmXB7y3savHWjFD8br/ueisKFm+Vw37SScch2wY+uN/ZXwH8owvqgGzKtwql SAJvjOlnDi5eloQvlUvJ/k92XnOwXDgvmtOswmUPCTj1fCp5A1GIcU0mUlJZ4l5cTt qvLQ9tSjU6KyWtf1HmjAeaMUell7Zk0RL/Udn6WZ8xQLKB4S7wcJuKl6bKlTnnSath niQQ//lm+Z5zA9d/udJsM+sbMI3zGHICTGGJWpZwe2KX+FpNS6O+HQxpX9Fmsc+Lf6 9AISVV/UsrGcx17c6Zr8NJC+zgdKR6ZZwDsxjw27WxTmmGNdjR7LnEBFm9tInDVb3u k6CI4WpsAoReg== Received: by mail-lf1-f70.google.com with SMTP id 2adb3069b0e04-50e7b20360bso5520736e87.3 for ; Wed, 03 Jan 2024 05:29:11 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704288542; x=1704893342; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=j8polI0w/bjJ8tZqB1jGYw0XXYsOmvLZx8MNesRoCUY=; b=CR3c1vmGvQQkGzle/cb3Rfg/ow4kHU09sWKLIjjPcJhZA819b70ndICUq15PIHiwjd xOeTDstK1j1HEAhbM2q0R63zvfd98kyrOYUZJVrhnMKKgRDYA1YF+7nG/8Byc52tPMUI yhikf3Ow4+3FMNUAZJnZPrqwstnnGxk3z/WFSmI/97gXNModHse377eywzPRYf79jZph HLOidFen1mzcJOilaKDYgoxZcVpCHm7OXXRYnnQFrgReAt1lm4xnNbutikFlzRSQ/Dn4 J5Ge6aB7077Fiz5x/X+NkuzvnkumczZRfzptIRCy0WDV7nwvG7i9w4IKBoM5w2tlpRGw Xsrw== X-Gm-Message-State: AOJu0YxNYrY7hNsc6gOvglOLHf3v3i0kGQ701prhmB6e3d8E8ESq4Tge wQpSFsUfGsrqMHDt1k2FHm64CpqUWHOX3tOrhPZiR2tNOrdtYe5d/OTUVC1Ff3fNxBcViilpZ0G TVsT42iNGCO1t2nbAFp8am+n2hXl6qqGo93i6Yz92bKv2mA== X-Received: by 2002:a05:6512:1145:b0:50e:3767:d381 with SMTP id m5-20020a056512114500b0050e3767d381mr7432120lfg.139.1704288541956; Wed, 03 Jan 2024 05:29:01 -0800 (PST) X-Google-Smtp-Source: AGHT+IEJt4/P/j0GlWbqbKebsvHvV6+jrN2+ONRLeoH23443/k+kOFBIdKz9RoGU2lF8BDUFzg5rrQ== X-Received: by 2002:a05:6512:1145:b0:50e:3767:d381 with SMTP id m5-20020a056512114500b0050e3767d381mr7432116lfg.139.1704288541775; Wed, 03 Jan 2024 05:29:01 -0800 (PST) Received: from stitch.. ([2a01:4262:1ab:c:5af0:999b:bb78:7614]) by smtp.gmail.com with ESMTPSA id eu18-20020a170907299200b00a26e53be089sm9549873ejc.44.2024.01.03.05.29.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 Jan 2024 05:29:01 -0800 (PST) From: Emil Renner Berthing To: linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Guo Ren , Fu Wei , Paul Walmsley , Palmer Dabbelt , Drew Fustini Subject: [PATCH v2 8/8] riscv: dtb: thead: Add BeagleV Ahead LEDs Date: Wed, 3 Jan 2024 14:28:45 +0100 Message-ID: <20240103132852.298964-9-emil.renner.berthing@canonical.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240103132852.298964-1-emil.renner.berthing@canonical.com> References: <20240103132852.298964-1-emil.renner.berthing@canonical.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add nodes for the 5 user controllable LEDs on the BeagleV Ahead board. Signed-off-by: Emil Renner Berthing --- .../boot/dts/thead/th1520-beaglev-ahead.dts | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts index c697a50ca9b1..0b309c770202 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -7,6 +7,8 @@ /dts-v1/; #include "th1520.dtsi" +#include +#include / { model = "BeagleV Ahead"; @@ -34,7 +36,42 @@ chosen { memory@0 { device_type = "memory"; reg = <0x0 0x00000000 0x1 0x00000000>; + }; + leds { + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + compatible = "gpio-leds"; + + led-1 { + gpios = <&gpio4 8 GPIO_ACTIVE_LOW>; + color = ; + label = "led1"; + }; + + led-2 { + gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; + color = ; + label = "led2"; + }; + + led-3 { + gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; + color = ; + label = "led3"; + }; + + led-4 { + gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + color = ; + label = "led4"; + }; + + led-5 { + gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + color = ; + label = "led5"; + }; }; }; @@ -62,6 +99,24 @@ &dmac0 { status = "okay"; }; +&padctrl_aosys { + led_pins: led-0 { + led-pins { + pins = "AUDIO_PA8", /* GPIO4_8 */ + "AUDIO_PA9", /* GPIO4_9 */ + "AUDIO_PA10", /* GPIO4_10 */ + "AUDIO_PA11", /* GPIO4_11 */ + "AUDIO_PA12"; /* GPIO4_12 */ + function = "gpio"; + bias-disable; + drive-strength = <3>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; +}; + &padctrl0_apsys { uart0_pins: uart0-0 { tx-pins {