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[178.235.179.36]) by smtp.gmail.com with ESMTPSA id et10-20020a170907294a00b00a2699a54888sm11968835ejc.64.2024.01.02.10.30.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 10:30:08 -0800 (PST) From: Konrad Dybcio Date: Tue, 02 Jan 2024 19:29:47 +0100 Subject: [PATCH 1/4] interconnect: qcom: x1e80100: Remove bogus per-RSC BCMs and nodes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240102-topic-x1e_fixes-v1-1-70723e08d5f6@linaro.org> References: <20240102-topic-x1e_fixes-v1-0-70723e08d5f6@linaro.org> In-Reply-To: <20240102-topic-x1e_fixes-v1-0-70723e08d5f6@linaro.org> To: Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rajendra Nayak , Sibi Sankar , Abel Vesa Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1704220203; l=12344; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=mNa869fDrci8rw/llu3AyPu8WaoxGUB7b59qLee5D8M=; b=66uM6q+cMMnpZG6Ar45PAj4O/OnCy5/2zXaet0FGaC2kUJy44ePPf8fL5QJSub08IDqpiTPFw DYzoFe6mcDnBZS6CAvpvmfrhv2TPWZJNgniS5K3sHHUmkZYi5llcWhh X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= The downstream kernel has infrastructure for passing votes from different interconnect nodes onto different RPMh RSCs. This neither implemented, not is going to be implemented upstream (in favor of a different solution using ICC tags through the same node). Unfortunately, as it happens, meaningless (in the upstream context) parts of the vendor driver were copied, ending up causing havoc - since all "per-RSC" (in quotes because they all point to the main APPS one) BCMs defined within the driver overwrite the value in RPMh on every aggregation. To both avoid keeping bogus code around and possibly introducing impossible-to-track-down bugs (busses shutting down for no reason), get rid of the duplicated BCMs and their associated ICC nodes. Signed-off-by: Konrad Dybcio Reviewed-by: Rajendra Nayak --- drivers/interconnect/qcom/x1e80100.c | 315 ----------------------------------- 1 file changed, 315 deletions(-) diff --git a/drivers/interconnect/qcom/x1e80100.c b/drivers/interconnect/qcom/x1e80100.c index d19501d913b3..5b2de9c3a1d6 100644 --- a/drivers/interconnect/qcom/x1e80100.c +++ b/drivers/interconnect/qcom/x1e80100.c @@ -670,150 +670,6 @@ static struct qcom_icc_node xm_usb4_2 = { .links = { X1E80100_SLAVE_AGGRE_USB_SOUTH }, }; -static struct qcom_icc_node qnm_mnoc_hf_disp = { - .name = "qnm_mnoc_hf_disp", - .id = X1E80100_MASTER_MNOC_HF_MEM_NOC_DISP, - .channels = 2, - .buswidth = 32, - .num_links = 1, - .links = { X1E80100_SLAVE_LLCC_DISP }, -}; - -static struct qcom_icc_node qnm_pcie_disp = { - .name = "qnm_pcie_disp", - .id = X1E80100_MASTER_ANOC_PCIE_GEM_NOC_DISP, - .channels = 1, - .buswidth = 64, - .num_links = 1, - .links = { X1E80100_SLAVE_LLCC_DISP }, -}; - -static struct qcom_icc_node llcc_mc_disp = { - .name = "llcc_mc_disp", - .id = X1E80100_MASTER_LLCC_DISP, - .channels = 8, - .buswidth = 4, - .num_links = 1, - .links = { X1E80100_SLAVE_EBI1_DISP }, -}; - -static struct qcom_icc_node qnm_mdp_disp = { - .name = "qnm_mdp_disp", - .id = X1E80100_MASTER_MDP_DISP, - .channels = 2, - .buswidth = 32, - .num_links = 1, - .links = { X1E80100_SLAVE_MNOC_HF_MEM_NOC_DISP }, -}; - -static struct qcom_icc_node qnm_pcie_pcie = { - .name = "qnm_pcie_pcie", - .id = X1E80100_MASTER_ANOC_PCIE_GEM_NOC_PCIE, - .channels = 1, - .buswidth = 64, - .num_links = 1, - .links = { X1E80100_SLAVE_LLCC_PCIE }, -}; - -static struct qcom_icc_node llcc_mc_pcie = { - .name = "llcc_mc_pcie", - .id = X1E80100_MASTER_LLCC_PCIE, - .channels = 8, - .buswidth = 4, - .num_links = 1, - .links = { X1E80100_SLAVE_EBI1_PCIE }, -}; - -static struct qcom_icc_node qnm_pcie_north_gem_noc_pcie = { - .name = "qnm_pcie_north_gem_noc_pcie", - .id = X1E80100_MASTER_PCIE_NORTH_PCIE, - .channels = 1, - .buswidth = 64, - .num_links = 1, - .links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE }, -}; - -static struct qcom_icc_node qnm_pcie_south_gem_noc_pcie = { - .name = "qnm_pcie_south_gem_noc_pcie", - .id = X1E80100_MASTER_PCIE_SOUTH_PCIE, - .channels = 1, - .buswidth = 64, - .num_links = 1, - .links = { X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE }, -}; - -static struct qcom_icc_node xm_pcie_3_pcie = { - .name = "xm_pcie_3_pcie", - .id = X1E80100_MASTER_PCIE_3_PCIE, - .channels = 1, - .buswidth = 64, - .num_links = 1, - .links = { X1E80100_SLAVE_PCIE_NORTH_PCIE }, -}; - -static struct qcom_icc_node xm_pcie_4_pcie = { - .name = "xm_pcie_4_pcie", - .id = X1E80100_MASTER_PCIE_4_PCIE, - .channels = 1, - .buswidth = 8, - .num_links = 1, - .links = { X1E80100_SLAVE_PCIE_NORTH_PCIE }, -}; - -static struct qcom_icc_node xm_pcie_5_pcie = { - .name = "xm_pcie_5_pcie", - .id = X1E80100_MASTER_PCIE_5_PCIE, - .channels = 1, - .buswidth = 8, - .num_links = 1, - .links = { X1E80100_SLAVE_PCIE_NORTH_PCIE }, -}; - -static struct qcom_icc_node xm_pcie_0_pcie = { - .name = "xm_pcie_0_pcie", - .id = X1E80100_MASTER_PCIE_0_PCIE, - .channels = 1, - .buswidth = 16, - .num_links = 1, - .links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE }, -}; - -static struct qcom_icc_node xm_pcie_1_pcie = { - .name = "xm_pcie_1_pcie", - .id = X1E80100_MASTER_PCIE_1_PCIE, - .channels = 1, - .buswidth = 16, - .num_links = 1, - .links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE }, -}; - -static struct qcom_icc_node xm_pcie_2_pcie = { - .name = "xm_pcie_2_pcie", - .id = X1E80100_MASTER_PCIE_2_PCIE, - .channels = 1, - .buswidth = 16, - .num_links = 1, - .links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE }, -}; - -static struct qcom_icc_node xm_pcie_6a_pcie = { - .name = "xm_pcie_6a_pcie", - .id = X1E80100_MASTER_PCIE_6A_PCIE, - .channels = 1, - .buswidth = 32, - .num_links = 1, - .links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE }, -}; - -static struct qcom_icc_node xm_pcie_6b_pcie = { - .name = "xm_pcie_6b_pcie", - .id = X1E80100_MASTER_PCIE_6B_PCIE, - .channels = 1, - .buswidth = 16, - .num_links = 1, - .links = { X1E80100_SLAVE_PCIE_SOUTH_PCIE }, -}; - static struct qcom_icc_node qns_a1noc_snoc = { .name = "qns_a1noc_snoc", .id = X1E80100_SLAVE_A1NOC_SNOC, @@ -1514,76 +1370,6 @@ static struct qcom_icc_node qns_aggre_usb_south_snoc = { .links = { X1E80100_MASTER_AGGRE_USB_SOUTH }, }; -static struct qcom_icc_node qns_llcc_disp = { - .name = "qns_llcc_disp", - .id = X1E80100_SLAVE_LLCC_DISP, - .channels = 8, - .buswidth = 16, - .num_links = 1, - .links = { X1E80100_MASTER_LLCC_DISP }, -}; - -static struct qcom_icc_node ebi_disp = { - .name = "ebi_disp", - .id = X1E80100_SLAVE_EBI1_DISP, - .channels = 8, - .buswidth = 4, - .num_links = 0, -}; - -static struct qcom_icc_node qns_mem_noc_hf_disp = { - .name = "qns_mem_noc_hf_disp", - .id = X1E80100_SLAVE_MNOC_HF_MEM_NOC_DISP, - .channels = 2, - .buswidth = 32, - .num_links = 1, - .links = { X1E80100_MASTER_MNOC_HF_MEM_NOC_DISP }, -}; - -static struct qcom_icc_node qns_llcc_pcie = { - .name = "qns_llcc_pcie", - .id = X1E80100_SLAVE_LLCC_PCIE, - .channels = 8, - .buswidth = 16, - .num_links = 1, - .links = { X1E80100_MASTER_LLCC_PCIE }, -}; - -static struct qcom_icc_node ebi_pcie = { - .name = "ebi_pcie", - .id = X1E80100_SLAVE_EBI1_PCIE, - .channels = 8, - .buswidth = 4, - .num_links = 0, -}; - -static struct qcom_icc_node qns_pcie_mem_noc_pcie = { - .name = "qns_pcie_mem_noc_pcie", - .id = X1E80100_SLAVE_ANOC_PCIE_GEM_NOC_PCIE, - .channels = 1, - .buswidth = 64, - .num_links = 1, - .links = { X1E80100_MASTER_ANOC_PCIE_GEM_NOC_PCIE }, -}; - -static struct qcom_icc_node qns_pcie_north_gem_noc_pcie = { - .name = "qns_pcie_north_gem_noc_pcie", - .id = X1E80100_SLAVE_PCIE_NORTH_PCIE, - .channels = 1, - .buswidth = 64, - .num_links = 1, - .links = { X1E80100_MASTER_PCIE_NORTH_PCIE }, -}; - -static struct qcom_icc_node qns_pcie_south_gem_noc_pcie = { - .name = "qns_pcie_south_gem_noc_pcie", - .id = X1E80100_SLAVE_PCIE_SOUTH_PCIE, - .channels = 1, - .buswidth = 64, - .num_links = 1, - .links = { X1E80100_MASTER_PCIE_SOUTH_PCIE }, -}; - static struct qcom_icc_bcm bcm_acv = { .name = "ACV", .num_nodes = 1, @@ -1755,72 +1541,6 @@ static struct qcom_icc_bcm bcm_sn4 = { .nodes = { &qnm_usb_anoc }, }; -static struct qcom_icc_bcm bcm_acv_disp = { - .name = "ACV", - .num_nodes = 1, - .nodes = { &ebi_disp }, -}; - -static struct qcom_icc_bcm bcm_mc0_disp = { - .name = "MC0", - .num_nodes = 1, - .nodes = { &ebi_disp }, -}; - -static struct qcom_icc_bcm bcm_mm0_disp = { - .name = "MM0", - .num_nodes = 1, - .nodes = { &qns_mem_noc_hf_disp }, -}; - -static struct qcom_icc_bcm bcm_mm1_disp = { - .name = "MM1", - .num_nodes = 1, - .nodes = { &qnm_mdp_disp }, -}; - -static struct qcom_icc_bcm bcm_sh0_disp = { - .name = "SH0", - .num_nodes = 1, - .nodes = { &qns_llcc_disp }, -}; - -static struct qcom_icc_bcm bcm_sh1_disp = { - .name = "SH1", - .num_nodes = 2, - .nodes = { &qnm_mnoc_hf_disp, &qnm_pcie_disp }, -}; - -static struct qcom_icc_bcm bcm_acv_pcie = { - .name = "ACV", - .num_nodes = 1, - .nodes = { &ebi_pcie }, -}; - -static struct qcom_icc_bcm bcm_mc0_pcie = { - .name = "MC0", - .num_nodes = 1, - .nodes = { &ebi_pcie }, -}; - -static struct qcom_icc_bcm bcm_pc0_pcie = { - .name = "PC0", - .num_nodes = 1, - .nodes = { &qns_pcie_mem_noc_pcie }, -}; - -static struct qcom_icc_bcm bcm_sh0_pcie = { - .name = "SH0", - .num_nodes = 1, - .nodes = { &qns_llcc_pcie }, -}; - -static struct qcom_icc_bcm bcm_sh1_pcie = { - .name = "SH1", - .num_nodes = 1, - .nodes = { &qnm_pcie_pcie }, -}; - static struct qcom_icc_bcm *aggre1_noc_bcms[] = { }; @@ -1982,10 +1702,6 @@ static const struct qcom_icc_desc x1e80100_cnoc_main = { static struct qcom_icc_bcm * const gem_noc_bcms[] = { &bcm_sh0, &bcm_sh1, - &bcm_sh0_disp, - &bcm_sh1_disp, - &bcm_sh0_pcie, - &bcm_sh1_pcie, }; static struct qcom_icc_node * const gem_noc_nodes[] = { @@ -2004,11 +1720,6 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc, [SLAVE_LLCC] = &qns_llcc, [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie, - [MASTER_MNOC_HF_MEM_NOC_DISP] = &qnm_mnoc_hf_disp, - [MASTER_ANOC_PCIE_GEM_NOC_DISP] = &qnm_pcie_disp, - [SLAVE_LLCC_DISP] = &qns_llcc_disp, - [MASTER_ANOC_PCIE_GEM_NOC_PCIE] = &qnm_pcie_pcie, - [SLAVE_LLCC_PCIE] = &qns_llcc_pcie, }; static const struct qcom_icc_desc x1e80100_gem_noc = { @@ -2067,19 +1778,11 @@ static const struct qcom_icc_desc x1e80100_lpass_lpicx_noc = { static struct qcom_icc_bcm * const mc_virt_bcms[] = { &bcm_acv, &bcm_mc0, - &bcm_acv_disp, - &bcm_mc0_disp, - &bcm_acv_pcie, - &bcm_mc0_pcie, }; static struct qcom_icc_node * const mc_virt_nodes[] = { [MASTER_LLCC] = &llcc_mc, [SLAVE_EBI1] = &ebi, - [MASTER_LLCC_DISP] = &llcc_mc_disp, - [SLAVE_EBI1_DISP] = &ebi_disp, - [MASTER_LLCC_PCIE] = &llcc_mc_pcie, - [SLAVE_EBI1_PCIE] = &ebi_pcie, }; static const struct qcom_icc_desc x1e80100_mc_virt = { @@ -2092,8 +1795,6 @@ static const struct qcom_icc_desc x1e80100_mc_virt = { static struct qcom_icc_bcm * const mmss_noc_bcms[] = { &bcm_mm0, &bcm_mm1, - &bcm_mm0_disp, - &bcm_mm1_disp, }; static struct qcom_icc_node * const mmss_noc_nodes[] = { @@ -2110,8 +1811,6 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { [SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf, [SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf, [SLAVE_SERVICE_MNOC] = &srvc_mnoc, - [MASTER_MDP_DISP] = &qnm_mdp_disp, - [SLAVE_MNOC_HF_MEM_NOC_DISP] = &qns_mem_noc_hf_disp, }; static const struct qcom_icc_desc x1e80100_mmss_noc = { @@ -2139,16 +1838,12 @@ static const struct qcom_icc_desc x1e80100_nsp_noc = { static struct qcom_icc_bcm * const pcie_center_anoc_bcms[] = { &bcm_pc0, - &bcm_pc0_pcie, }; static struct qcom_icc_node * const pcie_center_anoc_nodes[] = { [MASTER_PCIE_NORTH] = &qnm_pcie_north_gem_noc, [MASTER_PCIE_SOUTH] = &qnm_pcie_south_gem_noc, [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc, - [MASTER_PCIE_NORTH_PCIE] = &qnm_pcie_north_gem_noc_pcie, - [MASTER_PCIE_SOUTH_PCIE] = &qnm_pcie_south_gem_noc_pcie, - [SLAVE_ANOC_PCIE_GEM_NOC_PCIE] = &qns_pcie_mem_noc_pcie, }; static const struct qcom_icc_desc x1e80100_pcie_center_anoc = { @@ -2166,10 +1861,6 @@ static struct qcom_icc_node * const pcie_north_anoc_nodes[] = { [MASTER_PCIE_4] = &xm_pcie_4, [MASTER_PCIE_5] = &xm_pcie_5, [SLAVE_PCIE_NORTH] = &qns_pcie_north_gem_noc, - [MASTER_PCIE_3_PCIE] = &xm_pcie_3_pcie, - [MASTER_PCIE_4_PCIE] = &xm_pcie_4_pcie, - [MASTER_PCIE_5_PCIE] = &xm_pcie_5_pcie, - [SLAVE_PCIE_NORTH_PCIE] = &qns_pcie_north_gem_noc_pcie, }; static const struct qcom_icc_desc x1e80100_pcie_north_anoc = { @@ -2189,12 +1880,6 @@ static struct qcom_icc_node * const pcie_south_anoc_nodes[] = { [MASTER_PCIE_6A] = &xm_pcie_6a, [MASTER_PCIE_6B] = &xm_pcie_6b, [SLAVE_PCIE_SOUTH] = &qns_pcie_south_gem_noc, - [MASTER_PCIE_0_PCIE] = &xm_pcie_0_pcie, - [MASTER_PCIE_1_PCIE] = &xm_pcie_1_pcie, - [MASTER_PCIE_2_PCIE] = &xm_pcie_2_pcie, - [MASTER_PCIE_6A_PCIE] = &xm_pcie_6a_pcie, - [MASTER_PCIE_6B_PCIE] = &xm_pcie_6b_pcie, - [SLAVE_PCIE_SOUTH_PCIE] = &qns_pcie_south_gem_noc_pcie, }; static const struct qcom_icc_desc x1e80100_pcie_south_anoc = { From patchwork Tue Jan 2 18:29:48 2024 Content-Type: text/plain; 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[178.235.179.36]) by smtp.gmail.com with ESMTPSA id et10-20020a170907294a00b00a2699a54888sm11968835ejc.64.2024.01.02.10.30.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 10:30:09 -0800 (PST) From: Konrad Dybcio Date: Tue, 02 Jan 2024 19:29:48 +0100 Subject: [PATCH 2/4] dt-bindings: interconnect: Remove bogus interconnect nodes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240102-topic-x1e_fixes-v1-2-70723e08d5f6@linaro.org> References: <20240102-topic-x1e_fixes-v1-0-70723e08d5f6@linaro.org> In-Reply-To: <20240102-topic-x1e_fixes-v1-0-70723e08d5f6@linaro.org> To: Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rajendra Nayak , Sibi Sankar , Abel Vesa Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1704220203; l=3092; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=NPuCT7zmHc1LyvgFc2ZzbWoHNtv/ZUIjfd1BvzfKmKk=; b=Bs8cE1QNbc7YB3Qe7cprzsSBnjqrn3LNy1CHW2Gx1DmO66cAcVrv5B/lW7QsCdr2IqESRHVrx IWbFrTLxfUkCTJV1HbAtUK2uySDKxg1U/cNEpNrbFE9pfEkVj/Y0ROv X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= The downstream kernel has infrastructure for passing votes from different interconnect nodes onto different RPMh RSCs. This neither implemented, not is going to be implemented upstream (in favor of a different solution using ICC tags through the same node). Unfortunately, as it happens, meaningless (in the upstream context) parts of the vendor driver were copied, ending up causing havoc - since all "per-RSC" (in quotes because they all point to the main APPS one) BCMs defined within the driver overwrite the value in RPMh on every aggregation. To both avoid keeping bogus code around and possibly introducing impossible-to-track-down bugs (busses shutting down for no reason), get rid of the duplicated ICC node definitions. Signed-off-by: Konrad Dybcio --- .../dt-bindings/interconnect/qcom,x1e80100-rpmh.h | 24 ---------------------- 1 file changed, 24 deletions(-) diff --git a/include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h b/include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h index a38c3472698a..7d9710881149 100644 --- a/include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h +++ b/include/dt-bindings/interconnect/qcom,x1e80100-rpmh.h @@ -112,11 +112,6 @@ #define SLAVE_GEM_NOC_CNOC 12 #define SLAVE_LLCC 13 #define SLAVE_MEM_NOC_PCIE_SNOC 14 -#define MASTER_MNOC_HF_MEM_NOC_DISP 15 -#define MASTER_ANOC_PCIE_GEM_NOC_DISP 16 -#define SLAVE_LLCC_DISP 17 -#define MASTER_ANOC_PCIE_GEM_NOC_PCIE 18 -#define SLAVE_LLCC_PCIE 19 #define MASTER_LPIAON_NOC 0 #define SLAVE_LPASS_GEM_NOC 1 @@ -129,10 +124,6 @@ #define MASTER_LLCC 0 #define SLAVE_EBI1 1 -#define MASTER_LLCC_DISP 2 -#define SLAVE_EBI1_DISP 3 -#define MASTER_LLCC_PCIE 4 -#define SLAVE_EBI1_PCIE 5 #define MASTER_AV1_ENC 0 #define MASTER_CAMNOC_HF 1 @@ -147,8 +138,6 @@ #define SLAVE_MNOC_HF_MEM_NOC 10 #define SLAVE_MNOC_SF_MEM_NOC 11 #define SLAVE_SERVICE_MNOC 12 -#define MASTER_MDP_DISP 13 -#define SLAVE_MNOC_HF_MEM_NOC_DISP 14 #define MASTER_CDSP_PROC 0 #define SLAVE_CDSP_MEM_NOC 1 @@ -156,18 +145,11 @@ #define MASTER_PCIE_NORTH 0 #define MASTER_PCIE_SOUTH 1 #define SLAVE_ANOC_PCIE_GEM_NOC 2 -#define MASTER_PCIE_NORTH_PCIE 3 -#define MASTER_PCIE_SOUTH_PCIE 4 -#define SLAVE_ANOC_PCIE_GEM_NOC_PCIE 5 #define MASTER_PCIE_3 0 #define MASTER_PCIE_4 1 #define MASTER_PCIE_5 2 #define SLAVE_PCIE_NORTH 3 -#define MASTER_PCIE_3_PCIE 4 -#define MASTER_PCIE_4_PCIE 5 -#define MASTER_PCIE_5_PCIE 6 -#define SLAVE_PCIE_NORTH_PCIE 7 #define MASTER_PCIE_0 0 #define MASTER_PCIE_1 1 @@ -175,12 +157,6 @@ #define MASTER_PCIE_6A 3 #define MASTER_PCIE_6B 4 #define SLAVE_PCIE_SOUTH 5 -#define MASTER_PCIE_0_PCIE 6 -#define MASTER_PCIE_1_PCIE 7 -#define MASTER_PCIE_2_PCIE 8 -#define MASTER_PCIE_6A_PCIE 9 -#define MASTER_PCIE_6B_PCIE 10 -#define SLAVE_PCIE_SOUTH_PCIE 11 #define MASTER_A1NOC_SNOC 0 #define MASTER_A2NOC_SNOC 1 From patchwork Tue Jan 2 18:29:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 759430 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A96C315AE4 for ; Tue, 2 Jan 2024 18:30:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="VuH+b9LZ" Received: by mail-wr1-f52.google.com with SMTP id ffacd0b85a97d-33674f60184so9781389f8f.1 for ; Tue, 02 Jan 2024 10:30:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704220211; x=1704825011; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=nWRCEPo3uk8PO0iqeS9GD+AGuH5MLy4R7Glqs9RzmNA=; b=VuH+b9LZsjaCoaRs/ZLXcDOcfYngSSzhp0I+uHw2vEF+gSWhT0diO13aOxcaxexq7j 22/t2jYG7PNjBKJiLX+oE2ZGnu7Z1PiMmoPwRT5HFwFNIwN0djNFkBHMzJTWmjX+XsnZ aV51w1SeT7Sm8H68Q78zwbjIiQDz+WBY2lbvMASc1aazXNtX5QuapFbE1QxlpF9dxQbD oiSKFnlFrNTpMzOe34jrCdRejM68y6s0UsyJxvu4xFxRBY9dw7CXJb7UAEfE77W+SRQ7 qgbw1YmDeqacrJNpJa/jr76KxFpxs1LERdFl0nkHrOs921HH0BRevIv5imJTG05MlVK/ QFGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704220211; x=1704825011; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nWRCEPo3uk8PO0iqeS9GD+AGuH5MLy4R7Glqs9RzmNA=; b=gyvX5aAmvZ/YEbjUawRM6Rbxf47JQPfa+CCezFQUEIHPn86zHuxDvQ+HJv+lR+t24y nRO20TQiQrnfXwDlLKzcgA92XbYeBb7zq6U78MK6GszEfFCcd+k1nu1XulxGZsL0sosB 7oBJZ7e6s4vuzSOyeeogyXSfP2AMXWhN7QqjWKT1eI0Uf7vPKinJakzZtkt7tngMZhXo F6vHgrjiLxykX8lY+BKostOchqQ8j4qCeHVk+XI3OpE6KeiuNvID4QnkeSpZThwnsGp4 8KtlbMdlPUENUXVhld+QRY0ibV7UpyS8xTQd/6piREZCFUGmOXiZO/NKu9ThJghKxQBo znhw== X-Gm-Message-State: AOJu0Yy2NOcLhk6+vCXrRLF6lPRsQc9pO6RnVCykSNhQLQEDeaE1Blx7 ADVbPT4QYNIkORB2qBSX6Pi/D/j910wQHw== X-Google-Smtp-Source: AGHT+IFX3GSSUEbN6TOB3T8kBbk7okSpo54ycIvJoOBfMFq2gsg7UVxTpK4OdqdeWI02/7yr1jYAbw== X-Received: by 2002:a05:600c:4514:b0:40d:8397:e6ef with SMTP id t20-20020a05600c451400b0040d8397e6efmr2516168wmo.144.1704220210903; Tue, 02 Jan 2024 10:30:10 -0800 (PST) Received: from [10.167.154.1] (178235179036.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.36]) by smtp.gmail.com with ESMTPSA id et10-20020a170907294a00b00a2699a54888sm11968835ejc.64.2024.01.02.10.30.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 10:30:10 -0800 (PST) From: Konrad Dybcio Date: Tue, 02 Jan 2024 19:29:49 +0100 Subject: [PATCH 3/4] arm64: dts: qcom: x1e80100: Add missing system-wide PSCI power domain Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240102-topic-x1e_fixes-v1-3-70723e08d5f6@linaro.org> References: <20240102-topic-x1e_fixes-v1-0-70723e08d5f6@linaro.org> In-Reply-To: <20240102-topic-x1e_fixes-v1-0-70723e08d5f6@linaro.org> To: Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rajendra Nayak , Sibi Sankar , Abel Vesa Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1704220203; l=1514; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=a/TSf4p7qbd3BP7GuDisMtggCpN6jL7pGZHmOCzvoa0=; b=Z2+Ub7tjMe4FVBz3xh+JlHpM49o8IStSPlM4cL67eGCib5gN4+iKoJ3Ia03IysXQCJQdWXlPf sgDTgFj2DWxAiJ6trozz4GiSpm9w396bLUbh9mOjGL4AnQ7XlCYrX3Y X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Previous Qualcomm SoCs over the past couple years have used the Arm DSU architecture, which basically unified the meaning of the "cluster" and "system". This is however clearly not the case on X1E, as can be seen by three separate cluster power domains. Add the lacking system-level power domain. For now it's going to be always-on, as no system-wide idle states are defined at the moment. Signed-off-by: Konrad Dybcio Reviewed-by: Abel Vesa --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 6f75fc342ceb..fc164b9b3ef1 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -395,16 +395,24 @@ CPU_PD11: power-domain-cpu11 { CLUSTER_PD0: power-domain-cpu-cluster0 { #power-domain-cells = <0>; domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; + power-domains = <&SYSTEM_PD>; }; CLUSTER_PD1: power-domain-cpu-cluster1 { #power-domain-cells = <0>; domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; + power-domains = <&SYSTEM_PD>; }; CLUSTER_PD2: power-domain-cpu-cluster2 { #power-domain-cells = <0>; domain-idle-states = <&CLUSTER_CL4>, <&CLUSTER_CL5>; + power-domains = <&SYSTEM_PD>; + }; + + SYSTEM_PD: power-domain-system { + #power-domain-cells = <0>; + /* TODO: system-wide idle states */ }; }; From patchwork Tue Jan 2 18:29:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 759702 Received: from mail-ej1-f41.google.com (mail-ej1-f41.google.com [209.85.218.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A25E15ADB for ; Tue, 2 Jan 2024 18:30:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="vWcnYTO1" Received: by mail-ej1-f41.google.com with SMTP id a640c23a62f3a-a2821884a09so101850366b.2 for ; Tue, 02 Jan 2024 10:30:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1704220213; x=1704825013; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=cp5GNYs8COIpVS3xr0MHdRdJQ4iBxaqmuCTnKQzb9HQ=; b=vWcnYTO1HYUYJviMjPW/Omttgckm6yu/65N/K/836mrO/+6fo5Vg6ZSXbV4GcRtDah 0AFYeoLi3J/YIzfEyQtRvWpoDB/giitUw9ln9w1T4duMJbqxQeHgRioLbA2oZOwIkk6D iJOJfBFIy/PR57nwxHTHH8xj86R8X1KUZ1FOUcKITx0ctMD4VXmSKTxIHwg2mZ5deUQF YphfV+nN3cS+pBTDYxTZlD48yLKlDq/1IM1rvcG3ISlvGei5COmuvfs8FrXdCpjRDFwy v3EUpGd9Kj9JSnEbrm3xsFR1J/g5wbU6SBG1V3KKYptKzH1ai7911xxG7CuwDMDpPHOY v17w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1704220213; x=1704825013; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cp5GNYs8COIpVS3xr0MHdRdJQ4iBxaqmuCTnKQzb9HQ=; b=bmfLt2huyKPpZDhYihOr6780zPyC/XrASdufXPLGTNdB4ysHXlBpt6NHEQuaKAQ9ds dyKnb06Ejit3FbGkYAGUkbMm7SKaxGnbqD2ug/KcSvbsP4mlvx5xx9LHOyyYVG/1LsrO kNqjuRjr37dIzBnvqW3BD0v7TKVdikm4wZNv5btACUAczHUhwoITcQyGTWw33c/pg9uA PlMHoaUsuhOU2Nvcbzv2ZJeNWkhqhQh0EHm4i25vfIjgciyGbl93Lo/oeJmX642NCc0d BV7FchChTacwGUeinYTWbO2XosmDnkvUrYRDG3YwyjoypeGRIEOMGZtwqlcEZoBIAVPv r1AA== X-Gm-Message-State: AOJu0Ywb/2ny2Ymh6xNJz1dXXu/rlEgUosDZQT2/xbFwEzPKAUR1PYdm yIpLsiLeulSHukVZC4GHTzQ7MPRsL0wR/Q== X-Google-Smtp-Source: AGHT+IEtrEeyMfPqrNLa3Jtqiv9w2sKozdJ2TbgYHjpAJW+k52RxgM/5dlUFCx+gNLIZkLr24Jpv+w== X-Received: by 2002:a17:906:413:b0:a28:2165:7c74 with SMTP id d19-20020a170906041300b00a2821657c74mr1307851eja.13.1704220212903; Tue, 02 Jan 2024 10:30:12 -0800 (PST) Received: from [10.167.154.1] (178235179036.dynamic-4-waw-k-1-3-0.vectranet.pl. [178.235.179.36]) by smtp.gmail.com with ESMTPSA id et10-20020a170907294a00b00a2699a54888sm11968835ejc.64.2024.01.02.10.30.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jan 2024 10:30:12 -0800 (PST) From: Konrad Dybcio Date: Tue, 02 Jan 2024 19:29:50 +0100 Subject: [PATCH 4/4] arm64: dts: qcom: x1e80100: Flush RSC sleep & wake votes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240102-topic-x1e_fixes-v1-4-70723e08d5f6@linaro.org> References: <20240102-topic-x1e_fixes-v1-0-70723e08d5f6@linaro.org> In-Reply-To: <20240102-topic-x1e_fixes-v1-0-70723e08d5f6@linaro.org> To: Bjorn Andersson , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Rajendra Nayak , Sibi Sankar , Abel Vesa Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1704220203; l=982; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=ZMHte+R+v5WQ2x6Ng6sIhmvNpiEdoapaHW4wE0VSFZ4=; b=7um3uB/1kZ41KjjEu9/1KhmrD49Zm4CmzwAHeG/8u+R44ad6kRC5yv6KeqQ8a44EBZeBZKKAG sZ5DqheX/UACWzaZr8mqKzg6SQO0/ZNgd/wLY4Ks6b0ACbRoShImT3b X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= The RPMh driver will cache sleep and wake votes until the cluster power-domain is about to enter idle, to avoid unnecessary writes. So associate the apps_rsc with the cluster pd, so that it can be notified about this event. Without this, only AMC votes are being committed. Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") Signed-off-by: Konrad Dybcio Reviewed-by: Abel Vesa --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index fc164b9b3ef1..2a14e8e39b3b 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3334,6 +3334,7 @@ apps_rsc: rsc@17500000 { , ; label = "apps_rsc"; + power-domains = <&SYSTEM_PD>; apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter";