From patchwork Thu Dec 28 03:17:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans Hu X-Patchwork-Id: 758902 Received: from mx2.zhaoxin.com (mx2.zhaoxin.com [203.110.167.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 313663C07 for ; Thu, 28 Dec 2023 03:17:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=zhaoxin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zhaoxin.com X-ASG-Debug-ID: 1703733467-1eb14e0c7f06b70002-PT6Irj Received: from ZXSHMBX1.zhaoxin.com (ZXSHMBX1.zhaoxin.com [10.28.252.163]) by mx2.zhaoxin.com with ESMTP id ulGYRMDMUDxyOsav (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NO); Thu, 28 Dec 2023 11:17:47 +0800 (CST) X-Barracuda-Envelope-From: HansHu-oc@zhaoxin.com X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.163 Received: from ZXBJMBX03.zhaoxin.com (10.29.252.7) by ZXSHMBX1.zhaoxin.com (10.28.252.163) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 28 Dec 2023 11:17:47 +0800 Received: from ml-HP-ProDesk-680-G4-MT.zhaoxin.com (10.28.66.68) by ZXBJMBX03.zhaoxin.com (10.29.252.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 28 Dec 2023 11:17:46 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.163 From: Hans Hu X-Barracuda-RBL-Trusted-Forwarder: 10.29.252.7 To: , CC: , , Subject: [PATCH v5 1/8] i2c: wmt: create wmt_i2c_init for general init Date: Thu, 28 Dec 2023 11:17:39 +0800 X-ASG-Orig-Subj: [PATCH v5 1/8] i2c: wmt: create wmt_i2c_init for general init Message-ID: <98561c2550e96a44a514d661950f4ae89007b73d.1703733126.git.hanshu-oc@zhaoxin.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To ZXBJMBX03.zhaoxin.com (10.29.252.7) X-Barracuda-Connect: ZXSHMBX1.zhaoxin.com[10.28.252.163] X-Barracuda-Start-Time: 1703733467 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.36:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 3376 X-Barracuda-BRTS-Status: 0 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.118654 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- v4->v5: add previous prototype 'static' for wmt_i2c_init(). Some common initialization actions are put in the function wmt_i2c_init(), which is convenient to share with zhaoxin. Signed-off-by: Hans Hu --- drivers/i2c/busses/i2c-wmt.c | 67 +++++++++++++++++++----------------- 1 file changed, 36 insertions(+), 31 deletions(-) diff --git a/drivers/i2c/busses/i2c-wmt.c b/drivers/i2c/busses/i2c-wmt.c index ec2a8da134e5..f1888f100d83 100644 --- a/drivers/i2c/busses/i2c-wmt.c +++ b/drivers/i2c/busses/i2c-wmt.c @@ -286,6 +286,38 @@ static irqreturn_t wmt_i2c_isr(int irq, void *data) return IRQ_HANDLED; } +static int wmt_i2c_init(struct platform_device *pdev, struct wmt_i2c_dev **pi2c_dev) +{ + int err; + struct wmt_i2c_dev *i2c_dev; + struct device_node *np = pdev->dev.of_node; + + i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); + if (!i2c_dev) + return -ENOMEM; + + i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); + if (IS_ERR(i2c_dev->base)) + return PTR_ERR(i2c_dev->base); + + i2c_dev->irq = irq_of_parse_and_map(np, 0); + if (!i2c_dev->irq) + return -EINVAL; + + err = devm_request_irq(&pdev->dev, i2c_dev->irq, wmt_i2c_isr, + 0, pdev->name, i2c_dev); + if (err) + return dev_err_probe(&pdev->dev, err, + "failed to request irq %i\n", i2c_dev->irq); + + i2c_dev->dev = &pdev->dev; + init_completion(&i2c_dev->complete); + platform_set_drvdata(pdev, i2c_dev); + + *pi2c_dev = i2c_dev; + return 0; +} + static int wmt_i2c_reset_hardware(struct wmt_i2c_dev *i2c_dev) { int err; @@ -327,19 +359,9 @@ static int wmt_i2c_probe(struct platform_device *pdev) int err; u32 clk_rate; - i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); - if (!i2c_dev) - return -ENOMEM; - - i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); - if (IS_ERR(i2c_dev->base)) - return PTR_ERR(i2c_dev->base); - - i2c_dev->irq = irq_of_parse_and_map(np, 0); - if (!i2c_dev->irq) { - dev_err(&pdev->dev, "irq missing or invalid\n"); - return -EINVAL; - } + err = wmt_i2c_init(pdev, &i2c_dev); + if (err) + return err; i2c_dev->clk = of_clk_get(np, 0); if (IS_ERR(i2c_dev->clk)) { @@ -351,15 +373,6 @@ static int wmt_i2c_probe(struct platform_device *pdev) if (!err && (clk_rate == I2C_MAX_FAST_MODE_FREQ)) i2c_dev->tcr = TCR_FAST_MODE; - i2c_dev->dev = &pdev->dev; - - err = devm_request_irq(&pdev->dev, i2c_dev->irq, wmt_i2c_isr, 0, - "i2c", i2c_dev); - if (err) { - dev_err(&pdev->dev, "failed to request irq %i\n", i2c_dev->irq); - return err; - } - adap = &i2c_dev->adapter; i2c_set_adapdata(adap, i2c_dev); strscpy(adap->name, "WMT I2C adapter", sizeof(adap->name)); @@ -368,21 +381,13 @@ static int wmt_i2c_probe(struct platform_device *pdev) adap->dev.parent = &pdev->dev; adap->dev.of_node = pdev->dev.of_node; - init_completion(&i2c_dev->complete); - err = wmt_i2c_reset_hardware(i2c_dev); if (err) { dev_err(&pdev->dev, "error initializing hardware\n"); return err; } - err = i2c_add_adapter(adap); - if (err) - return err; - - platform_set_drvdata(pdev, i2c_dev); - - return 0; + return i2c_add_adapter(adap); } static void wmt_i2c_remove(struct platform_device *pdev) From patchwork Thu Dec 28 03:17:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans Hu X-Patchwork-Id: 758900 Received: from mx1.zhaoxin.com (MX1.ZHAOXIN.COM [210.0.225.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB5873C1D for ; Thu, 28 Dec 2023 03:17:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=zhaoxin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=zhaoxin.com X-ASG-Debug-ID: 1703733468-086e230f2707c80001-PT6Irj Received: from ZXSHMBX3.zhaoxin.com (ZXSHMBX3.zhaoxin.com [10.28.252.165]) by mx1.zhaoxin.com with ESMTP id JU0ThnGzB7m9Sy3o (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NO); Thu, 28 Dec 2023 11:17:48 +0800 (CST) X-Barracuda-Envelope-From: HansHu-oc@zhaoxin.com X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.165 Received: from ZXBJMBX03.zhaoxin.com (10.29.252.7) by ZXSHMBX3.zhaoxin.com (10.28.252.165) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 28 Dec 2023 11:17:48 +0800 Received: from ml-HP-ProDesk-680-G4-MT.zhaoxin.com (10.28.66.68) by ZXBJMBX03.zhaoxin.com (10.29.252.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 28 Dec 2023 11:17:47 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.165 From: Hans Hu X-Barracuda-RBL-Trusted-Forwarder: 10.29.252.7 To: , CC: , , Subject: [PATCH v5 2/8] i2c: wmt: rename marcos with prefix WMTI2C_ Date: Thu, 28 Dec 2023 11:17:40 +0800 X-ASG-Orig-Subj: [PATCH v5 2/8] i2c: wmt: rename marcos with prefix WMTI2C_ Message-ID: <4722ecc89afec9c625c5382cb48c5c8eed908974.1703733126.git.hanshu-oc@zhaoxin.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To ZXBJMBX03.zhaoxin.com (10.29.252.7) X-Barracuda-Connect: ZXSHMBX3.zhaoxin.com[10.28.252.165] X-Barracuda-Start-Time: 1703733468 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.35:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 10901 X-Barracuda-BRTS-Status: 0 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.118655 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- Tweaked a few formatting things: rename marcos with prefix WMTI2C_ Signed-off-by: Hans Hu --- drivers/i2c/busses/i2c-wmt.c | 176 +++++++++++++++++------------------ 1 file changed, 88 insertions(+), 88 deletions(-) diff --git a/drivers/i2c/busses/i2c-wmt.c b/drivers/i2c/busses/i2c-wmt.c index f1888f100d83..95d739fde34f 100644 --- a/drivers/i2c/busses/i2c-wmt.c +++ b/drivers/i2c/busses/i2c-wmt.c @@ -20,59 +20,59 @@ #include #include -#define REG_CR 0x00 -#define REG_TCR 0x02 -#define REG_CSR 0x04 -#define REG_ISR 0x06 -#define REG_IMR 0x08 -#define REG_CDR 0x0A -#define REG_TR 0x0C -#define REG_MCR 0x0E -#define REG_SLAVE_CR 0x10 -#define REG_SLAVE_SR 0x12 -#define REG_SLAVE_ISR 0x14 -#define REG_SLAVE_IMR 0x16 -#define REG_SLAVE_DR 0x18 -#define REG_SLAVE_TR 0x1A +#define WMTI2C_REG_CR 0x00 +#define WMTI2C_REG_TCR 0x02 +#define WMTI2C_REG_CSR 0x04 +#define WMTI2C_REG_ISR 0x06 +#define WMTI2C_REG_IMR 0x08 +#define WMTI2C_REG_CDR 0x0A +#define WMTI2C_REG_TR 0x0C +#define WMTI2C_REG_MCR 0x0E +#define WMTI2C_REG_SLAVE_CR 0x10 +#define WMTI2C_REG_SLAVE_SR 0x12 +#define WMTI2C_REG_SLAVE_ISR 0x14 +#define WMTI2C_REG_SLAVE_IMR 0x16 +#define WMTI2C_REG_SLAVE_DR 0x18 +#define WMTI2C_REG_SLAVE_TR 0x1A /* REG_CR Bit fields */ -#define CR_TX_NEXT_ACK 0x0000 -#define CR_ENABLE 0x0001 -#define CR_TX_NEXT_NO_ACK 0x0002 -#define CR_TX_END 0x0004 -#define CR_CPU_RDY 0x0008 -#define SLAV_MODE_SEL 0x8000 +#define WMTI2C_CR_TX_NEXT_ACK 0x0000 +#define WMTI2C_CR_ENABLE 0x0001 +#define WMTI2C_CR_TX_NEXT_NO_ACK 0x0002 +#define WMTI2C_CR_TX_END 0x0004 +#define WMTI2C_CR_CPU_RDY 0x0008 +#define WMTI2C_SLAV_MODE_SEL 0x8000 /* REG_TCR Bit fields */ -#define TCR_STANDARD_MODE 0x0000 -#define TCR_MASTER_WRITE 0x0000 -#define TCR_HS_MODE 0x2000 -#define TCR_MASTER_READ 0x4000 -#define TCR_FAST_MODE 0x8000 -#define TCR_SLAVE_ADDR_MASK 0x007F +#define WMTI2C_TCR_STANDARD_MODE 0x0000 +#define WMTI2C_TCR_MASTER_WRITE 0x0000 +#define WMTI2C_TCR_HS_MODE 0x2000 +#define WMTI2C_TCR_MASTER_READ 0x4000 +#define WMTI2C_TCR_FAST_MODE 0x8000 +#define WMTI2C_TCR_SLAVE_ADDR_MASK 0x007F /* REG_ISR Bit fields */ -#define ISR_NACK_ADDR 0x0001 -#define ISR_BYTE_END 0x0002 -#define ISR_SCL_TIMEOUT 0x0004 -#define ISR_WRITE_ALL 0x0007 +#define WMTI2C_ISR_NACK_ADDR 0x0001 +#define WMTI2C_ISR_BYTE_END 0x0002 +#define WMTI2C_ISR_SCL_TIMEOUT 0x0004 +#define WMTI2C_ISR_WRITE_ALL 0x0007 /* REG_IMR Bit fields */ -#define IMR_ENABLE_ALL 0x0007 +#define WMTI2C_IMR_ENABLE_ALL 0x0007 /* REG_CSR Bit fields */ -#define CSR_RCV_NOT_ACK 0x0001 -#define CSR_RCV_ACK_MASK 0x0001 -#define CSR_READY_MASK 0x0002 +#define WMTI2C_CSR_RCV_NOT_ACK 0x0001 +#define WMTI2C_CSR_RCV_ACK_MASK 0x0001 +#define WMTI2C_CSR_READY_MASK 0x0002 /* REG_TR */ -#define SCL_TIMEOUT(x) (((x) & 0xFF) << 8) -#define TR_STD 0x0064 -#define TR_HS 0x0019 +#define WMTI2C_SCL_TIMEOUT(x) (((x) & 0xFF) << 8) +#define WMTI2C_TR_STD 0x0064 +#define WMTI2C_TR_HS 0x0019 /* REG_MCR */ -#define MCR_APB_96M 7 -#define MCR_APB_166M 12 +#define WMTI2C_MCR_APB_96M 7 +#define WMTI2C_MCR_APB_166M 12 #define WMT_I2C_TIMEOUT (msecs_to_jiffies(1000)) @@ -92,7 +92,7 @@ static int wmt_i2c_wait_bus_not_busy(struct wmt_i2c_dev *i2c_dev) unsigned long timeout; timeout = jiffies + WMT_I2C_TIMEOUT; - while (!(readw(i2c_dev->base + REG_CSR) & CSR_READY_MASK)) { + while (!(readw(i2c_dev->base + WMTI2C_REG_CSR) & WMTI2C_CSR_READY_MASK)) { if (time_after(jiffies, timeout)) { dev_warn(i2c_dev->dev, "timeout waiting for bus ready\n"); return -EBUSY; @@ -113,10 +113,10 @@ static int wmt_check_status(struct wmt_i2c_dev *i2c_dev) if (!wait_result) return -ETIMEDOUT; - if (i2c_dev->cmd_status & ISR_NACK_ADDR) + if (i2c_dev->cmd_status & WMTI2C_ISR_NACK_ADDR) ret = -EIO; - if (i2c_dev->cmd_status & ISR_SCL_TIMEOUT) + if (i2c_dev->cmd_status & WMTI2C_ISR_SCL_TIMEOUT) ret = -ETIMEDOUT; return ret; @@ -135,28 +135,28 @@ static int wmt_i2c_write(struct wmt_i2c_dev *i2c_dev, struct i2c_msg *pmsg, * start at -1 and break out early from the loop */ xfer_len = -1; - writew(0, i2c_dev->base + REG_CDR); + writew(0, i2c_dev->base + WMTI2C_REG_CDR); } else { - writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR); + writew(pmsg->buf[0] & 0xFF, i2c_dev->base + WMTI2C_REG_CDR); } if (!(pmsg->flags & I2C_M_NOSTART)) { - val = readw(i2c_dev->base + REG_CR); - val &= ~CR_TX_END; - val |= CR_CPU_RDY; - writew(val, i2c_dev->base + REG_CR); + val = readw(i2c_dev->base + WMTI2C_REG_CR); + val &= ~WMTI2C_CR_TX_END; + val |= WMTI2C_CR_CPU_RDY; + writew(val, i2c_dev->base + WMTI2C_REG_CR); } reinit_completion(&i2c_dev->complete); - tcr_val |= (TCR_MASTER_WRITE | (pmsg->addr & TCR_SLAVE_ADDR_MASK)); + tcr_val |= (WMTI2C_TCR_MASTER_WRITE | (pmsg->addr & WMTI2C_TCR_SLAVE_ADDR_MASK)); - writew(tcr_val, i2c_dev->base + REG_TCR); + writew(tcr_val, i2c_dev->base + WMTI2C_REG_TCR); if (pmsg->flags & I2C_M_NOSTART) { - val = readw(i2c_dev->base + REG_CR); - val |= CR_CPU_RDY; - writew(val, i2c_dev->base + REG_CR); + val = readw(i2c_dev->base + WMTI2C_REG_CR); + val |= WMTI2C_CR_CPU_RDY; + writew(val, i2c_dev->base + WMTI2C_REG_CR); } while (xfer_len < pmsg->len) { @@ -166,25 +166,25 @@ static int wmt_i2c_write(struct wmt_i2c_dev *i2c_dev, struct i2c_msg *pmsg, xfer_len++; - val = readw(i2c_dev->base + REG_CSR); - if ((val & CSR_RCV_ACK_MASK) == CSR_RCV_NOT_ACK) { + val = readw(i2c_dev->base + WMTI2C_REG_CSR); + if ((val & WMTI2C_CSR_RCV_ACK_MASK) == WMTI2C_CSR_RCV_NOT_ACK) { dev_dbg(i2c_dev->dev, "write RCV NACK error\n"); return -EIO; } if (pmsg->len == 0) { - val = CR_TX_END | CR_CPU_RDY | CR_ENABLE; - writew(val, i2c_dev->base + REG_CR); + val = WMTI2C_CR_TX_END | WMTI2C_CR_CPU_RDY | WMTI2C_CR_ENABLE; + writew(val, i2c_dev->base + WMTI2C_REG_CR); break; } if (xfer_len == pmsg->len) { if (last != 1) - writew(CR_ENABLE, i2c_dev->base + REG_CR); + writew(WMTI2C_CR_ENABLE, i2c_dev->base + WMTI2C_REG_CR); } else { writew(pmsg->buf[xfer_len] & 0xFF, i2c_dev->base + - REG_CDR); - writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR); + WMTI2C_REG_CDR); + writew(WMTI2C_CR_CPU_RDY | WMTI2C_CR_ENABLE, i2c_dev->base + WMTI2C_REG_CR); } } @@ -197,27 +197,27 @@ static int wmt_i2c_read(struct wmt_i2c_dev *i2c_dev, struct i2c_msg *pmsg) int ret; u32 xfer_len = 0; - val = readw(i2c_dev->base + REG_CR); - val &= ~(CR_TX_END | CR_TX_NEXT_NO_ACK); + val = readw(i2c_dev->base + WMTI2C_REG_CR); + val &= ~(WMTI2C_CR_TX_END | WMTI2C_CR_TX_NEXT_NO_ACK); if (!(pmsg->flags & I2C_M_NOSTART)) - val |= CR_CPU_RDY; + val |= WMTI2C_CR_CPU_RDY; if (pmsg->len == 1) - val |= CR_TX_NEXT_NO_ACK; + val |= WMTI2C_CR_TX_NEXT_NO_ACK; - writew(val, i2c_dev->base + REG_CR); + writew(val, i2c_dev->base + WMTI2C_REG_CR); reinit_completion(&i2c_dev->complete); - tcr_val |= TCR_MASTER_READ | (pmsg->addr & TCR_SLAVE_ADDR_MASK); + tcr_val |= WMTI2C_TCR_MASTER_READ | (pmsg->addr & WMTI2C_TCR_SLAVE_ADDR_MASK); - writew(tcr_val, i2c_dev->base + REG_TCR); + writew(tcr_val, i2c_dev->base + WMTI2C_REG_TCR); if (pmsg->flags & I2C_M_NOSTART) { - val = readw(i2c_dev->base + REG_CR); - val |= CR_CPU_RDY; - writew(val, i2c_dev->base + REG_CR); + val = readw(i2c_dev->base + WMTI2C_REG_CR); + val |= WMTI2C_CR_CPU_RDY; + writew(val, i2c_dev->base + WMTI2C_REG_CR); } while (xfer_len < pmsg->len) { @@ -225,13 +225,13 @@ static int wmt_i2c_read(struct wmt_i2c_dev *i2c_dev, struct i2c_msg *pmsg) if (ret) return ret; - pmsg->buf[xfer_len] = readw(i2c_dev->base + REG_CDR) >> 8; + pmsg->buf[xfer_len] = readw(i2c_dev->base + WMTI2C_REG_CDR) >> 8; xfer_len++; - val = readw(i2c_dev->base + REG_CR) | CR_CPU_RDY; + val = readw(i2c_dev->base + WMTI2C_REG_CR) | WMTI2C_CR_CPU_RDY; if (xfer_len == pmsg->len - 1) - val |= CR_TX_NEXT_NO_ACK; - writew(val, i2c_dev->base + REG_CR); + val |= WMTI2C_CR_TX_NEXT_NO_ACK; + writew(val, i2c_dev->base + WMTI2C_REG_CR); } return 0; @@ -278,8 +278,8 @@ static irqreturn_t wmt_i2c_isr(int irq, void *data) struct wmt_i2c_dev *i2c_dev = data; /* save the status and write-clear it */ - i2c_dev->cmd_status = readw(i2c_dev->base + REG_ISR); - writew(i2c_dev->cmd_status, i2c_dev->base + REG_ISR); + i2c_dev->cmd_status = readw(i2c_dev->base + WMTI2C_REG_ISR); + writew(i2c_dev->cmd_status, i2c_dev->base + WMTI2C_REG_ISR); complete(&i2c_dev->complete); @@ -335,18 +335,18 @@ static int wmt_i2c_reset_hardware(struct wmt_i2c_dev *i2c_dev) return err; } - writew(0, i2c_dev->base + REG_CR); - writew(MCR_APB_166M, i2c_dev->base + REG_MCR); - writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR); - writew(IMR_ENABLE_ALL, i2c_dev->base + REG_IMR); - writew(CR_ENABLE, i2c_dev->base + REG_CR); - readw(i2c_dev->base + REG_CSR); /* read clear */ - writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR); + writew(0, i2c_dev->base + WMTI2C_REG_CR); + writew(WMTI2C_MCR_APB_166M, i2c_dev->base + WMTI2C_REG_MCR); + writew(WMTI2C_ISR_WRITE_ALL, i2c_dev->base + WMTI2C_REG_ISR); + writew(WMTI2C_IMR_ENABLE_ALL, i2c_dev->base + WMTI2C_REG_IMR); + writew(WMTI2C_CR_ENABLE, i2c_dev->base + WMTI2C_REG_CR); + readw(i2c_dev->base + WMTI2C_REG_CSR); /* read clear */ + writew(WMTI2C_ISR_WRITE_ALL, i2c_dev->base + WMTI2C_REG_ISR); - if (i2c_dev->tcr == TCR_FAST_MODE) - writew(SCL_TIMEOUT(128) | TR_HS, i2c_dev->base + REG_TR); + if (i2c_dev->tcr == WMTI2C_TCR_FAST_MODE) + writew(WMTI2C_SCL_TIMEOUT(128) | WMTI2C_TR_HS, i2c_dev->base + WMTI2C_REG_TR); else - writew(SCL_TIMEOUT(128) | TR_STD, i2c_dev->base + REG_TR); + writew(WMTI2C_SCL_TIMEOUT(128) | WMTI2C_TR_STD, i2c_dev->base + WMTI2C_REG_TR); return 0; } @@ -371,7 +371,7 @@ static int wmt_i2c_probe(struct platform_device *pdev) err = of_property_read_u32(np, "clock-frequency", &clk_rate); if (!err && (clk_rate == I2C_MAX_FAST_MODE_FREQ)) - i2c_dev->tcr = TCR_FAST_MODE; + i2c_dev->tcr = WMTI2C_TCR_FAST_MODE; adap = &i2c_dev->adapter; i2c_set_adapdata(adap, i2c_dev); @@ -395,7 +395,7 @@ static void wmt_i2c_remove(struct platform_device *pdev) struct wmt_i2c_dev *i2c_dev = platform_get_drvdata(pdev); /* Disable interrupts, clock and delete adapter */ - writew(0, i2c_dev->base + REG_IMR); + writew(0, i2c_dev->base + WMTI2C_REG_IMR); clk_disable_unprepare(i2c_dev->clk); i2c_del_adapter(&i2c_dev->adapter); } From patchwork Thu Dec 28 03:17:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans Hu X-Patchwork-Id: 758901 Received: from mx2.zhaoxin.com (mx2.zhaoxin.com [203.110.167.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AAF743C16 for ; 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Thu, 28 Dec 2023 11:17:48 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.164 From: Hans Hu X-Barracuda-RBL-Trusted-Forwarder: 10.29.252.7 To: , CC: , , Subject: [PATCH v5 5/8] i2c: wmt: rename with prefix VIAI2C_ and viai2c_ Date: Thu, 28 Dec 2023 11:17:43 +0800 X-ASG-Orig-Subj: [PATCH v5 5/8] i2c: wmt: rename with prefix VIAI2C_ and viai2c_ Message-ID: <97b910b812f9e5e720f45fa776384f63c4f8da5c.1703733126.git.hanshu-oc@zhaoxin.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To ZXBJMBX03.zhaoxin.com (10.29.252.7) X-Barracuda-Connect: ZXSHMBX2.zhaoxin.com[10.28.252.164] X-Barracuda-Start-Time: 1703733469 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.36:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 14082 X-Barracuda-BRTS-Status: 0 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.118654 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- Since the I2C IP of both wmt and zhaoxin come from VIA. So, rename common register, function and variable's name to VIAI2C_ and viai2c_. Signed-off-by: Hans Hu --- drivers/i2c/busses/i2c-viai2c-common.c | 118 ++++++++++++------------- drivers/i2c/busses/i2c-viai2c-common.h | 60 ++++++------- drivers/i2c/busses/i2c-wmt-plt.c | 30 ++++--- 3 files changed, 105 insertions(+), 103 deletions(-) diff --git a/drivers/i2c/busses/i2c-viai2c-common.c b/drivers/i2c/busses/i2c-viai2c-common.c index 76058d6853a7..60a4d4ccaf12 100644 --- a/drivers/i2c/busses/i2c-viai2c-common.c +++ b/drivers/i2c/busses/i2c-viai2c-common.c @@ -2,15 +2,15 @@ #include #include "i2c-viai2c-common.h" -#define WMT_I2C_TIMEOUT (msecs_to_jiffies(1000)) +#define VIAI2C_TIMEOUT (msecs_to_jiffies(1000)) -static int wmt_i2c_wait_bus_not_busy(struct wmt_i2c *i2c) +static int viai2c_wait_bus_ready(struct viai2c *i2c) { unsigned long timeout; void __iomem *base = i2c->base; - timeout = jiffies + WMT_I2C_TIMEOUT; - while (!(readw(base + WMTI2C_REG_CSR) & WMTI2C_CSR_READY_MASK)) { + timeout = jiffies + VIAI2C_TIMEOUT; + while (!(readw(base + VIAI2C_REG_CSR) & VIAI2C_CSR_READY_MASK)) { if (time_after(jiffies, timeout)) { dev_warn(i2c->dev, "timeout waiting for bus ready\n"); @@ -22,7 +22,7 @@ static int wmt_i2c_wait_bus_not_busy(struct wmt_i2c *i2c) return 0; } -static int wmt_check_status(struct wmt_i2c *i2c) +static int viai2c_wait_status(struct viai2c *i2c) { int ret = 0; unsigned long wait_result; @@ -32,29 +32,29 @@ static int wmt_check_status(struct wmt_i2c *i2c) if (!wait_result) return -ETIMEDOUT; - if (i2c->cmd_status & WMTI2C_ISR_NACK_ADDR) + if (i2c->cmd_status & VIAI2C_ISR_NACK_ADDR) ret = -EIO; - if (i2c->cmd_status & WMTI2C_ISR_SCL_TIMEOUT) + if (i2c->cmd_status & VIAI2C_ISR_SCL_TIMEOUT) ret = -ETIMEDOUT; return ret; } -static irqreturn_t wmt_i2c_isr(int irq, void *data) +static irqreturn_t viai2c_isr(int irq, void *data) { - struct wmt_i2c *i2c = data; + struct viai2c *i2c = data; /* save the status and write-clear it */ - i2c->cmd_status = readw(i2c->base + WMTI2C_REG_ISR); - writew(i2c->cmd_status, i2c->base + WMTI2C_REG_ISR); + i2c->cmd_status = readw(i2c->base + VIAI2C_REG_ISR); + writew(i2c->cmd_status, i2c->base + VIAI2C_REG_ISR); complete(&i2c->complete); return IRQ_HANDLED; } -static int wmt_i2c_write(struct wmt_i2c *i2c, struct i2c_msg *pmsg, +static int viai2c_write(struct viai2c *i2c, struct i2c_msg *pmsg, int last) { u16 val, tcr_val = i2c->tcr; @@ -68,143 +68,143 @@ static int wmt_i2c_write(struct wmt_i2c *i2c, struct i2c_msg *pmsg, * start at -1 and break out early from the loop */ xfer_len = -1; - writew(0, base + WMTI2C_REG_CDR); + writew(0, base + VIAI2C_REG_CDR); } else { - writew(pmsg->buf[0] & 0xFF, base + WMTI2C_REG_CDR); + writew(pmsg->buf[0] & 0xFF, base + VIAI2C_REG_CDR); } if (!(pmsg->flags & I2C_M_NOSTART)) { - val = readw(base + WMTI2C_REG_CR); - val &= ~WMTI2C_CR_TX_END; - val |= WMTI2C_CR_CPU_RDY; - writew(val, base + WMTI2C_REG_CR); + val = readw(base + VIAI2C_REG_CR); + val &= ~VIAI2C_CR_TX_END; + val |= VIAI2C_CR_CPU_RDY; + writew(val, base + VIAI2C_REG_CR); } reinit_completion(&i2c->complete); - tcr_val |= (WMTI2C_TCR_MASTER_WRITE - | (pmsg->addr & WMTI2C_TCR_SLAVE_ADDR_MASK)); + tcr_val |= (VIAI2C_TCR_MASTER_WRITE + | (pmsg->addr & VIAI2C_TCR_SLAVE_ADDR_MASK)); - writew(tcr_val, base + WMTI2C_REG_TCR); + writew(tcr_val, base + VIAI2C_REG_TCR); if (pmsg->flags & I2C_M_NOSTART) { - val = readw(base + WMTI2C_REG_CR); - val |= WMTI2C_CR_CPU_RDY; - writew(val, base + WMTI2C_REG_CR); + val = readw(base + VIAI2C_REG_CR); + val |= VIAI2C_CR_CPU_RDY; + writew(val, base + VIAI2C_REG_CR); } while (xfer_len < pmsg->len) { - ret = wmt_check_status(i2c); + ret = viai2c_wait_status(i2c); if (ret) return ret; xfer_len++; - val = readw(base + WMTI2C_REG_CSR); - if (val & WMTI2C_CSR_RCV_NOT_ACK) { + val = readw(base + VIAI2C_REG_CSR); + if (val & VIAI2C_CSR_RCV_NOT_ACK) { dev_dbg(i2c->dev, "write RCV NACK error\n"); return -EIO; } if (pmsg->len == 0) { - val = WMTI2C_CR_TX_END | WMTI2C_CR_CPU_RDY - | WMTI2C_CR_ENABLE; - writew(val, base + WMTI2C_REG_CR); + val = VIAI2C_CR_TX_END | VIAI2C_CR_CPU_RDY + | VIAI2C_CR_ENABLE; + writew(val, base + VIAI2C_REG_CR); break; } if (xfer_len == pmsg->len) { if (last != 1) - writew(WMTI2C_CR_ENABLE, base + WMTI2C_REG_CR); + writew(VIAI2C_CR_ENABLE, base + VIAI2C_REG_CR); } else { writew(pmsg->buf[xfer_len] & 0xFF, - base + WMTI2C_REG_CDR); - writew(WMTI2C_CR_CPU_RDY | WMTI2C_CR_ENABLE, - base + WMTI2C_REG_CR); + base + VIAI2C_REG_CDR); + writew(VIAI2C_CR_CPU_RDY | VIAI2C_CR_ENABLE, + base + VIAI2C_REG_CR); } } return 0; } -static int wmt_i2c_read(struct wmt_i2c *i2c, struct i2c_msg *pmsg) +static int viai2c_read(struct viai2c *i2c, struct i2c_msg *pmsg) { u16 val, tcr_val = i2c->tcr; int ret; u32 xfer_len = 0; void __iomem *base = i2c->base; - val = readw(base + WMTI2C_REG_CR); - val &= ~(WMTI2C_CR_TX_END | WMTI2C_CR_TX_NEXT_NO_ACK); + val = readw(base + VIAI2C_REG_CR); + val &= ~(VIAI2C_CR_TX_END | VIAI2C_CR_RX_END); if (!(pmsg->flags & I2C_M_NOSTART)) - val |= WMTI2C_CR_CPU_RDY; + val |= VIAI2C_CR_CPU_RDY; if (pmsg->len == 1) - val |= WMTI2C_CR_TX_NEXT_NO_ACK; + val |= VIAI2C_CR_RX_END; - writew(val, base + WMTI2C_REG_CR); + writew(val, base + VIAI2C_REG_CR); reinit_completion(&i2c->complete); - tcr_val |= WMTI2C_TCR_MASTER_READ - | (pmsg->addr & WMTI2C_TCR_SLAVE_ADDR_MASK); + tcr_val |= VIAI2C_TCR_MASTER_READ + | (pmsg->addr & VIAI2C_TCR_SLAVE_ADDR_MASK); - writew(tcr_val, base + WMTI2C_REG_TCR); + writew(tcr_val, base + VIAI2C_REG_TCR); if (pmsg->flags & I2C_M_NOSTART) { - val = readw(base + WMTI2C_REG_CR); - val |= WMTI2C_CR_CPU_RDY; - writew(val, base + WMTI2C_REG_CR); + val = readw(base + VIAI2C_REG_CR); + val |= VIAI2C_CR_CPU_RDY; + writew(val, base + VIAI2C_REG_CR); } while (xfer_len < pmsg->len) { - ret = wmt_check_status(i2c); + ret = viai2c_wait_status(i2c); if (ret) return ret; - pmsg->buf[xfer_len] = readw(base + WMTI2C_REG_CDR) >> 8; + pmsg->buf[xfer_len] = readw(base + VIAI2C_REG_CDR) >> 8; xfer_len++; - val = readw(base + WMTI2C_REG_CR) | WMTI2C_CR_CPU_RDY; + val = readw(base + VIAI2C_REG_CR) | VIAI2C_CR_CPU_RDY; if (xfer_len == pmsg->len - 1) - val |= WMTI2C_CR_TX_NEXT_NO_ACK; - writew(val, base + WMTI2C_REG_CR); + val |= VIAI2C_CR_RX_END; + writew(val, base + VIAI2C_REG_CR); } return 0; } -int wmt_i2c_xfer(struct i2c_adapter *adap, +int viai2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) { struct i2c_msg *pmsg; int i; int ret = 0; - struct wmt_i2c *i2c = i2c_get_adapdata(adap); + struct viai2c *i2c = i2c_get_adapdata(adap); for (i = 0; ret >= 0 && i < num; i++) { pmsg = &msgs[i]; if (!(pmsg->flags & I2C_M_NOSTART)) { - ret = wmt_i2c_wait_bus_not_busy(i2c); + ret = viai2c_wait_bus_ready(i2c); if (ret < 0) return ret; } if (pmsg->flags & I2C_M_RD) - ret = wmt_i2c_read(i2c, pmsg); + ret = viai2c_read(i2c, pmsg); else - ret = wmt_i2c_write(i2c, pmsg, (i + 1) == num); + ret = viai2c_write(i2c, pmsg, (i + 1) == num); } return (ret < 0) ? ret : i; } -int wmt_i2c_init(struct platform_device *pdev, struct wmt_i2c **pi2c) +int viai2c_init(struct platform_device *pdev, struct viai2c **pi2c) { int err; - struct wmt_i2c *i2c; + struct viai2c *i2c; struct device_node *np = pdev->dev.of_node; i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); @@ -219,7 +219,7 @@ int wmt_i2c_init(struct platform_device *pdev, struct wmt_i2c **pi2c) if (!i2c->irq) return -EINVAL; - err = devm_request_irq(&pdev->dev, i2c->irq, wmt_i2c_isr, + err = devm_request_irq(&pdev->dev, i2c->irq, viai2c_isr, 0, pdev->name, i2c); if (err) return dev_err_probe(&pdev->dev, err, diff --git a/drivers/i2c/busses/i2c-viai2c-common.h b/drivers/i2c/busses/i2c-viai2c-common.h index e57da0dc68a5..f171f81e4d0f 100644 --- a/drivers/i2c/busses/i2c-viai2c-common.h +++ b/drivers/i2c/busses/i2c-viai2c-common.h @@ -12,44 +12,44 @@ #include /* REG_CR Bit fields */ -#define WMTI2C_REG_CR 0x00 -#define WMTI2C_CR_TX_NEXT_ACK 0x0000 -#define WMTI2C_CR_ENABLE 0x0001 -#define WMTI2C_CR_TX_NEXT_NO_ACK 0x0002 -#define WMTI2C_CR_TX_END 0x0004 -#define WMTI2C_CR_CPU_RDY 0x0008 +#define VIAI2C_REG_CR 0x00 +#define VIAI2C_CR_ENABLE BIT(0) +#define VIAI2C_CR_RX_END BIT(1) +#define VIAI2C_CR_TX_END BIT(2) +#define VIAI2C_CR_CPU_RDY BIT(3) +#define VIAI2C_CR_END_MASK GENMASK(2, 1) /* REG_TCR Bit fields */ -#define WMTI2C_REG_TCR 0x02 -#define WMTI2C_TCR_STANDARD_MODE 0x0000 -#define WMTI2C_TCR_MASTER_WRITE 0x0000 -#define WMTI2C_TCR_HS_MODE 0x2000 -#define WMTI2C_TCR_MASTER_READ 0x4000 -#define WMTI2C_TCR_FAST_MODE 0x8000 -#define WMTI2C_TCR_SLAVE_ADDR_MASK 0x007F +#define VIAI2C_REG_TCR 0x02 +#define VIAI2C_TCR_MASTER_WRITE 0x0000 +#define VIAI2C_TCR_HS_MODE BIT(13) +#define VIAI2C_TCR_MASTER_READ BIT(14) +#define VIAI2C_TCR_FAST BIT(15) +#define VIAI2C_TCR_SLAVE_ADDR_MASK GENMASK(6, 0) /* REG_CSR Bit fields */ -#define WMTI2C_REG_CSR 0x04 -#define WMTI2C_CSR_RCV_NOT_ACK 0x0001 -#define WMTI2C_CSR_RCV_ACK_MASK 0x0001 -#define WMTI2C_CSR_READY_MASK 0x0002 +#define VIAI2C_REG_CSR 0x04 +#define VIAI2C_CSR_RCV_NOT_ACK BIT(0) +#define VIAI2C_CSR_RCV_ACK_MASK BIT(0) +#define VIAI2C_CSR_READY_MASK BIT(1) /* REG_ISR Bit fields */ -#define WMTI2C_REG_ISR 0x06 -#define WMTI2C_ISR_NACK_ADDR 0x0001 -#define WMTI2C_ISR_BYTE_END 0x0002 -#define WMTI2C_ISR_SCL_TIMEOUT 0x0004 -#define WMTI2C_ISR_WRITE_ALL 0x0007 +#define VIAI2C_REG_ISR 0x06 +#define VIAI2C_ISR_NACK_ADDR BIT(0) +#define VIAI2C_ISR_BYTE_END BIT(1) +#define VIAI2C_ISR_SCL_TIMEOUT BIT(2) +#define VIAI2C_ISR_MASK_ALL GENMASK(2, 0) /* REG_IMR Bit fields */ -#define WMTI2C_REG_IMR 0x08 -#define WMTI2C_IMR_ENABLE_ALL 0x0007 +#define VIAI2C_REG_IMR 0x08 +#define VIAI2C_IMR_BYTE BIT(1) +#define VIAI2C_IMR_ENABLE_ALL GENMASK(2, 0) -#define WMTI2C_REG_CDR 0x0A -#define WMTI2C_REG_TR 0x0C -#define WMTI2C_REG_MCR 0x0E +#define VIAI2C_REG_CDR 0x0A +#define VIAI2C_REG_TR 0x0C +#define VIAI2C_REG_MCR 0x0E -struct wmt_i2c { +struct viai2c { struct i2c_adapter adapter; struct completion complete; struct device *dev; @@ -60,7 +60,7 @@ struct wmt_i2c { u16 cmd_status; }; -int wmt_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num); -int wmt_i2c_init(struct platform_device *pdev, struct wmt_i2c **pi2c); +int viai2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num); +int viai2c_init(struct platform_device *pdev, struct viai2c **pi2c); #endif diff --git a/drivers/i2c/busses/i2c-wmt-plt.c b/drivers/i2c/busses/i2c-wmt-plt.c index e0ffccf8a40a..8f506888cff7 100644 --- a/drivers/i2c/busses/i2c-wmt-plt.c +++ b/drivers/i2c/busses/i2c-wmt-plt.c @@ -22,13 +22,15 @@ #define WMTI2C_MCR_APB_96M 7 #define WMTI2C_MCR_APB_166M 12 +#define wmt_i2c viai2c + static u32 wmt_i2c_func(struct i2c_adapter *adap) { return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART; } static const struct i2c_algorithm wmt_i2c_algo = { - .master_xfer = wmt_i2c_xfer, + .master_xfer = viai2c_xfer, .functionality = wmt_i2c_func, }; @@ -50,18 +52,18 @@ static int wmt_i2c_reset_hardware(struct wmt_i2c *i2c) return err; } - writew(0, base + WMTI2C_REG_CR); - writew(WMTI2C_MCR_APB_166M, base + WMTI2C_REG_MCR); - writew(WMTI2C_ISR_WRITE_ALL, base + WMTI2C_REG_ISR); - writew(WMTI2C_IMR_ENABLE_ALL, base + WMTI2C_REG_IMR); - writew(WMTI2C_CR_ENABLE, base + WMTI2C_REG_CR); - readw(base + WMTI2C_REG_CSR); /* read clear */ - writew(WMTI2C_ISR_WRITE_ALL, base + WMTI2C_REG_ISR); + writew(0, base + VIAI2C_REG_CR); + writew(WMTI2C_MCR_APB_166M, base + VIAI2C_REG_MCR); + writew(VIAI2C_ISR_MASK_ALL, base + VIAI2C_REG_ISR); + writew(VIAI2C_IMR_ENABLE_ALL, base + VIAI2C_REG_IMR); + writew(VIAI2C_CR_ENABLE, base + VIAI2C_REG_CR); + readw(base + VIAI2C_REG_CSR); /* read clear */ + writew(VIAI2C_ISR_MASK_ALL, base + VIAI2C_REG_ISR); - if (i2c->tcr == WMTI2C_TCR_FAST_MODE) - writew(WMTI2C_SCL_TIMEOUT(128) | WMTI2C_TR_HS, base + WMTI2C_REG_TR); + if (i2c->tcr == VIAI2C_TCR_FAST) + writew(WMTI2C_SCL_TIMEOUT(128) | WMTI2C_TR_HS, base + VIAI2C_REG_TR); else - writew(WMTI2C_SCL_TIMEOUT(128) | WMTI2C_TR_STD, base + WMTI2C_REG_TR); + writew(WMTI2C_SCL_TIMEOUT(128) | WMTI2C_TR_STD, base + VIAI2C_REG_TR); return 0; } @@ -74,7 +76,7 @@ static int wmt_i2c_probe(struct platform_device *pdev) int err; u32 clk_rate; - err = wmt_i2c_init(pdev, &i2c); + err = viai2c_init(pdev, &i2c); if (err) return err; @@ -86,7 +88,7 @@ static int wmt_i2c_probe(struct platform_device *pdev) err = of_property_read_u32(np, "clock-frequency", &clk_rate); if (!err && (clk_rate == I2C_MAX_FAST_MODE_FREQ)) - i2c->tcr = WMTI2C_TCR_FAST_MODE; + i2c->tcr = VIAI2C_TCR_FAST; adap = &i2c->adapter; i2c_set_adapdata(adap, i2c); @@ -110,7 +112,7 @@ static void wmt_i2c_remove(struct platform_device *pdev) struct wmt_i2c *i2c = platform_get_drvdata(pdev); /* Disable interrupts, clock and delete adapter */ - writew(0, i2c->base + WMTI2C_REG_IMR); + writew(0, i2c->base + VIAI2C_REG_IMR); clk_disable_unprepare(i2c->clk); i2c_del_adapter(&i2c->adapter); } From patchwork Thu Dec 28 03:17:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans Hu X-Patchwork-Id: 758899 Received: from mx2.zhaoxin.com (mx2.zhaoxin.com [203.110.167.99]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 01D4F46A5 for ; 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Thu, 28 Dec 2023 11:17:49 +0800 X-Barracuda-RBL-Trusted-Forwarder: 10.28.252.164 From: Hans Hu X-Barracuda-RBL-Trusted-Forwarder: 10.29.252.7 To: , CC: , , Subject: [PATCH v5 7/8] i2c: wmt: add platform type VIAI2C_PLAT_WMT Date: Thu, 28 Dec 2023 11:17:45 +0800 X-ASG-Orig-Subj: [PATCH v5 7/8] i2c: wmt: add platform type VIAI2C_PLAT_WMT Message-ID: <1790ceacf479e31fdb6508307fcb1940199a52ab.1703733126.git.hanshu-oc@zhaoxin.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-i2c@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: zxbjmbx1.zhaoxin.com (10.29.252.163) To ZXBJMBX03.zhaoxin.com (10.29.252.7) X-Barracuda-Connect: ZXSHMBX2.zhaoxin.com[10.28.252.164] X-Barracuda-Start-Time: 1703733470 X-Barracuda-Encrypted: ECDHE-RSA-AES128-GCM-SHA256 X-Barracuda-URL: https://10.28.252.36:4443/cgi-mod/mark.cgi X-Virus-Scanned: by bsmtpd at zhaoxin.com X-Barracuda-Scan-Msg-Size: 5306 X-Barracuda-BRTS-Status: 0 X-Barracuda-Bayes: INNOCENT GLOBAL 0.0000 1.0000 -2.0210 X-Barracuda-Spam-Score: -2.02 X-Barracuda-Spam-Status: No, SCORE=-2.02 using global scores of TAG_LEVEL=1000.0 QUARANTINE_LEVEL=1000.0 KILL_LEVEL=9.0 tests= X-Barracuda-Spam-Report: Code version 3.2, rules version 3.2.3.118654 Rule breakdown below pts rule name description ---- ---------------------- -------------------------------------------------- Enumeration variables are added to differentiate between different platforms. Signed-off-by: Hans Hu --- drivers/i2c/busses/i2c-viai2c-common.c | 34 ++++++++++++++++---------- drivers/i2c/busses/i2c-viai2c-common.h | 7 +++++- drivers/i2c/busses/i2c-wmt-plt.c | 2 +- 3 files changed, 28 insertions(+), 15 deletions(-) diff --git a/drivers/i2c/busses/i2c-viai2c-common.c b/drivers/i2c/busses/i2c-viai2c-common.c index e5eca10efedc..930f4c5c1797 100644 --- a/drivers/i2c/busses/i2c-viai2c-common.c +++ b/drivers/i2c/busses/i2c-viai2c-common.c @@ -78,8 +78,7 @@ static irqreturn_t viai2c_isr(int irq, void *data) return IRQ_HANDLED; } -static int viai2c_write(struct viai2c *i2c, struct i2c_msg *pmsg, - int last) +static int viai2c_write(struct viai2c *i2c, struct i2c_msg *pmsg, bool last) { u16 val, tcr_val = i2c->tcr; int ret; @@ -97,7 +96,7 @@ static int viai2c_write(struct viai2c *i2c, struct i2c_msg *pmsg, writew(pmsg->buf[0] & 0xFF, base + VIAI2C_REG_CDR); } - if (!(pmsg->flags & I2C_M_NOSTART)) { + if (i2c->platform == VIAI2C_PLAT_WMT && !(pmsg->flags & I2C_M_NOSTART)) { val = readw(base + VIAI2C_REG_CR); val &= ~VIAI2C_CR_TX_END; val |= VIAI2C_CR_CPU_RDY; @@ -111,7 +110,7 @@ static int viai2c_write(struct viai2c *i2c, struct i2c_msg *pmsg, writew(tcr_val, base + VIAI2C_REG_TCR); - if (pmsg->flags & I2C_M_NOSTART) { + if (i2c->platform == VIAI2C_PLAT_WMT && pmsg->flags & I2C_M_NOSTART) { val = readw(base + VIAI2C_REG_CR); val |= VIAI2C_CR_CPU_RDY; writew(val, base + VIAI2C_REG_CR); @@ -138,7 +137,7 @@ static int viai2c_write(struct viai2c *i2c, struct i2c_msg *pmsg, } if (xfer_len == pmsg->len) { - if (last != 1) + if (i2c->platform == VIAI2C_PLAT_WMT && !last) writew(VIAI2C_CR_ENABLE, base + VIAI2C_REG_CR); } else { writew(pmsg->buf[xfer_len] & 0xFF, @@ -161,7 +160,7 @@ static int viai2c_read(struct viai2c *i2c, struct i2c_msg *pmsg) val = readw(base + VIAI2C_REG_CR); val &= ~(VIAI2C_CR_TX_END | VIAI2C_CR_RX_END); - if (!(pmsg->flags & I2C_M_NOSTART)) + if (i2c->platform == VIAI2C_PLAT_WMT && !(pmsg->flags & I2C_M_NOSTART)) val |= VIAI2C_CR_CPU_RDY; if (pmsg->len == 1) @@ -176,7 +175,7 @@ static int viai2c_read(struct viai2c *i2c, struct i2c_msg *pmsg) writew(tcr_val, base + VIAI2C_REG_TCR); - if (pmsg->flags & I2C_M_NOSTART) { + if (i2c->platform == VIAI2C_PLAT_WMT && (pmsg->flags & I2C_M_NOSTART)) { val = readw(base + VIAI2C_REG_CR); val |= VIAI2C_CR_CPU_RDY; writew(val, base + VIAI2C_REG_CR); @@ -211,7 +210,8 @@ int viai2c_xfer(struct i2c_adapter *adap, i2c->to = i2c->ti = ktime_get(); for (i = 0; ret >= 0 && i < num; i++) { pmsg = &msgs[i]; - if (!(pmsg->flags & I2C_M_NOSTART)) { + if ((i2c->platform == VIAI2C_PLAT_WMT) + && !(pmsg->flags & I2C_M_NOSTART)) { ret = viai2c_wait_bus_ready(i2c); if (ret < 0) return ret; @@ -226,9 +226,10 @@ int viai2c_xfer(struct i2c_adapter *adap, return (ret < 0) ? ret : i; } -int viai2c_init(struct platform_device *pdev, struct viai2c **pi2c) +int viai2c_init(struct platform_device *pdev, struct viai2c **pi2c, int plat) { int err; + int irq_flags; struct viai2c *i2c; struct device_node *np = pdev->dev.of_node; @@ -240,12 +241,19 @@ int viai2c_init(struct platform_device *pdev, struct viai2c **pi2c) if (IS_ERR(i2c->base)) return PTR_ERR(i2c->base); - i2c->irq = irq_of_parse_and_map(np, 0); - if (!i2c->irq) - return -EINVAL; + if (plat == VIAI2C_PLAT_WMT) { + irq_flags = 0; + i2c->irq = irq_of_parse_and_map(np, 0); + if (!i2c->irq) + return -EINVAL; + } else + return dev_err_probe(&pdev->dev, -EINVAL, + "wrong platform type\n"); + + i2c->platform = plat; err = devm_request_irq(&pdev->dev, i2c->irq, viai2c_isr, - 0, pdev->name, i2c); + irq_flags, pdev->name, i2c); if (err) return dev_err_probe(&pdev->dev, err, "failed to request irq %i\n", i2c->irq); diff --git a/drivers/i2c/busses/i2c-viai2c-common.h b/drivers/i2c/busses/i2c-viai2c-common.h index 73a88398d763..6d210e562c9a 100644 --- a/drivers/i2c/busses/i2c-viai2c-common.h +++ b/drivers/i2c/busses/i2c-viai2c-common.h @@ -49,6 +49,10 @@ #define VIAI2C_REG_TR 0x0C #define VIAI2C_REG_MCR 0x0E +enum { + VIAI2C_PLAT_WMT = 1, +}; + struct viai2c { struct i2c_adapter adapter; struct completion complete; @@ -60,9 +64,10 @@ struct viai2c { u16 cmd_status; ktime_t ti; ktime_t to; + int platform; }; int viai2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num); -int viai2c_init(struct platform_device *pdev, struct viai2c **pi2c); +int viai2c_init(struct platform_device *pdev, struct viai2c **pi2c, int plat); #endif diff --git a/drivers/i2c/busses/i2c-wmt-plt.c b/drivers/i2c/busses/i2c-wmt-plt.c index 8f506888cff7..6afb830eeb40 100644 --- a/drivers/i2c/busses/i2c-wmt-plt.c +++ b/drivers/i2c/busses/i2c-wmt-plt.c @@ -76,7 +76,7 @@ static int wmt_i2c_probe(struct platform_device *pdev) int err; u32 clk_rate; - err = viai2c_init(pdev, &i2c); + err = viai2c_init(pdev, &i2c, VIAI2C_PLAT_WMT); if (err) return err;