From patchwork Wed Dec 27 12:32:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elad Nachman X-Patchwork-Id: 759190 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37CCF4500F; Wed, 27 Dec 2023 12:34:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.helo=mx0b-0016f401.pphosted.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="VyiuF+oU" Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BRBbPl7031722; Wed, 27 Dec 2023 04:33:19 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=rUWlKryEb22Hs4Pknbtj0KZ4rivmTLmOvfofmKYCJ9o=; b=Vyi uF+oUPZC+qUgsRhR/le+I78BIrbelkEo0GthVIXDcaVEgLGy8o9TKny0f4FvsiPC fRXk86vamOopjPBRdanT5rIOvnB9tWHBUkN7wn3yWhpTs8pPsZ98HtYdKUxiZ1WS 9eLF8QHNJitRKeBMFVUFKX46FxPzbDWM4loD7/ev7L1iAjnV/Po22dJctMrfc6tX xL2EsFWP1RqVzHolQFYo662DenTpyG5IrFxV5p8E+h2ObevvDgzMC8iHkwYm073f kY+RUnRjfyOUe8myrgYO1CgEHsXiBVJRVAPt8gAXFi4W95Ce4qZZmMn5txQlxs4Q phWCXJSLXnKe/AWKHUg== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3v5yxp0a5g-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 27 Dec 2023 04:33:14 -0800 (PST) Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 27 Dec 2023 04:33:12 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 27 Dec 2023 04:33:12 -0800 Received: from dc3lp-swdev041.marvell.com (dc3lp-swdev041.marvell.com [10.6.60.191]) by maili.marvell.com (Postfix) with ESMTP id 59C6C5B693A; Wed, 27 Dec 2023 04:33:06 -0800 (PST) From: Elad Nachman To: , , , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH 1/4] arm64: mm: Fix SOCs with DDR starting above zero Date: Wed, 27 Dec 2023 14:32:54 +0200 Message-ID: <20231227123257.1170590-2-enachman@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231227123257.1170590-1-enachman@marvell.com> References: <20231227123257.1170590-1-enachman@marvell.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: uF-9YZtNEMKWZTs9-yyi1S6OtB64HJik X-Proofpoint-GUID: uF-9YZtNEMKWZTs9-yyi1S6OtB64HJik X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 From: Elad Nachman Some SOCs, like the Marvell AC5/X/IM, have a combination of DDR starting at 0x2_0000_0000 coupled with DMA controllers limited to 31 and 32 bit of addressing. This requires to properly arrange ZONE_DMA and ZONE_DMA32 for these SOCs, so swiotlb and coherent DMA allocation would work properly. Change initialization so device tree dma zone bits are taken as function of offset from DRAM start, and when calculating the maximal zone physical RAM address for physical DDR starting above 32-bit, combine the physical address start plus the zone mask passed as parameter. This creates the proper zone splitting for these SOCs: 0..2GB for ZONE_DMA 2GB..4GB for ZONE_DMA32 4GB..8GB for ZONE_NORMAL Signed-off-by: Elad Nachman --- arch/arm64/mm/init.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c index 74c1db8ce271..8288c778916e 100644 --- a/arch/arm64/mm/init.c +++ b/arch/arm64/mm/init.c @@ -115,20 +115,21 @@ static void __init arch_reserve_crashkernel(void) /* * Return the maximum physical address for a zone accessible by the given bits - * limit. If DRAM starts above 32-bit, expand the zone to the maximum - * available memory, otherwise cap it at 32-bit. + * limit. If DRAM starts above 32-bit, expand the zone to the available memory + * start limited by the zone bits mask, otherwise cap it at 32-bit. */ static phys_addr_t __init max_zone_phys(unsigned int zone_bits) { phys_addr_t zone_mask = DMA_BIT_MASK(zone_bits); phys_addr_t phys_start = memblock_start_of_DRAM(); + phys_addr_t phys_end = memblock_end_of_DRAM(); if (phys_start > U32_MAX) - zone_mask = PHYS_ADDR_MAX; + zone_mask = phys_start | zone_mask; else if (phys_start > zone_mask) zone_mask = U32_MAX; - return min(zone_mask, memblock_end_of_DRAM() - 1) + 1; + return min(zone_mask, phys_end - 1) + 1; } static void __init zone_sizes_init(void) @@ -140,7 +141,16 @@ static void __init zone_sizes_init(void) #ifdef CONFIG_ZONE_DMA acpi_zone_dma_bits = fls64(acpi_iort_dma_get_max_cpu_address()); - dt_zone_dma_bits = fls64(of_dma_get_max_cpu_address(NULL)); + /* + * When calculating the dma zone bits from the device tree, subtract + * the DRAM start address, in case it does not start from address + * zero. This way. we pass only the zone size related bits to + * max_zone_phys(), which will add them to the base of the DRAM. + * This prevents miscalculations on arm64 SOCs which combines + * DDR starting above 4GB with memory controllers limited to + * 32-bits or less: + */ + dt_zone_dma_bits = fls64(of_dma_get_max_cpu_address(NULL) - memblock_start_of_DRAM()); zone_dma_bits = min3(32U, dt_zone_dma_bits, acpi_zone_dma_bits); arm64_dma_phys_limit = max_zone_phys(zone_dma_bits); max_zone_pfns[ZONE_DMA] = PFN_DOWN(arm64_dma_phys_limit); From patchwork Wed Dec 27 12:32:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elad Nachman X-Patchwork-Id: 759191 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 256BF45001; Wed, 27 Dec 2023 12:34:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 27 Dec 2023 04:33:20 -0800 (PST) Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Wed, 27 Dec 2023 04:33:18 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 27 Dec 2023 04:33:17 -0800 Received: from dc3lp-swdev041.marvell.com (dc3lp-swdev041.marvell.com [10.6.60.191]) by maili.marvell.com (Postfix) with ESMTP id E8A515B6937; Wed, 27 Dec 2023 04:33:11 -0800 (PST) From: Elad Nachman To: , , , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH 2/4] dt-bindings: mmc: add Marvell ac5 Date: Wed, 27 Dec 2023 14:32:55 +0200 Message-ID: <20231227123257.1170590-3-enachman@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231227123257.1170590-1-enachman@marvell.com> References: <20231227123257.1170590-1-enachman@marvell.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: GCD9rNl3OXNNyd3NGLlHc9V8yELlGl5x X-Proofpoint-GUID: GCD9rNl3OXNNyd3NGLlHc9V8yELlGl5x X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 From: Elad Nachman Add dt bindings for Marvell ac5 eMMC controller Signed-off-by: Elad Nachman --- Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml index 3a8e74894ae0..50c6de8bf0bc 100644 --- a/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/marvell,xenon-sdhci.yaml @@ -34,6 +34,9 @@ properties: - const: marvell,armada-3700-sdhci - const: marvell,sdhci-xenon + - items: + - const: marvell,ac5-sdhci + - const: marvell,armada-ap806-sdhci reg: minItems: 1 maxItems: 2 From patchwork Wed Dec 27 12:32:56 2023 Content-Type: text/plain; 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Wed, 27 Dec 2023 04:33:23 -0800 Received: from dc3lp-swdev041.marvell.com (dc3lp-swdev041.marvell.com [10.6.60.191]) by maili.marvell.com (Postfix) with ESMTP id 8D8165B6933; Wed, 27 Dec 2023 04:33:17 -0800 (PST) From: Elad Nachman To: , , , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH 3/4] arm64: dts: ac5: add mmc node and clock Date: Wed, 27 Dec 2023 14:32:56 +0200 Message-ID: <20231227123257.1170590-4-enachman@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231227123257.1170590-1-enachman@marvell.com> References: <20231227123257.1170590-1-enachman@marvell.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: ewsmlGZgsY4Tm6ZHwAxGaGZEcgmGdzFE X-Proofpoint-GUID: ewsmlGZgsY4Tm6ZHwAxGaGZEcgmGdzFE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 From: Elad Nachman Add mmc and mmc clock nodes to ac5 and ac5x device tree files Signed-off-by: Elad Nachman --- arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 33 ++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi index b5e042b8e929..decad14d0db8 100644 --- a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi @@ -77,7 +77,6 @@ soc { #address-cells = <2>; #size-cells = <2>; ranges; - dma-ranges; internal-regs@7f000000 { #address-cells = <1>; @@ -204,6 +203,31 @@ gpio1: gpio@18140 { }; }; + mmc_dma: mmc-dma-peripherals@80500000 { + compatible = "simple-bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + dma-ranges = <0x0 0x0 0x2 0x0 0x0 0x80000000>; + dma-coherent; + + sdhci: mmc@805c0000 { + compatible = "marvell,ac5-sdhci", + "marvell,armada-ap806-sdhci"; + reg = <0x0 0x805c0000 0x0 0x1000>; + interrupts = ; + clocks = <&emmc_clock>, <&cnm_clock>; + clock-names = "core", "axi"; + status = "okay"; + bus-width = <8>; + /*marvell,xenon-phy-slow-mode;*/ + non-removable; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + }; + }; + /* * Dedicated section for devices behind 32bit controllers so we * can configure specific DMA mapping for them @@ -335,5 +359,12 @@ nand_clock: nand-clock { #clock-cells = <0>; clock-frequency = <400000000>; }; + + emmc_clock: emmc_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; + }; }; From patchwork Wed Dec 27 12:32:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elad Nachman X-Patchwork-Id: 758550 Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37C9D4500E; Wed, 27 Dec 2023 12:34:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.helo=mx0b-0016f401.pphosted.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="WckRmBnm" Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BQMrU8r004230; Wed, 27 Dec 2023 04:33:31 -0800 DKIM-Signature: v=1; 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Wed, 27 Dec 2023 04:33:29 -0800 Received: from dc3lp-swdev041.marvell.com (dc3lp-swdev041.marvell.com [10.6.60.191]) by maili.marvell.com (Postfix) with ESMTP id 27EC95B6936; Wed, 27 Dec 2023 04:33:22 -0800 (PST) From: Elad Nachman To: , , , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH 4/4] mmc: xenon: Add ac5 support via bounce buffer Date: Wed, 27 Dec 2023 14:32:57 +0200 Message-ID: <20231227123257.1170590-5-enachman@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231227123257.1170590-1-enachman@marvell.com> References: <20231227123257.1170590-1-enachman@marvell.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: aBy5T6LeTda5mzPy40wZXafzn84gvjX4 X-Proofpoint-GUID: aBy5T6LeTda5mzPy40wZXafzn84gvjX4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 From: Elad Nachman AC5/X/IM SOCs has a variant of the Xenon eMMC controller, in which only 31-bit of addressing pass from the controller on the AXI bus. Since we cannot guarantee that only buffers from the first 2GB of memory will reach the driver, the driver is configured for SDMA mode, without 64-bit mode, overriding the DMA mask to 34-bit to support the DDR memory mapping, which starts at offset 8GB. Signed-off-by: Elad Nachman Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-xenon.c | 33 ++++++++++++++++++++++++++++++++- drivers/mmc/host/sdhci-xenon.h | 3 ++- 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci-xenon.c b/drivers/mmc/host/sdhci-xenon.c index 25ba7aecc3be..4d6df1815da1 100644 --- a/drivers/mmc/host/sdhci-xenon.c +++ b/drivers/mmc/host/sdhci-xenon.c @@ -18,6 +18,8 @@ #include #include #include +#include +#include #include "sdhci-pltfm.h" #include "sdhci-xenon.h" @@ -422,6 +424,7 @@ static int xenon_probe_params(struct platform_device *pdev) struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); u32 sdhc_id, nr_sdhc; u32 tuning_count; + struct sysinfo si; /* Disable HS200 on Armada AP806 */ if (priv->hw_version == XENON_AP806) @@ -450,6 +453,23 @@ static int xenon_probe_params(struct platform_device *pdev) } priv->tuning_count = tuning_count; + /* + * AC5/X/IM HW has only 31-bits passed in the crossbar switch. + * If we have more than 2GB of memory, this means we might pass + * memory pointers which are above 2GB and which cannot be properly + * represented. In this case, disable ADMA, 64-bit DMA and allow only SDMA. + * This effectively will enable bounce buffer quirk in the + * generic SDHCI driver, which will make sure DMA is only done + * from supported memory regions: + */ + if (priv->hw_version == XENON_AC5) { + si_meminfo(&si); + if (si.totalram * si.mem_unit > SZ_2G) { + host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; + host->quirks2 |= SDHCI_QUIRK2_BROKEN_64_BIT_DMA; + } + } + return xenon_phy_parse_params(dev, host); } @@ -562,7 +582,17 @@ static int xenon_probe(struct platform_device *pdev) goto remove_sdhc; pm_runtime_put_autosuspend(&pdev->dev); - + /* + * If we previously detected AC5 with over 2GB of memory, + * then we disable ADMA and 64-bit DMA. + * This means generic SDHCI driver has set the DMA mask to + * 32-bit. Since DDR starts at 0x2_0000_0000, we must use + * 34-bit DMA mask to access this DDR memory: + */ + if (priv->hw_version == XENON_AC5) { + if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA) + dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(34)); + } return 0; remove_sdhc: @@ -680,6 +710,7 @@ static const struct of_device_id sdhci_xenon_dt_ids[] = { { .compatible = "marvell,armada-ap807-sdhci", .data = (void *)XENON_AP807}, { .compatible = "marvell,armada-cp110-sdhci", .data = (void *)XENON_CP110}, { .compatible = "marvell,armada-3700-sdhci", .data = (void *)XENON_A3700}, + { .compatible = "marvell,ac5-sdhci", .data = (void *)XENON_AC5}, {} }; MODULE_DEVICE_TABLE(of, sdhci_xenon_dt_ids); diff --git a/drivers/mmc/host/sdhci-xenon.h b/drivers/mmc/host/sdhci-xenon.h index 3e9c6c908a79..0460d97aad26 100644 --- a/drivers/mmc/host/sdhci-xenon.h +++ b/drivers/mmc/host/sdhci-xenon.h @@ -57,7 +57,8 @@ enum xenon_variant { XENON_A3700, XENON_AP806, XENON_AP807, - XENON_CP110 + XENON_CP110, + XENON_AC5 }; struct xenon_priv {