From patchwork Tue Dec 26 05:38:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: JeeHeng Sia X-Patchwork-Id: 758438 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D56464B14C; Tue, 26 Dec 2023 05:39:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=starfivetech.com Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 50DBD24E28B; Tue, 26 Dec 2023 13:39:16 +0800 (CST) Received: from EXMBX066.cuchost.com (172.16.7.66) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 26 Dec 2023 13:39:16 +0800 Received: from jsia-virtual-machine.localdomain (202.188.176.82) by EXMBX066.cuchost.com (172.16.6.66) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 26 Dec 2023 13:39:10 +0800 From: Sia Jee Heng To: , , , , , , , , , , , , CC: , , , , , Subject: [RFC 02/16] reset: starfive: Convert the word "jh71x0" to "starfive" Date: Tue, 26 Dec 2023 13:38:34 +0800 Message-ID: <20231226053848.25089-3-jeeheng.sia@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231226053848.25089-1-jeeheng.sia@starfivetech.com> References: <20231226053848.25089-1-jeeheng.sia@starfivetech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX066.cuchost.com (172.16.6.66) X-YovoleRuleAgent: yovoleflag Function names that consist of the 'jh71x0' naming convention are renamed to use the 'starfive' wording. Signed-off-by: Sia Jee Heng Reviewed-by: Ley Foon Tan Reviewed-by: Emil Renner Berthing --- .../clk/starfive/clk-starfive-jh7110-sys.c | 4 +- .../reset/starfive/reset-starfive-common.c | 64 +++++++++---------- .../reset/starfive/reset-starfive-common.h | 8 +-- .../reset/starfive/reset-starfive-jh7100.c | 2 +- .../reset/starfive/reset-starfive-jh7110.c | 4 +- include/soc/starfive/reset-starfive-common.h | 6 +- 6 files changed, 44 insertions(+), 44 deletions(-) diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c index 6e45c580c9ba..e63353c70209 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c @@ -345,7 +345,7 @@ static void jh7110_reset_unregister_adev(void *_adev) static void jh7110_reset_adev_release(struct device *dev) { struct auxiliary_device *adev = to_auxiliary_dev(dev); - struct jh71x0_reset_adev *rdev = to_jh71x0_reset_adev(adev); + struct starfive_reset_adev *rdev = to_starfive_reset_adev(adev); kfree(rdev); } @@ -354,7 +354,7 @@ int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv, const char *adev_name, u32 adev_id) { - struct jh71x0_reset_adev *rdev; + struct starfive_reset_adev *rdev; struct auxiliary_device *adev; int ret; diff --git a/drivers/reset/starfive/reset-starfive-common.c b/drivers/reset/starfive/reset-starfive-common.c index dab454e46bbf..8d8dec9e5d7a 100644 --- a/drivers/reset/starfive/reset-starfive-common.c +++ b/drivers/reset/starfive/reset-starfive-common.c @@ -14,7 +14,7 @@ #include "reset-starfive-common.h" -struct jh71x0_reset { +struct starfive_reset { struct reset_controller_dev rcdev; /* protect registers against concurrent read-modify-write */ spinlock_t lock; @@ -23,16 +23,16 @@ struct jh71x0_reset { const u32 *asserted; }; -static inline struct jh71x0_reset * -jh71x0_reset_from(struct reset_controller_dev *rcdev) +static inline struct starfive_reset * +starfive_reset_from(struct reset_controller_dev *rcdev) { - return container_of(rcdev, struct jh71x0_reset, rcdev); + return container_of(rcdev, struct starfive_reset, rcdev); } -static int jh71x0_reset_update(struct reset_controller_dev *rcdev, - unsigned long id, bool assert) +static int starfive_reset_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) { - struct jh71x0_reset *data = jh71x0_reset_from(rcdev); + struct starfive_reset *data = starfive_reset_from(rcdev); unsigned long offset = id / 32; u32 mask = BIT(id % 32); void __iomem *reg_assert = data->assert + offset * sizeof(u32); @@ -61,34 +61,34 @@ static int jh71x0_reset_update(struct reset_controller_dev *rcdev, return ret; } -static int jh71x0_reset_assert(struct reset_controller_dev *rcdev, - unsigned long id) +static int starfive_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) { - return jh71x0_reset_update(rcdev, id, true); + return starfive_reset_update(rcdev, id, true); } -static int jh71x0_reset_deassert(struct reset_controller_dev *rcdev, - unsigned long id) +static int starfive_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) { - return jh71x0_reset_update(rcdev, id, false); + return starfive_reset_update(rcdev, id, false); } -static int jh71x0_reset_reset(struct reset_controller_dev *rcdev, - unsigned long id) +static int starfive_reset_reset(struct reset_controller_dev *rcdev, + unsigned long id) { int ret; - ret = jh71x0_reset_assert(rcdev, id); + ret = starfive_reset_assert(rcdev, id); if (ret) return ret; - return jh71x0_reset_deassert(rcdev, id); + return starfive_reset_deassert(rcdev, id); } -static int jh71x0_reset_status(struct reset_controller_dev *rcdev, - unsigned long id) +static int starfive_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) { - struct jh71x0_reset *data = jh71x0_reset_from(rcdev); + struct starfive_reset *data = starfive_reset_from(rcdev); unsigned long offset = id / 32; u32 mask = BIT(id % 32); void __iomem *reg_status = data->status + offset * sizeof(u32); @@ -97,25 +97,25 @@ static int jh71x0_reset_status(struct reset_controller_dev *rcdev, return !((value ^ data->asserted[offset]) & mask); } -static const struct reset_control_ops jh71x0_reset_ops = { - .assert = jh71x0_reset_assert, - .deassert = jh71x0_reset_deassert, - .reset = jh71x0_reset_reset, - .status = jh71x0_reset_status, +static const struct reset_control_ops starfive_reset_ops = { + .assert = starfive_reset_assert, + .deassert = starfive_reset_deassert, + .reset = starfive_reset_reset, + .status = starfive_reset_status, }; -int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node, - void __iomem *assert, void __iomem *status, - const u32 *asserted, unsigned int nr_resets, - struct module *owner) +int reset_starfive_register(struct device *dev, struct device_node *of_node, + void __iomem *assert, void __iomem *status, + const u32 *asserted, unsigned int nr_resets, + struct module *owner) { - struct jh71x0_reset *data; + struct starfive_reset *data; data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); if (!data) return -ENOMEM; - data->rcdev.ops = &jh71x0_reset_ops; + data->rcdev.ops = &starfive_reset_ops; data->rcdev.owner = owner; data->rcdev.nr_resets = nr_resets; data->rcdev.dev = dev; @@ -128,4 +128,4 @@ int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_no return devm_reset_controller_register(dev, &data->rcdev); } -EXPORT_SYMBOL_GPL(reset_starfive_jh71x0_register); +EXPORT_SYMBOL_GPL(reset_starfive_register); diff --git a/drivers/reset/starfive/reset-starfive-common.h b/drivers/reset/starfive/reset-starfive-common.h index 266acc4b2caf..83461b22ee55 100644 --- a/drivers/reset/starfive/reset-starfive-common.h +++ b/drivers/reset/starfive/reset-starfive-common.h @@ -6,9 +6,9 @@ #ifndef __RESET_STARFIVE_COMMON_H #define __RESET_STARFIVE_COMMON_H -int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node, - void __iomem *assert, void __iomem *status, - const u32 *asserted, unsigned int nr_resets, - struct module *owner); +int reset_starfive_register(struct device *dev, struct device_node *of_node, + void __iomem *assert, void __iomem *status, + const u32 *asserted, unsigned int nr_resets, + struct module *owner); #endif /* __RESET_STARFIVE_COMMON_H */ diff --git a/drivers/reset/starfive/reset-starfive-jh7100.c b/drivers/reset/starfive/reset-starfive-jh7100.c index 546dea2e5811..122ac6c3893b 100644 --- a/drivers/reset/starfive/reset-starfive-jh7100.c +++ b/drivers/reset/starfive/reset-starfive-jh7100.c @@ -51,7 +51,7 @@ static int __init jh7100_reset_probe(struct platform_device *pdev) if (IS_ERR(base)) return PTR_ERR(base); - return reset_starfive_jh71x0_register(&pdev->dev, pdev->dev.of_node, + return reset_starfive_register(&pdev->dev, pdev->dev.of_node, base + JH7100_RESET_ASSERT0, base + JH7100_RESET_STATUS0, jh7100_reset_asserted, diff --git a/drivers/reset/starfive/reset-starfive-jh7110.c b/drivers/reset/starfive/reset-starfive-jh7110.c index 87dba01491ae..c4dd21761e53 100644 --- a/drivers/reset/starfive/reset-starfive-jh7110.c +++ b/drivers/reset/starfive/reset-starfive-jh7110.c @@ -53,13 +53,13 @@ static int jh7110_reset_probe(struct auxiliary_device *adev, const struct auxiliary_device_id *id) { struct jh7110_reset_info *info = (struct jh7110_reset_info *)(id->driver_data); - struct jh71x0_reset_adev *rdev = to_jh71x0_reset_adev(adev); + struct starfive_reset_adev *rdev = to_starfive_reset_adev(adev); void __iomem *base = rdev->base; if (!info || !base) return -ENODEV; - return reset_starfive_jh71x0_register(&adev->dev, adev->dev.parent->of_node, + return reset_starfive_register(&adev->dev, adev->dev.parent->of_node, base + info->assert_offset, base + info->status_offset, NULL, diff --git a/include/soc/starfive/reset-starfive-common.h b/include/soc/starfive/reset-starfive-common.h index 56d8f413cf18..16df46a074bc 100644 --- a/include/soc/starfive/reset-starfive-common.h +++ b/include/soc/starfive/reset-starfive-common.h @@ -6,12 +6,12 @@ #include #include -struct jh71x0_reset_adev { +struct starfive_reset_adev { void __iomem *base; struct auxiliary_device adev; }; -#define to_jh71x0_reset_adev(_adev) \ - container_of((_adev), struct jh71x0_reset_adev, adev) +#define to_starfive_reset_adev(_adev) \ + container_of((_adev), struct starfive_reset_adev, adev) #endif From patchwork Tue Dec 26 05:38:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: JeeHeng Sia X-Patchwork-Id: 758437 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 340CC4C3DE; Tue, 26 Dec 2023 05:39:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=starfivetech.com Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 1445824E29A; Tue, 26 Dec 2023 13:39:30 +0800 (CST) Received: from EXMBX066.cuchost.com (172.16.7.66) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 26 Dec 2023 13:39:29 +0800 Received: from jsia-virtual-machine.localdomain (202.188.176.82) by EXMBX066.cuchost.com (172.16.6.66) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 26 Dec 2023 13:39:23 +0800 From: Sia Jee Heng To: , , , , , , , , , , , , CC: , , , , , Subject: [RFC 04/16] clk: starfive: Convert the word "jh71x0" to "starfive" Date: Tue, 26 Dec 2023 13:38:36 +0800 Message-ID: <20231226053848.25089-5-jeeheng.sia@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231226053848.25089-1-jeeheng.sia@starfivetech.com> References: <20231226053848.25089-1-jeeheng.sia@starfivetech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX066.cuchost.com (172.16.6.66) X-YovoleRuleAgent: yovoleflag Function names that consist of the 'jh71x0' naming convention are renamed to use the 'starfive' wording. Signed-off-by: Sia Jee Heng Reviewed-by: Ley Foon Tan Reviewed-by: Emil Renner Berthing --- drivers/clk/starfive/clk-starfive-common.c | 290 +++++----- drivers/clk/starfive/clk-starfive-common.h | 68 +-- .../clk/starfive/clk-starfive-jh7100-audio.c | 125 ++--- drivers/clk/starfive/clk-starfive-jh7100.c | 501 ++++++++--------- .../clk/starfive/clk-starfive-jh7110-aon.c | 62 +-- .../clk/starfive/clk-starfive-jh7110-isp.c | 72 +-- .../clk/starfive/clk-starfive-jh7110-stg.c | 94 ++-- .../clk/starfive/clk-starfive-jh7110-sys.c | 517 +++++++++--------- .../clk/starfive/clk-starfive-jh7110-vout.c | 74 +-- drivers/clk/starfive/clk-starfive-jh7110.h | 2 +- 10 files changed, 908 insertions(+), 897 deletions(-) diff --git a/drivers/clk/starfive/clk-starfive-common.c b/drivers/clk/starfive/clk-starfive-common.c index a12490c97957..fd608286ca13 100644 --- a/drivers/clk/starfive/clk-starfive-common.c +++ b/drivers/clk/starfive/clk-starfive-common.c @@ -12,27 +12,27 @@ #include "clk-starfive-common.h" -static struct jh71x0_clk *jh71x0_clk_from(struct clk_hw *hw) +static struct starfive_clk *starfive_clk_from(struct clk_hw *hw) { - return container_of(hw, struct jh71x0_clk, hw); + return container_of(hw, struct starfive_clk, hw); } -static struct jh71x0_clk_priv *jh71x0_priv_from(struct jh71x0_clk *clk) +static struct starfive_clk_priv *starfive_priv_from(struct starfive_clk *clk) { - return container_of(clk, struct jh71x0_clk_priv, reg[clk->idx]); + return container_of(clk, struct starfive_clk_priv, reg[clk->idx]); } -static u32 jh71x0_clk_reg_get(struct jh71x0_clk *clk) +static u32 starfive_clk_reg_get(struct starfive_clk *clk) { - struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk); + struct starfive_clk_priv *priv = starfive_priv_from(clk); void __iomem *reg = priv->base + 4 * clk->idx; return readl_relaxed(reg); } -static void jh71x0_clk_reg_rmw(struct jh71x0_clk *clk, u32 mask, u32 value) +static void starfive_clk_reg_rmw(struct starfive_clk *clk, u32 mask, u32 value) { - struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk); + struct starfive_clk_priv *priv = starfive_priv_from(clk); void __iomem *reg = priv->base + 4 * clk->idx; unsigned long flags; @@ -42,41 +42,41 @@ static void jh71x0_clk_reg_rmw(struct jh71x0_clk *clk, u32 mask, u32 value) spin_unlock_irqrestore(&priv->rmw_lock, flags); } -static int jh71x0_clk_enable(struct clk_hw *hw) +static int starfive_clk_enable(struct clk_hw *hw) { - struct jh71x0_clk *clk = jh71x0_clk_from(hw); + struct starfive_clk *clk = starfive_clk_from(hw); - jh71x0_clk_reg_rmw(clk, JH71X0_CLK_ENABLE, JH71X0_CLK_ENABLE); + starfive_clk_reg_rmw(clk, STARFIVE_CLK_ENABLE, STARFIVE_CLK_ENABLE); return 0; } -static void jh71x0_clk_disable(struct clk_hw *hw) +static void starfive_clk_disable(struct clk_hw *hw) { - struct jh71x0_clk *clk = jh71x0_clk_from(hw); + struct starfive_clk *clk = starfive_clk_from(hw); - jh71x0_clk_reg_rmw(clk, JH71X0_CLK_ENABLE, 0); + starfive_clk_reg_rmw(clk, STARFIVE_CLK_ENABLE, 0); } -static int jh71x0_clk_is_enabled(struct clk_hw *hw) +static int starfive_clk_is_enabled(struct clk_hw *hw) { - struct jh71x0_clk *clk = jh71x0_clk_from(hw); + struct starfive_clk *clk = starfive_clk_from(hw); - return !!(jh71x0_clk_reg_get(clk) & JH71X0_CLK_ENABLE); + return !!(starfive_clk_reg_get(clk) & STARFIVE_CLK_ENABLE); } -static unsigned long jh71x0_clk_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) +static unsigned long starfive_clk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) { - struct jh71x0_clk *clk = jh71x0_clk_from(hw); - u32 div = jh71x0_clk_reg_get(clk) & JH71X0_CLK_DIV_MASK; + struct starfive_clk *clk = starfive_clk_from(hw); + u32 div = starfive_clk_reg_get(clk) & STARFIVE_CLK_DIV_MASK; return div ? parent_rate / div : 0; } -static int jh71x0_clk_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) +static int starfive_clk_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { - struct jh71x0_clk *clk = jh71x0_clk_from(hw); + struct starfive_clk *clk = starfive_clk_from(hw); unsigned long parent = req->best_parent_rate; unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate); unsigned long div = min_t(unsigned long, DIV_ROUND_UP(parent, rate), clk->max_div); @@ -102,226 +102,226 @@ static int jh71x0_clk_determine_rate(struct clk_hw *hw, return 0; } -static int jh71x0_clk_set_rate(struct clk_hw *hw, - unsigned long rate, - unsigned long parent_rate) +static int starfive_clk_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) { - struct jh71x0_clk *clk = jh71x0_clk_from(hw); + struct starfive_clk *clk = starfive_clk_from(hw); unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate), 1UL, (unsigned long)clk->max_div); - jh71x0_clk_reg_rmw(clk, JH71X0_CLK_DIV_MASK, div); + starfive_clk_reg_rmw(clk, STARFIVE_CLK_DIV_MASK, div); return 0; } -static unsigned long jh71x0_clk_frac_recalc_rate(struct clk_hw *hw, - unsigned long parent_rate) +static unsigned long starfive_clk_frac_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) { - struct jh71x0_clk *clk = jh71x0_clk_from(hw); - u32 reg = jh71x0_clk_reg_get(clk); - unsigned long div100 = 100 * (reg & JH71X0_CLK_INT_MASK) + - ((reg & JH71X0_CLK_FRAC_MASK) >> JH71X0_CLK_FRAC_SHIFT); + struct starfive_clk *clk = starfive_clk_from(hw); + u32 reg = starfive_clk_reg_get(clk); + unsigned long div100 = 100 * (reg & STARFIVE_CLK_INT_MASK) + + ((reg & STARFIVE_CLK_FRAC_MASK) >> STARFIVE_CLK_FRAC_SHIFT); - return (div100 >= JH71X0_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0; + return (div100 >= STARFIVE_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0; } -static int jh71x0_clk_frac_determine_rate(struct clk_hw *hw, - struct clk_rate_request *req) +static int starfive_clk_frac_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) { unsigned long parent100 = 100 * req->best_parent_rate; unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate); unsigned long div100 = clamp(DIV_ROUND_CLOSEST(parent100, rate), - JH71X0_CLK_FRAC_MIN, JH71X0_CLK_FRAC_MAX); + STARFIVE_CLK_FRAC_MIN, STARFIVE_CLK_FRAC_MAX); unsigned long result = parent100 / div100; - /* clamp the result as in jh71x0_clk_determine_rate() above */ - if (result > req->max_rate && div100 < JH71X0_CLK_FRAC_MAX) + /* clamp the result as in starfive_clk_determine_rate() above */ + if (result > req->max_rate && div100 < STARFIVE_CLK_FRAC_MAX) result = parent100 / (div100 + 1); - if (result < req->min_rate && div100 > JH71X0_CLK_FRAC_MIN) + if (result < req->min_rate && div100 > STARFIVE_CLK_FRAC_MIN) result = parent100 / (div100 - 1); req->rate = result; return 0; } -static int jh71x0_clk_frac_set_rate(struct clk_hw *hw, - unsigned long rate, - unsigned long parent_rate) +static int starfive_clk_frac_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) { - struct jh71x0_clk *clk = jh71x0_clk_from(hw); + struct starfive_clk *clk = starfive_clk_from(hw); unsigned long div100 = clamp(DIV_ROUND_CLOSEST(100 * parent_rate, rate), - JH71X0_CLK_FRAC_MIN, JH71X0_CLK_FRAC_MAX); - u32 value = ((div100 % 100) << JH71X0_CLK_FRAC_SHIFT) | (div100 / 100); + STARFIVE_CLK_FRAC_MIN, STARFIVE_CLK_FRAC_MAX); + u32 value = ((div100 % 100) << STARFIVE_CLK_FRAC_SHIFT) | (div100 / 100); - jh71x0_clk_reg_rmw(clk, JH71X0_CLK_DIV_MASK, value); + starfive_clk_reg_rmw(clk, STARFIVE_CLK_DIV_MASK, value); return 0; } -static u8 jh71x0_clk_get_parent(struct clk_hw *hw) +static u8 starfive_clk_get_parent(struct clk_hw *hw) { - struct jh71x0_clk *clk = jh71x0_clk_from(hw); - u32 value = jh71x0_clk_reg_get(clk); + struct starfive_clk *clk = starfive_clk_from(hw); + u32 value = starfive_clk_reg_get(clk); - return (value & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT; + return (value & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT; } -static int jh71x0_clk_set_parent(struct clk_hw *hw, u8 index) +static int starfive_clk_set_parent(struct clk_hw *hw, u8 index) { - struct jh71x0_clk *clk = jh71x0_clk_from(hw); - u32 value = (u32)index << JH71X0_CLK_MUX_SHIFT; + struct starfive_clk *clk = starfive_clk_from(hw); + u32 value = (u32)index << STARFIVE_CLK_MUX_SHIFT; - jh71x0_clk_reg_rmw(clk, JH71X0_CLK_MUX_MASK, value); + starfive_clk_reg_rmw(clk, STARFIVE_CLK_MUX_MASK, value); return 0; } -static int jh71x0_clk_get_phase(struct clk_hw *hw) +static int starfive_clk_get_phase(struct clk_hw *hw) { - struct jh71x0_clk *clk = jh71x0_clk_from(hw); - u32 value = jh71x0_clk_reg_get(clk); + struct starfive_clk *clk = starfive_clk_from(hw); + u32 value = starfive_clk_reg_get(clk); - return (value & JH71X0_CLK_INVERT) ? 180 : 0; + return (value & STARFIVE_CLK_INVERT) ? 180 : 0; } -static int jh71x0_clk_set_phase(struct clk_hw *hw, int degrees) +static int starfive_clk_set_phase(struct clk_hw *hw, int degrees) { - struct jh71x0_clk *clk = jh71x0_clk_from(hw); + struct starfive_clk *clk = starfive_clk_from(hw); u32 value; if (degrees == 0) value = 0; else if (degrees == 180) - value = JH71X0_CLK_INVERT; + value = STARFIVE_CLK_INVERT; else return -EINVAL; - jh71x0_clk_reg_rmw(clk, JH71X0_CLK_INVERT, value); + starfive_clk_reg_rmw(clk, STARFIVE_CLK_INVERT, value); return 0; } #ifdef CONFIG_DEBUG_FS -static void jh71x0_clk_debug_init(struct clk_hw *hw, struct dentry *dentry) +static void starfive_clk_debug_init(struct clk_hw *hw, struct dentry *dentry) { - static const struct debugfs_reg32 jh71x0_clk_reg = { + static const struct debugfs_reg32 starfive_clk_reg = { .name = "CTRL", .offset = 0, }; - struct jh71x0_clk *clk = jh71x0_clk_from(hw); - struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk); + struct starfive_clk *clk = starfive_clk_from(hw); + struct starfive_clk_priv *priv = starfive_priv_from(clk); struct debugfs_regset32 *regset; regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL); if (!regset) return; - regset->regs = &jh71x0_clk_reg; + regset->regs = &starfive_clk_reg; regset->nregs = 1; regset->base = priv->base + 4 * clk->idx; debugfs_create_regset32("registers", 0400, dentry, regset); } #else -#define jh71x0_clk_debug_init NULL +#define starfive_clk_debug_init NULL #endif -static const struct clk_ops jh71x0_clk_gate_ops = { - .enable = jh71x0_clk_enable, - .disable = jh71x0_clk_disable, - .is_enabled = jh71x0_clk_is_enabled, - .debug_init = jh71x0_clk_debug_init, +static const struct clk_ops starfive_clk_gate_ops = { + .enable = starfive_clk_enable, + .disable = starfive_clk_disable, + .is_enabled = starfive_clk_is_enabled, + .debug_init = starfive_clk_debug_init, }; -static const struct clk_ops jh71x0_clk_div_ops = { - .recalc_rate = jh71x0_clk_recalc_rate, - .determine_rate = jh71x0_clk_determine_rate, - .set_rate = jh71x0_clk_set_rate, - .debug_init = jh71x0_clk_debug_init, +static const struct clk_ops starfive_clk_div_ops = { + .recalc_rate = starfive_clk_recalc_rate, + .determine_rate = starfive_clk_determine_rate, + .set_rate = starfive_clk_set_rate, + .debug_init = starfive_clk_debug_init, }; -static const struct clk_ops jh71x0_clk_fdiv_ops = { - .recalc_rate = jh71x0_clk_frac_recalc_rate, - .determine_rate = jh71x0_clk_frac_determine_rate, - .set_rate = jh71x0_clk_frac_set_rate, - .debug_init = jh71x0_clk_debug_init, +static const struct clk_ops starfive_clk_fdiv_ops = { + .recalc_rate = starfive_clk_frac_recalc_rate, + .determine_rate = starfive_clk_frac_determine_rate, + .set_rate = starfive_clk_frac_set_rate, + .debug_init = starfive_clk_debug_init, }; -static const struct clk_ops jh71x0_clk_gdiv_ops = { - .enable = jh71x0_clk_enable, - .disable = jh71x0_clk_disable, - .is_enabled = jh71x0_clk_is_enabled, - .recalc_rate = jh71x0_clk_recalc_rate, - .determine_rate = jh71x0_clk_determine_rate, - .set_rate = jh71x0_clk_set_rate, - .debug_init = jh71x0_clk_debug_init, +static const struct clk_ops starfive_clk_gdiv_ops = { + .enable = starfive_clk_enable, + .disable = starfive_clk_disable, + .is_enabled = starfive_clk_is_enabled, + .recalc_rate = starfive_clk_recalc_rate, + .determine_rate = starfive_clk_determine_rate, + .set_rate = starfive_clk_set_rate, + .debug_init = starfive_clk_debug_init, }; -static const struct clk_ops jh71x0_clk_mux_ops = { +static const struct clk_ops starfive_clk_mux_ops = { .determine_rate = __clk_mux_determine_rate, - .set_parent = jh71x0_clk_set_parent, - .get_parent = jh71x0_clk_get_parent, - .debug_init = jh71x0_clk_debug_init, + .set_parent = starfive_clk_set_parent, + .get_parent = starfive_clk_get_parent, + .debug_init = starfive_clk_debug_init, }; -static const struct clk_ops jh71x0_clk_gmux_ops = { - .enable = jh71x0_clk_enable, - .disable = jh71x0_clk_disable, - .is_enabled = jh71x0_clk_is_enabled, +static const struct clk_ops starfive_clk_gmux_ops = { + .enable = starfive_clk_enable, + .disable = starfive_clk_disable, + .is_enabled = starfive_clk_is_enabled, .determine_rate = __clk_mux_determine_rate, - .set_parent = jh71x0_clk_set_parent, - .get_parent = jh71x0_clk_get_parent, - .debug_init = jh71x0_clk_debug_init, + .set_parent = starfive_clk_set_parent, + .get_parent = starfive_clk_get_parent, + .debug_init = starfive_clk_debug_init, }; -static const struct clk_ops jh71x0_clk_mdiv_ops = { - .recalc_rate = jh71x0_clk_recalc_rate, - .determine_rate = jh71x0_clk_determine_rate, - .get_parent = jh71x0_clk_get_parent, - .set_parent = jh71x0_clk_set_parent, - .set_rate = jh71x0_clk_set_rate, - .debug_init = jh71x0_clk_debug_init, +static const struct clk_ops starfive_clk_mdiv_ops = { + .recalc_rate = starfive_clk_recalc_rate, + .determine_rate = starfive_clk_determine_rate, + .get_parent = starfive_clk_get_parent, + .set_parent = starfive_clk_set_parent, + .set_rate = starfive_clk_set_rate, + .debug_init = starfive_clk_debug_init, }; -static const struct clk_ops jh71x0_clk_gmd_ops = { - .enable = jh71x0_clk_enable, - .disable = jh71x0_clk_disable, - .is_enabled = jh71x0_clk_is_enabled, - .recalc_rate = jh71x0_clk_recalc_rate, - .determine_rate = jh71x0_clk_determine_rate, - .get_parent = jh71x0_clk_get_parent, - .set_parent = jh71x0_clk_set_parent, - .set_rate = jh71x0_clk_set_rate, - .debug_init = jh71x0_clk_debug_init, +static const struct clk_ops starfive_clk_gmd_ops = { + .enable = starfive_clk_enable, + .disable = starfive_clk_disable, + .is_enabled = starfive_clk_is_enabled, + .recalc_rate = starfive_clk_recalc_rate, + .determine_rate = starfive_clk_determine_rate, + .get_parent = starfive_clk_get_parent, + .set_parent = starfive_clk_set_parent, + .set_rate = starfive_clk_set_rate, + .debug_init = starfive_clk_debug_init, }; -static const struct clk_ops jh71x0_clk_inv_ops = { - .get_phase = jh71x0_clk_get_phase, - .set_phase = jh71x0_clk_set_phase, - .debug_init = jh71x0_clk_debug_init, +static const struct clk_ops starfive_clk_inv_ops = { + .get_phase = starfive_clk_get_phase, + .set_phase = starfive_clk_set_phase, + .debug_init = starfive_clk_debug_init, }; -const struct clk_ops *starfive_jh71x0_clk_ops(u32 max) +const struct clk_ops *starfive_clk_ops(u32 max) { - if (max & JH71X0_CLK_DIV_MASK) { - if (max & JH71X0_CLK_MUX_MASK) { - if (max & JH71X0_CLK_ENABLE) - return &jh71x0_clk_gmd_ops; - return &jh71x0_clk_mdiv_ops; + if (max & STARFIVE_CLK_DIV_MASK) { + if (max & STARFIVE_CLK_MUX_MASK) { + if (max & STARFIVE_CLK_ENABLE) + return &starfive_clk_gmd_ops; + return &starfive_clk_mdiv_ops; } - if (max & JH71X0_CLK_ENABLE) - return &jh71x0_clk_gdiv_ops; - if (max == JH71X0_CLK_FRAC_MAX) - return &jh71x0_clk_fdiv_ops; - return &jh71x0_clk_div_ops; + if (max & STARFIVE_CLK_ENABLE) + return &starfive_clk_gdiv_ops; + if (max == STARFIVE_CLK_FRAC_MAX) + return &starfive_clk_fdiv_ops; + return &starfive_clk_div_ops; } - if (max & JH71X0_CLK_MUX_MASK) { - if (max & JH71X0_CLK_ENABLE) - return &jh71x0_clk_gmux_ops; - return &jh71x0_clk_mux_ops; + if (max & STARFIVE_CLK_MUX_MASK) { + if (max & STARFIVE_CLK_ENABLE) + return &starfive_clk_gmux_ops; + return &starfive_clk_mux_ops; } - if (max & JH71X0_CLK_ENABLE) - return &jh71x0_clk_gate_ops; + if (max & STARFIVE_CLK_ENABLE) + return &starfive_clk_gate_ops; - return &jh71x0_clk_inv_ops; + return &starfive_clk_inv_ops; } -EXPORT_SYMBOL_GPL(starfive_jh71x0_clk_ops); +EXPORT_SYMBOL_GPL(starfive_clk_ops); diff --git a/drivers/clk/starfive/clk-starfive-common.h b/drivers/clk/starfive/clk-starfive-common.h index 1f32f7024e9f..fed45311360c 100644 --- a/drivers/clk/starfive/clk-starfive-common.h +++ b/drivers/clk/starfive/clk-starfive-common.h @@ -8,36 +8,36 @@ #include /* register fields */ -#define JH71X0_CLK_ENABLE BIT(31) -#define JH71X0_CLK_INVERT BIT(30) -#define JH71X0_CLK_MUX_MASK GENMASK(27, 24) -#define JH71X0_CLK_MUX_SHIFT 24 -#define JH71X0_CLK_DIV_MASK GENMASK(23, 0) -#define JH71X0_CLK_FRAC_MASK GENMASK(15, 8) -#define JH71X0_CLK_FRAC_SHIFT 8 -#define JH71X0_CLK_INT_MASK GENMASK(7, 0) +#define STARFIVE_CLK_ENABLE BIT(31) +#define STARFIVE_CLK_INVERT BIT(30) +#define STARFIVE_CLK_MUX_MASK GENMASK(27, 24) +#define STARFIVE_CLK_MUX_SHIFT 24 +#define STARFIVE_CLK_DIV_MASK GENMASK(23, 0) +#define STARFIVE_CLK_FRAC_MASK GENMASK(15, 8) +#define STARFIVE_CLK_FRAC_SHIFT 8 +#define STARFIVE_CLK_INT_MASK GENMASK(7, 0) /* fractional divider min/max */ -#define JH71X0_CLK_FRAC_MIN 100UL -#define JH71X0_CLK_FRAC_MAX 25599UL +#define STARFIVE_CLK_FRAC_MIN 100UL +#define STARFIVE_CLK_FRAC_MAX 25599UL /* clock data */ -struct jh71x0_clk_data { +struct starfive_clk_data { const char *name; unsigned long flags; u32 max; u8 parents[4]; }; -#define JH71X0_GATE(_idx, _name, _flags, _parent) \ +#define STARFIVE_GATE(_idx, _name, _flags, _parent) \ [_idx] = { \ .name = _name, \ .flags = CLK_SET_RATE_PARENT | (_flags), \ - .max = JH71X0_CLK_ENABLE, \ + .max = STARFIVE_CLK_ENABLE, \ .parents = { [0] = _parent }, \ } -#define JH71X0__DIV(_idx, _name, _max, _parent) \ +#define STARFIVE__DIV(_idx, _name, _max, _parent) \ [_idx] = { \ .name = _name, \ .flags = 0, \ @@ -45,79 +45,79 @@ struct jh71x0_clk_data { .parents = { [0] = _parent }, \ } -#define JH71X0_GDIV(_idx, _name, _flags, _max, _parent) \ +#define STARFIVE_GDIV(_idx, _name, _flags, _max, _parent) \ [_idx] = { \ .name = _name, \ .flags = _flags, \ - .max = JH71X0_CLK_ENABLE | (_max), \ + .max = STARFIVE_CLK_ENABLE | (_max), \ .parents = { [0] = _parent }, \ } -#define JH71X0_FDIV(_idx, _name, _parent) \ +#define STARFIVE_FDIV(_idx, _name, _parent) \ [_idx] = { \ .name = _name, \ .flags = 0, \ - .max = JH71X0_CLK_FRAC_MAX, \ + .max = STARFIVE_CLK_FRAC_MAX, \ .parents = { [0] = _parent }, \ } -#define JH71X0__MUX(_idx, _name, _nparents, ...) \ +#define STARFIVE__MUX(_idx, _name, _nparents, ...) \ [_idx] = { \ .name = _name, \ .flags = 0, \ - .max = ((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT, \ + .max = ((_nparents) - 1) << STARFIVE_CLK_MUX_SHIFT, \ .parents = { __VA_ARGS__ }, \ } -#define JH71X0_GMUX(_idx, _name, _flags, _nparents, ...) \ +#define STARFIVE_GMUX(_idx, _name, _flags, _nparents, ...) \ [_idx] = { \ .name = _name, \ .flags = _flags, \ - .max = JH71X0_CLK_ENABLE | \ - (((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT), \ + .max = STARFIVE_CLK_ENABLE | \ + (((_nparents) - 1) << STARFIVE_CLK_MUX_SHIFT), \ .parents = { __VA_ARGS__ }, \ } -#define JH71X0_MDIV(_idx, _name, _max, _nparents, ...) \ +#define STARFIVE_MDIV(_idx, _name, _max, _nparents, ...) \ [_idx] = { \ .name = _name, \ .flags = 0, \ - .max = (((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT) | (_max), \ + .max = (((_nparents) - 1) << STARFIVE_CLK_MUX_SHIFT) | (_max), \ .parents = { __VA_ARGS__ }, \ } -#define JH71X0__GMD(_idx, _name, _flags, _max, _nparents, ...) \ +#define STARFIVE__GMD(_idx, _name, _flags, _max, _nparents, ...) \ [_idx] = { \ .name = _name, \ .flags = _flags, \ - .max = JH71X0_CLK_ENABLE | \ - (((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT) | (_max), \ + .max = STARFIVE_CLK_ENABLE | \ + (((_nparents) - 1) << STARFIVE_CLK_MUX_SHIFT) | (_max), \ .parents = { __VA_ARGS__ }, \ } -#define JH71X0__INV(_idx, _name, _parent) \ +#define STARFIVE__INV(_idx, _name, _parent) \ [_idx] = { \ .name = _name, \ .flags = CLK_SET_RATE_PARENT, \ - .max = JH71X0_CLK_INVERT, \ + .max = STARFIVE_CLK_INVERT, \ .parents = { [0] = _parent }, \ } -struct jh71x0_clk { +struct starfive_clk { struct clk_hw hw; unsigned int idx; unsigned int max_div; }; -struct jh71x0_clk_priv { +struct starfive_clk_priv { /* protect clk enable and set rate/parent from happening at the same time */ spinlock_t rmw_lock; struct device *dev; void __iomem *base; struct clk_hw *pll[3]; - struct jh71x0_clk reg[]; + struct starfive_clk reg[]; }; -const struct clk_ops *starfive_jh71x0_clk_ops(u32 max); +const struct clk_ops *starfive_clk_ops(u32 max); #endif diff --git a/drivers/clk/starfive/clk-starfive-jh7100-audio.c b/drivers/clk/starfive/clk-starfive-jh7100-audio.c index dc4c278606d7..dfe2befddce5 100644 --- a/drivers/clk/starfive/clk-starfive-jh7100-audio.c +++ b/drivers/clk/starfive/clk-starfive-jh7100-audio.c @@ -27,66 +27,68 @@ #define JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD (JH7100_AUDCLK_END + 6) #define JH7100_AUDCLK_VAD_INTMEM (JH7100_AUDCLK_END + 7) -static const struct jh71x0_clk_data jh7100_audclk_data[] = { - JH71X0__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2, - JH7100_AUDCLK_AUDIO_SRC, - JH7100_AUDCLK_AUDIO_12288), - JH71X0__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2, - JH7100_AUDCLK_AUDIO_SRC, - JH7100_AUDCLK_AUDIO_12288), - JH71X0_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS), - JH71X0_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2, - JH7100_AUDCLK_ADC_MCLK, - JH7100_AUDCLK_I2SADC_BCLK_IOPAD), - JH71X0__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK), - JH71X0_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3, - JH7100_AUDCLK_I2SADC_BCLK_N, - JH7100_AUDCLK_I2SADC_LRCLK_IOPAD, - JH7100_AUDCLK_I2SADC_BCLK), - JH71X0_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS), - JH71X0__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2, - JH7100_AUDCLK_AUDIO_SRC, - JH7100_AUDCLK_AUDIO_12288), - JH71X0_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS), - JH71X0__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2, - JH7100_AUDCLK_AUDIO_SRC, - JH7100_AUDCLK_AUDIO_12288), - JH71X0_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS), - JH71X0_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS), - JH71X0__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2, - JH7100_AUDCLK_AUDIO_SRC, - JH7100_AUDCLK_AUDIO_12288), - JH71X0_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS), - JH71X0_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2, - JH7100_AUDCLK_DAC_MCLK, - JH7100_AUDCLK_I2SDAC_BCLK_IOPAD), - JH71X0__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK), - JH71X0_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2, - JH7100_AUDCLK_I2S1_MCLK, - JH7100_AUDCLK_I2SDAC_BCLK_IOPAD), - JH71X0_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS), - JH71X0_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2, - JH7100_AUDCLK_I2S1_MCLK, - JH7100_AUDCLK_I2SDAC_BCLK_IOPAD), - JH71X0__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK), - JH71X0_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3, - JH7100_AUDCLK_I2S1_BCLK_N, - JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD), - JH71X0_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS), - JH71X0__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS), - JH71X0_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS), - JH71X0_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN), - JH71X0_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB), - JH71X0_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB), - JH71X0__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS), - JH71X0__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2, - JH7100_AUDCLK_VAD_INTMEM, - JH7100_AUDCLK_AUDIO_12288), +static const struct starfive_clk_data jh7100_audclk_data[] = { + STARFIVE__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2, + JH7100_AUDCLK_AUDIO_SRC, + JH7100_AUDCLK_AUDIO_12288), + STARFIVE__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2, + JH7100_AUDCLK_AUDIO_SRC, + JH7100_AUDCLK_AUDIO_12288), + STARFIVE_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS), + STARFIVE_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2, + JH7100_AUDCLK_ADC_MCLK, + JH7100_AUDCLK_I2SADC_BCLK_IOPAD), + STARFIVE__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK), + STARFIVE_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3, + JH7100_AUDCLK_I2SADC_BCLK_N, + JH7100_AUDCLK_I2SADC_LRCLK_IOPAD, + JH7100_AUDCLK_I2SADC_BCLK), + STARFIVE_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS), + STARFIVE__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2, + JH7100_AUDCLK_AUDIO_SRC, + JH7100_AUDCLK_AUDIO_12288), + STARFIVE_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS), + STARFIVE__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2, + JH7100_AUDCLK_AUDIO_SRC, + JH7100_AUDCLK_AUDIO_12288), + STARFIVE_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS), + STARFIVE_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS), + STARFIVE__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2, + JH7100_AUDCLK_AUDIO_SRC, + JH7100_AUDCLK_AUDIO_12288), + STARFIVE_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS), + STARFIVE_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2, + JH7100_AUDCLK_DAC_MCLK, + JH7100_AUDCLK_I2SDAC_BCLK_IOPAD), + STARFIVE__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK), + STARFIVE_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2, + JH7100_AUDCLK_I2S1_MCLK, + JH7100_AUDCLK_I2SDAC_BCLK_IOPAD), + STARFIVE_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS), + STARFIVE_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2, + JH7100_AUDCLK_I2S1_MCLK, + JH7100_AUDCLK_I2SDAC_BCLK_IOPAD), + STARFIVE__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK), + STARFIVE_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3, + JH7100_AUDCLK_I2S1_BCLK_N, + JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD), + STARFIVE_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS), + STARFIVE__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS), + STARFIVE_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS), + STARFIVE_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN), + STARFIVE_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, + JH7100_AUDCLK_USB_APB), + STARFIVE_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, + JH7100_AUDCLK_USB_APB), + STARFIVE__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS), + STARFIVE__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2, + JH7100_AUDCLK_VAD_INTMEM, + JH7100_AUDCLK_AUDIO_12288), }; static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *data) { - struct jh71x0_clk_priv *priv = data; + struct starfive_clk_priv *priv = data; unsigned int idx = clkspec->args[0]; if (idx < JH7100_AUDCLK_END) @@ -97,7 +99,7 @@ static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *d static int jh7100_audclk_probe(struct platform_device *pdev) { - struct jh71x0_clk_priv *priv; + struct starfive_clk_priv *priv; unsigned int idx; int ret; @@ -116,12 +118,13 @@ static int jh7100_audclk_probe(struct platform_device *pdev) struct clk_parent_data parents[4] = {}; struct clk_init_data init = { .name = jh7100_audclk_data[idx].name, - .ops = starfive_jh71x0_clk_ops(max), + .ops = starfive_clk_ops(max), .parent_data = parents, - .num_parents = ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1, + .num_parents = ((max & STARFIVE_CLK_MUX_MASK) + >> STARFIVE_CLK_MUX_SHIFT) + 1, .flags = jh7100_audclk_data[idx].flags, }; - struct jh71x0_clk *clk = &priv->reg[idx]; + struct starfive_clk *clk = &priv->reg[idx]; unsigned int i; for (i = 0; i < init.num_parents; i++) { @@ -139,7 +142,7 @@ static int jh7100_audclk_probe(struct platform_device *pdev) clk->hw.init = &init; clk->idx = idx; - clk->max_div = max & JH71X0_CLK_DIV_MASK; + clk->max_div = max & STARFIVE_CLK_DIV_MASK; ret = devm_clk_hw_register(priv->dev, &clk->hw); if (ret) diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c index 6bb6a6af9f28..946a437f534b 100644 --- a/drivers/clk/starfive/clk-starfive-jh7100.c +++ b/drivers/clk/starfive/clk-starfive-jh7100.c @@ -23,253 +23,257 @@ #define JH7100_CLK_GMAC_RMII_REF (JH7100_CLK_END + 2) #define JH7100_CLK_GMAC_GR_MII_RX (JH7100_CLK_END + 3) -static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = { - JH71X0__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4, - JH7100_CLK_OSC_SYS, - JH7100_CLK_PLL0_OUT, - JH7100_CLK_PLL1_OUT, - JH7100_CLK_PLL2_OUT), - JH71X0__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3, - JH7100_CLK_OSC_SYS, - JH7100_CLK_PLL1_OUT, - JH7100_CLK_PLL2_OUT), - JH71X0__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4, - JH7100_CLK_OSC_SYS, - JH7100_CLK_PLL0_OUT, - JH7100_CLK_PLL1_OUT, - JH7100_CLK_PLL2_OUT), - JH71X0__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3, - JH7100_CLK_OSC_SYS, - JH7100_CLK_PLL0_OUT, - JH7100_CLK_PLL2_OUT), - JH71X0__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2, - JH7100_CLK_OSC_SYS, - JH7100_CLK_PLL0_OUT), - JH71X0__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2, - JH7100_CLK_OSC_SYS, - JH7100_CLK_PLL2_OUT), - JH71X0__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3, - JH7100_CLK_OSC_SYS, - JH7100_CLK_PLL1_OUT, - JH7100_CLK_PLL2_OUT), - JH71X0__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3, - JH7100_CLK_OSC_AUD, - JH7100_CLK_PLL0_OUT, - JH7100_CLK_PLL2_OUT), - JH71X0_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT), - JH71X0__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3, - JH7100_CLK_OSC_SYS, - JH7100_CLK_PLL1_OUT, - JH7100_CLK_PLL2_OUT), - JH71X0__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3, - JH7100_CLK_OSC_SYS, - JH7100_CLK_PLL0_OUT, - JH7100_CLK_PLL1_OUT), - JH71X0__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3, - JH7100_CLK_OSC_AUD, - JH7100_CLK_PLL0_OUT, - JH7100_CLK_PLL2_OUT), - JH71X0__DIV(JH7100_CLK_CPUNBUS_ROOT_DIV, "cpunbus_root_div", 2, JH7100_CLK_CPUNDBUS_ROOT), - JH71X0__DIV(JH7100_CLK_DSP_ROOT_DIV, "dsp_root_div", 4, JH7100_CLK_DSP_ROOT), - JH71X0__DIV(JH7100_CLK_PERH0_SRC, "perh0_src", 4, JH7100_CLK_PERH0_ROOT), - JH71X0__DIV(JH7100_CLK_PERH1_SRC, "perh1_src", 4, JH7100_CLK_PERH1_ROOT), - JH71X0_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC), - JH71X0_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT), - JH71X0_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC), - JH71X0__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2, - JH7100_CLK_OSC_SYS, - JH7100_CLK_OSC_AUD), - JH71X0__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV), - JH71X0__DIV(JH7100_CLK_CPU_AXI, "cpu_axi", 8, JH7100_CLK_CPU_CORE), - JH71X0__DIV(JH7100_CLK_AHB_BUS, "ahb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV), - JH71X0__DIV(JH7100_CLK_APB1_BUS, "apb1_bus", 8, JH7100_CLK_AHB_BUS), - JH71X0__DIV(JH7100_CLK_APB2_BUS, "apb2_bus", 8, JH7100_CLK_AHB_BUS), - JH71X0_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS), - JH71X0_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS), - JH71X0_GATE(JH7100_CLK_U74_CORE0, "u74_core0", CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE), - JH71X0_GDIV(JH7100_CLK_U74_CORE1, "u74_core1", CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE), - JH71X0_GATE(JH7100_CLK_U74_AXI, "u74_axi", CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI), - JH71X0_GATE(JH7100_CLK_U74RTC_TOGGLE, "u74rtc_toggle", CLK_IS_CRITICAL, JH7100_CLK_OSC_SYS), - JH71X0_GATE(JH7100_CLK_SGDMA2P_AXI, "sgdma2p_axi", 0, JH7100_CLK_CPU_AXI), - JH71X0_GATE(JH7100_CLK_DMA2PNOC_AXI, "dma2pnoc_axi", 0, JH7100_CLK_CPU_AXI), - JH71X0_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb", 0, JH7100_CLK_AHB_BUS), - JH71X0__DIV(JH7100_CLK_DLA_BUS, "dla_bus", 4, JH7100_CLK_DLA_ROOT), - JH71X0_GATE(JH7100_CLK_DLA_AXI, "dla_axi", 0, JH7100_CLK_DLA_BUS), - JH71X0_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", 0, JH7100_CLK_DLA_BUS), - JH71X0_GATE(JH7100_CLK_DLA_APB, "dla_apb", 0, JH7100_CLK_APB1_BUS), - JH71X0_GDIV(JH7100_CLK_VP6_CORE, "vp6_core", 0, 4, JH7100_CLK_DSP_ROOT_DIV), - JH71X0__DIV(JH7100_CLK_VP6BUS_SRC, "vp6bus_src", 4, JH7100_CLK_DSP_ROOT), - JH71X0_GDIV(JH7100_CLK_VP6_AXI, "vp6_axi", 0, 4, JH7100_CLK_VP6BUS_SRC), - JH71X0__DIV(JH7100_CLK_VCDECBUS_SRC, "vcdecbus_src", 4, JH7100_CLK_CDECHIFI4_ROOT), - JH71X0__DIV(JH7100_CLK_VDEC_BUS, "vdec_bus", 8, JH7100_CLK_VCDECBUS_SRC), - JH71X0_GATE(JH7100_CLK_VDEC_AXI, "vdec_axi", 0, JH7100_CLK_VDEC_BUS), - JH71X0_GATE(JH7100_CLK_VDECBRG_MAIN, "vdecbrg_mainclk", 0, JH7100_CLK_VDEC_BUS), - JH71X0_GDIV(JH7100_CLK_VDEC_BCLK, "vdec_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC), - JH71X0_GDIV(JH7100_CLK_VDEC_CCLK, "vdec_cclk", 0, 8, JH7100_CLK_CDEC_ROOT), - JH71X0_GATE(JH7100_CLK_VDEC_APB, "vdec_apb", 0, JH7100_CLK_APB1_BUS), - JH71X0_GDIV(JH7100_CLK_JPEG_AXI, "jpeg_axi", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV), - JH71X0_GDIV(JH7100_CLK_JPEG_CCLK, "jpeg_cclk", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV), - JH71X0_GATE(JH7100_CLK_JPEG_APB, "jpeg_apb", 0, JH7100_CLK_APB1_BUS), - JH71X0_GDIV(JH7100_CLK_GC300_2X, "gc300_2x", 0, 8, JH7100_CLK_CDECHIFI4_ROOT), - JH71X0_GATE(JH7100_CLK_GC300_AHB, "gc300_ahb", 0, JH7100_CLK_AHB_BUS), - JH71X0__DIV(JH7100_CLK_JPCGC300_AXIBUS, "jpcgc300_axibus", 8, JH7100_CLK_VCDECBUS_SRC), - JH71X0_GATE(JH7100_CLK_GC300_AXI, "gc300_axi", 0, JH7100_CLK_JPCGC300_AXIBUS), - JH71X0_GATE(JH7100_CLK_JPCGC300_MAIN, "jpcgc300_mainclk", 0, JH7100_CLK_JPCGC300_AXIBUS), - JH71X0__DIV(JH7100_CLK_VENC_BUS, "venc_bus", 8, JH7100_CLK_VCDECBUS_SRC), - JH71X0_GATE(JH7100_CLK_VENC_AXI, "venc_axi", 0, JH7100_CLK_VENC_BUS), - JH71X0_GATE(JH7100_CLK_VENCBRG_MAIN, "vencbrg_mainclk", 0, JH7100_CLK_VENC_BUS), - JH71X0_GDIV(JH7100_CLK_VENC_BCLK, "venc_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC), - JH71X0_GDIV(JH7100_CLK_VENC_CCLK, "venc_cclk", 0, 8, JH7100_CLK_CDEC_ROOT), - JH71X0_GATE(JH7100_CLK_VENC_APB, "venc_apb", 0, JH7100_CLK_APB1_BUS), - JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV2, "ddrpll_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_PLL1_OUT), - JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV4, "ddrpll_div4", CLK_IS_CRITICAL, 2, - JH7100_CLK_DDRPLL_DIV2), - JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV8, "ddrpll_div8", CLK_IS_CRITICAL, 2, - JH7100_CLK_DDRPLL_DIV4), - JH71X0_GDIV(JH7100_CLK_DDROSC_DIV2, "ddrosc_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_OSC_SYS), - JH71X0_GMUX(JH7100_CLK_DDRC0, "ddrc0", CLK_IS_CRITICAL, 4, - JH7100_CLK_DDROSC_DIV2, - JH7100_CLK_DDRPLL_DIV2, - JH7100_CLK_DDRPLL_DIV4, - JH7100_CLK_DDRPLL_DIV8), - JH71X0_GMUX(JH7100_CLK_DDRC1, "ddrc1", CLK_IS_CRITICAL, 4, - JH7100_CLK_DDROSC_DIV2, - JH7100_CLK_DDRPLL_DIV2, - JH7100_CLK_DDRPLL_DIV4, - JH7100_CLK_DDRPLL_DIV8), - JH71X0_GATE(JH7100_CLK_DDRPHY_APB, "ddrphy_apb", 0, JH7100_CLK_APB1_BUS), - JH71X0__DIV(JH7100_CLK_NOC_ROB, "noc_rob", 8, JH7100_CLK_CPUNBUS_ROOT_DIV), - JH71X0__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT), - JH71X0_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS), - JH71X0__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT), - JH71X0__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2, - JH7100_CLK_CPU_AXI, - JH7100_CLK_NNEBUS_SRC1), - JH71X0_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS), - JH71X0_GATE(JH7100_CLK_NNENOC_AXI, "nnenoc_axi", 0, JH7100_CLK_NNE_BUS), - JH71X0_GATE(JH7100_CLK_DLASLV_AXI, "dlaslv_axi", 0, JH7100_CLK_NNE_BUS), - JH71X0_GATE(JH7100_CLK_DSPX2C_AXI, "dspx2c_axi", CLK_IS_CRITICAL, JH7100_CLK_NNE_BUS), - JH71X0__DIV(JH7100_CLK_HIFI4_SRC, "hifi4_src", 4, JH7100_CLK_CDECHIFI4_ROOT), - JH71X0__DIV(JH7100_CLK_HIFI4_COREFREE, "hifi4_corefree", 8, JH7100_CLK_HIFI4_SRC), - JH71X0_GATE(JH7100_CLK_HIFI4_CORE, "hifi4_core", 0, JH7100_CLK_HIFI4_COREFREE), - JH71X0__DIV(JH7100_CLK_HIFI4_BUS, "hifi4_bus", 8, JH7100_CLK_HIFI4_COREFREE), - JH71X0_GATE(JH7100_CLK_HIFI4_AXI, "hifi4_axi", 0, JH7100_CLK_HIFI4_BUS), - JH71X0_GATE(JH7100_CLK_HIFI4NOC_AXI, "hifi4noc_axi", 0, JH7100_CLK_HIFI4_BUS), - JH71X0__DIV(JH7100_CLK_SGDMA1P_BUS, "sgdma1p_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV), - JH71X0_GATE(JH7100_CLK_SGDMA1P_AXI, "sgdma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS), - JH71X0_GATE(JH7100_CLK_DMA1P_AXI, "dma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS), - JH71X0_GDIV(JH7100_CLK_X2C_AXI, "x2c_axi", CLK_IS_CRITICAL, 8, JH7100_CLK_CPUNBUS_ROOT_DIV), - JH71X0__DIV(JH7100_CLK_USB_BUS, "usb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV), - JH71X0_GATE(JH7100_CLK_USB_AXI, "usb_axi", 0, JH7100_CLK_USB_BUS), - JH71X0_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi", 0, JH7100_CLK_USB_BUS), - JH71X0__DIV(JH7100_CLK_USBPHY_ROOTDIV, "usbphy_rootdiv", 4, JH7100_CLK_GMACUSB_ROOT), - JH71X0_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV), - JH71X0_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32, - JH7100_CLK_USBPHY_ROOTDIV), - JH71X0__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2, - JH7100_CLK_OSC_SYS, - JH7100_CLK_USBPHY_PLLDIV25M), - JH71X0_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT), - JH71X0_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV), - JH71X0_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD), - JH71X0_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT), - JH71X0__DIV(JH7100_CLK_ISP0_BUS, "isp0_bus", 8, JH7100_CLK_VIN_SRC), - JH71X0_GATE(JH7100_CLK_ISP0_AXI, "isp0_axi", 0, JH7100_CLK_ISP0_BUS), - JH71X0_GATE(JH7100_CLK_ISP0NOC_AXI, "isp0noc_axi", 0, JH7100_CLK_ISP0_BUS), - JH71X0_GATE(JH7100_CLK_ISPSLV_AXI, "ispslv_axi", 0, JH7100_CLK_ISP0_BUS), - JH71X0__DIV(JH7100_CLK_ISP1_BUS, "isp1_bus", 8, JH7100_CLK_VIN_SRC), - JH71X0_GATE(JH7100_CLK_ISP1_AXI, "isp1_axi", 0, JH7100_CLK_ISP1_BUS), - JH71X0_GATE(JH7100_CLK_ISP1NOC_AXI, "isp1noc_axi", 0, JH7100_CLK_ISP1_BUS), - JH71X0__DIV(JH7100_CLK_VIN_BUS, "vin_bus", 8, JH7100_CLK_VIN_SRC), - JH71X0_GATE(JH7100_CLK_VIN_AXI, "vin_axi", 0, JH7100_CLK_VIN_BUS), - JH71X0_GATE(JH7100_CLK_VINNOC_AXI, "vinnoc_axi", 0, JH7100_CLK_VIN_BUS), - JH71X0_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", 0, 4, JH7100_CLK_VOUT_ROOT), - JH71X0__DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src", 4, JH7100_CLK_VOUTBUS_ROOT), - JH71X0__DIV(JH7100_CLK_DISP_BUS, "disp_bus", 4, JH7100_CLK_DISPBUS_SRC), - JH71X0_GATE(JH7100_CLK_DISP_AXI, "disp_axi", 0, JH7100_CLK_DISP_BUS), - JH71X0_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", 0, JH7100_CLK_DISP_BUS), - JH71X0_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb", 0, JH7100_CLK_AHB_BUS), - JH71X0_GDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint", 0, 24, JH7100_CLK_PERH0_SRC), - JH71X0__INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv", JH7100_CLK_SDIO0_CCLKINT), - JH71X0_GATE(JH7100_CLK_SDIO1_AHB, "sdio1_ahb", 0, JH7100_CLK_AHB_BUS), - JH71X0_GDIV(JH7100_CLK_SDIO1_CCLKINT, "sdio1_cclkint", 0, 24, JH7100_CLK_PERH1_SRC), - JH71X0__INV(JH7100_CLK_SDIO1_CCLKINT_INV, "sdio1_cclkint_inv", JH7100_CLK_SDIO1_CCLKINT), - JH71X0_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", 0, JH7100_CLK_AHB_BUS), - JH71X0__DIV(JH7100_CLK_GMAC_ROOT_DIV, "gmac_root_div", 8, JH7100_CLK_GMACUSB_ROOT), - JH71X0_GDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk", 0, 31, JH7100_CLK_GMAC_ROOT_DIV), - JH71X0_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV), - JH71X0_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF), - JH71X0_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF), - JH71X0__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3, - JH7100_CLK_GMAC_GTX, - JH7100_CLK_GMAC_TX_INV, - JH7100_CLK_GMAC_RMII_TX), - JH71X0__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX), - JH71X0__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2, - JH7100_CLK_GMAC_GR_MII_RX, - JH7100_CLK_GMAC_RMII_RX), - JH71X0__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE), - JH71X0_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii", 0, JH7100_CLK_GMAC_RMII_REF), - JH71X0_GDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref", 0, 127, JH7100_CLK_GMAC_ROOT_DIV), - JH71X0_GATE(JH7100_CLK_SPI2AHB_AHB, "spi2ahb_ahb", 0, JH7100_CLK_AHB_BUS), - JH71X0_GDIV(JH7100_CLK_SPI2AHB_CORE, "spi2ahb_core", 0, 31, JH7100_CLK_PERH0_SRC), - JH71X0_GATE(JH7100_CLK_EZMASTER_AHB, "ezmaster_ahb", 0, JH7100_CLK_AHB_BUS), - JH71X0_GATE(JH7100_CLK_E24_AHB, "e24_ahb", 0, JH7100_CLK_AHB_BUS), - JH71X0_GATE(JH7100_CLK_E24RTC_TOGGLE, "e24rtc_toggle", 0, JH7100_CLK_OSC_SYS), - JH71X0_GATE(JH7100_CLK_QSPI_AHB, "qspi_ahb", 0, JH7100_CLK_AHB_BUS), - JH71X0_GATE(JH7100_CLK_QSPI_APB, "qspi_apb", 0, JH7100_CLK_APB1_BUS), - JH71X0_GDIV(JH7100_CLK_QSPI_REF, "qspi_refclk", 0, 31, JH7100_CLK_PERH0_SRC), - JH71X0_GATE(JH7100_CLK_SEC_AHB, "sec_ahb", 0, JH7100_CLK_AHB_BUS), - JH71X0_GATE(JH7100_CLK_AES, "aes_clk", 0, JH7100_CLK_SEC_AHB), - JH71X0_GATE(JH7100_CLK_SHA, "sha_clk", 0, JH7100_CLK_SEC_AHB), - JH71X0_GATE(JH7100_CLK_PKA, "pka_clk", 0, JH7100_CLK_SEC_AHB), - JH71X0_GATE(JH7100_CLK_TRNG_APB, "trng_apb", 0, JH7100_CLK_APB1_BUS), - JH71X0_GATE(JH7100_CLK_OTP_APB, "otp_apb", 0, JH7100_CLK_APB1_BUS), - JH71X0_GATE(JH7100_CLK_UART0_APB, "uart0_apb", 0, JH7100_CLK_APB1_BUS), - JH71X0_GDIV(JH7100_CLK_UART0_CORE, "uart0_core", 0, 63, JH7100_CLK_PERH1_SRC), - JH71X0_GATE(JH7100_CLK_UART1_APB, "uart1_apb", 0, JH7100_CLK_APB1_BUS), - JH71X0_GDIV(JH7100_CLK_UART1_CORE, "uart1_core", 0, 63, JH7100_CLK_PERH1_SRC), - JH71X0_GATE(JH7100_CLK_SPI0_APB, "spi0_apb", 0, JH7100_CLK_APB1_BUS), - JH71X0_GDIV(JH7100_CLK_SPI0_CORE, "spi0_core", 0, 63, JH7100_CLK_PERH1_SRC), - JH71X0_GATE(JH7100_CLK_SPI1_APB, "spi1_apb", 0, JH7100_CLK_APB1_BUS), - JH71X0_GDIV(JH7100_CLK_SPI1_CORE, "spi1_core", 0, 63, JH7100_CLK_PERH1_SRC), - JH71X0_GATE(JH7100_CLK_I2C0_APB, "i2c0_apb", 0, JH7100_CLK_APB1_BUS), - JH71X0_GDIV(JH7100_CLK_I2C0_CORE, "i2c0_core", 0, 63, JH7100_CLK_PERH1_SRC), - JH71X0_GATE(JH7100_CLK_I2C1_APB, "i2c1_apb", 0, JH7100_CLK_APB1_BUS), - JH71X0_GDIV(JH7100_CLK_I2C1_CORE, "i2c1_core", 0, 63, JH7100_CLK_PERH1_SRC), - JH71X0_GATE(JH7100_CLK_GPIO_APB, "gpio_apb", 0, JH7100_CLK_APB1_BUS), - JH71X0_GATE(JH7100_CLK_UART2_APB, "uart2_apb", 0, JH7100_CLK_APB2_BUS), - JH71X0_GDIV(JH7100_CLK_UART2_CORE, "uart2_core", 0, 63, JH7100_CLK_PERH0_SRC), - JH71X0_GATE(JH7100_CLK_UART3_APB, "uart3_apb", 0, JH7100_CLK_APB2_BUS), - JH71X0_GDIV(JH7100_CLK_UART3_CORE, "uart3_core", 0, 63, JH7100_CLK_PERH0_SRC), - JH71X0_GATE(JH7100_CLK_SPI2_APB, "spi2_apb", 0, JH7100_CLK_APB2_BUS), - JH71X0_GDIV(JH7100_CLK_SPI2_CORE, "spi2_core", 0, 63, JH7100_CLK_PERH0_SRC), - JH71X0_GATE(JH7100_CLK_SPI3_APB, "spi3_apb", 0, JH7100_CLK_APB2_BUS), - JH71X0_GDIV(JH7100_CLK_SPI3_CORE, "spi3_core", 0, 63, JH7100_CLK_PERH0_SRC), - JH71X0_GATE(JH7100_CLK_I2C2_APB, "i2c2_apb", 0, JH7100_CLK_APB2_BUS), - JH71X0_GDIV(JH7100_CLK_I2C2_CORE, "i2c2_core", 0, 63, JH7100_CLK_PERH0_SRC), - JH71X0_GATE(JH7100_CLK_I2C3_APB, "i2c3_apb", 0, JH7100_CLK_APB2_BUS), - JH71X0_GDIV(JH7100_CLK_I2C3_CORE, "i2c3_core", 0, 63, JH7100_CLK_PERH0_SRC), - JH71X0_GATE(JH7100_CLK_WDTIMER_APB, "wdtimer_apb", 0, JH7100_CLK_APB2_BUS), - JH71X0_GDIV(JH7100_CLK_WDT_CORE, "wdt_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), - JH71X0_GDIV(JH7100_CLK_TIMER0_CORE, "timer0_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), - JH71X0_GDIV(JH7100_CLK_TIMER1_CORE, "timer1_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), - JH71X0_GDIV(JH7100_CLK_TIMER2_CORE, "timer2_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), - JH71X0_GDIV(JH7100_CLK_TIMER3_CORE, "timer3_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), - JH71X0_GDIV(JH7100_CLK_TIMER4_CORE, "timer4_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), - JH71X0_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), - JH71X0_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), - JH71X0_GATE(JH7100_CLK_VP6INTC_APB, "vp6intc_apb", 0, JH7100_CLK_APB2_BUS), - JH71X0_GATE(JH7100_CLK_PWM_APB, "pwm_apb", 0, JH7100_CLK_APB2_BUS), - JH71X0_GATE(JH7100_CLK_MSI_APB, "msi_apb", 0, JH7100_CLK_APB2_BUS), - JH71X0_GATE(JH7100_CLK_TEMP_APB, "temp_apb", 0, JH7100_CLK_APB2_BUS), - JH71X0_GDIV(JH7100_CLK_TEMP_SENSE, "temp_sense", 0, 31, JH7100_CLK_OSC_SYS), - JH71X0_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS), +static const struct starfive_clk_data jh7100_clk_data[] __initconst = { + STARFIVE__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4, + JH7100_CLK_OSC_SYS, + JH7100_CLK_PLL0_OUT, + JH7100_CLK_PLL1_OUT, + JH7100_CLK_PLL2_OUT), + STARFIVE__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3, + JH7100_CLK_OSC_SYS, + JH7100_CLK_PLL1_OUT, + JH7100_CLK_PLL2_OUT), + STARFIVE__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4, + JH7100_CLK_OSC_SYS, + JH7100_CLK_PLL0_OUT, + JH7100_CLK_PLL1_OUT, + JH7100_CLK_PLL2_OUT), + STARFIVE__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3, + JH7100_CLK_OSC_SYS, + JH7100_CLK_PLL0_OUT, + JH7100_CLK_PLL2_OUT), + STARFIVE__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2, + JH7100_CLK_OSC_SYS, + JH7100_CLK_PLL0_OUT), + STARFIVE__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2, + JH7100_CLK_OSC_SYS, + JH7100_CLK_PLL2_OUT), + STARFIVE__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3, + JH7100_CLK_OSC_SYS, + JH7100_CLK_PLL1_OUT, + JH7100_CLK_PLL2_OUT), + STARFIVE__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3, + JH7100_CLK_OSC_AUD, + JH7100_CLK_PLL0_OUT, + JH7100_CLK_PLL2_OUT), + STARFIVE_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT), + STARFIVE__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3, + JH7100_CLK_OSC_SYS, + JH7100_CLK_PLL1_OUT, + JH7100_CLK_PLL2_OUT), + STARFIVE__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3, + JH7100_CLK_OSC_SYS, + JH7100_CLK_PLL0_OUT, + JH7100_CLK_PLL1_OUT), + STARFIVE__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3, + JH7100_CLK_OSC_AUD, + JH7100_CLK_PLL0_OUT, + JH7100_CLK_PLL2_OUT), + STARFIVE__DIV(JH7100_CLK_CPUNBUS_ROOT_DIV, "cpunbus_root_div", 2, JH7100_CLK_CPUNDBUS_ROOT), + STARFIVE__DIV(JH7100_CLK_DSP_ROOT_DIV, "dsp_root_div", 4, JH7100_CLK_DSP_ROOT), + STARFIVE__DIV(JH7100_CLK_PERH0_SRC, "perh0_src", 4, JH7100_CLK_PERH0_ROOT), + STARFIVE__DIV(JH7100_CLK_PERH1_SRC, "perh1_src", 4, JH7100_CLK_PERH1_ROOT), + STARFIVE_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC), + STARFIVE_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT), + STARFIVE_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC), + STARFIVE__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2, + JH7100_CLK_OSC_SYS, + JH7100_CLK_OSC_AUD), + STARFIVE__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV), + STARFIVE__DIV(JH7100_CLK_CPU_AXI, "cpu_axi", 8, JH7100_CLK_CPU_CORE), + STARFIVE__DIV(JH7100_CLK_AHB_BUS, "ahb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV), + STARFIVE__DIV(JH7100_CLK_APB1_BUS, "apb1_bus", 8, JH7100_CLK_AHB_BUS), + STARFIVE__DIV(JH7100_CLK_APB2_BUS, "apb2_bus", 8, JH7100_CLK_AHB_BUS), + STARFIVE_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS), + STARFIVE_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS), + STARFIVE_GATE(JH7100_CLK_U74_CORE0, "u74_core0", CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE), + STARFIVE_GDIV(JH7100_CLK_U74_CORE1, "u74_core1", CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE), + STARFIVE_GATE(JH7100_CLK_U74_AXI, "u74_axi", CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI), + STARFIVE_GATE(JH7100_CLK_U74RTC_TOGGLE, "u74rtc_toggle", CLK_IS_CRITICAL, + JH7100_CLK_OSC_SYS), + STARFIVE_GATE(JH7100_CLK_SGDMA2P_AXI, "sgdma2p_axi", 0, JH7100_CLK_CPU_AXI), + STARFIVE_GATE(JH7100_CLK_DMA2PNOC_AXI, "dma2pnoc_axi", 0, JH7100_CLK_CPU_AXI), + STARFIVE_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb", 0, JH7100_CLK_AHB_BUS), + STARFIVE__DIV(JH7100_CLK_DLA_BUS, "dla_bus", 4, JH7100_CLK_DLA_ROOT), + STARFIVE_GATE(JH7100_CLK_DLA_AXI, "dla_axi", 0, JH7100_CLK_DLA_BUS), + STARFIVE_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", 0, JH7100_CLK_DLA_BUS), + STARFIVE_GATE(JH7100_CLK_DLA_APB, "dla_apb", 0, JH7100_CLK_APB1_BUS), + STARFIVE_GDIV(JH7100_CLK_VP6_CORE, "vp6_core", 0, 4, JH7100_CLK_DSP_ROOT_DIV), + STARFIVE__DIV(JH7100_CLK_VP6BUS_SRC, "vp6bus_src", 4, JH7100_CLK_DSP_ROOT), + STARFIVE_GDIV(JH7100_CLK_VP6_AXI, "vp6_axi", 0, 4, JH7100_CLK_VP6BUS_SRC), + STARFIVE__DIV(JH7100_CLK_VCDECBUS_SRC, "vcdecbus_src", 4, JH7100_CLK_CDECHIFI4_ROOT), + STARFIVE__DIV(JH7100_CLK_VDEC_BUS, "vdec_bus", 8, JH7100_CLK_VCDECBUS_SRC), + STARFIVE_GATE(JH7100_CLK_VDEC_AXI, "vdec_axi", 0, JH7100_CLK_VDEC_BUS), + STARFIVE_GATE(JH7100_CLK_VDECBRG_MAIN, "vdecbrg_mainclk", 0, JH7100_CLK_VDEC_BUS), + STARFIVE_GDIV(JH7100_CLK_VDEC_BCLK, "vdec_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC), + STARFIVE_GDIV(JH7100_CLK_VDEC_CCLK, "vdec_cclk", 0, 8, JH7100_CLK_CDEC_ROOT), + STARFIVE_GATE(JH7100_CLK_VDEC_APB, "vdec_apb", 0, JH7100_CLK_APB1_BUS), + STARFIVE_GDIV(JH7100_CLK_JPEG_AXI, "jpeg_axi", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV), + STARFIVE_GDIV(JH7100_CLK_JPEG_CCLK, "jpeg_cclk", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV), + STARFIVE_GATE(JH7100_CLK_JPEG_APB, "jpeg_apb", 0, JH7100_CLK_APB1_BUS), + STARFIVE_GDIV(JH7100_CLK_GC300_2X, "gc300_2x", 0, 8, JH7100_CLK_CDECHIFI4_ROOT), + STARFIVE_GATE(JH7100_CLK_GC300_AHB, "gc300_ahb", 0, JH7100_CLK_AHB_BUS), + STARFIVE__DIV(JH7100_CLK_JPCGC300_AXIBUS, "jpcgc300_axibus", 8, JH7100_CLK_VCDECBUS_SRC), + STARFIVE_GATE(JH7100_CLK_GC300_AXI, "gc300_axi", 0, JH7100_CLK_JPCGC300_AXIBUS), + STARFIVE_GATE(JH7100_CLK_JPCGC300_MAIN, "jpcgc300_mainclk", 0, JH7100_CLK_JPCGC300_AXIBUS), + STARFIVE__DIV(JH7100_CLK_VENC_BUS, "venc_bus", 8, JH7100_CLK_VCDECBUS_SRC), + STARFIVE_GATE(JH7100_CLK_VENC_AXI, "venc_axi", 0, JH7100_CLK_VENC_BUS), + STARFIVE_GATE(JH7100_CLK_VENCBRG_MAIN, "vencbrg_mainclk", 0, JH7100_CLK_VENC_BUS), + STARFIVE_GDIV(JH7100_CLK_VENC_BCLK, "venc_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC), + STARFIVE_GDIV(JH7100_CLK_VENC_CCLK, "venc_cclk", 0, 8, JH7100_CLK_CDEC_ROOT), + STARFIVE_GATE(JH7100_CLK_VENC_APB, "venc_apb", 0, JH7100_CLK_APB1_BUS), + STARFIVE_GDIV(JH7100_CLK_DDRPLL_DIV2, "ddrpll_div2", CLK_IS_CRITICAL, 2, + JH7100_CLK_PLL1_OUT), + STARFIVE_GDIV(JH7100_CLK_DDRPLL_DIV4, "ddrpll_div4", CLK_IS_CRITICAL, 2, + JH7100_CLK_DDRPLL_DIV2), + STARFIVE_GDIV(JH7100_CLK_DDRPLL_DIV8, "ddrpll_div8", CLK_IS_CRITICAL, 2, + JH7100_CLK_DDRPLL_DIV4), + STARFIVE_GDIV(JH7100_CLK_DDROSC_DIV2, "ddrosc_div2", CLK_IS_CRITICAL, 2, + JH7100_CLK_OSC_SYS), + STARFIVE_GMUX(JH7100_CLK_DDRC0, "ddrc0", CLK_IS_CRITICAL, 4, + JH7100_CLK_DDROSC_DIV2, + JH7100_CLK_DDRPLL_DIV2, + JH7100_CLK_DDRPLL_DIV4, + JH7100_CLK_DDRPLL_DIV8), + STARFIVE_GMUX(JH7100_CLK_DDRC1, "ddrc1", CLK_IS_CRITICAL, 4, + JH7100_CLK_DDROSC_DIV2, + JH7100_CLK_DDRPLL_DIV2, + JH7100_CLK_DDRPLL_DIV4, + JH7100_CLK_DDRPLL_DIV8), + STARFIVE_GATE(JH7100_CLK_DDRPHY_APB, "ddrphy_apb", 0, JH7100_CLK_APB1_BUS), + STARFIVE__DIV(JH7100_CLK_NOC_ROB, "noc_rob", 8, JH7100_CLK_CPUNBUS_ROOT_DIV), + STARFIVE__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT), + STARFIVE_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS), + STARFIVE__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT), + STARFIVE__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2, + JH7100_CLK_CPU_AXI, + JH7100_CLK_NNEBUS_SRC1), + STARFIVE_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS), + STARFIVE_GATE(JH7100_CLK_NNENOC_AXI, "nnenoc_axi", 0, JH7100_CLK_NNE_BUS), + STARFIVE_GATE(JH7100_CLK_DLASLV_AXI, "dlaslv_axi", 0, JH7100_CLK_NNE_BUS), + STARFIVE_GATE(JH7100_CLK_DSPX2C_AXI, "dspx2c_axi", CLK_IS_CRITICAL, JH7100_CLK_NNE_BUS), + STARFIVE__DIV(JH7100_CLK_HIFI4_SRC, "hifi4_src", 4, JH7100_CLK_CDECHIFI4_ROOT), + STARFIVE__DIV(JH7100_CLK_HIFI4_COREFREE, "hifi4_corefree", 8, JH7100_CLK_HIFI4_SRC), + STARFIVE_GATE(JH7100_CLK_HIFI4_CORE, "hifi4_core", 0, JH7100_CLK_HIFI4_COREFREE), + STARFIVE__DIV(JH7100_CLK_HIFI4_BUS, "hifi4_bus", 8, JH7100_CLK_HIFI4_COREFREE), + STARFIVE_GATE(JH7100_CLK_HIFI4_AXI, "hifi4_axi", 0, JH7100_CLK_HIFI4_BUS), + STARFIVE_GATE(JH7100_CLK_HIFI4NOC_AXI, "hifi4noc_axi", 0, JH7100_CLK_HIFI4_BUS), + STARFIVE__DIV(JH7100_CLK_SGDMA1P_BUS, "sgdma1p_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV), + STARFIVE_GATE(JH7100_CLK_SGDMA1P_AXI, "sgdma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS), + STARFIVE_GATE(JH7100_CLK_DMA1P_AXI, "dma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS), + STARFIVE_GDIV(JH7100_CLK_X2C_AXI, "x2c_axi", CLK_IS_CRITICAL, 8, + JH7100_CLK_CPUNBUS_ROOT_DIV), + STARFIVE__DIV(JH7100_CLK_USB_BUS, "usb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV), + STARFIVE_GATE(JH7100_CLK_USB_AXI, "usb_axi", 0, JH7100_CLK_USB_BUS), + STARFIVE_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi", 0, JH7100_CLK_USB_BUS), + STARFIVE__DIV(JH7100_CLK_USBPHY_ROOTDIV, "usbphy_rootdiv", 4, JH7100_CLK_GMACUSB_ROOT), + STARFIVE_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV), + STARFIVE_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32, + JH7100_CLK_USBPHY_ROOTDIV), + STARFIVE__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2, + JH7100_CLK_OSC_SYS, + JH7100_CLK_USBPHY_PLLDIV25M), + STARFIVE_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT), + STARFIVE_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV), + STARFIVE_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD), + STARFIVE_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT), + STARFIVE__DIV(JH7100_CLK_ISP0_BUS, "isp0_bus", 8, JH7100_CLK_VIN_SRC), + STARFIVE_GATE(JH7100_CLK_ISP0_AXI, "isp0_axi", 0, JH7100_CLK_ISP0_BUS), + STARFIVE_GATE(JH7100_CLK_ISP0NOC_AXI, "isp0noc_axi", 0, JH7100_CLK_ISP0_BUS), + STARFIVE_GATE(JH7100_CLK_ISPSLV_AXI, "ispslv_axi", 0, JH7100_CLK_ISP0_BUS), + STARFIVE__DIV(JH7100_CLK_ISP1_BUS, "isp1_bus", 8, JH7100_CLK_VIN_SRC), + STARFIVE_GATE(JH7100_CLK_ISP1_AXI, "isp1_axi", 0, JH7100_CLK_ISP1_BUS), + STARFIVE_GATE(JH7100_CLK_ISP1NOC_AXI, "isp1noc_axi", 0, JH7100_CLK_ISP1_BUS), + STARFIVE__DIV(JH7100_CLK_VIN_BUS, "vin_bus", 8, JH7100_CLK_VIN_SRC), + STARFIVE_GATE(JH7100_CLK_VIN_AXI, "vin_axi", 0, JH7100_CLK_VIN_BUS), + STARFIVE_GATE(JH7100_CLK_VINNOC_AXI, "vinnoc_axi", 0, JH7100_CLK_VIN_BUS), + STARFIVE_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", 0, 4, JH7100_CLK_VOUT_ROOT), + STARFIVE__DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src", 4, JH7100_CLK_VOUTBUS_ROOT), + STARFIVE__DIV(JH7100_CLK_DISP_BUS, "disp_bus", 4, JH7100_CLK_DISPBUS_SRC), + STARFIVE_GATE(JH7100_CLK_DISP_AXI, "disp_axi", 0, JH7100_CLK_DISP_BUS), + STARFIVE_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", 0, JH7100_CLK_DISP_BUS), + STARFIVE_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb", 0, JH7100_CLK_AHB_BUS), + STARFIVE_GDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint", 0, 24, JH7100_CLK_PERH0_SRC), + STARFIVE__INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv", JH7100_CLK_SDIO0_CCLKINT), + STARFIVE_GATE(JH7100_CLK_SDIO1_AHB, "sdio1_ahb", 0, JH7100_CLK_AHB_BUS), + STARFIVE_GDIV(JH7100_CLK_SDIO1_CCLKINT, "sdio1_cclkint", 0, 24, JH7100_CLK_PERH1_SRC), + STARFIVE__INV(JH7100_CLK_SDIO1_CCLKINT_INV, "sdio1_cclkint_inv", JH7100_CLK_SDIO1_CCLKINT), + STARFIVE_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", 0, JH7100_CLK_AHB_BUS), + STARFIVE__DIV(JH7100_CLK_GMAC_ROOT_DIV, "gmac_root_div", 8, JH7100_CLK_GMACUSB_ROOT), + STARFIVE_GDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk", 0, 31, JH7100_CLK_GMAC_ROOT_DIV), + STARFIVE_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV), + STARFIVE_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF), + STARFIVE_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF), + STARFIVE__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3, + JH7100_CLK_GMAC_GTX, + JH7100_CLK_GMAC_TX_INV, + JH7100_CLK_GMAC_RMII_TX), + STARFIVE__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX), + STARFIVE__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2, + JH7100_CLK_GMAC_GR_MII_RX, + JH7100_CLK_GMAC_RMII_RX), + STARFIVE__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE), + STARFIVE_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii", 0, JH7100_CLK_GMAC_RMII_REF), + STARFIVE_GDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref", 0, 127, JH7100_CLK_GMAC_ROOT_DIV), + STARFIVE_GATE(JH7100_CLK_SPI2AHB_AHB, "spi2ahb_ahb", 0, JH7100_CLK_AHB_BUS), + STARFIVE_GDIV(JH7100_CLK_SPI2AHB_CORE, "spi2ahb_core", 0, 31, JH7100_CLK_PERH0_SRC), + STARFIVE_GATE(JH7100_CLK_EZMASTER_AHB, "ezmaster_ahb", 0, JH7100_CLK_AHB_BUS), + STARFIVE_GATE(JH7100_CLK_E24_AHB, "e24_ahb", 0, JH7100_CLK_AHB_BUS), + STARFIVE_GATE(JH7100_CLK_E24RTC_TOGGLE, "e24rtc_toggle", 0, JH7100_CLK_OSC_SYS), + STARFIVE_GATE(JH7100_CLK_QSPI_AHB, "qspi_ahb", 0, JH7100_CLK_AHB_BUS), + STARFIVE_GATE(JH7100_CLK_QSPI_APB, "qspi_apb", 0, JH7100_CLK_APB1_BUS), + STARFIVE_GDIV(JH7100_CLK_QSPI_REF, "qspi_refclk", 0, 31, JH7100_CLK_PERH0_SRC), + STARFIVE_GATE(JH7100_CLK_SEC_AHB, "sec_ahb", 0, JH7100_CLK_AHB_BUS), + STARFIVE_GATE(JH7100_CLK_AES, "aes_clk", 0, JH7100_CLK_SEC_AHB), + STARFIVE_GATE(JH7100_CLK_SHA, "sha_clk", 0, JH7100_CLK_SEC_AHB), + STARFIVE_GATE(JH7100_CLK_PKA, "pka_clk", 0, JH7100_CLK_SEC_AHB), + STARFIVE_GATE(JH7100_CLK_TRNG_APB, "trng_apb", 0, JH7100_CLK_APB1_BUS), + STARFIVE_GATE(JH7100_CLK_OTP_APB, "otp_apb", 0, JH7100_CLK_APB1_BUS), + STARFIVE_GATE(JH7100_CLK_UART0_APB, "uart0_apb", 0, JH7100_CLK_APB1_BUS), + STARFIVE_GDIV(JH7100_CLK_UART0_CORE, "uart0_core", 0, 63, JH7100_CLK_PERH1_SRC), + STARFIVE_GATE(JH7100_CLK_UART1_APB, "uart1_apb", 0, JH7100_CLK_APB1_BUS), + STARFIVE_GDIV(JH7100_CLK_UART1_CORE, "uart1_core", 0, 63, JH7100_CLK_PERH1_SRC), + STARFIVE_GATE(JH7100_CLK_SPI0_APB, "spi0_apb", 0, JH7100_CLK_APB1_BUS), + STARFIVE_GDIV(JH7100_CLK_SPI0_CORE, "spi0_core", 0, 63, JH7100_CLK_PERH1_SRC), + STARFIVE_GATE(JH7100_CLK_SPI1_APB, "spi1_apb", 0, JH7100_CLK_APB1_BUS), + STARFIVE_GDIV(JH7100_CLK_SPI1_CORE, "spi1_core", 0, 63, JH7100_CLK_PERH1_SRC), + STARFIVE_GATE(JH7100_CLK_I2C0_APB, "i2c0_apb", 0, JH7100_CLK_APB1_BUS), + STARFIVE_GDIV(JH7100_CLK_I2C0_CORE, "i2c0_core", 0, 63, JH7100_CLK_PERH1_SRC), + STARFIVE_GATE(JH7100_CLK_I2C1_APB, "i2c1_apb", 0, JH7100_CLK_APB1_BUS), + STARFIVE_GDIV(JH7100_CLK_I2C1_CORE, "i2c1_core", 0, 63, JH7100_CLK_PERH1_SRC), + STARFIVE_GATE(JH7100_CLK_GPIO_APB, "gpio_apb", 0, JH7100_CLK_APB1_BUS), + STARFIVE_GATE(JH7100_CLK_UART2_APB, "uart2_apb", 0, JH7100_CLK_APB2_BUS), + STARFIVE_GDIV(JH7100_CLK_UART2_CORE, "uart2_core", 0, 63, JH7100_CLK_PERH0_SRC), + STARFIVE_GATE(JH7100_CLK_UART3_APB, "uart3_apb", 0, JH7100_CLK_APB2_BUS), + STARFIVE_GDIV(JH7100_CLK_UART3_CORE, "uart3_core", 0, 63, JH7100_CLK_PERH0_SRC), + STARFIVE_GATE(JH7100_CLK_SPI2_APB, "spi2_apb", 0, JH7100_CLK_APB2_BUS), + STARFIVE_GDIV(JH7100_CLK_SPI2_CORE, "spi2_core", 0, 63, JH7100_CLK_PERH0_SRC), + STARFIVE_GATE(JH7100_CLK_SPI3_APB, "spi3_apb", 0, JH7100_CLK_APB2_BUS), + STARFIVE_GDIV(JH7100_CLK_SPI3_CORE, "spi3_core", 0, 63, JH7100_CLK_PERH0_SRC), + STARFIVE_GATE(JH7100_CLK_I2C2_APB, "i2c2_apb", 0, JH7100_CLK_APB2_BUS), + STARFIVE_GDIV(JH7100_CLK_I2C2_CORE, "i2c2_core", 0, 63, JH7100_CLK_PERH0_SRC), + STARFIVE_GATE(JH7100_CLK_I2C3_APB, "i2c3_apb", 0, JH7100_CLK_APB2_BUS), + STARFIVE_GDIV(JH7100_CLK_I2C3_CORE, "i2c3_core", 0, 63, JH7100_CLK_PERH0_SRC), + STARFIVE_GATE(JH7100_CLK_WDTIMER_APB, "wdtimer_apb", 0, JH7100_CLK_APB2_BUS), + STARFIVE_GDIV(JH7100_CLK_WDT_CORE, "wdt_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), + STARFIVE_GDIV(JH7100_CLK_TIMER0_CORE, "timer0_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), + STARFIVE_GDIV(JH7100_CLK_TIMER1_CORE, "timer1_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), + STARFIVE_GDIV(JH7100_CLK_TIMER2_CORE, "timer2_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), + STARFIVE_GDIV(JH7100_CLK_TIMER3_CORE, "timer3_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), + STARFIVE_GDIV(JH7100_CLK_TIMER4_CORE, "timer4_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), + STARFIVE_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), + STARFIVE_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk", 0, 63, JH7100_CLK_PERH0_SRC), + STARFIVE_GATE(JH7100_CLK_VP6INTC_APB, "vp6intc_apb", 0, JH7100_CLK_APB2_BUS), + STARFIVE_GATE(JH7100_CLK_PWM_APB, "pwm_apb", 0, JH7100_CLK_APB2_BUS), + STARFIVE_GATE(JH7100_CLK_MSI_APB, "msi_apb", 0, JH7100_CLK_APB2_BUS), + STARFIVE_GATE(JH7100_CLK_TEMP_APB, "temp_apb", 0, JH7100_CLK_APB2_BUS), + STARFIVE_GDIV(JH7100_CLK_TEMP_SENSE, "temp_sense", 0, 31, JH7100_CLK_OSC_SYS), + STARFIVE_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS), }; static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data) { - struct jh71x0_clk_priv *priv = data; + struct starfive_clk_priv *priv = data; unsigned int idx = clkspec->args[0]; if (idx < JH7100_CLK_PLL0_OUT) @@ -283,7 +287,7 @@ static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data static int __init clk_starfive_jh7100_probe(struct platform_device *pdev) { - struct jh71x0_clk_priv *priv; + struct starfive_clk_priv *priv; unsigned int idx; int ret; @@ -317,12 +321,13 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev) struct clk_parent_data parents[4] = {}; struct clk_init_data init = { .name = jh7100_clk_data[idx].name, - .ops = starfive_jh71x0_clk_ops(max), + .ops = starfive_clk_ops(max), .parent_data = parents, - .num_parents = ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1, + .num_parents = ((max & STARFIVE_CLK_MUX_MASK) + >> STARFIVE_CLK_MUX_SHIFT) + 1, .flags = jh7100_clk_data[idx].flags, }; - struct jh71x0_clk *clk = &priv->reg[idx]; + struct starfive_clk *clk = &priv->reg[idx]; unsigned int i; for (i = 0; i < init.num_parents; i++) { @@ -344,7 +349,7 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev) clk->hw.init = &init; clk->idx = idx; - clk->max_div = max & JH71X0_CLK_DIV_MASK; + clk->max_div = max & STARFIVE_CLK_DIV_MASK; ret = devm_clk_hw_register(priv->dev, &clk->hw); if (ret) diff --git a/drivers/clk/starfive/clk-starfive-jh7110-aon.c b/drivers/clk/starfive/clk-starfive-jh7110-aon.c index 62954eb7b50a..a7ce89b566eb 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110-aon.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-aon.c @@ -23,40 +23,40 @@ #define JH7110_AONCLK_GMAC0_GTXCLK (JH7110_AONCLK_END + 5) #define JH7110_AONCLK_RTC_OSC (JH7110_AONCLK_END + 6) -static const struct jh71x0_clk_data jh7110_aonclk_data[] = { +static const struct starfive_clk_data jh7110_aonclk_data[] = { /* source */ - JH71X0__DIV(JH7110_AONCLK_OSC_DIV4, "osc_div4", 4, JH7110_AONCLK_OSC), - JH71X0__MUX(JH7110_AONCLK_APB_FUNC, "apb_func", 2, - JH7110_AONCLK_OSC_DIV4, - JH7110_AONCLK_OSC), + STARFIVE__DIV(JH7110_AONCLK_OSC_DIV4, "osc_div4", 4, JH7110_AONCLK_OSC), + STARFIVE__MUX(JH7110_AONCLK_APB_FUNC, "apb_func", 2, + JH7110_AONCLK_OSC_DIV4, + JH7110_AONCLK_OSC), /* gmac0 */ - JH71X0_GATE(JH7110_AONCLK_GMAC0_AHB, "gmac0_ahb", 0, JH7110_AONCLK_STG_AXIAHB), - JH71X0_GATE(JH7110_AONCLK_GMAC0_AXI, "gmac0_axi", 0, JH7110_AONCLK_STG_AXIAHB), - JH71X0__DIV(JH7110_AONCLK_GMAC0_RMII_RTX, "gmac0_rmii_rtx", 30, - JH7110_AONCLK_GMAC0_RMII_REFIN), - JH71X0_GMUX(JH7110_AONCLK_GMAC0_TX, "gmac0_tx", - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2, - JH7110_AONCLK_GMAC0_GTXCLK, - JH7110_AONCLK_GMAC0_RMII_RTX), - JH71X0__INV(JH7110_AONCLK_GMAC0_TX_INV, "gmac0_tx_inv", JH7110_AONCLK_GMAC0_TX), - JH71X0__MUX(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", 2, - JH7110_AONCLK_GMAC0_RGMII_RXIN, - JH7110_AONCLK_GMAC0_RMII_RTX), - JH71X0__INV(JH7110_AONCLK_GMAC0_RX_INV, "gmac0_rx_inv", JH7110_AONCLK_GMAC0_RX), + STARFIVE_GATE(JH7110_AONCLK_GMAC0_AHB, "gmac0_ahb", 0, JH7110_AONCLK_STG_AXIAHB), + STARFIVE_GATE(JH7110_AONCLK_GMAC0_AXI, "gmac0_axi", 0, JH7110_AONCLK_STG_AXIAHB), + STARFIVE__DIV(JH7110_AONCLK_GMAC0_RMII_RTX, "gmac0_rmii_rtx", 30, + JH7110_AONCLK_GMAC0_RMII_REFIN), + STARFIVE_GMUX(JH7110_AONCLK_GMAC0_TX, "gmac0_tx", + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2, + JH7110_AONCLK_GMAC0_GTXCLK, + JH7110_AONCLK_GMAC0_RMII_RTX), + STARFIVE__INV(JH7110_AONCLK_GMAC0_TX_INV, "gmac0_tx_inv", JH7110_AONCLK_GMAC0_TX), + STARFIVE__MUX(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", 2, + JH7110_AONCLK_GMAC0_RGMII_RXIN, + JH7110_AONCLK_GMAC0_RMII_RTX), + STARFIVE__INV(JH7110_AONCLK_GMAC0_RX_INV, "gmac0_rx_inv", JH7110_AONCLK_GMAC0_RX), /* otpc */ - JH71X0_GATE(JH7110_AONCLK_OTPC_APB, "otpc_apb", 0, JH7110_AONCLK_APB_BUS), + STARFIVE_GATE(JH7110_AONCLK_OTPC_APB, "otpc_apb", 0, JH7110_AONCLK_APB_BUS), /* rtc */ - JH71X0_GATE(JH7110_AONCLK_RTC_APB, "rtc_apb", 0, JH7110_AONCLK_APB_BUS), - JH71X0__DIV(JH7110_AONCLK_RTC_INTERNAL, "rtc_internal", 1022, JH7110_AONCLK_OSC), - JH71X0__MUX(JH7110_AONCLK_RTC_32K, "rtc_32k", 2, - JH7110_AONCLK_RTC_OSC, - JH7110_AONCLK_RTC_INTERNAL), - JH71X0_GATE(JH7110_AONCLK_RTC_CAL, "rtc_cal", 0, JH7110_AONCLK_OSC), + STARFIVE_GATE(JH7110_AONCLK_RTC_APB, "rtc_apb", 0, JH7110_AONCLK_APB_BUS), + STARFIVE__DIV(JH7110_AONCLK_RTC_INTERNAL, "rtc_internal", 1022, JH7110_AONCLK_OSC), + STARFIVE__MUX(JH7110_AONCLK_RTC_32K, "rtc_32k", 2, + JH7110_AONCLK_RTC_OSC, + JH7110_AONCLK_RTC_INTERNAL), + STARFIVE_GATE(JH7110_AONCLK_RTC_CAL, "rtc_cal", 0, JH7110_AONCLK_OSC), }; static struct clk_hw *jh7110_aonclk_get(struct of_phandle_args *clkspec, void *data) { - struct jh71x0_clk_priv *priv = data; + struct starfive_clk_priv *priv = data; unsigned int idx = clkspec->args[0]; if (idx < JH7110_AONCLK_END) @@ -67,7 +67,7 @@ static struct clk_hw *jh7110_aonclk_get(struct of_phandle_args *clkspec, void *d static int jh7110_aoncrg_probe(struct platform_device *pdev) { - struct jh71x0_clk_priv *priv; + struct starfive_clk_priv *priv; unsigned int idx; int ret; @@ -88,13 +88,13 @@ static int jh7110_aoncrg_probe(struct platform_device *pdev) struct clk_parent_data parents[4] = {}; struct clk_init_data init = { .name = jh7110_aonclk_data[idx].name, - .ops = starfive_jh71x0_clk_ops(max), + .ops = starfive_clk_ops(max), .parent_data = parents, .num_parents = - ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1, + ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1, .flags = jh7110_aonclk_data[idx].flags, }; - struct jh71x0_clk *clk = &priv->reg[idx]; + struct starfive_clk *clk = &priv->reg[idx]; unsigned int i; for (i = 0; i < init.num_parents; i++) { @@ -120,7 +120,7 @@ static int jh7110_aoncrg_probe(struct platform_device *pdev) clk->hw.init = &init; clk->idx = idx; - clk->max_div = max & JH71X0_CLK_DIV_MASK; + clk->max_div = max & STARFIVE_CLK_DIV_MASK; ret = devm_clk_hw_register(&pdev->dev, &clk->hw); if (ret) diff --git a/drivers/clk/starfive/clk-starfive-jh7110-isp.c b/drivers/clk/starfive/clk-starfive-jh7110-isp.c index ce034ed28532..be6040f718c0 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110-isp.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-isp.c @@ -28,41 +28,41 @@ static struct clk_bulk_data jh7110_isp_top_clks[] = { { .id = "isp_top_axi" } }; -static const struct jh71x0_clk_data jh7110_ispclk_data[] = { +static const struct starfive_clk_data jh7110_ispclk_data[] = { /* syscon */ - JH71X0__DIV(JH7110_ISPCLK_DOM4_APB_FUNC, "dom4_apb_func", 15, - JH7110_ISPCLK_ISP_TOP_AXI), - JH71X0__DIV(JH7110_ISPCLK_MIPI_RX0_PXL, "mipi_rx0_pxl", 8, - JH7110_ISPCLK_ISP_TOP_CORE), - JH71X0__INV(JH7110_ISPCLK_DVP_INV, "dvp_inv", JH7110_ISPCLK_DVP_CLK), + STARFIVE__DIV(JH7110_ISPCLK_DOM4_APB_FUNC, "dom4_apb_func", 15, + JH7110_ISPCLK_ISP_TOP_AXI), + STARFIVE__DIV(JH7110_ISPCLK_MIPI_RX0_PXL, "mipi_rx0_pxl", 8, + JH7110_ISPCLK_ISP_TOP_CORE), + STARFIVE__INV(JH7110_ISPCLK_DVP_INV, "dvp_inv", JH7110_ISPCLK_DVP_CLK), /* vin */ - JH71X0__DIV(JH7110_ISPCLK_M31DPHY_CFG_IN, "m31dphy_cfg_in", 16, - JH7110_ISPCLK_ISP_TOP_CORE), - JH71X0__DIV(JH7110_ISPCLK_M31DPHY_REF_IN, "m31dphy_ref_in", 16, - JH7110_ISPCLK_ISP_TOP_CORE), - JH71X0__DIV(JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0, "m31dphy_tx_esc_lan0", 60, - JH7110_ISPCLK_ISP_TOP_CORE), - JH71X0_GATE(JH7110_ISPCLK_VIN_APB, "vin_apb", 0, - JH7110_ISPCLK_DOM4_APB_FUNC), - JH71X0__DIV(JH7110_ISPCLK_VIN_SYS, "vin_sys", 8, JH7110_ISPCLK_ISP_TOP_CORE), - JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF0, "vin_pixel_if0", 0, - JH7110_ISPCLK_MIPI_RX0_PXL), - JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF1, "vin_pixel_if1", 0, - JH7110_ISPCLK_MIPI_RX0_PXL), - JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF2, "vin_pixel_if2", 0, - JH7110_ISPCLK_MIPI_RX0_PXL), - JH71X0_GATE(JH7110_ISPCLK_VIN_PIXEL_IF3, "vin_pixel_if3", 0, - JH7110_ISPCLK_MIPI_RX0_PXL), - JH71X0__MUX(JH7110_ISPCLK_VIN_P_AXI_WR, "vin_p_axi_wr", 2, - JH7110_ISPCLK_MIPI_RX0_PXL, - JH7110_ISPCLK_DVP_INV), + STARFIVE__DIV(JH7110_ISPCLK_M31DPHY_CFG_IN, "m31dphy_cfg_in", 16, + JH7110_ISPCLK_ISP_TOP_CORE), + STARFIVE__DIV(JH7110_ISPCLK_M31DPHY_REF_IN, "m31dphy_ref_in", 16, + JH7110_ISPCLK_ISP_TOP_CORE), + STARFIVE__DIV(JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0, "m31dphy_tx_esc_lan0", 60, + JH7110_ISPCLK_ISP_TOP_CORE), + STARFIVE_GATE(JH7110_ISPCLK_VIN_APB, "vin_apb", 0, + JH7110_ISPCLK_DOM4_APB_FUNC), + STARFIVE__DIV(JH7110_ISPCLK_VIN_SYS, "vin_sys", 8, JH7110_ISPCLK_ISP_TOP_CORE), + STARFIVE_GATE(JH7110_ISPCLK_VIN_PIXEL_IF0, "vin_pixel_if0", 0, + JH7110_ISPCLK_MIPI_RX0_PXL), + STARFIVE_GATE(JH7110_ISPCLK_VIN_PIXEL_IF1, "vin_pixel_if1", 0, + JH7110_ISPCLK_MIPI_RX0_PXL), + STARFIVE_GATE(JH7110_ISPCLK_VIN_PIXEL_IF2, "vin_pixel_if2", 0, + JH7110_ISPCLK_MIPI_RX0_PXL), + STARFIVE_GATE(JH7110_ISPCLK_VIN_PIXEL_IF3, "vin_pixel_if3", 0, + JH7110_ISPCLK_MIPI_RX0_PXL), + STARFIVE__MUX(JH7110_ISPCLK_VIN_P_AXI_WR, "vin_p_axi_wr", 2, + JH7110_ISPCLK_MIPI_RX0_PXL, + JH7110_ISPCLK_DVP_INV), /* ispv2_top_wrapper */ - JH71X0_GMUX(JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C, "ispv2_top_wrapper_c", 0, 2, - JH7110_ISPCLK_MIPI_RX0_PXL, - JH7110_ISPCLK_DVP_INV), + STARFIVE_GMUX(JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C, "ispv2_top_wrapper_c", 0, 2, + JH7110_ISPCLK_MIPI_RX0_PXL, + JH7110_ISPCLK_DVP_INV), }; -static inline int jh7110_isp_top_rst_init(struct jh71x0_clk_priv *priv) +static inline int jh7110_isp_top_rst_init(struct starfive_clk_priv *priv) { struct reset_control *top_rsts; @@ -77,7 +77,7 @@ static inline int jh7110_isp_top_rst_init(struct jh71x0_clk_priv *priv) static struct clk_hw *jh7110_ispclk_get(struct of_phandle_args *clkspec, void *data) { - struct jh71x0_clk_priv *priv = data; + struct starfive_clk_priv *priv = data; unsigned int idx = clkspec->args[0]; if (idx < JH7110_ISPCLK_END) @@ -110,7 +110,7 @@ static const struct dev_pm_ops jh7110_ispcrg_pm_ops = { static int jh7110_ispcrg_probe(struct platform_device *pdev) { - struct jh71x0_clk_priv *priv; + struct starfive_clk_priv *priv; struct jh7110_top_sysclk *top; unsigned int idx; int ret; @@ -153,13 +153,13 @@ static int jh7110_ispcrg_probe(struct platform_device *pdev) struct clk_parent_data parents[4] = {}; struct clk_init_data init = { .name = jh7110_ispclk_data[idx].name, - .ops = starfive_jh71x0_clk_ops(max), + .ops = starfive_clk_ops(max), .parent_data = parents, .num_parents = - ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1, + ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1, .flags = jh7110_ispclk_data[idx].flags, }; - struct jh71x0_clk *clk = &priv->reg[idx]; + struct starfive_clk *clk = &priv->reg[idx]; unsigned int i; const char *fw_name[JH7110_ISPCLK_EXT_END - JH7110_ISPCLK_END] = { "isp_top_core", @@ -179,7 +179,7 @@ static int jh7110_ispcrg_probe(struct platform_device *pdev) clk->hw.init = &init; clk->idx = idx; - clk->max_div = max & JH71X0_CLK_DIV_MASK; + clk->max_div = max & STARFIVE_CLK_DIV_MASK; ret = devm_clk_hw_register(&pdev->dev, &clk->hw); if (ret) diff --git a/drivers/clk/starfive/clk-starfive-jh7110-stg.c b/drivers/clk/starfive/clk-starfive-jh7110-stg.c index dafcb7190592..2d6ee0ad343a 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110-stg.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-stg.c @@ -25,59 +25,59 @@ #define JH7110_STGCLK_APB_BUS (JH7110_STGCLK_END + 7) #define JH7110_STGCLK_EXT_END (JH7110_STGCLK_END + 8) -static const struct jh71x0_clk_data jh7110_stgclk_data[] = { +static const struct starfive_clk_data jh7110_stgclk_data[] = { /* hifi4 */ - JH71X0_GATE(JH7110_STGCLK_HIFI4_CLK_CORE, "hifi4_clk_core", 0, - JH7110_STGCLK_HIFI4_CORE), + STARFIVE_GATE(JH7110_STGCLK_HIFI4_CLK_CORE, "hifi4_clk_core", 0, + JH7110_STGCLK_HIFI4_CORE), /* usb */ - JH71X0_GATE(JH7110_STGCLK_USB0_APB, "usb0_apb", 0, JH7110_STGCLK_APB_BUS), - JH71X0_GATE(JH7110_STGCLK_USB0_UTMI_APB, "usb0_utmi_apb", 0, JH7110_STGCLK_APB_BUS), - JH71X0_GATE(JH7110_STGCLK_USB0_AXI, "usb0_axi", 0, JH7110_STGCLK_STG_AXIAHB), - JH71X0_GDIV(JH7110_STGCLK_USB0_LPM, "usb0_lpm", 0, 2, JH7110_STGCLK_OSC), - JH71X0_GDIV(JH7110_STGCLK_USB0_STB, "usb0_stb", 0, 4, JH7110_STGCLK_OSC), - JH71X0_GATE(JH7110_STGCLK_USB0_APP_125, "usb0_app_125", 0, JH7110_STGCLK_USB_125M), - JH71X0__DIV(JH7110_STGCLK_USB0_REFCLK, "usb0_refclk", 2, JH7110_STGCLK_OSC), + STARFIVE_GATE(JH7110_STGCLK_USB0_APB, "usb0_apb", 0, JH7110_STGCLK_APB_BUS), + STARFIVE_GATE(JH7110_STGCLK_USB0_UTMI_APB, "usb0_utmi_apb", 0, JH7110_STGCLK_APB_BUS), + STARFIVE_GATE(JH7110_STGCLK_USB0_AXI, "usb0_axi", 0, JH7110_STGCLK_STG_AXIAHB), + STARFIVE_GDIV(JH7110_STGCLK_USB0_LPM, "usb0_lpm", 0, 2, JH7110_STGCLK_OSC), + STARFIVE_GDIV(JH7110_STGCLK_USB0_STB, "usb0_stb", 0, 4, JH7110_STGCLK_OSC), + STARFIVE_GATE(JH7110_STGCLK_USB0_APP_125, "usb0_app_125", 0, JH7110_STGCLK_USB_125M), + STARFIVE__DIV(JH7110_STGCLK_USB0_REFCLK, "usb0_refclk", 2, JH7110_STGCLK_OSC), /* pci-e */ - JH71X0_GATE(JH7110_STGCLK_PCIE0_AXI_MST0, "pcie0_axi_mst0", 0, - JH7110_STGCLK_STG_AXIAHB), - JH71X0_GATE(JH7110_STGCLK_PCIE0_APB, "pcie0_apb", 0, JH7110_STGCLK_APB_BUS), - JH71X0_GATE(JH7110_STGCLK_PCIE0_TL, "pcie0_tl", 0, JH7110_STGCLK_STG_AXIAHB), - JH71X0_GATE(JH7110_STGCLK_PCIE1_AXI_MST0, "pcie1_axi_mst0", 0, - JH7110_STGCLK_STG_AXIAHB), - JH71X0_GATE(JH7110_STGCLK_PCIE1_APB, "pcie1_apb", 0, JH7110_STGCLK_APB_BUS), - JH71X0_GATE(JH7110_STGCLK_PCIE1_TL, "pcie1_tl", 0, JH7110_STGCLK_STG_AXIAHB), - JH71X0_GATE(JH7110_STGCLK_PCIE_SLV_MAIN, "pcie_slv_main", CLK_IS_CRITICAL, - JH7110_STGCLK_STG_AXIAHB), + STARFIVE_GATE(JH7110_STGCLK_PCIE0_AXI_MST0, "pcie0_axi_mst0", 0, + JH7110_STGCLK_STG_AXIAHB), + STARFIVE_GATE(JH7110_STGCLK_PCIE0_APB, "pcie0_apb", 0, JH7110_STGCLK_APB_BUS), + STARFIVE_GATE(JH7110_STGCLK_PCIE0_TL, "pcie0_tl", 0, JH7110_STGCLK_STG_AXIAHB), + STARFIVE_GATE(JH7110_STGCLK_PCIE1_AXI_MST0, "pcie1_axi_mst0", 0, + JH7110_STGCLK_STG_AXIAHB), + STARFIVE_GATE(JH7110_STGCLK_PCIE1_APB, "pcie1_apb", 0, JH7110_STGCLK_APB_BUS), + STARFIVE_GATE(JH7110_STGCLK_PCIE1_TL, "pcie1_tl", 0, JH7110_STGCLK_STG_AXIAHB), + STARFIVE_GATE(JH7110_STGCLK_PCIE_SLV_MAIN, "pcie_slv_main", CLK_IS_CRITICAL, + JH7110_STGCLK_STG_AXIAHB), /* security */ - JH71X0_GATE(JH7110_STGCLK_SEC_AHB, "sec_ahb", 0, JH7110_STGCLK_STG_AXIAHB), - JH71X0_GATE(JH7110_STGCLK_SEC_MISC_AHB, "sec_misc_ahb", 0, JH7110_STGCLK_STG_AXIAHB), + STARFIVE_GATE(JH7110_STGCLK_SEC_AHB, "sec_ahb", 0, JH7110_STGCLK_STG_AXIAHB), + STARFIVE_GATE(JH7110_STGCLK_SEC_MISC_AHB, "sec_misc_ahb", 0, JH7110_STGCLK_STG_AXIAHB), /* stg mtrx */ - JH71X0_GATE(JH7110_STGCLK_GRP0_MAIN, "mtrx_grp0_main", CLK_IS_CRITICAL, - JH7110_STGCLK_CPU_BUS), - JH71X0_GATE(JH7110_STGCLK_GRP0_BUS, "mtrx_grp0_bus", CLK_IS_CRITICAL, - JH7110_STGCLK_NOCSTG_BUS), - JH71X0_GATE(JH7110_STGCLK_GRP0_STG, "mtrx_grp0_stg", CLK_IS_CRITICAL, - JH7110_STGCLK_STG_AXIAHB), - JH71X0_GATE(JH7110_STGCLK_GRP1_MAIN, "mtrx_grp1_main", CLK_IS_CRITICAL, - JH7110_STGCLK_CPU_BUS), - JH71X0_GATE(JH7110_STGCLK_GRP1_BUS, "mtrx_grp1_bus", CLK_IS_CRITICAL, - JH7110_STGCLK_NOCSTG_BUS), - JH71X0_GATE(JH7110_STGCLK_GRP1_STG, "mtrx_grp1_stg", CLK_IS_CRITICAL, - JH7110_STGCLK_STG_AXIAHB), - JH71X0_GATE(JH7110_STGCLK_GRP1_HIFI, "mtrx_grp1_hifi", CLK_IS_CRITICAL, - JH7110_STGCLK_HIFI4_AXI), + STARFIVE_GATE(JH7110_STGCLK_GRP0_MAIN, "mtrx_grp0_main", CLK_IS_CRITICAL, + JH7110_STGCLK_CPU_BUS), + STARFIVE_GATE(JH7110_STGCLK_GRP0_BUS, "mtrx_grp0_bus", CLK_IS_CRITICAL, + JH7110_STGCLK_NOCSTG_BUS), + STARFIVE_GATE(JH7110_STGCLK_GRP0_STG, "mtrx_grp0_stg", CLK_IS_CRITICAL, + JH7110_STGCLK_STG_AXIAHB), + STARFIVE_GATE(JH7110_STGCLK_GRP1_MAIN, "mtrx_grp1_main", CLK_IS_CRITICAL, + JH7110_STGCLK_CPU_BUS), + STARFIVE_GATE(JH7110_STGCLK_GRP1_BUS, "mtrx_grp1_bus", CLK_IS_CRITICAL, + JH7110_STGCLK_NOCSTG_BUS), + STARFIVE_GATE(JH7110_STGCLK_GRP1_STG, "mtrx_grp1_stg", CLK_IS_CRITICAL, + JH7110_STGCLK_STG_AXIAHB), + STARFIVE_GATE(JH7110_STGCLK_GRP1_HIFI, "mtrx_grp1_hifi", CLK_IS_CRITICAL, + JH7110_STGCLK_HIFI4_AXI), /* e24_rvpi */ - JH71X0_GDIV(JH7110_STGCLK_E2_RTC, "e2_rtc", 0, 24, JH7110_STGCLK_OSC), - JH71X0_GATE(JH7110_STGCLK_E2_CORE, "e2_core", 0, JH7110_STGCLK_STG_AXIAHB), - JH71X0_GATE(JH7110_STGCLK_E2_DBG, "e2_dbg", 0, JH7110_STGCLK_STG_AXIAHB), + STARFIVE_GDIV(JH7110_STGCLK_E2_RTC, "e2_rtc", 0, 24, JH7110_STGCLK_OSC), + STARFIVE_GATE(JH7110_STGCLK_E2_CORE, "e2_core", 0, JH7110_STGCLK_STG_AXIAHB), + STARFIVE_GATE(JH7110_STGCLK_E2_DBG, "e2_dbg", 0, JH7110_STGCLK_STG_AXIAHB), /* dw_sgdma1p */ - JH71X0_GATE(JH7110_STGCLK_DMA1P_AXI, "dma1p_axi", 0, JH7110_STGCLK_STG_AXIAHB), - JH71X0_GATE(JH7110_STGCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7110_STGCLK_STG_AXIAHB), + STARFIVE_GATE(JH7110_STGCLK_DMA1P_AXI, "dma1p_axi", 0, JH7110_STGCLK_STG_AXIAHB), + STARFIVE_GATE(JH7110_STGCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7110_STGCLK_STG_AXIAHB), }; static struct clk_hw *jh7110_stgclk_get(struct of_phandle_args *clkspec, void *data) { - struct jh71x0_clk_priv *priv = data; + struct starfive_clk_priv *priv = data; unsigned int idx = clkspec->args[0]; if (idx < JH7110_STGCLK_END) @@ -88,7 +88,7 @@ static struct clk_hw *jh7110_stgclk_get(struct of_phandle_args *clkspec, void *d static int jh7110_stgcrg_probe(struct platform_device *pdev) { - struct jh71x0_clk_priv *priv; + struct starfive_clk_priv *priv; unsigned int idx; int ret; @@ -108,13 +108,13 @@ static int jh7110_stgcrg_probe(struct platform_device *pdev) struct clk_parent_data parents[4] = {}; struct clk_init_data init = { .name = jh7110_stgclk_data[idx].name, - .ops = starfive_jh71x0_clk_ops(max), + .ops = starfive_clk_ops(max), .parent_data = parents, .num_parents = - ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1, + ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1, .flags = jh7110_stgclk_data[idx].flags, }; - struct jh71x0_clk *clk = &priv->reg[idx]; + struct starfive_clk *clk = &priv->reg[idx]; const char *fw_name[JH7110_STGCLK_EXT_END - JH7110_STGCLK_END] = { "osc", "hifi4_core", @@ -138,7 +138,7 @@ static int jh7110_stgcrg_probe(struct platform_device *pdev) clk->hw.init = &init; clk->idx = idx; - clk->max_div = max & JH71X0_CLK_DIV_MASK; + clk->max_div = max & STARFIVE_CLK_DIV_MASK; ret = devm_clk_hw_register(&pdev->dev, &clk->hw); if (ret) diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c index e63353c70209..00ef88d9c2fd 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c @@ -34,298 +34,301 @@ #define JH7110_SYSCLK_PLL1_OUT (JH7110_SYSCLK_END + 10) #define JH7110_SYSCLK_PLL2_OUT (JH7110_SYSCLK_END + 11) -static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = { +static const struct starfive_clk_data jh7110_sysclk_data[] __initconst = { /* root */ - JH71X0__MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", 2, - JH7110_SYSCLK_OSC, - JH7110_SYSCLK_PLL0_OUT), - JH71X0__DIV(JH7110_SYSCLK_CPU_CORE, "cpu_core", 7, JH7110_SYSCLK_CPU_ROOT), - JH71X0__DIV(JH7110_SYSCLK_CPU_BUS, "cpu_bus", 2, JH7110_SYSCLK_CPU_CORE), - JH71X0__MUX(JH7110_SYSCLK_GPU_ROOT, "gpu_root", 2, - JH7110_SYSCLK_PLL2_OUT, - JH7110_SYSCLK_PLL1_OUT), - JH71X0_MDIV(JH7110_SYSCLK_PERH_ROOT, "perh_root", 2, 2, - JH7110_SYSCLK_PLL0_OUT, - JH7110_SYSCLK_PLL2_OUT), - JH71X0__MUX(JH7110_SYSCLK_BUS_ROOT, "bus_root", 2, - JH7110_SYSCLK_OSC, - JH7110_SYSCLK_PLL2_OUT), - JH71X0__DIV(JH7110_SYSCLK_NOCSTG_BUS, "nocstg_bus", 3, JH7110_SYSCLK_BUS_ROOT), - JH71X0__DIV(JH7110_SYSCLK_AXI_CFG0, "axi_cfg0", 3, JH7110_SYSCLK_BUS_ROOT), - JH71X0__DIV(JH7110_SYSCLK_STG_AXIAHB, "stg_axiahb", 2, JH7110_SYSCLK_AXI_CFG0), - JH71X0_GATE(JH7110_SYSCLK_AHB0, "ahb0", CLK_IS_CRITICAL, JH7110_SYSCLK_STG_AXIAHB), - JH71X0_GATE(JH7110_SYSCLK_AHB1, "ahb1", CLK_IS_CRITICAL, JH7110_SYSCLK_STG_AXIAHB), - JH71X0__DIV(JH7110_SYSCLK_APB_BUS, "apb_bus", 8, JH7110_SYSCLK_STG_AXIAHB), - JH71X0_GATE(JH7110_SYSCLK_APB0, "apb0", CLK_IS_CRITICAL, JH7110_SYSCLK_APB_BUS), - JH71X0__DIV(JH7110_SYSCLK_PLL0_DIV2, "pll0_div2", 2, JH7110_SYSCLK_PLL0_OUT), - JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV2, "pll1_div2", 2, JH7110_SYSCLK_PLL1_OUT), - JH71X0__DIV(JH7110_SYSCLK_PLL2_DIV2, "pll2_div2", 2, JH7110_SYSCLK_PLL2_OUT), - JH71X0__DIV(JH7110_SYSCLK_AUDIO_ROOT, "audio_root", 8, JH7110_SYSCLK_PLL2_OUT), - JH71X0__DIV(JH7110_SYSCLK_MCLK_INNER, "mclk_inner", 64, JH7110_SYSCLK_AUDIO_ROOT), - JH71X0__MUX(JH7110_SYSCLK_MCLK, "mclk", 2, - JH7110_SYSCLK_MCLK_INNER, - JH7110_SYSCLK_MCLK_EXT), - JH71X0_GATE(JH7110_SYSCLK_MCLK_OUT, "mclk_out", 0, JH7110_SYSCLK_MCLK_INNER), - JH71X0_MDIV(JH7110_SYSCLK_ISP_2X, "isp_2x", 8, 2, - JH7110_SYSCLK_PLL2_OUT, - JH7110_SYSCLK_PLL1_OUT), - JH71X0__DIV(JH7110_SYSCLK_ISP_AXI, "isp_axi", 4, JH7110_SYSCLK_ISP_2X), - JH71X0_GDIV(JH7110_SYSCLK_GCLK0, "gclk0", 0, 62, JH7110_SYSCLK_PLL0_DIV2), - JH71X0_GDIV(JH7110_SYSCLK_GCLK1, "gclk1", 0, 62, JH7110_SYSCLK_PLL1_DIV2), - JH71X0_GDIV(JH7110_SYSCLK_GCLK2, "gclk2", 0, 62, JH7110_SYSCLK_PLL2_DIV2), + STARFIVE__MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", 2, + JH7110_SYSCLK_OSC, + JH7110_SYSCLK_PLL0_OUT), + STARFIVE__DIV(JH7110_SYSCLK_CPU_CORE, "cpu_core", 7, JH7110_SYSCLK_CPU_ROOT), + STARFIVE__DIV(JH7110_SYSCLK_CPU_BUS, "cpu_bus", 2, JH7110_SYSCLK_CPU_CORE), + STARFIVE__MUX(JH7110_SYSCLK_GPU_ROOT, "gpu_root", 2, + JH7110_SYSCLK_PLL2_OUT, + JH7110_SYSCLK_PLL1_OUT), + STARFIVE_MDIV(JH7110_SYSCLK_PERH_ROOT, "perh_root", 2, 2, + JH7110_SYSCLK_PLL0_OUT, + JH7110_SYSCLK_PLL2_OUT), + STARFIVE__MUX(JH7110_SYSCLK_BUS_ROOT, "bus_root", 2, + JH7110_SYSCLK_OSC, + JH7110_SYSCLK_PLL2_OUT), + STARFIVE__DIV(JH7110_SYSCLK_NOCSTG_BUS, "nocstg_bus", 3, JH7110_SYSCLK_BUS_ROOT), + STARFIVE__DIV(JH7110_SYSCLK_AXI_CFG0, "axi_cfg0", 3, JH7110_SYSCLK_BUS_ROOT), + STARFIVE__DIV(JH7110_SYSCLK_STG_AXIAHB, "stg_axiahb", 2, JH7110_SYSCLK_AXI_CFG0), + STARFIVE_GATE(JH7110_SYSCLK_AHB0, "ahb0", CLK_IS_CRITICAL, JH7110_SYSCLK_STG_AXIAHB), + STARFIVE_GATE(JH7110_SYSCLK_AHB1, "ahb1", CLK_IS_CRITICAL, JH7110_SYSCLK_STG_AXIAHB), + STARFIVE__DIV(JH7110_SYSCLK_APB_BUS, "apb_bus", 8, JH7110_SYSCLK_STG_AXIAHB), + STARFIVE_GATE(JH7110_SYSCLK_APB0, "apb0", CLK_IS_CRITICAL, JH7110_SYSCLK_APB_BUS), + STARFIVE__DIV(JH7110_SYSCLK_PLL0_DIV2, "pll0_div2", 2, JH7110_SYSCLK_PLL0_OUT), + STARFIVE__DIV(JH7110_SYSCLK_PLL1_DIV2, "pll1_div2", 2, JH7110_SYSCLK_PLL1_OUT), + STARFIVE__DIV(JH7110_SYSCLK_PLL2_DIV2, "pll2_div2", 2, JH7110_SYSCLK_PLL2_OUT), + STARFIVE__DIV(JH7110_SYSCLK_AUDIO_ROOT, "audio_root", 8, JH7110_SYSCLK_PLL2_OUT), + STARFIVE__DIV(JH7110_SYSCLK_MCLK_INNER, "mclk_inner", 64, JH7110_SYSCLK_AUDIO_ROOT), + STARFIVE__MUX(JH7110_SYSCLK_MCLK, "mclk", 2, + JH7110_SYSCLK_MCLK_INNER, + JH7110_SYSCLK_MCLK_EXT), + STARFIVE_GATE(JH7110_SYSCLK_MCLK_OUT, "mclk_out", 0, JH7110_SYSCLK_MCLK_INNER), + STARFIVE_MDIV(JH7110_SYSCLK_ISP_2X, "isp_2x", 8, 2, + JH7110_SYSCLK_PLL2_OUT, + JH7110_SYSCLK_PLL1_OUT), + STARFIVE__DIV(JH7110_SYSCLK_ISP_AXI, "isp_axi", 4, JH7110_SYSCLK_ISP_2X), + STARFIVE_GDIV(JH7110_SYSCLK_GCLK0, "gclk0", 0, 62, JH7110_SYSCLK_PLL0_DIV2), + STARFIVE_GDIV(JH7110_SYSCLK_GCLK1, "gclk1", 0, 62, JH7110_SYSCLK_PLL1_DIV2), + STARFIVE_GDIV(JH7110_SYSCLK_GCLK2, "gclk2", 0, 62, JH7110_SYSCLK_PLL2_DIV2), /* cores */ - JH71X0_GATE(JH7110_SYSCLK_CORE, "core", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE), - JH71X0_GATE(JH7110_SYSCLK_CORE1, "core1", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE), - JH71X0_GATE(JH7110_SYSCLK_CORE2, "core2", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE), - JH71X0_GATE(JH7110_SYSCLK_CORE3, "core3", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE), - JH71X0_GATE(JH7110_SYSCLK_CORE4, "core4", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE), - JH71X0_GATE(JH7110_SYSCLK_DEBUG, "debug", 0, JH7110_SYSCLK_CPU_BUS), - JH71X0__DIV(JH7110_SYSCLK_RTC_TOGGLE, "rtc_toggle", 6, JH7110_SYSCLK_OSC), - JH71X0_GATE(JH7110_SYSCLK_TRACE0, "trace0", 0, JH7110_SYSCLK_CPU_CORE), - JH71X0_GATE(JH7110_SYSCLK_TRACE1, "trace1", 0, JH7110_SYSCLK_CPU_CORE), - JH71X0_GATE(JH7110_SYSCLK_TRACE2, "trace2", 0, JH7110_SYSCLK_CPU_CORE), - JH71X0_GATE(JH7110_SYSCLK_TRACE3, "trace3", 0, JH7110_SYSCLK_CPU_CORE), - JH71X0_GATE(JH7110_SYSCLK_TRACE4, "trace4", 0, JH7110_SYSCLK_CPU_CORE), - JH71X0_GATE(JH7110_SYSCLK_TRACE_COM, "trace_com", 0, JH7110_SYSCLK_CPU_BUS), + STARFIVE_GATE(JH7110_SYSCLK_CORE, "core", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE), + STARFIVE_GATE(JH7110_SYSCLK_CORE1, "core1", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE), + STARFIVE_GATE(JH7110_SYSCLK_CORE2, "core2", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE), + STARFIVE_GATE(JH7110_SYSCLK_CORE3, "core3", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE), + STARFIVE_GATE(JH7110_SYSCLK_CORE4, "core4", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE), + STARFIVE_GATE(JH7110_SYSCLK_DEBUG, "debug", 0, JH7110_SYSCLK_CPU_BUS), + STARFIVE__DIV(JH7110_SYSCLK_RTC_TOGGLE, "rtc_toggle", 6, JH7110_SYSCLK_OSC), + STARFIVE_GATE(JH7110_SYSCLK_TRACE0, "trace0", 0, JH7110_SYSCLK_CPU_CORE), + STARFIVE_GATE(JH7110_SYSCLK_TRACE1, "trace1", 0, JH7110_SYSCLK_CPU_CORE), + STARFIVE_GATE(JH7110_SYSCLK_TRACE2, "trace2", 0, JH7110_SYSCLK_CPU_CORE), + STARFIVE_GATE(JH7110_SYSCLK_TRACE3, "trace3", 0, JH7110_SYSCLK_CPU_CORE), + STARFIVE_GATE(JH7110_SYSCLK_TRACE4, "trace4", 0, JH7110_SYSCLK_CPU_CORE), + STARFIVE_GATE(JH7110_SYSCLK_TRACE_COM, "trace_com", 0, JH7110_SYSCLK_CPU_BUS), /* noc */ - JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_CPU_AXI, "noc_bus_cpu_axi", CLK_IS_CRITICAL, - JH7110_SYSCLK_CPU_BUS), - JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI, "noc_bus_axicfg0_axi", CLK_IS_CRITICAL, - JH7110_SYSCLK_AXI_CFG0), + STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_CPU_AXI, "noc_bus_cpu_axi", CLK_IS_CRITICAL, + JH7110_SYSCLK_CPU_BUS), + STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI, "noc_bus_axicfg0_axi", CLK_IS_CRITICAL, + JH7110_SYSCLK_AXI_CFG0), /* ddr */ - JH71X0__DIV(JH7110_SYSCLK_OSC_DIV2, "osc_div2", 2, JH7110_SYSCLK_OSC), - JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV4, "pll1_div4", 2, JH7110_SYSCLK_PLL1_DIV2), - JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV8, "pll1_div8", 2, JH7110_SYSCLK_PLL1_DIV4), - JH71X0__MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", 4, - JH7110_SYSCLK_OSC_DIV2, - JH7110_SYSCLK_PLL1_DIV2, - JH7110_SYSCLK_PLL1_DIV4, - JH7110_SYSCLK_PLL1_DIV8), - JH71X0_GATE(JH7110_SYSCLK_DDR_AXI, "ddr_axi", CLK_IS_CRITICAL, JH7110_SYSCLK_DDR_BUS), + STARFIVE__DIV(JH7110_SYSCLK_OSC_DIV2, "osc_div2", 2, JH7110_SYSCLK_OSC), + STARFIVE__DIV(JH7110_SYSCLK_PLL1_DIV4, "pll1_div4", 2, JH7110_SYSCLK_PLL1_DIV2), + STARFIVE__DIV(JH7110_SYSCLK_PLL1_DIV8, "pll1_div8", 2, JH7110_SYSCLK_PLL1_DIV4), + STARFIVE__MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", 4, + JH7110_SYSCLK_OSC_DIV2, + JH7110_SYSCLK_PLL1_DIV2, + JH7110_SYSCLK_PLL1_DIV4, + JH7110_SYSCLK_PLL1_DIV8), + STARFIVE_GATE(JH7110_SYSCLK_DDR_AXI, "ddr_axi", CLK_IS_CRITICAL, JH7110_SYSCLK_DDR_BUS), /* gpu */ - JH71X0__DIV(JH7110_SYSCLK_GPU_CORE, "gpu_core", 7, JH7110_SYSCLK_GPU_ROOT), - JH71X0_GATE(JH7110_SYSCLK_GPU_CORE_CLK, "gpu_core_clk", 0, JH7110_SYSCLK_GPU_CORE), - JH71X0_GATE(JH7110_SYSCLK_GPU_SYS_CLK, "gpu_sys_clk", 0, JH7110_SYSCLK_ISP_AXI), - JH71X0_GATE(JH7110_SYSCLK_GPU_APB, "gpu_apb", 0, JH7110_SYSCLK_APB_BUS), - JH71X0_GDIV(JH7110_SYSCLK_GPU_RTC_TOGGLE, "gpu_rtc_toggle", 0, 12, JH7110_SYSCLK_OSC), - JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_GPU_AXI, "noc_bus_gpu_axi", 0, JH7110_SYSCLK_GPU_CORE), + STARFIVE__DIV(JH7110_SYSCLK_GPU_CORE, "gpu_core", 7, JH7110_SYSCLK_GPU_ROOT), + STARFIVE_GATE(JH7110_SYSCLK_GPU_CORE_CLK, "gpu_core_clk", 0, JH7110_SYSCLK_GPU_CORE), + STARFIVE_GATE(JH7110_SYSCLK_GPU_SYS_CLK, "gpu_sys_clk", 0, JH7110_SYSCLK_ISP_AXI), + STARFIVE_GATE(JH7110_SYSCLK_GPU_APB, "gpu_apb", 0, JH7110_SYSCLK_APB_BUS), + STARFIVE_GDIV(JH7110_SYSCLK_GPU_RTC_TOGGLE, "gpu_rtc_toggle", 0, 12, JH7110_SYSCLK_OSC), + STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_GPU_AXI, "noc_bus_gpu_axi", 0, JH7110_SYSCLK_GPU_CORE), /* isp */ - JH71X0_GATE(JH7110_SYSCLK_ISP_TOP_CORE, "isp_top_core", 0, JH7110_SYSCLK_ISP_2X), - JH71X0_GATE(JH7110_SYSCLK_ISP_TOP_AXI, "isp_top_axi", 0, JH7110_SYSCLK_ISP_AXI), - JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_ISP_AXI, "noc_bus_isp_axi", CLK_IS_CRITICAL, - JH7110_SYSCLK_ISP_AXI), + STARFIVE_GATE(JH7110_SYSCLK_ISP_TOP_CORE, "isp_top_core", 0, JH7110_SYSCLK_ISP_2X), + STARFIVE_GATE(JH7110_SYSCLK_ISP_TOP_AXI, "isp_top_axi", 0, JH7110_SYSCLK_ISP_AXI), + STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_ISP_AXI, "noc_bus_isp_axi", CLK_IS_CRITICAL, + JH7110_SYSCLK_ISP_AXI), /* hifi4 */ - JH71X0__DIV(JH7110_SYSCLK_HIFI4_CORE, "hifi4_core", 15, JH7110_SYSCLK_BUS_ROOT), - JH71X0__DIV(JH7110_SYSCLK_HIFI4_AXI, "hifi4_axi", 2, JH7110_SYSCLK_HIFI4_CORE), + STARFIVE__DIV(JH7110_SYSCLK_HIFI4_CORE, "hifi4_core", 15, JH7110_SYSCLK_BUS_ROOT), + STARFIVE__DIV(JH7110_SYSCLK_HIFI4_AXI, "hifi4_axi", 2, JH7110_SYSCLK_HIFI4_CORE), /* axi_cfg1 */ - JH71X0_GATE(JH7110_SYSCLK_AXI_CFG1_MAIN, "axi_cfg1_main", CLK_IS_CRITICAL, - JH7110_SYSCLK_ISP_AXI), - JH71X0_GATE(JH7110_SYSCLK_AXI_CFG1_AHB, "axi_cfg1_ahb", CLK_IS_CRITICAL, - JH7110_SYSCLK_AHB0), + STARFIVE_GATE(JH7110_SYSCLK_AXI_CFG1_MAIN, "axi_cfg1_main", CLK_IS_CRITICAL, + JH7110_SYSCLK_ISP_AXI), + STARFIVE_GATE(JH7110_SYSCLK_AXI_CFG1_AHB, "axi_cfg1_ahb", CLK_IS_CRITICAL, + JH7110_SYSCLK_AHB0), /* vout */ - JH71X0_GATE(JH7110_SYSCLK_VOUT_SRC, "vout_src", 0, JH7110_SYSCLK_PLL2_OUT), - JH71X0__DIV(JH7110_SYSCLK_VOUT_AXI, "vout_axi", 7, JH7110_SYSCLK_PLL2_OUT), - JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_DISP_AXI, "noc_bus_disp_axi", 0, JH7110_SYSCLK_VOUT_AXI), - JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_AHB, "vout_top_ahb", 0, JH7110_SYSCLK_AHB1), - JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_AXI, "vout_top_axi", 0, JH7110_SYSCLK_VOUT_AXI), - JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK, "vout_top_hdmitx0_mclk", 0, - JH7110_SYSCLK_MCLK), - JH71X0__DIV(JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF, "vout_top_mipiphy_ref", 2, - JH7110_SYSCLK_OSC), + STARFIVE_GATE(JH7110_SYSCLK_VOUT_SRC, "vout_src", 0, JH7110_SYSCLK_PLL2_OUT), + STARFIVE__DIV(JH7110_SYSCLK_VOUT_AXI, "vout_axi", 7, JH7110_SYSCLK_PLL2_OUT), + STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_DISP_AXI, "noc_bus_disp_axi", 0, + JH7110_SYSCLK_VOUT_AXI), + STARFIVE_GATE(JH7110_SYSCLK_VOUT_TOP_AHB, "vout_top_ahb", 0, JH7110_SYSCLK_AHB1), + STARFIVE_GATE(JH7110_SYSCLK_VOUT_TOP_AXI, "vout_top_axi", 0, JH7110_SYSCLK_VOUT_AXI), + STARFIVE_GATE(JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK, "vout_top_hdmitx0_mclk", 0, + JH7110_SYSCLK_MCLK), + STARFIVE__DIV(JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF, "vout_top_mipiphy_ref", 2, + JH7110_SYSCLK_OSC), /* jpegc */ - JH71X0__DIV(JH7110_SYSCLK_JPEGC_AXI, "jpegc_axi", 16, JH7110_SYSCLK_PLL2_OUT), - JH71X0_GATE(JH7110_SYSCLK_CODAJ12_AXI, "codaj12_axi", 0, JH7110_SYSCLK_JPEGC_AXI), - JH71X0_GDIV(JH7110_SYSCLK_CODAJ12_CORE, "codaj12_core", 0, 16, JH7110_SYSCLK_PLL2_OUT), - JH71X0_GATE(JH7110_SYSCLK_CODAJ12_APB, "codaj12_apb", 0, JH7110_SYSCLK_APB_BUS), + STARFIVE__DIV(JH7110_SYSCLK_JPEGC_AXI, "jpegc_axi", 16, JH7110_SYSCLK_PLL2_OUT), + STARFIVE_GATE(JH7110_SYSCLK_CODAJ12_AXI, "codaj12_axi", 0, JH7110_SYSCLK_JPEGC_AXI), + STARFIVE_GDIV(JH7110_SYSCLK_CODAJ12_CORE, "codaj12_core", 0, 16, JH7110_SYSCLK_PLL2_OUT), + STARFIVE_GATE(JH7110_SYSCLK_CODAJ12_APB, "codaj12_apb", 0, JH7110_SYSCLK_APB_BUS), /* vdec */ - JH71X0__DIV(JH7110_SYSCLK_VDEC_AXI, "vdec_axi", 7, JH7110_SYSCLK_BUS_ROOT), - JH71X0_GATE(JH7110_SYSCLK_WAVE511_AXI, "wave511_axi", 0, JH7110_SYSCLK_VDEC_AXI), - JH71X0_GDIV(JH7110_SYSCLK_WAVE511_BPU, "wave511_bpu", 0, 7, JH7110_SYSCLK_BUS_ROOT), - JH71X0_GDIV(JH7110_SYSCLK_WAVE511_VCE, "wave511_vce", 0, 7, JH7110_SYSCLK_PLL0_OUT), - JH71X0_GATE(JH7110_SYSCLK_WAVE511_APB, "wave511_apb", 0, JH7110_SYSCLK_APB_BUS), - JH71X0_GATE(JH7110_SYSCLK_VDEC_JPG, "vdec_jpg", 0, JH7110_SYSCLK_JPEGC_AXI), - JH71X0_GATE(JH7110_SYSCLK_VDEC_MAIN, "vdec_main", 0, JH7110_SYSCLK_VDEC_AXI), - JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_VDEC_AXI, "noc_bus_vdec_axi", 0, JH7110_SYSCLK_VDEC_AXI), + STARFIVE__DIV(JH7110_SYSCLK_VDEC_AXI, "vdec_axi", 7, JH7110_SYSCLK_BUS_ROOT), + STARFIVE_GATE(JH7110_SYSCLK_WAVE511_AXI, "wave511_axi", 0, JH7110_SYSCLK_VDEC_AXI), + STARFIVE_GDIV(JH7110_SYSCLK_WAVE511_BPU, "wave511_bpu", 0, 7, JH7110_SYSCLK_BUS_ROOT), + STARFIVE_GDIV(JH7110_SYSCLK_WAVE511_VCE, "wave511_vce", 0, 7, JH7110_SYSCLK_PLL0_OUT), + STARFIVE_GATE(JH7110_SYSCLK_WAVE511_APB, "wave511_apb", 0, JH7110_SYSCLK_APB_BUS), + STARFIVE_GATE(JH7110_SYSCLK_VDEC_JPG, "vdec_jpg", 0, JH7110_SYSCLK_JPEGC_AXI), + STARFIVE_GATE(JH7110_SYSCLK_VDEC_MAIN, "vdec_main", 0, JH7110_SYSCLK_VDEC_AXI), + STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_VDEC_AXI, "noc_bus_vdec_axi", 0, + JH7110_SYSCLK_VDEC_AXI), /* venc */ - JH71X0__DIV(JH7110_SYSCLK_VENC_AXI, "venc_axi", 15, JH7110_SYSCLK_PLL2_OUT), - JH71X0_GATE(JH7110_SYSCLK_WAVE420L_AXI, "wave420l_axi", 0, JH7110_SYSCLK_VENC_AXI), - JH71X0_GDIV(JH7110_SYSCLK_WAVE420L_BPU, "wave420l_bpu", 0, 15, JH7110_SYSCLK_PLL2_OUT), - JH71X0_GDIV(JH7110_SYSCLK_WAVE420L_VCE, "wave420l_vce", 0, 15, JH7110_SYSCLK_PLL2_OUT), - JH71X0_GATE(JH7110_SYSCLK_WAVE420L_APB, "wave420l_apb", 0, JH7110_SYSCLK_APB_BUS), - JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_VENC_AXI, "noc_bus_venc_axi", 0, JH7110_SYSCLK_VENC_AXI), + STARFIVE__DIV(JH7110_SYSCLK_VENC_AXI, "venc_axi", 15, JH7110_SYSCLK_PLL2_OUT), + STARFIVE_GATE(JH7110_SYSCLK_WAVE420L_AXI, "wave420l_axi", 0, JH7110_SYSCLK_VENC_AXI), + STARFIVE_GDIV(JH7110_SYSCLK_WAVE420L_BPU, "wave420l_bpu", 0, 15, JH7110_SYSCLK_PLL2_OUT), + STARFIVE_GDIV(JH7110_SYSCLK_WAVE420L_VCE, "wave420l_vce", 0, 15, JH7110_SYSCLK_PLL2_OUT), + STARFIVE_GATE(JH7110_SYSCLK_WAVE420L_APB, "wave420l_apb", 0, JH7110_SYSCLK_APB_BUS), + STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_VENC_AXI, "noc_bus_venc_axi", 0, + JH7110_SYSCLK_VENC_AXI), /* axi_cfg0 */ - JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN_DIV, "axi_cfg0_main_div", CLK_IS_CRITICAL, - JH7110_SYSCLK_AHB1), - JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN, "axi_cfg0_main", CLK_IS_CRITICAL, - JH7110_SYSCLK_AXI_CFG0), - JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_HIFI4, "axi_cfg0_hifi4", CLK_IS_CRITICAL, - JH7110_SYSCLK_HIFI4_AXI), + STARFIVE_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN_DIV, "axi_cfg0_main_div", CLK_IS_CRITICAL, + JH7110_SYSCLK_AHB1), + STARFIVE_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN, "axi_cfg0_main", CLK_IS_CRITICAL, + JH7110_SYSCLK_AXI_CFG0), + STARFIVE_GATE(JH7110_SYSCLK_AXI_CFG0_HIFI4, "axi_cfg0_hifi4", CLK_IS_CRITICAL, + JH7110_SYSCLK_HIFI4_AXI), /* intmem */ - JH71X0_GATE(JH7110_SYSCLK_AXIMEM2_AXI, "aximem2_axi", 0, JH7110_SYSCLK_AXI_CFG0), + STARFIVE_GATE(JH7110_SYSCLK_AXIMEM2_AXI, "aximem2_axi", 0, JH7110_SYSCLK_AXI_CFG0), /* qspi */ - JH71X0_GATE(JH7110_SYSCLK_QSPI_AHB, "qspi_ahb", 0, JH7110_SYSCLK_AHB1), - JH71X0_GATE(JH7110_SYSCLK_QSPI_APB, "qspi_apb", 0, JH7110_SYSCLK_APB_BUS), - JH71X0__DIV(JH7110_SYSCLK_QSPI_REF_SRC, "qspi_ref_src", 16, JH7110_SYSCLK_PLL0_OUT), - JH71X0_GMUX(JH7110_SYSCLK_QSPI_REF, "qspi_ref", 0, 2, - JH7110_SYSCLK_OSC, - JH7110_SYSCLK_QSPI_REF_SRC), + STARFIVE_GATE(JH7110_SYSCLK_QSPI_AHB, "qspi_ahb", 0, JH7110_SYSCLK_AHB1), + STARFIVE_GATE(JH7110_SYSCLK_QSPI_APB, "qspi_apb", 0, JH7110_SYSCLK_APB_BUS), + STARFIVE__DIV(JH7110_SYSCLK_QSPI_REF_SRC, "qspi_ref_src", 16, JH7110_SYSCLK_PLL0_OUT), + STARFIVE_GMUX(JH7110_SYSCLK_QSPI_REF, "qspi_ref", 0, 2, + JH7110_SYSCLK_OSC, + JH7110_SYSCLK_QSPI_REF_SRC), /* sdio */ - JH71X0_GATE(JH7110_SYSCLK_SDIO0_AHB, "sdio0_ahb", 0, JH7110_SYSCLK_AHB0), - JH71X0_GATE(JH7110_SYSCLK_SDIO1_AHB, "sdio1_ahb", 0, JH7110_SYSCLK_AHB0), - JH71X0_GDIV(JH7110_SYSCLK_SDIO0_SDCARD, "sdio0_sdcard", 0, 15, JH7110_SYSCLK_AXI_CFG0), - JH71X0_GDIV(JH7110_SYSCLK_SDIO1_SDCARD, "sdio1_sdcard", 0, 15, JH7110_SYSCLK_AXI_CFG0), + STARFIVE_GATE(JH7110_SYSCLK_SDIO0_AHB, "sdio0_ahb", 0, JH7110_SYSCLK_AHB0), + STARFIVE_GATE(JH7110_SYSCLK_SDIO1_AHB, "sdio1_ahb", 0, JH7110_SYSCLK_AHB0), + STARFIVE_GDIV(JH7110_SYSCLK_SDIO0_SDCARD, "sdio0_sdcard", 0, 15, JH7110_SYSCLK_AXI_CFG0), + STARFIVE_GDIV(JH7110_SYSCLK_SDIO1_SDCARD, "sdio1_sdcard", 0, 15, JH7110_SYSCLK_AXI_CFG0), /* stg */ - JH71X0__DIV(JH7110_SYSCLK_USB_125M, "usb_125m", 15, JH7110_SYSCLK_PLL0_OUT), - JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_STG_AXI, "noc_bus_stg_axi", CLK_IS_CRITICAL, - JH7110_SYSCLK_NOCSTG_BUS), + STARFIVE__DIV(JH7110_SYSCLK_USB_125M, "usb_125m", 15, JH7110_SYSCLK_PLL0_OUT), + STARFIVE_GATE(JH7110_SYSCLK_NOC_BUS_STG_AXI, "noc_bus_stg_axi", CLK_IS_CRITICAL, + JH7110_SYSCLK_NOCSTG_BUS), /* gmac1 */ - JH71X0_GATE(JH7110_SYSCLK_GMAC1_AHB, "gmac1_ahb", 0, JH7110_SYSCLK_AHB0), - JH71X0_GATE(JH7110_SYSCLK_GMAC1_AXI, "gmac1_axi", 0, JH7110_SYSCLK_STG_AXIAHB), - JH71X0__DIV(JH7110_SYSCLK_GMAC_SRC, "gmac_src", 7, JH7110_SYSCLK_PLL0_OUT), - JH71X0__DIV(JH7110_SYSCLK_GMAC1_GTXCLK, "gmac1_gtxclk", 15, JH7110_SYSCLK_PLL0_OUT), - JH71X0__DIV(JH7110_SYSCLK_GMAC1_RMII_RTX, "gmac1_rmii_rtx", 30, - JH7110_SYSCLK_GMAC1_RMII_REFIN), - JH71X0_GDIV(JH7110_SYSCLK_GMAC1_PTP, "gmac1_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC), - JH71X0__MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", 2, - JH7110_SYSCLK_GMAC1_RGMII_RXIN, - JH7110_SYSCLK_GMAC1_RMII_RTX), - JH71X0__INV(JH7110_SYSCLK_GMAC1_RX_INV, "gmac1_rx_inv", JH7110_SYSCLK_GMAC1_RX), - JH71X0_GMUX(JH7110_SYSCLK_GMAC1_TX, "gmac1_tx", - CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2, - JH7110_SYSCLK_GMAC1_GTXCLK, - JH7110_SYSCLK_GMAC1_RMII_RTX), - JH71X0__INV(JH7110_SYSCLK_GMAC1_TX_INV, "gmac1_tx_inv", JH7110_SYSCLK_GMAC1_TX), - JH71X0_GATE(JH7110_SYSCLK_GMAC1_GTXC, "gmac1_gtxc", 0, JH7110_SYSCLK_GMAC1_GTXCLK), + STARFIVE_GATE(JH7110_SYSCLK_GMAC1_AHB, "gmac1_ahb", 0, JH7110_SYSCLK_AHB0), + STARFIVE_GATE(JH7110_SYSCLK_GMAC1_AXI, "gmac1_axi", 0, JH7110_SYSCLK_STG_AXIAHB), + STARFIVE__DIV(JH7110_SYSCLK_GMAC_SRC, "gmac_src", 7, JH7110_SYSCLK_PLL0_OUT), + STARFIVE__DIV(JH7110_SYSCLK_GMAC1_GTXCLK, "gmac1_gtxclk", 15, JH7110_SYSCLK_PLL0_OUT), + STARFIVE__DIV(JH7110_SYSCLK_GMAC1_RMII_RTX, "gmac1_rmii_rtx", 30, + JH7110_SYSCLK_GMAC1_RMII_REFIN), + STARFIVE_GDIV(JH7110_SYSCLK_GMAC1_PTP, "gmac1_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC), + STARFIVE__MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", 2, + JH7110_SYSCLK_GMAC1_RGMII_RXIN, + JH7110_SYSCLK_GMAC1_RMII_RTX), + STARFIVE__INV(JH7110_SYSCLK_GMAC1_RX_INV, "gmac1_rx_inv", JH7110_SYSCLK_GMAC1_RX), + STARFIVE_GMUX(JH7110_SYSCLK_GMAC1_TX, "gmac1_tx", + CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, 2, + JH7110_SYSCLK_GMAC1_GTXCLK, + JH7110_SYSCLK_GMAC1_RMII_RTX), + STARFIVE__INV(JH7110_SYSCLK_GMAC1_TX_INV, "gmac1_tx_inv", JH7110_SYSCLK_GMAC1_TX), + STARFIVE_GATE(JH7110_SYSCLK_GMAC1_GTXC, "gmac1_gtxc", 0, JH7110_SYSCLK_GMAC1_GTXCLK), /* gmac0 */ - JH71X0_GDIV(JH7110_SYSCLK_GMAC0_GTXCLK, "gmac0_gtxclk", 0, 15, JH7110_SYSCLK_PLL0_OUT), - JH71X0_GDIV(JH7110_SYSCLK_GMAC0_PTP, "gmac0_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC), - JH71X0_GDIV(JH7110_SYSCLK_GMAC_PHY, "gmac_phy", 0, 31, JH7110_SYSCLK_GMAC_SRC), - JH71X0_GATE(JH7110_SYSCLK_GMAC0_GTXC, "gmac0_gtxc", 0, JH7110_SYSCLK_GMAC0_GTXCLK), + STARFIVE_GDIV(JH7110_SYSCLK_GMAC0_GTXCLK, "gmac0_gtxclk", 0, 15, JH7110_SYSCLK_PLL0_OUT), + STARFIVE_GDIV(JH7110_SYSCLK_GMAC0_PTP, "gmac0_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC), + STARFIVE_GDIV(JH7110_SYSCLK_GMAC_PHY, "gmac_phy", 0, 31, JH7110_SYSCLK_GMAC_SRC), + STARFIVE_GATE(JH7110_SYSCLK_GMAC0_GTXC, "gmac0_gtxc", 0, JH7110_SYSCLK_GMAC0_GTXCLK), /* apb misc */ - JH71X0_GATE(JH7110_SYSCLK_IOMUX_APB, "iomux_apb", 0, JH7110_SYSCLK_APB_BUS), - JH71X0_GATE(JH7110_SYSCLK_MAILBOX_APB, "mailbox_apb", 0, JH7110_SYSCLK_APB_BUS), - JH71X0_GATE(JH7110_SYSCLK_INT_CTRL_APB, "int_ctrl_apb", 0, JH7110_SYSCLK_APB_BUS), + STARFIVE_GATE(JH7110_SYSCLK_IOMUX_APB, "iomux_apb", 0, JH7110_SYSCLK_APB_BUS), + STARFIVE_GATE(JH7110_SYSCLK_MAILBOX_APB, "mailbox_apb", 0, JH7110_SYSCLK_APB_BUS), + STARFIVE_GATE(JH7110_SYSCLK_INT_CTRL_APB, "int_ctrl_apb", 0, JH7110_SYSCLK_APB_BUS), /* can0 */ - JH71X0_GATE(JH7110_SYSCLK_CAN0_APB, "can0_apb", 0, JH7110_SYSCLK_APB_BUS), - JH71X0_GDIV(JH7110_SYSCLK_CAN0_TIMER, "can0_timer", 0, 24, JH7110_SYSCLK_OSC), - JH71X0_GDIV(JH7110_SYSCLK_CAN0_CAN, "can0_can", 0, 63, JH7110_SYSCLK_PERH_ROOT), + STARFIVE_GATE(JH7110_SYSCLK_CAN0_APB, "can0_apb", 0, JH7110_SYSCLK_APB_BUS), + STARFIVE_GDIV(JH7110_SYSCLK_CAN0_TIMER, "can0_timer", 0, 24, JH7110_SYSCLK_OSC), + STARFIVE_GDIV(JH7110_SYSCLK_CAN0_CAN, "can0_can", 0, 63, JH7110_SYSCLK_PERH_ROOT), /* can1 */ - JH71X0_GATE(JH7110_SYSCLK_CAN1_APB, "can1_apb", 0, JH7110_SYSCLK_APB_BUS), - JH71X0_GDIV(JH7110_SYSCLK_CAN1_TIMER, "can1_timer", 0, 24, JH7110_SYSCLK_OSC), - JH71X0_GDIV(JH7110_SYSCLK_CAN1_CAN, "can1_can", 0, 63, JH7110_SYSCLK_PERH_ROOT), + STARFIVE_GATE(JH7110_SYSCLK_CAN1_APB, "can1_apb", 0, JH7110_SYSCLK_APB_BUS), + STARFIVE_GDIV(JH7110_SYSCLK_CAN1_TIMER, "can1_timer", 0, 24, JH7110_SYSCLK_OSC), + STARFIVE_GDIV(JH7110_SYSCLK_CAN1_CAN, "can1_can", 0, 63, JH7110_SYSCLK_PERH_ROOT), /* pwm */ - JH71X0_GATE(JH7110_SYSCLK_PWM_APB, "pwm_apb", 0, JH7110_SYSCLK_APB_BUS), + STARFIVE_GATE(JH7110_SYSCLK_PWM_APB, "pwm_apb", 0, JH7110_SYSCLK_APB_BUS), /* wdt */ - JH71X0_GATE(JH7110_SYSCLK_WDT_APB, "wdt_apb", 0, JH7110_SYSCLK_APB_BUS), - JH71X0_GATE(JH7110_SYSCLK_WDT_CORE, "wdt_core", 0, JH7110_SYSCLK_OSC), + STARFIVE_GATE(JH7110_SYSCLK_WDT_APB, "wdt_apb", 0, JH7110_SYSCLK_APB_BUS), + STARFIVE_GATE(JH7110_SYSCLK_WDT_CORE, "wdt_core", 0, JH7110_SYSCLK_OSC), /* timer */ - JH71X0_GATE(JH7110_SYSCLK_TIMER_APB, "timer_apb", 0, JH7110_SYSCLK_APB_BUS), - JH71X0_GATE(JH7110_SYSCLK_TIMER0, "timer0", 0, JH7110_SYSCLK_OSC), - JH71X0_GATE(JH7110_SYSCLK_TIMER1, "timer1", 0, JH7110_SYSCLK_OSC), - JH71X0_GATE(JH7110_SYSCLK_TIMER2, "timer2", 0, JH7110_SYSCLK_OSC), - JH71X0_GATE(JH7110_SYSCLK_TIMER3, "timer3", 0, JH7110_SYSCLK_OSC), + STARFIVE_GATE(JH7110_SYSCLK_TIMER_APB, "timer_apb", 0, JH7110_SYSCLK_APB_BUS), + STARFIVE_GATE(JH7110_SYSCLK_TIMER0, "timer0", 0, JH7110_SYSCLK_OSC), + STARFIVE_GATE(JH7110_SYSCLK_TIMER1, "timer1", 0, JH7110_SYSCLK_OSC), + STARFIVE_GATE(JH7110_SYSCLK_TIMER2, "timer2", 0, JH7110_SYSCLK_OSC), + STARFIVE_GATE(JH7110_SYSCLK_TIMER3, "timer3", 0, JH7110_SYSCLK_OSC), /* temp sensor */ - JH71X0_GATE(JH7110_SYSCLK_TEMP_APB, "temp_apb", 0, JH7110_SYSCLK_APB_BUS), - JH71X0_GDIV(JH7110_SYSCLK_TEMP_CORE, "temp_core", 0, 24, JH7110_SYSCLK_OSC), + STARFIVE_GATE(JH7110_SYSCLK_TEMP_APB, "temp_apb", 0, JH7110_SYSCLK_APB_BUS), + STARFIVE_GDIV(JH7110_SYSCLK_TEMP_CORE, "temp_core", 0, 24, JH7110_SYSCLK_OSC), /* spi */ - JH71X0_GATE(JH7110_SYSCLK_SPI0_APB, "spi0_apb", 0, JH7110_SYSCLK_APB0), - JH71X0_GATE(JH7110_SYSCLK_SPI1_APB, "spi1_apb", 0, JH7110_SYSCLK_APB0), - JH71X0_GATE(JH7110_SYSCLK_SPI2_APB, "spi2_apb", 0, JH7110_SYSCLK_APB0), - JH71X0_GATE(JH7110_SYSCLK_SPI3_APB, "spi3_apb", 0, JH7110_SYSCLK_APB_BUS), - JH71X0_GATE(JH7110_SYSCLK_SPI4_APB, "spi4_apb", 0, JH7110_SYSCLK_APB_BUS), - JH71X0_GATE(JH7110_SYSCLK_SPI5_APB, "spi5_apb", 0, JH7110_SYSCLK_APB_BUS), - JH71X0_GATE(JH7110_SYSCLK_SPI6_APB, "spi6_apb", 0, JH7110_SYSCLK_APB_BUS), + STARFIVE_GATE(JH7110_SYSCLK_SPI0_APB, "spi0_apb", 0, JH7110_SYSCLK_APB0), + STARFIVE_GATE(JH7110_SYSCLK_SPI1_APB, "spi1_apb", 0, JH7110_SYSCLK_APB0), + STARFIVE_GATE(JH7110_SYSCLK_SPI2_APB, "spi2_apb", 0, JH7110_SYSCLK_APB0), + STARFIVE_GATE(JH7110_SYSCLK_SPI3_APB, "spi3_apb", 0, JH7110_SYSCLK_APB_BUS), + STARFIVE_GATE(JH7110_SYSCLK_SPI4_APB, "spi4_apb", 0, JH7110_SYSCLK_APB_BUS), + STARFIVE_GATE(JH7110_SYSCLK_SPI5_APB, "spi5_apb", 0, JH7110_SYSCLK_APB_BUS), + STARFIVE_GATE(JH7110_SYSCLK_SPI6_APB, "spi6_apb", 0, JH7110_SYSCLK_APB_BUS), /* i2c */ - JH71X0_GATE(JH7110_SYSCLK_I2C0_APB, "i2c0_apb", 0, JH7110_SYSCLK_APB0), - JH71X0_GATE(JH7110_SYSCLK_I2C1_APB, "i2c1_apb", 0, JH7110_SYSCLK_APB0), - JH71X0_GATE(JH7110_SYSCLK_I2C2_APB, "i2c2_apb", 0, JH7110_SYSCLK_APB0), - JH71X0_GATE(JH7110_SYSCLK_I2C3_APB, "i2c3_apb", 0, JH7110_SYSCLK_APB_BUS), - JH71X0_GATE(JH7110_SYSCLK_I2C4_APB, "i2c4_apb", 0, JH7110_SYSCLK_APB_BUS), - JH71X0_GATE(JH7110_SYSCLK_I2C5_APB, "i2c5_apb", 0, JH7110_SYSCLK_APB_BUS), - JH71X0_GATE(JH7110_SYSCLK_I2C6_APB, "i2c6_apb", 0, JH7110_SYSCLK_APB_BUS), + STARFIVE_GATE(JH7110_SYSCLK_I2C0_APB, "i2c0_apb", 0, JH7110_SYSCLK_APB0), + STARFIVE_GATE(JH7110_SYSCLK_I2C1_APB, "i2c1_apb", 0, JH7110_SYSCLK_APB0), + STARFIVE_GATE(JH7110_SYSCLK_I2C2_APB, "i2c2_apb", 0, JH7110_SYSCLK_APB0), + STARFIVE_GATE(JH7110_SYSCLK_I2C3_APB, "i2c3_apb", 0, JH7110_SYSCLK_APB_BUS), + STARFIVE_GATE(JH7110_SYSCLK_I2C4_APB, "i2c4_apb", 0, JH7110_SYSCLK_APB_BUS), + STARFIVE_GATE(JH7110_SYSCLK_I2C5_APB, "i2c5_apb", 0, JH7110_SYSCLK_APB_BUS), + STARFIVE_GATE(JH7110_SYSCLK_I2C6_APB, "i2c6_apb", 0, JH7110_SYSCLK_APB_BUS), /* uart */ - JH71X0_GATE(JH7110_SYSCLK_UART0_APB, "uart0_apb", 0, JH7110_SYSCLK_APB0), - JH71X0_GATE(JH7110_SYSCLK_UART0_CORE, "uart0_core", 0, JH7110_SYSCLK_OSC), - JH71X0_GATE(JH7110_SYSCLK_UART1_APB, "uart1_apb", 0, JH7110_SYSCLK_APB0), - JH71X0_GATE(JH7110_SYSCLK_UART1_CORE, "uart1_core", 0, JH7110_SYSCLK_OSC), - JH71X0_GATE(JH7110_SYSCLK_UART2_APB, "uart2_apb", 0, JH7110_SYSCLK_APB0), - JH71X0_GATE(JH7110_SYSCLK_UART2_CORE, "uart2_core", 0, JH7110_SYSCLK_OSC), - JH71X0_GATE(JH7110_SYSCLK_UART3_APB, "uart3_apb", 0, JH7110_SYSCLK_APB0), - JH71X0_GDIV(JH7110_SYSCLK_UART3_CORE, "uart3_core", 0, 10, JH7110_SYSCLK_PERH_ROOT), - JH71X0_GATE(JH7110_SYSCLK_UART4_APB, "uart4_apb", 0, JH7110_SYSCLK_APB0), - JH71X0_GDIV(JH7110_SYSCLK_UART4_CORE, "uart4_core", 0, 10, JH7110_SYSCLK_PERH_ROOT), - JH71X0_GATE(JH7110_SYSCLK_UART5_APB, "uart5_apb", 0, JH7110_SYSCLK_APB0), - JH71X0_GDIV(JH7110_SYSCLK_UART5_CORE, "uart5_core", 0, 10, JH7110_SYSCLK_PERH_ROOT), + STARFIVE_GATE(JH7110_SYSCLK_UART0_APB, "uart0_apb", 0, JH7110_SYSCLK_APB0), + STARFIVE_GATE(JH7110_SYSCLK_UART0_CORE, "uart0_core", 0, JH7110_SYSCLK_OSC), + STARFIVE_GATE(JH7110_SYSCLK_UART1_APB, "uart1_apb", 0, JH7110_SYSCLK_APB0), + STARFIVE_GATE(JH7110_SYSCLK_UART1_CORE, "uart1_core", 0, JH7110_SYSCLK_OSC), + STARFIVE_GATE(JH7110_SYSCLK_UART2_APB, "uart2_apb", 0, JH7110_SYSCLK_APB0), + STARFIVE_GATE(JH7110_SYSCLK_UART2_CORE, "uart2_core", 0, JH7110_SYSCLK_OSC), + STARFIVE_GATE(JH7110_SYSCLK_UART3_APB, "uart3_apb", 0, JH7110_SYSCLK_APB0), + STARFIVE_GDIV(JH7110_SYSCLK_UART3_CORE, "uart3_core", 0, 10, JH7110_SYSCLK_PERH_ROOT), + STARFIVE_GATE(JH7110_SYSCLK_UART4_APB, "uart4_apb", 0, JH7110_SYSCLK_APB0), + STARFIVE_GDIV(JH7110_SYSCLK_UART4_CORE, "uart4_core", 0, 10, JH7110_SYSCLK_PERH_ROOT), + STARFIVE_GATE(JH7110_SYSCLK_UART5_APB, "uart5_apb", 0, JH7110_SYSCLK_APB0), + STARFIVE_GDIV(JH7110_SYSCLK_UART5_CORE, "uart5_core", 0, 10, JH7110_SYSCLK_PERH_ROOT), /* pwmdac */ - JH71X0_GATE(JH7110_SYSCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7110_SYSCLK_APB0), - JH71X0_GDIV(JH7110_SYSCLK_PWMDAC_CORE, "pwmdac_core", 0, 256, JH7110_SYSCLK_AUDIO_ROOT), + STARFIVE_GATE(JH7110_SYSCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7110_SYSCLK_APB0), + STARFIVE_GDIV(JH7110_SYSCLK_PWMDAC_CORE, "pwmdac_core", 0, 256, JH7110_SYSCLK_AUDIO_ROOT), /* spdif */ - JH71X0_GATE(JH7110_SYSCLK_SPDIF_APB, "spdif_apb", 0, JH7110_SYSCLK_APB0), - JH71X0_GATE(JH7110_SYSCLK_SPDIF_CORE, "spdif_core", 0, JH7110_SYSCLK_MCLK), + STARFIVE_GATE(JH7110_SYSCLK_SPDIF_APB, "spdif_apb", 0, JH7110_SYSCLK_APB0), + STARFIVE_GATE(JH7110_SYSCLK_SPDIF_CORE, "spdif_core", 0, JH7110_SYSCLK_MCLK), /* i2stx0 */ - JH71X0_GATE(JH7110_SYSCLK_I2STX0_APB, "i2stx0_apb", 0, JH7110_SYSCLK_APB0), - JH71X0_GDIV(JH7110_SYSCLK_I2STX0_BCLK_MST, "i2stx0_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK), - JH71X0__INV(JH7110_SYSCLK_I2STX0_BCLK_MST_INV, "i2stx0_bclk_mst_inv", - JH7110_SYSCLK_I2STX0_BCLK_MST), - JH71X0_MDIV(JH7110_SYSCLK_I2STX0_LRCK_MST, "i2stx0_lrck_mst", 64, 2, - JH7110_SYSCLK_I2STX0_BCLK_MST_INV, - JH7110_SYSCLK_I2STX0_BCLK_MST), - JH71X0__MUX(JH7110_SYSCLK_I2STX0_BCLK, "i2stx0_bclk", 2, - JH7110_SYSCLK_I2STX0_BCLK_MST, - JH7110_SYSCLK_I2STX_BCLK_EXT), - JH71X0__INV(JH7110_SYSCLK_I2STX0_BCLK_INV, "i2stx0_bclk_inv", JH7110_SYSCLK_I2STX0_BCLK), - JH71X0__MUX(JH7110_SYSCLK_I2STX0_LRCK, "i2stx0_lrck", 2, - JH7110_SYSCLK_I2STX0_LRCK_MST, - JH7110_SYSCLK_I2STX_LRCK_EXT), + STARFIVE_GATE(JH7110_SYSCLK_I2STX0_APB, "i2stx0_apb", 0, JH7110_SYSCLK_APB0), + STARFIVE_GDIV(JH7110_SYSCLK_I2STX0_BCLK_MST, "i2stx0_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK), + STARFIVE__INV(JH7110_SYSCLK_I2STX0_BCLK_MST_INV, "i2stx0_bclk_mst_inv", + JH7110_SYSCLK_I2STX0_BCLK_MST), + STARFIVE_MDIV(JH7110_SYSCLK_I2STX0_LRCK_MST, "i2stx0_lrck_mst", 64, 2, + JH7110_SYSCLK_I2STX0_BCLK_MST_INV, + JH7110_SYSCLK_I2STX0_BCLK_MST), + STARFIVE__MUX(JH7110_SYSCLK_I2STX0_BCLK, "i2stx0_bclk", 2, + JH7110_SYSCLK_I2STX0_BCLK_MST, + JH7110_SYSCLK_I2STX_BCLK_EXT), + STARFIVE__INV(JH7110_SYSCLK_I2STX0_BCLK_INV, "i2stx0_bclk_inv", JH7110_SYSCLK_I2STX0_BCLK), + STARFIVE__MUX(JH7110_SYSCLK_I2STX0_LRCK, "i2stx0_lrck", 2, + JH7110_SYSCLK_I2STX0_LRCK_MST, + JH7110_SYSCLK_I2STX_LRCK_EXT), /* i2stx1 */ - JH71X0_GATE(JH7110_SYSCLK_I2STX1_APB, "i2stx1_apb", 0, JH7110_SYSCLK_APB0), - JH71X0_GDIV(JH7110_SYSCLK_I2STX1_BCLK_MST, "i2stx1_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK), - JH71X0__INV(JH7110_SYSCLK_I2STX1_BCLK_MST_INV, "i2stx1_bclk_mst_inv", - JH7110_SYSCLK_I2STX1_BCLK_MST), - JH71X0_MDIV(JH7110_SYSCLK_I2STX1_LRCK_MST, "i2stx1_lrck_mst", 64, 2, - JH7110_SYSCLK_I2STX1_BCLK_MST_INV, - JH7110_SYSCLK_I2STX1_BCLK_MST), - JH71X0__MUX(JH7110_SYSCLK_I2STX1_BCLK, "i2stx1_bclk", 2, - JH7110_SYSCLK_I2STX1_BCLK_MST, - JH7110_SYSCLK_I2STX_BCLK_EXT), - JH71X0__INV(JH7110_SYSCLK_I2STX1_BCLK_INV, "i2stx1_bclk_inv", JH7110_SYSCLK_I2STX1_BCLK), - JH71X0__MUX(JH7110_SYSCLK_I2STX1_LRCK, "i2stx1_lrck", 2, - JH7110_SYSCLK_I2STX1_LRCK_MST, - JH7110_SYSCLK_I2STX_LRCK_EXT), + STARFIVE_GATE(JH7110_SYSCLK_I2STX1_APB, "i2stx1_apb", 0, JH7110_SYSCLK_APB0), + STARFIVE_GDIV(JH7110_SYSCLK_I2STX1_BCLK_MST, "i2stx1_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK), + STARFIVE__INV(JH7110_SYSCLK_I2STX1_BCLK_MST_INV, "i2stx1_bclk_mst_inv", + JH7110_SYSCLK_I2STX1_BCLK_MST), + STARFIVE_MDIV(JH7110_SYSCLK_I2STX1_LRCK_MST, "i2stx1_lrck_mst", 64, 2, + JH7110_SYSCLK_I2STX1_BCLK_MST_INV, + JH7110_SYSCLK_I2STX1_BCLK_MST), + STARFIVE__MUX(JH7110_SYSCLK_I2STX1_BCLK, "i2stx1_bclk", 2, + JH7110_SYSCLK_I2STX1_BCLK_MST, + JH7110_SYSCLK_I2STX_BCLK_EXT), + STARFIVE__INV(JH7110_SYSCLK_I2STX1_BCLK_INV, "i2stx1_bclk_inv", JH7110_SYSCLK_I2STX1_BCLK), + STARFIVE__MUX(JH7110_SYSCLK_I2STX1_LRCK, "i2stx1_lrck", 2, + JH7110_SYSCLK_I2STX1_LRCK_MST, + JH7110_SYSCLK_I2STX_LRCK_EXT), /* i2srx */ - JH71X0_GATE(JH7110_SYSCLK_I2SRX_APB, "i2srx_apb", 0, JH7110_SYSCLK_APB0), - JH71X0_GDIV(JH7110_SYSCLK_I2SRX_BCLK_MST, "i2srx_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK), - JH71X0__INV(JH7110_SYSCLK_I2SRX_BCLK_MST_INV, "i2srx_bclk_mst_inv", - JH7110_SYSCLK_I2SRX_BCLK_MST), - JH71X0_MDIV(JH7110_SYSCLK_I2SRX_LRCK_MST, "i2srx_lrck_mst", 64, 2, - JH7110_SYSCLK_I2SRX_BCLK_MST_INV, - JH7110_SYSCLK_I2SRX_BCLK_MST), - JH71X0__MUX(JH7110_SYSCLK_I2SRX_BCLK, "i2srx_bclk", 2, - JH7110_SYSCLK_I2SRX_BCLK_MST, - JH7110_SYSCLK_I2SRX_BCLK_EXT), - JH71X0__INV(JH7110_SYSCLK_I2SRX_BCLK_INV, "i2srx_bclk_inv", JH7110_SYSCLK_I2SRX_BCLK), - JH71X0__MUX(JH7110_SYSCLK_I2SRX_LRCK, "i2srx_lrck", 2, - JH7110_SYSCLK_I2SRX_LRCK_MST, - JH7110_SYSCLK_I2SRX_LRCK_EXT), + STARFIVE_GATE(JH7110_SYSCLK_I2SRX_APB, "i2srx_apb", 0, JH7110_SYSCLK_APB0), + STARFIVE_GDIV(JH7110_SYSCLK_I2SRX_BCLK_MST, "i2srx_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK), + STARFIVE__INV(JH7110_SYSCLK_I2SRX_BCLK_MST_INV, "i2srx_bclk_mst_inv", + JH7110_SYSCLK_I2SRX_BCLK_MST), + STARFIVE_MDIV(JH7110_SYSCLK_I2SRX_LRCK_MST, "i2srx_lrck_mst", 64, 2, + JH7110_SYSCLK_I2SRX_BCLK_MST_INV, + JH7110_SYSCLK_I2SRX_BCLK_MST), + STARFIVE__MUX(JH7110_SYSCLK_I2SRX_BCLK, "i2srx_bclk", 2, + JH7110_SYSCLK_I2SRX_BCLK_MST, + JH7110_SYSCLK_I2SRX_BCLK_EXT), + STARFIVE__INV(JH7110_SYSCLK_I2SRX_BCLK_INV, "i2srx_bclk_inv", JH7110_SYSCLK_I2SRX_BCLK), + STARFIVE__MUX(JH7110_SYSCLK_I2SRX_LRCK, "i2srx_lrck", 2, + JH7110_SYSCLK_I2SRX_LRCK_MST, + JH7110_SYSCLK_I2SRX_LRCK_EXT), /* pdm */ - JH71X0_GDIV(JH7110_SYSCLK_PDM_DMIC, "pdm_dmic", 0, 64, JH7110_SYSCLK_MCLK), - JH71X0_GATE(JH7110_SYSCLK_PDM_APB, "pdm_apb", 0, JH7110_SYSCLK_APB0), + STARFIVE_GDIV(JH7110_SYSCLK_PDM_DMIC, "pdm_dmic", 0, 64, JH7110_SYSCLK_MCLK), + STARFIVE_GATE(JH7110_SYSCLK_PDM_APB, "pdm_apb", 0, JH7110_SYSCLK_APB0), /* tdm */ - JH71X0_GATE(JH7110_SYSCLK_TDM_AHB, "tdm_ahb", 0, JH7110_SYSCLK_AHB0), - JH71X0_GATE(JH7110_SYSCLK_TDM_APB, "tdm_apb", 0, JH7110_SYSCLK_APB0), - JH71X0_GDIV(JH7110_SYSCLK_TDM_INTERNAL, "tdm_internal", 0, 64, JH7110_SYSCLK_MCLK), - JH71X0__MUX(JH7110_SYSCLK_TDM_TDM, "tdm_tdm", 2, - JH7110_SYSCLK_TDM_INTERNAL, - JH7110_SYSCLK_TDM_EXT), - JH71X0__INV(JH7110_SYSCLK_TDM_TDM_INV, "tdm_tdm_inv", JH7110_SYSCLK_TDM_TDM), + STARFIVE_GATE(JH7110_SYSCLK_TDM_AHB, "tdm_ahb", 0, JH7110_SYSCLK_AHB0), + STARFIVE_GATE(JH7110_SYSCLK_TDM_APB, "tdm_apb", 0, JH7110_SYSCLK_APB0), + STARFIVE_GDIV(JH7110_SYSCLK_TDM_INTERNAL, "tdm_internal", 0, 64, JH7110_SYSCLK_MCLK), + STARFIVE__MUX(JH7110_SYSCLK_TDM_TDM, "tdm_tdm", 2, + JH7110_SYSCLK_TDM_INTERNAL, + JH7110_SYSCLK_TDM_EXT), + STARFIVE__INV(JH7110_SYSCLK_TDM_TDM_INV, "tdm_tdm_inv", JH7110_SYSCLK_TDM_TDM), /* jtag */ - JH71X0__DIV(JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG, "jtag_certification_trng", 4, - JH7110_SYSCLK_OSC), + STARFIVE__DIV(JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG, "jtag_certification_trng", 4, + JH7110_SYSCLK_OSC), }; static struct clk_hw *jh7110_sysclk_get(struct of_phandle_args *clkspec, void *data) { - struct jh71x0_clk_priv *priv = data; + struct starfive_clk_priv *priv = data; unsigned int idx = clkspec->args[0]; if (idx < JH7110_SYSCLK_END) @@ -350,7 +353,7 @@ static void jh7110_reset_adev_release(struct device *dev) kfree(rdev); } -int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv, +int jh7110_reset_controller_register(struct starfive_clk_priv *priv, const char *adev_name, u32 adev_id) { @@ -387,7 +390,7 @@ EXPORT_SYMBOL_GPL(jh7110_reset_controller_register); static int __init jh7110_syscrg_probe(struct platform_device *pdev) { - struct jh71x0_clk_priv *priv; + struct starfive_clk_priv *priv; unsigned int idx; int ret; struct clk *pllclk; @@ -446,13 +449,13 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev) struct clk_parent_data parents[4] = {}; struct clk_init_data init = { .name = jh7110_sysclk_data[idx].name, - .ops = starfive_jh71x0_clk_ops(max), + .ops = starfive_clk_ops(max), .parent_data = parents, .num_parents = - ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1, + ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1, .flags = jh7110_sysclk_data[idx].flags, }; - struct jh71x0_clk *clk = &priv->reg[idx]; + struct starfive_clk *clk = &priv->reg[idx]; unsigned int i; for (i = 0; i < init.num_parents; i++) { @@ -490,7 +493,7 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev) clk->hw.init = &init; clk->idx = idx; - clk->max_div = max & JH71X0_CLK_DIV_MASK; + clk->max_div = max & STARFIVE_CLK_DIV_MASK; ret = devm_clk_hw_register(&pdev->dev, &clk->hw); if (ret) diff --git a/drivers/clk/starfive/clk-starfive-jh7110-vout.c b/drivers/clk/starfive/clk-starfive-jh7110-vout.c index 10cc1ec43925..aca93c370bce 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110-vout.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-vout.c @@ -30,45 +30,45 @@ static struct clk_bulk_data jh7110_vout_top_clks[] = { { .id = "vout_top_ahb" } }; -static const struct jh71x0_clk_data jh7110_voutclk_data[] = { +static const struct starfive_clk_data jh7110_voutclk_data[] = { /* divider */ - JH71X0__DIV(JH7110_VOUTCLK_APB, "apb", 8, JH7110_VOUTCLK_VOUT_TOP_AHB), - JH71X0__DIV(JH7110_VOUTCLK_DC8200_PIX, "dc8200_pix", 63, JH7110_VOUTCLK_VOUT_SRC), - JH71X0__DIV(JH7110_VOUTCLK_DSI_SYS, "dsi_sys", 31, JH7110_VOUTCLK_VOUT_SRC), - JH71X0__DIV(JH7110_VOUTCLK_TX_ESC, "tx_esc", 31, JH7110_VOUTCLK_VOUT_TOP_AHB), + STARFIVE__DIV(JH7110_VOUTCLK_APB, "apb", 8, JH7110_VOUTCLK_VOUT_TOP_AHB), + STARFIVE__DIV(JH7110_VOUTCLK_DC8200_PIX, "dc8200_pix", 63, JH7110_VOUTCLK_VOUT_SRC), + STARFIVE__DIV(JH7110_VOUTCLK_DSI_SYS, "dsi_sys", 31, JH7110_VOUTCLK_VOUT_SRC), + STARFIVE__DIV(JH7110_VOUTCLK_TX_ESC, "tx_esc", 31, JH7110_VOUTCLK_VOUT_TOP_AHB), /* dc8200 */ - JH71X0_GATE(JH7110_VOUTCLK_DC8200_AXI, "dc8200_axi", 0, JH7110_VOUTCLK_VOUT_TOP_AXI), - JH71X0_GATE(JH7110_VOUTCLK_DC8200_CORE, "dc8200_core", 0, JH7110_VOUTCLK_VOUT_TOP_AXI), - JH71X0_GATE(JH7110_VOUTCLK_DC8200_AHB, "dc8200_ahb", 0, JH7110_VOUTCLK_VOUT_TOP_AHB), - JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", 0, 2, - JH7110_VOUTCLK_DC8200_PIX, - JH7110_VOUTCLK_HDMITX0_PIXELCLK), - JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", 0, 2, - JH7110_VOUTCLK_DC8200_PIX, - JH7110_VOUTCLK_HDMITX0_PIXELCLK), + STARFIVE_GATE(JH7110_VOUTCLK_DC8200_AXI, "dc8200_axi", 0, JH7110_VOUTCLK_VOUT_TOP_AXI), + STARFIVE_GATE(JH7110_VOUTCLK_DC8200_CORE, "dc8200_core", 0, JH7110_VOUTCLK_VOUT_TOP_AXI), + STARFIVE_GATE(JH7110_VOUTCLK_DC8200_AHB, "dc8200_ahb", 0, JH7110_VOUTCLK_VOUT_TOP_AHB), + STARFIVE_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", 0, 2, + JH7110_VOUTCLK_DC8200_PIX, + JH7110_VOUTCLK_HDMITX0_PIXELCLK), + STARFIVE_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", 0, 2, + JH7110_VOUTCLK_DC8200_PIX, + JH7110_VOUTCLK_HDMITX0_PIXELCLK), /* LCD */ - JH71X0_GMUX(JH7110_VOUTCLK_DOM_VOUT_TOP_LCD, "dom_vout_top_lcd", 0, 2, - JH7110_VOUTCLK_DC8200_PIX0, - JH7110_VOUTCLK_DC8200_PIX1), + STARFIVE_GMUX(JH7110_VOUTCLK_DOM_VOUT_TOP_LCD, "dom_vout_top_lcd", 0, 2, + JH7110_VOUTCLK_DC8200_PIX0, + JH7110_VOUTCLK_DC8200_PIX1), /* dsiTx */ - JH71X0_GATE(JH7110_VOUTCLK_DSITX_APB, "dsiTx_apb", 0, JH7110_VOUTCLK_DSI_SYS), - JH71X0_GATE(JH7110_VOUTCLK_DSITX_SYS, "dsiTx_sys", 0, JH7110_VOUTCLK_DSI_SYS), - JH71X0_GMUX(JH7110_VOUTCLK_DSITX_DPI, "dsiTx_dpi", 0, 2, - JH7110_VOUTCLK_DC8200_PIX, - JH7110_VOUTCLK_HDMITX0_PIXELCLK), - JH71X0_GATE(JH7110_VOUTCLK_DSITX_TXESC, "dsiTx_txesc", 0, JH7110_VOUTCLK_TX_ESC), + STARFIVE_GATE(JH7110_VOUTCLK_DSITX_APB, "dsiTx_apb", 0, JH7110_VOUTCLK_DSI_SYS), + STARFIVE_GATE(JH7110_VOUTCLK_DSITX_SYS, "dsiTx_sys", 0, JH7110_VOUTCLK_DSI_SYS), + STARFIVE_GMUX(JH7110_VOUTCLK_DSITX_DPI, "dsiTx_dpi", 0, 2, + JH7110_VOUTCLK_DC8200_PIX, + JH7110_VOUTCLK_HDMITX0_PIXELCLK), + STARFIVE_GATE(JH7110_VOUTCLK_DSITX_TXESC, "dsiTx_txesc", 0, JH7110_VOUTCLK_TX_ESC), /* mipitx DPHY */ - JH71X0_GATE(JH7110_VOUTCLK_MIPITX_DPHY_TXESC, "mipitx_dphy_txesc", 0, - JH7110_VOUTCLK_TX_ESC), + STARFIVE_GATE(JH7110_VOUTCLK_MIPITX_DPHY_TXESC, "mipitx_dphy_txesc", 0, + JH7110_VOUTCLK_TX_ESC), /* hdmi */ - JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_MCLK, "hdmi_tx_mclk", 0, - JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK), - JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_BCLK, "hdmi_tx_bclk", 0, - JH7110_VOUTCLK_I2STX0_BCLK), - JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_SYS, "hdmi_tx_sys", 0, JH7110_VOUTCLK_APB), + STARFIVE_GATE(JH7110_VOUTCLK_HDMI_TX_MCLK, "hdmi_tx_mclk", 0, + JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK), + STARFIVE_GATE(JH7110_VOUTCLK_HDMI_TX_BCLK, "hdmi_tx_bclk", 0, + JH7110_VOUTCLK_I2STX0_BCLK), + STARFIVE_GATE(JH7110_VOUTCLK_HDMI_TX_SYS, "hdmi_tx_sys", 0, JH7110_VOUTCLK_APB), }; -static int jh7110_vout_top_rst_init(struct jh71x0_clk_priv *priv) +static int jh7110_vout_top_rst_init(struct starfive_clk_priv *priv) { struct reset_control *top_rst; @@ -82,7 +82,7 @@ static int jh7110_vout_top_rst_init(struct jh71x0_clk_priv *priv) static struct clk_hw *jh7110_voutclk_get(struct of_phandle_args *clkspec, void *data) { - struct jh71x0_clk_priv *priv = data; + struct starfive_clk_priv *priv = data; unsigned int idx = clkspec->args[0]; if (idx < JH7110_VOUTCLK_END) @@ -115,7 +115,7 @@ static const struct dev_pm_ops jh7110_voutcrg_pm_ops = { static int jh7110_voutcrg_probe(struct platform_device *pdev) { - struct jh71x0_clk_priv *priv; + struct starfive_clk_priv *priv; struct jh7110_top_sysclk *top; unsigned int idx; int ret; @@ -158,13 +158,13 @@ static int jh7110_voutcrg_probe(struct platform_device *pdev) struct clk_parent_data parents[4] = {}; struct clk_init_data init = { .name = jh7110_voutclk_data[idx].name, - .ops = starfive_jh71x0_clk_ops(max), + .ops = starfive_clk_ops(max), .parent_data = parents, .num_parents = - ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1, + ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1, .flags = jh7110_voutclk_data[idx].flags, }; - struct jh71x0_clk *clk = &priv->reg[idx]; + struct starfive_clk *clk = &priv->reg[idx]; unsigned int i; const char *fw_name[JH7110_VOUTCLK_EXT_END - JH7110_VOUTCLK_END] = { "vout_src", @@ -186,7 +186,7 @@ static int jh7110_voutcrg_probe(struct platform_device *pdev) clk->hw.init = &init; clk->idx = idx; - clk->max_div = max & JH71X0_CLK_DIV_MASK; + clk->max_div = max & STARFIVE_CLK_DIV_MASK; ret = devm_clk_hw_register(&pdev->dev, &clk->hw); if (ret) diff --git a/drivers/clk/starfive/clk-starfive-jh7110.h b/drivers/clk/starfive/clk-starfive-jh7110.h index 6b1bdf860f00..4a6dfd8d8636 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110.h +++ b/drivers/clk/starfive/clk-starfive-jh7110.h @@ -10,7 +10,7 @@ struct jh7110_top_sysclk { int top_clks_num; }; -int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv, +int jh7110_reset_controller_register(struct starfive_clk_priv *priv, const char *adev_name, u32 adev_id); From patchwork Tue Dec 26 05:38:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: JeeHeng Sia X-Patchwork-Id: 758436 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5CED24C63C; Tue, 26 Dec 2023 05:39:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=starfivetech.com Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 70A838022; Tue, 26 Dec 2023 13:39:36 +0800 (CST) Received: from EXMBX066.cuchost.com (172.16.7.66) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 26 Dec 2023 13:39:36 +0800 Received: from jsia-virtual-machine.localdomain (202.188.176.82) by EXMBX066.cuchost.com (172.16.6.66) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 26 Dec 2023 13:39:30 +0800 From: Sia Jee Heng To: , , , , , , , , , , , , CC: , , , , , Subject: [RFC 05/16] dt-bindings: clock: Add StarFive JH8100 System clock and reset generator Date: Tue, 26 Dec 2023 13:38:37 +0800 Message-ID: <20231226053848.25089-6-jeeheng.sia@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231226053848.25089-1-jeeheng.sia@starfivetech.com> References: <20231226053848.25089-1-jeeheng.sia@starfivetech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX066.cuchost.com (172.16.6.66) X-YovoleRuleAgent: yovoleflag Add bindings for the System clocks and reset generator (SYSCRG) on JH8100 SoC. Signed-off-by: Sia Jee Heng Reviewed-by: Ley Foon Tan --- .../clock/starfive,jh8100-syscrg.yaml | 77 +++++++++++ .../dt-bindings/clock/starfive,jh8100-crg.h | 122 ++++++++++++++++++ .../dt-bindings/reset/starfive,jh8100-crg.h | 21 +++ 3 files changed, 220 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg.yaml create mode 100644 include/dt-bindings/clock/starfive,jh8100-crg.h create mode 100644 include/dt-bindings/reset/starfive,jh8100-crg.h diff --git a/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg.yaml new file mode 100644 index 000000000000..853b13ce5562 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh8100-syscrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH8100 System Clock and Reset Generator + +maintainers: + - Sia Jee Heng + +properties: + compatible: + const: starfive,jh8100-syscrg + + reg: + maxItems: 1 + + clocks: + items: + - description: Main Oscillator (24 MHz) + - description: External MCLK clock + - description: PLL0 + - description: PLL1 + - description: PLL2 + - description: PLL3 + - description: PLL4 + - description: PLL6 + - description: PLL7 + + clock-names: + items: + - const: osc + - const: mclk-ext + - const: pll0 + - const: pll1 + - const: pll2 + - const: pll3 + - const: pll4 + - const: pll6 + - const: pll7 + + '#clock-cells': + const: 1 + description: + See for valid indices. + + '#reset-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@126d0000 { + compatible = "starfive,jh8100-syscrg"; + reg = <0x126d0000 0x10000>; + clocks = <&osc>, <&mclk_ext>, <&pll0>, <&pll1>, + <&pll2>, <&pll3>, <&pll4>, <&pll6>, <&pll7>; + clock-names = "osc", "mclk-ext", "pll0", "pll1", + "pll2", "pll3", "pll4", + "pll6", "pll7"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jh8100-crg.h b/include/dt-bindings/clock/starfive,jh8100-crg.h new file mode 100644 index 000000000000..611613961e17 --- /dev/null +++ b/include/dt-bindings/clock/starfive,jh8100-crg.h @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (C) 2023 StarFive Technology Co., Ltd. + * Sia Jee Heng + * + */ + +#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ +#define __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ + +/* SYSCRG clocks */ +#define JH8100_SYSCLK_VDEC_ROOT_PREOSC 0 +#define JH8100_SYSCLK_VDEC_ROOT 1 +#define JH8100_SYSCLK_VENC_ROOT_PREOSC 2 +#define JH8100_SYSCLK_VENC_ROOT 3 +#define JH8100_SYSCLK_GPU_ROOT 4 +#define JH8100_SYSCLK_GPU_CORE 5 +#define JH8100_SYSCLK_VOUT_ROOT0_PREOSC 6 +#define JH8100_SYSCLK_VOUT_ROOT0 7 +#define JH8100_SYSCLK_VOUT_ROOT1_PREOSC 8 +#define JH8100_SYSCLK_VOUT_ROOT1 9 +#define JH8100_SYSCLK_VOUT_SCAN_ATS 10 +#define JH8100_SYSCLK_PERH_ROOT_PREOSC 11 +#define JH8100_SYSCLK_PERH_ROOT 12 +#define JH8100_SYSCLK_AXI_200_PREOSC 13 +#define JH8100_SYSCLK_AXI_200 14 +#define JH8100_SYSCLK_AXI_200_GMAC 15 +#define JH8100_SYSCLK_AXI_500_PREOSC 16 +#define JH8100_SYSCLK_AXI_500 17 +#define JH8100_SYSCLK_AXI_500_PCIEX1A 18 +#define JH8100_SYSCLK_AXI_500_PCIEX1B 19 +#define JH8100_SYSCLK_AXI_500_PCIEX2 20 +#define JH8100_SYSCLK_AXI_500_PCIEX8 21 +#define JH8100_SYSCLK_AXI_400_PREOSC 22 +#define JH8100_SYSCLK_AXI_400 23 +#define JH8100_SYSCLK_AXI_400_APBOOTRAM 24 +#define JH8100_SYSCLK_AXI_125_PREOSC 25 +#define JH8100_SYSCLK_AXI_125 26 +#define JH8100_SYSCLK_AHB0_PREOSC 27 +#define JH8100_SYSCLK_AHB0 28 +#define JH8100_SYSCLK_APB_BUS_FUNC 29 +#define JH8100_SYSCLK_APB_BUS 30 +#define JH8100_SYSCLK_APB_BUS_PER0 31 +#define JH8100_SYSCLK_APB_BUS_PER1 32 +#define JH8100_SYSCLK_APB_BUS_PER2 33 +#define JH8100_SYSCLK_APB_BUS_PER3 34 +#define JH8100_SYSCLK_APB_BUS_PER4 35 +#define JH8100_SYSCLK_APB_BUS_PER5 36 +#define JH8100_SYSCLK_APB_BUS_PER6 37 +#define JH8100_SYSCLK_APB_BUS_PER7 38 +#define JH8100_SYSCLK_APB_BUS_PER8 39 +#define JH8100_SYSCLK_APB_BUS_PER9 40 +#define JH8100_SYSCLK_APB_BUS_PER10 41 +#define JH8100_SYSCLK_SPI_CORE_100 42 +#define JH8100_SYSCLK_PLL1_DIV2 43 +#define JH8100_SYSCLK_PLL2_DIV2 44 +#define JH8100_SYSCLK_PLL3_DIV2 45 +#define JH8100_SYSCLK_PLL4_DIV2 46 +#define JH8100_SYSCLK_PLL6_DIV2 47 +#define JH8100_SYSCLK_PLL7_DIV2 48 +#define JH8100_SYSCLK_AUDIO_ROOT 49 +#define JH8100_SYSCLK_MCLK_INNER 50 +#define JH8100_SYSCLK_MCLK 51 +#define JH8100_SYSCLK_MCLK_OUT 52 +#define JH8100_SYSCLK_ISP_2X_PREOSC 53 +#define JH8100_SYSCLK_ISP_2X 54 +#define JH8100_SYSCLK_ISP_AXI 55 +#define JH8100_SYSCLK_GCLK1 56 +#define JH8100_SYSCLK_GCLK2 57 +#define JH8100_SYSCLK_GCLK3 58 +#define JH8100_SYSCLK_GCLK4 59 +#define JH8100_SYSCLK_GCLK6 60 +#define JH8100_SYSCLK_GCLK7 61 +#define JH8100_SYSCLK_FLEXNOC0_PREOSC 62 +#define JH8100_SYSCLK_FLEXNOC0 63 +#define JH8100_SYSCLK_FLEXNOC1_PREOSC 64 +#define JH8100_SYSCLK_FLEXNOC1 65 +#define JH8100_SYSCLK_FLEXNOC2_PREOSC 66 +#define JH8100_SYSCLK_FLEXNOC2 67 +#define JH8100_SYSCLK_VDEC_CORE 68 +#define JH8100_SYSCLK_GPU_CORE_ICG 69 +#define JH8100_SYSCLK_IMG_GPU_CLK_APB 70 +#define JH8100_SYSCLK_IMG_GPU_RTC_TOGGLE 71 +#define JH8100_SYSCLK_IMG_GPU_TIMER_USC 72 +#define JH8100_SYSCLK_HIFI4_CORE_PREOSC 73 +#define JH8100_SYSCLK_HIFI4_CORE 74 +#define JH8100_SYSCLK_E_200_PREOSC 75 +#define JH8100_SYSCLK_E_200 76 +#define JH8100_SYSCLK_HD_AUDIO_48M 77 +#define JH8100_SYSCLK_VOUT_DC_CORE 78 +#define JH8100_SYSCLK_VOUT_AXI 79 +#define JH8100_SYSCLK_USB_WRAP_625 80 +#define JH8100_SYSCLK_USB_WRAP_480 81 +#define JH8100_SYSCLK_USB_WRAP_240 82 +#define JH8100_SYSCLK_USB_WRAP_60 83 +#define JH8100_SYSCLK_USB_WRAP_156P25 84 +#define JH8100_SYSCLK_USB_WRAP_312P5 85 +#define JH8100_SYSCLK_USB_125M 86 +#define JH8100_SYSCLK_FLEXNOC_APBOOTRAM 87 +#define JH8100_SYSCLK_FLEXNOC_PCIEX1AMST 88 +#define JH8100_SYSCLK_FLEXNOC_PCIEX1ASLV 89 +#define JH8100_SYSCLK_FLEXNOC_PCIEX1BMST 90 +#define JH8100_SYSCLK_FLEXNOC_PCIEX1BSLV 91 +#define JH8100_SYSCLK_FLEXNOC_PCIEX2MST 92 +#define JH8100_SYSCLK_FLEXNOC_PCIEX2SLV 93 +#define JH8100_SYSCLK_FLEXNOC_PCIEX8MST 94 +#define JH8100_SYSCLK_FLEXNOC_PCIEX8SLV 95 +#define JH8100_SYSCLK_FLEXNOC_GMACSYSSLV 96 +#define JH8100_SYSCLK_GMAC_SRC 97 +#define JH8100_SYSCLK_GMAC1_GTXCLK_TOP 98 +#define JH8100_SYSCLK_GMAC1_PTP 99 +#define JH8100_SYSCLK_HD_AUDIO_SYSTEM_CLOCK 100 +#define JH8100_SYSCLK_HD_AUDIO_CLOCK_48 101 +#define JH8100_SYSCLK_HD_AUDIO_BCLK_POST_OCC_IN 102 +#define JH8100_SYSCLK_NNE_VIP_ACLK 103 +#define JH8100_SYSCLK_NNE_VIP_HCLK 104 +#define JH8100_SYSCLK_NNE_VIP_CLKCORE 105 +#define JH8100_SYSCLK_GPU_ICG_EN 106 +#define JH8100_SYSCLK_HD_AUDIO_ICG_EN 107 +#define JH8100_SYSCLK_NNE_ICG_EN 108 + +#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */ diff --git a/include/dt-bindings/reset/starfive,jh8100-crg.h b/include/dt-bindings/reset/starfive,jh8100-crg.h new file mode 100644 index 000000000000..c4e2501491ab --- /dev/null +++ b/include/dt-bindings/reset/starfive,jh8100-crg.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* + * Copyright (c) 2022-2023 StarFive Technology Co., Ltd. + */ + +#ifndef __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ +#define __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ + +/* + * SYSCRG resets: assert0 + */ +#define JH8100_SYSRST_SYS_SYSCON 0 +#define JH8100_SYSRST_CLK_MOD 1 +#define JH8100_SYSRST_GPU 2 +#define JH8100_SYSRST_GPU_SPU 3 +#define JH8100_SYSRST_GPU_TVSENSOR 4 +#define JH8100_SYSRST_PPU_OP_NORET_GPU_RESET 5 +#define JH8100_SYSRST_NNE 6 +#define JH8100_SYSRST_HD_AUDIO 7 + +#endif /* __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ */ From patchwork Tue Dec 26 05:38:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: JeeHeng Sia X-Patchwork-Id: 758435 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B9924D10C; Tue, 26 Dec 2023 05:39:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=starfivetech.com Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 6B9658016; Tue, 26 Dec 2023 13:39:49 +0800 (CST) Received: from EXMBX066.cuchost.com (172.16.7.66) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 26 Dec 2023 13:39:49 +0800 Received: from jsia-virtual-machine.localdomain (202.188.176.82) by EXMBX066.cuchost.com (172.16.6.66) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 26 Dec 2023 13:39:43 +0800 From: Sia Jee Heng To: , , , , , , , , , , , , CC: , , , , , Subject: [RFC 07/16] dt-bindings: clock: Add StarFive JH8100 North-West clock and reset generator Date: Tue, 26 Dec 2023 13:38:39 +0800 Message-ID: <20231226053848.25089-8-jeeheng.sia@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231226053848.25089-1-jeeheng.sia@starfivetech.com> References: <20231226053848.25089-1-jeeheng.sia@starfivetech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX066.cuchost.com (172.16.6.66) X-YovoleRuleAgent: yovoleflag Add bindings for the North-West clock and reset generator (NWCRG) on JH8100 SoC. Signed-off-by: Sia Jee Heng Reviewed-by: Ley Foon Tan --- .../bindings/clock/starfive,jh8100-nwcrg.yaml | 119 ++++++++++++++++++ .../dt-bindings/clock/starfive,jh8100-crg.h | 43 +++++++ .../dt-bindings/reset/starfive,jh8100-crg.h | 14 +++ 3 files changed, 176 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-nwcrg.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jh8100-nwcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh8100-nwcrg.yaml new file mode 100644 index 000000000000..be0f94e64e6a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh8100-nwcrg.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh8100-nwcrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH8100 North-West Clock and Reset Generator + +maintainers: + - Sia Jee Heng + +properties: + compatible: + const: starfive,jh8100-nwcrg + + reg: + maxItems: 1 + + clocks: + items: + - description: Main Oscillator (24 MHz) + - description: APB_BUS clock from SYSCRG + - description: APB_BUS_PER4 clock from SYSCRG + - description: SPI_CORE_100 clock from SYSCRG + - description: ISP_2X clock from SYSCRG + - description: ISP_AXI clock from SYSCRG + - description: VOUT_ROOT0 clock from SYSCRG + - description: VOUT_ROOT1 clock from SYSCRG + - description: VOUT_SCAN_ATS clock from SYSCRG + - description: VOUT_DC_CORE clock from SYSCRG + - description: VOUT_AXI clock from SYSCRG + - description: AXI_400 clock from SYSCRG + - description: AHB0 clock from SYSCRG + - description: PERH_ROOT_PREOSC from SYSCRG + - description: External DVP clock + - description: External ISP DPHY TAP TCK clock + - description: External golbal clock + - description: External VOUT MIPI DPHY TAP TCK + - description: External VOUT eDP TAP TCK + - description: External SPI In2 clock + - description: PLL5 + + clock-names: + items: + - const: osc + - const: apb_bus + - const: apb_bus_per4 + - const: spi_core_100 + - const: isp_2x + - const: isp_axi + - const: vout_root0 + - const: vout_root1 + - const: vout_scan_ats + - const: vout_dc_core + - const: vout_axi + - const: axi_400 + - const: ahb0 + - const: perh_root_preosc + - const: dvp-ext + - const: isp-dphy-tap-tck-ext + - const: glb-ext-clk + - const: vout-mipi-dphy-tap-tck-ext + - const: vout-edp-tap-tck-ext + - const: spi-in2-ext + - const: pll5 + + '#clock-cells': + const: 1 + description: + See for valid indices. + + '#reset-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@123c0000 { + compatible = "starfive,jh8100-nwcrg"; + reg = <0x123c0000 0x10000>; + clocks = <&osc>, <&syscrg JH8100_SYSCLK_APB_BUS>, + <&syscrg JH8100_SYSCLK_APB_BUS_PER4>, + <&syscrh JH8100_SYSCLK_SPI_CORE_100>, + <&syscrg JH8100_SYSCLK_ISP_2X>, + <&syscrg JH8100_SYSCLK_ISP_AXI>, + <&syscrg JH8100_SYSCLK_VOUT_ROOT0>, + <&syscrg JH8100_SYSCLK_VOUT_ROOT1>, + <&syscrg JH8100_SYSCLK_VOUT_SCAN_ATS>, + <&syscrg JH8100_SYSCLK_VOUT_DC_CORE>, + <&syscrg JH8100_SYSCLK_VOUT_AXI>, + <&syscrg JH8100_SYSCLK_AXI_400>, + <&syscrg JH8100_SYSCLK_AHB0>, + <&syscrg JH8100_SYSCLK_PERH_ROOT_PREOSC>, + <&dvp_ext>, <&isp_dphy_tap_tck_ext>, + <&glb_ext_clk>, <&vout_mipi_dphy_tap_tck_ext>, + <&vout_edp_tap_tck_ext>, <&spi_in2_ext>, <&pll5>; + clock-names = "osc", "apb_bus", "apb_bus_per4", "spi_core_100", + "isp_2x", "isp_axi", "vout_root0", "vout_root1", + "vout_scan_ats", "vout_dc_core", "vout_axi", + "axi_400", "ahb0", "perh_root_preosc", "dvp-ext", + "isp-dphy-tap-tck-ext", "glb-ext-clk", + "vout-mipi-dphy-tap-tck-ext", "vout-edp-tap-tck-ext", + "spi-in2-ext", "pll5"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jh8100-crg.h b/include/dt-bindings/clock/starfive,jh8100-crg.h index 611613961e17..626173e14940 100644 --- a/include/dt-bindings/clock/starfive,jh8100-crg.h +++ b/include/dt-bindings/clock/starfive,jh8100-crg.h @@ -119,4 +119,47 @@ #define JH8100_SYSCLK_HD_AUDIO_ICG_EN 107 #define JH8100_SYSCLK_NNE_ICG_EN 108 +/* NWCRG clocks */ +#define JH8100_NWCLK_PLL5_DIV2 0 +#define JH8100_NWCLK_GCLK5 1 +#define JH8100_NWCLK_GPIO_100 2 +#define JH8100_NWCLK_GPIO_50 3 +#define JH8100_NWCLK_GPIO_150 4 +#define JH8100_NWCLK_GPIO_60 5 +#define JH8100_NWCLK_IOMUX_WEST_PCLK 6 +#define JH8100_NWCLK_I2C6_APB 7 +#define JH8100_NWCLK_I2C7_APB 8 +#define JH8100_NWCLK_SPI2_APB 9 +#define JH8100_NWCLK_SPI2_CORE 10 +#define JH8100_NWCLK_SPI2_SCLK_IN 11 +#define JH8100_NWCLK_SMBUS1_APB 12 +#define JH8100_NWCLK_SMBUS1_CORE 13 +#define JH8100_NWCLK_ISP_DVP 14 +#define JH8100_NWCLK_ISP_CORE_2X 15 +#define JH8100_NWCLK_ISP_AXI 16 +#define JH8100_NWCLK_ISP_DPHY_TAP_TCK 17 +#define JH8100_NWCLK_FLEXNOC_ISPSLV 18 +#define JH8100_NWCLK_VOUT_PIX0 19 +#define JH8100_NWCLK_VOUT_PIX1 20 +#define JH8100_NWCLK_VOUT_SCAN_ATS 21 +#define JH8100_NWCLK_VOUT_DC_CORE 22 +#define JH8100_NWCLK_VOUT_APB 23 +#define JH8100_NWCLK_VOUT_DSI 24 +#define JH8100_NWCLK_VOUT_AHB 25 +#define JH8100_NWCLK_VOUT_AXI 26 +#define JH8100_NWCLK_VOUT_MIPI_DPHY_TAP_TCK 27 +#define JH8100_NWCLK_VOUT_EDP_PHY_TAP_TCK 28 +#define JH8100_NWCLK_UART5_CORE_PREOSC 29 +#define JH8100_NWCLK_UART5_APB 30 +#define JH8100_NWCLK_UART5_CORE 31 +#define JH8100_NWCLK_UART6_CORE_PREOSC 32 +#define JH8100_NWCLK_UART6_APB 33 +#define JH8100_NWCLK_UART6_CORE 34 +#define JH8100_NWCLK_SPI2_ICG_EN 35 +#define JH8100_NWCLK_SMBUS1_ICG_EN 36 +#define JH8100_NWCLK_ISP_ICG_EN 37 +#define JH8100_NWCLK_VOUT_ICG_EN 38 +#define JH8100_NWCLK_UART5_ICG_EN 39 +#define JH8100_NWCLK_UART6_ICG_EN 40 + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */ diff --git a/include/dt-bindings/reset/starfive,jh8100-crg.h b/include/dt-bindings/reset/starfive,jh8100-crg.h index c4e2501491ab..b25f6522f3d4 100644 --- a/include/dt-bindings/reset/starfive,jh8100-crg.h +++ b/include/dt-bindings/reset/starfive,jh8100-crg.h @@ -18,4 +18,18 @@ #define JH8100_SYSRST_NNE 6 #define JH8100_SYSRST_HD_AUDIO 7 +/* + * NWCRG resets: assert0 + */ +#define JH8100_NWRST_PRESETN 0 +#define JH8100_NWRST_SYS_IOMUX_W 1 +#define JH8100_NWRST_I2C6 2 +#define JH8100_NWRST_I2C7 3 +#define JH8100_NWRST_SPI2 4 +#define JH8100_NWRST_SMBUS1 5 +#define JH8100_NWRST_UART5 6 +#define JH8100_NWRST_UART6 7 +#define JH8100_NWRST_MERAK0_TVSENSOR 8 +#define JH8100_NWRST_MERAK1_TVSENSOR 9 + #endif /* __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ */ From patchwork Tue Dec 26 05:38:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: JeeHeng Sia X-Patchwork-Id: 758434 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08F8E4D586; Tue, 26 Dec 2023 05:40:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=starfivetech.com Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id B91358062; Tue, 26 Dec 2023 13:40:02 +0800 (CST) Received: from EXMBX066.cuchost.com (172.16.7.66) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 26 Dec 2023 13:40:02 +0800 Received: from jsia-virtual-machine.localdomain (202.188.176.82) by EXMBX066.cuchost.com (172.16.6.66) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 26 Dec 2023 13:39:56 +0800 From: Sia Jee Heng To: , , , , , , , , , , , , CC: , , , , , Subject: [RFC 09/16] dt-bindings: clock: Add StarFive JH8100 North-East clock and reset generator Date: Tue, 26 Dec 2023 13:38:41 +0800 Message-ID: <20231226053848.25089-10-jeeheng.sia@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231226053848.25089-1-jeeheng.sia@starfivetech.com> References: <20231226053848.25089-1-jeeheng.sia@starfivetech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX066.cuchost.com (172.16.6.66) X-YovoleRuleAgent: yovoleflag Add bindings for the North-East clock and reset generator (NECRG) on JH8100 SoC. Signed-off-by: Sia Jee Heng Reviewed-by: Ley Foon Tan --- .../bindings/clock/starfive,jh8100-necrg.yaml | 153 +++++++++++++++ .../dt-bindings/clock/starfive,jh8100-crg.h | 177 ++++++++++++++++++ .../dt-bindings/reset/starfive,jh8100-crg.h | 59 ++++++ 3 files changed, 389 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-necrg.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jh8100-necrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh8100-necrg.yaml new file mode 100644 index 000000000000..f747b85fa457 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh8100-necrg.yaml @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh8100-necrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH8100 North-East Clock and Reset Generator + +maintainers: + - Sia Jee Heng + +properties: + compatible: + const: starfive,jh8100-necrg + + reg: + maxItems: 1 + + clocks: + items: + - description: Main Oscillator (24 MHz) + - description: AXI_400 clock from SYSCRG + - description: VOUT_ROOT0 clock from SYSCRG + - description: VOUT_ROOT1 clock from SYSCRG + - description: USB_WRAP_480 clock from SYSCRG + - description: USB_WRAP_625 clock from SYSCRG + - description: USB_WRAP_240 clock from SYSCRG + - description: USB_WRAP_60 clock from SYSCRG + - description: USB_WRAP_156P25 clock from SYSCRG + - description: USB_WRAP_312P5 clock from SYSCRG + - description: USB_125M clock from SYSCRG + - description: GPIO_100 clock from NWCRG + - description: PERH_ROOT clock from SYSCRG + - description: Master clock from SYSCRG + - description: PERH_ROOT_PREOSC clock from SYSCRG + - description: AHB0 clock from SYSCRG + - description: APB_BUS_PER1 clock from SYSCRG + - description: APB_BUS PER2 clock from SYSCRG + - description: APB_BUS_PER3 clock from SYSCRG + - description: APB_BUS_PER5 clock from SYSCRG + - description: VENC_ROOT clock from SYSCRG + - description: SPI_CORE_100 clock from SYSCRG + - description: External global clock + - description: External USB3_TAP_TCK clock + - description: External USB1_TAP_TCK clock + - description: External USB2_TAP_TCK clock + - description: External TYPEC_TAP_TCK clock + - description: External SPI_IN0 clock + - description: External SPI_IN1 clock + - description: External I2STX_BCLK clock + - description: External I2STX_LRCK clock + + clock-names: + items: + - const: osc + - const: axi_400 + - const: vout_root0 + - const: vout_root1 + - const: usb_wrap_480 + - const: usb_wrap_625 + - const: usb_wrap_240 + - const: usb_wrap_60 + - const: usb_wrap_156p25 + - const: usb_wrap_312p5 + - const: usb_125m + - const: gpio_100 + - const: perh_root + - const: mclk + - const: perh_root_preosc + - const: ahb0 + - const: apb_bus_per1 + - const: apb_bus_per2 + - const: apb_bus_per3 + - const: apb_bus_per5 + - const: venc_root + - const: spi_core_100 + - const: glb-ext-clk + - const: usb3-tap-tck-ext + - const: usb1-tap-tck-ext + - const: usb2-tap-tck-ext + - const: typec-tap-tck-ext + - const: spi-in0-ext + - const: spi-in1-ext + - const: i2stx-bclk-ext + - const: i2stx-lrck-ext + + '#clock-cells': + const: 1 + description: + See for valid indices. + + '#reset-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@12320000 { + compatible = "starfive,jh8100-necrg"; + reg = <0x12320000 0x10000>; + clocks = <&osc>, <&syscrg JH8100_SYSCLK_AXI_400>, + <&syscrg JH8100_SYSCLK_VOUT_ROOT0>, + <&syscrg JH8100_SYSCLK_VOUT_ROOT1>, + <&syscrg JH8100_SYSCLK_USB_WRAP_480>, + <&syscrg JH8100_SYSCLK_USB_WRAP_625>, + <&syscrg JH8100_SYSCLK_USB_WRAP_240>, + <&syscrg JH8100_SYSCLK_USB_WRAP_60>, + <&syscrg JH8100_SYSCLK_USB_WRAP_156P25>, + <&syscrg JH8100_SYSCLK_USB_WRAP_312P5>, + <&syscrg JH8100_SYSCLK_USB_125M>, + <&nwcrg JH8100_NWCLK_GPIO_100>, + <&syscrg JH8100_SYSCLK_PERH_ROOT>, + <&syscrg JH8100_SYSCLK_MCLK>, + <&syscrg JH8100_SYSCLK_PERH_ROOT_PREOSC>, + <&syscrg JH8100_SYSCLK_AHB0>, + <&syscrg JH8100_SYSCLK_APB_BUS_PER1>, + <&syscrg JH8100_SYSCLK_APB_BUS_PER2>, + <&syscrg JH8100_SYSCLK_APB_BUS_PER3>, + <&syscrg JH8100_SYSCLK_APB_BUS_PER5>, + <&syscrg JH8100_SYSCLK_VENC_ROOT>, + <&syscrg JH8100_SYSCLK_SPI_CORE_100>, + <&glb_ext_clk>, <&usb3_tap_tck_ext>, + <&usb1_tap_tck_ext>, <&usb2_tap_tck_ext>, + <&typec_tap_tck_ext>, <&spi_in0_ext>, + <&spi_in1_ext>, <&i2stx_bclk_ext>, + <&i2stx_lrck_ext>; + clock-names = "osc", "axi_400", "vout_root0", "vout_root1", + "usb_wrap_480", "usb_wrap_625", "usb_wrap_240", + "usb_wrap_60", "usb_wrap_156p25", "usb_wrap_312p5", + "usb_125m", "gpio_100", "perh_root", "mclk", + "perh_root_preosc", "ahb0", "apb_bus_per1", + "apb_bus_per2", "apb_bus_per3", "apb_bus_per5", + "venc_root", "spi_core_100", "glb-ext-clk", + "usb3-tap-tck-ext", "usb1-tap-tck-ext", + "usb2-tap-tck-ext", "typec-tap-tck-ext", + "spi-in0-ext", "spi-in1-ext", "i2stx-bclk-ext", + "i2stx-lrck-ext"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jh8100-crg.h b/include/dt-bindings/clock/starfive,jh8100-crg.h index 626173e14940..c37b42f3eacd 100644 --- a/include/dt-bindings/clock/starfive,jh8100-crg.h +++ b/include/dt-bindings/clock/starfive,jh8100-crg.h @@ -162,4 +162,181 @@ #define JH8100_NWCLK_UART5_ICG_EN 39 #define JH8100_NWCLK_UART6_ICG_EN 40 +/* NECRG clocks */ +#define JH8100_NECLK_FLEXNOC_DMASLV 0 +#define JH8100_NECLK_MAILBOX_APB 1 +#define JH8100_NECLK_SR5_TIMER0_APB 2 +#define JH8100_NECLK_SR5_TIMER0_CH0 3 +#define JH8100_NECLK_SR5_TIMER0_CH1 4 +#define JH8100_NECLK_SR5_TIMER0_CH2 5 +#define JH8100_NECLK_SR5_TIMER0_CH3 6 +#define JH8100_NECLK_SR5_TIMER1_APB 7 +#define JH8100_NECLK_SR5_TIMER1_CH0 8 +#define JH8100_NECLK_SR5_TIMER1_CH1 9 +#define JH8100_NECLK_SR5_TIMER1_CH2 10 +#define JH8100_NECLK_SR5_TIMER1_CH3 11 +#define JH8100_NECLK_USB3_CMN_SCAN_PLL 12 +#define JH8100_NECLK_USB3_CMN_SCAN_SER 13 +#define JH8100_NECLK_USB3_PIPE_IN_SCAN 14 +#define JH8100_NECLK_USB3_SCAN_PIPE 15 +#define JH8100_NECLK_USB3_SCAN_PSM 16 +#define JH8100_NECLK_USB3_SCAN_REF 17 +#define JH8100_NECLK_USB3_USB2_SCAN 18 +#define JH8100_NECLK_USB3_HSCLK 19 +#define JH8100_NECLK_USB3_HSSICLK 20 +#define JH8100_NECLK_USB3_SIECLK 21 +#define JH8100_NECLK_USB3_XCVR_SCAN_PLL 22 +#define JH8100_NECLK_USB3_XCVR_SCAN_SER 23 +#define JH8100_NECLK_USB3_TAP_TCK 24 +#define JH8100_NECLK_USB1_CMN_SCAN_PLL 25 +#define JH8100_NECLK_USB1_CMN_SCAN_SER 26 +#define JH8100_NECLK_USB1_PIPE_IN_SCAN 27 +#define JH8100_NECLK_USB1_SCAN_PIPE 28 +#define JH8100_NECLK_USB1_SCAN_PSM 29 +#define JH8100_NECLK_USB1_SCAN_REF 30 +#define JH8100_NECLK_USB1_USB2_SCAN 31 +#define JH8100_NECLK_USB1_HSCLK 32 +#define JH8100_NECLK_USB1_HSSICLK 33 +#define JH8100_NECLK_USB1_SIECLK 34 +#define JH8100_NECLK_USB1_XCVR_SCAN_PLL 35 +#define JH8100_NECLK_USB1_XCVR_SCAN_SER 36 +#define JH8100_NECLK_USB1_TAP_TCK 37 +#define JH8100_NECLK_USB2_CMN_SCAN_PLL 38 +#define JH8100_NECLK_USB2_CMN_SCAN_SER 39 +#define JH8100_NECLK_USB2_PIPE_IN_SCAN 40 +#define JH8100_NECLK_USB2_SCAN_PIPE 41 +#define JH8100_NECLK_USB2_SCAN_PSM 42 +#define JH8100_NECLK_USB2_SCAN_REF 43 +#define JH8100_NECLK_USB2_USB2_SCAN 44 +#define JH8100_NECLK_USB2_HSCLK 45 +#define JH8100_NECLK_USB2_HSSICLK 46 +#define JH8100_NECLK_USB2_SIECLK 47 +#define JH8100_NECLK_USB2_XCVR_SCAN_PLL 48 +#define JH8100_NECLK_USB2_XCVR_SCAN_SER 49 +#define JH8100_NECLK_USB2_TAP_TCK 50 +#define JH8100_NECLK_TYPEC_PIPE_DIV_SCAN 51 +#define JH8100_NECLK_TYPEC_CMN_SCAN_PLL 52 +#define JH8100_NECLK_TYPEC_CMN_SCAN_SER 53 +#define JH8100_NECLK_TYPEC_SCAN_PIPE 54 +#define JH8100_NECLK_TYPEC_SCAN_PSM 55 +#define JH8100_NECLK_TYPEC_SCAN_REF 56 +#define JH8100_NECLK_TYPEC_USB2_SCAN 57 +#define JH8100_NECLK_TYPEC_HSCLK 58 +#define JH8100_NECLK_TYPEC_HSSICLK 59 +#define JH8100_NECLK_TYPEC_SIECLK 60 +#define JH8100_NECLK_TYPEC_VID0 61 +#define JH8100_NECLK_TYPEC_VID1 62 +#define JH8100_NECLK_TYPEC_XCVR_SCAN_PLL0 63 +#define JH8100_NECLK_TYPEC_XCVR_SCAN_PLL1 64 +#define JH8100_NECLK_TYPEC_XCVR_SCAN_PLL2 65 +#define JH8100_NECLK_TYPEC_XCVR_SCAN_PLL3 66 +#define JH8100_NECLK_TYPEC_XCVR_SCAN_SER0 67 +#define JH8100_NECLK_TYPEC_XCVR_SCAN_SER1 68 +#define JH8100_NECLK_TYPEC_XCVR_SCAN_SER2 69 +#define JH8100_NECLK_TYPEC_XCVR_SCAN_SER3 70 +#define JH8100_NECLK_TYPEC_TAP_TCK 71 +#define JH8100_NECLK_VENC_AXI 72 +#define JH8100_NECLK_VC9000LE_AXI 73 +#define JH8100_NECLK_VC9000LE_APB 74 +#define JH8100_NECLK_VC9000LE_CORECLK 75 +#define JH8100_NECLK_INT_CTRL_APB 76 +#define JH8100_NECLK_PWM_8CH_APB 77 +#define JH8100_NECLK_WDT_APB 78 +#define JH8100_NECLK_WDT 79 +#define JH8100_NECLK_SPI0_APB 80 +#define JH8100_NECLK_SPI0_CORE 81 +#define JH8100_NECLK_SPI0_SCLK_IN 82 +#define JH8100_NECLK_SPI1_APB 83 +#define JH8100_NECLK_SPI1_CORE 84 +#define JH8100_NECLK_SPI1_SCLK_IN 85 +#define JH8100_NECLK_I2C0_APB 86 +#define JH8100_NECLK_I2C1_APB 87 +#define JH8100_NECLK_I2C2_APB 88 +#define JH8100_NECLK_I2C3_APB 89 +#define JH8100_NECLK_I2C4_APB 90 +#define JH8100_NECLK_I2C5_APB 91 +#define JH8100_NECLK_UART0_APB 92 +#define JH8100_NECLK_UART0_CORE 93 +#define JH8100_NECLK_UART1_CORE_PREOSC 94 +#define JH8100_NECLK_UART1_APB 95 +#define JH8100_NECLK_UART1_CORE 96 +#define JH8100_NECLK_UART2_CORE_PREOSC 97 +#define JH8100_NECLK_UART2_APB 98 +#define JH8100_NECLK_UART2_CORE 99 +#define JH8100_NECLK_UART3_CORE_PREOSC 100 +#define JH8100_NECLK_UART3_APB 101 +#define JH8100_NECLK_UART3_CORE 102 +#define JH8100_NECLK_UART4_CORE_PREOSC 103 +#define JH8100_NECLK_UART4_APB 104 +#define JH8100_NECLK_UART4_CORE 105 +#define JH8100_NECLK_I2S0_BCLK 106 +#define JH8100_NECLK_I2S0_LRCK 107 +#define JH8100_NECLK_I2S0_APB 108 +#define JH8100_NECLK_I2S0 109 +#define JH8100_NECLK_I2S0_N 110 +#define JH8100_NECLK_I2S0_BCLK_TX 111 +#define JH8100_NECLK_I2S0_LRCK_TX 112 +#define JH8100_NECLK_I2S0_BCLK_RX 113 +#define JH8100_NECLK_I2S0_LRCK_RX 114 +#define JH8100_NECLK_I2S1_BCLK 115 +#define JH8100_NECLK_I2S1_LRCK 116 +#define JH8100_NECLK_I2S1_APB 117 +#define JH8100_NECLK_I2S1 118 +#define JH8100_NECLK_I2S1_N 119 +#define JH8100_NECLK_I2S1_BCLK_TX 120 +#define JH8100_NECLK_I2S1_LRCK_TX 121 +#define JH8100_NECLK_I2S1_BCLK_RX 122 +#define JH8100_NECLK_I2S1_LRCK_RX 123 +#define JH8100_NECLK_I2S2_BCLK 124 +#define JH8100_NECLK_I2S2_LRCK 125 +#define JH8100_NECLK_I2S2_APB 126 +#define JH8100_NECLK_I2S2 127 +#define JH8100_NECLK_I2S2_N 128 +#define JH8100_NECLK_I2S2_BCLK_TX 129 +#define JH8100_NECLK_I2S2_LRCK_TX 130 +#define JH8100_NECLK_I2S2_BCLK_RX 131 +#define JH8100_NECLK_I2S2_LRCK_RX 132 +#define JH8100_NECLK_I2S3_BCLK 133 +#define JH8100_NECLK_I2S3_LRCK 134 +#define JH8100_NECLK_I2S0_STEREO_APB 135 +#define JH8100_NECLK_I2S0_STEREO 136 +#define JH8100_NECLK_I2S0_STEREO_N 137 +#define JH8100_NECLK_I2S0_STEREO_BCLK_TX 138 +#define JH8100_NECLK_I2S0_STEREO_LRCK_TX 139 +#define JH8100_NECLK_I2S0_STEREO_BCLK_RX_ICG 140 +#define JH8100_NECLK_I2S0_STEREO_LRCK_RX 141 +#define JH8100_NECLK_PDM_4MIC_DMIC 142 +#define JH8100_NECLK_PDM_4MIC_APB 143 +#define JH8100_NECLK_PDM_4MIC_SCAN 144 +#define JH8100_NECLK_CAN0_CTRL_PCLK 145 +#define JH8100_NECLK_CAN0_CTRL 146 +#define JH8100_NECLK_CAN0_CTRL_TIMER 147 +#define JH8100_NECLK_CAN1_CTRL_PCLK 148 +#define JH8100_NECLK_CAN1_CTRL 149 +#define JH8100_NECLK_CAN1_CTRL_TIMER 150 +#define JH8100_NECLK_SMBUS0_APB 151 +#define JH8100_NECLK_SMBUS0_CORE 152 +#define JH8100_NECLK_IOMUX_EAST_PCLK 153 +#define JH8100_NECLK_USB3_ICG_EN 154 +#define JH8100_NECLK_USB1_ICG_EN 155 +#define JH8100_NECLK_USB2_ICG_EN 156 +#define JH8100_NECLK_USBC_ICG_EN 157 +#define JH8100_NECLK_VENC_ICG_EN 158 +#define JH8100_NECLK_WDT0_ICG_EN 159 +#define JH8100_NECLK_SPI0_ICG_EN 160 +#define JH8100_NECLK_SPI1_ICG_EN 161 +#define JH8100_NECLK_UART0_ICG_EN 162 +#define JH8100_NECLK_UART1_ICG_EN 163 +#define JH8100_NECLK_UART2_ICG_EN 164 +#define JH8100_NECLK_UART3_ICG_EN 165 +#define JH8100_NECLK_UART4_ICG_EN 166 +#define JH8100_NECLK_I2S0_ICG_EN 167 +#define JH8100_NECLK_I2S1_ICG_EN 168 +#define JH8100_NECLK_I2S2_ICG_EN 169 +#define JH8100_NECLK_I2S_STEREO_ICG_EN 170 +#define JH8100_NECLK_PDM_4MIC_ICG_EN 171 +#define JH8100_NECLK_CAN0_ICG_EN 172 +#define JH8100_NECLK_CAN1_ICG_EN 173 +#define JH8100_NECLK_SMBUS0_ICG_EN 174 + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */ diff --git a/include/dt-bindings/reset/starfive,jh8100-crg.h b/include/dt-bindings/reset/starfive,jh8100-crg.h index b25f6522f3d4..30a99c78341a 100644 --- a/include/dt-bindings/reset/starfive,jh8100-crg.h +++ b/include/dt-bindings/reset/starfive,jh8100-crg.h @@ -32,4 +32,63 @@ #define JH8100_NWRST_MERAK0_TVSENSOR 8 #define JH8100_NWRST_MERAK1_TVSENSOR 9 +/* + * NECRG resets: assert0 + */ +#define JH8100_NERST_PRESETN 0 +#define JH8100_NERST_USB3_APB 1 +#define JH8100_NERST_USB3_TORR_PHY 2 +#define JH8100_NERST_USB3_CONFIG 3 +#define JH8100_NERST_USB1_APB 4 +#define JH8100_NERST_USB1_TORRENT_PHY 5 +#define JH8100_NERST_USB1_CONFIG 6 +#define JH8100_NERST_USB2_APB 7 +#define JH8100_NERST_USB2_TORRENT_PHY 8 +#define JH8100_NERST_USB2_CONFIG 9 +#define JH8100_NERST_USBC_APB 10 +#define JH8100_NERST_USBC_CONFIG 11 +#define JH8100_NERST_VC9000LE 12 +#define JH8100_NERST_INT_CTRL_APB 13 +#define JH8100_NERST_PWM_8CH_APB 14 +#define JH8100_NERST_WDT0 15 +#define JH8100_NERST_SPI0 16 +#define JH8100_NERST_SPI1 17 +#define JH8100_NERST_I2C0 18 +#define JH8100_NERST_I2C1 19 +#define JH8100_NERST_I2C2 20 +#define JH8100_NERST_I2C3 21 +#define JH8100_NERST_I2C4 22 +#define JH8100_NERST_I2C5 23 +#define JH8100_NERST_UART0 24 +#define JH8100_NERST_UART1 25 +#define JH8100_NERST_UART2 26 +#define JH8100_NERST_UART3 27 +#define JH8100_NERST_UART4 28 +#define JH8100_NERST_MAILBOX_PRESETN 29 +#define JH8100_NERST_TIMER0_APB 30 +#define JH8100_NERST_TIMER0_CH0 31 + +/* + * NECRG resets: assert1 + */ + +#define JH8100_NERST_TIMER0_CH1 32 +#define JH8100_NERST_TIMER0_CH2 33 +#define JH8100_NERST_TIMER0_CH3 34 +#define JH8100_NERST_TIMER1_APB 35 +#define JH8100_NERST_TIMER1_CH0 36 +#define JH8100_NERST_TIMER1_CH1 37 +#define JH8100_NERST_TIMER1_CH2 38 +#define JH8100_NERST_TIMER1_CH3 39 +#define JH8100_NERST_I2S0_RSTN_APB 40 +#define JH8100_NERST_I2S1_RSTN_APB 41 +#define JH8100_NERST_I2S2_RSTN_APB 42 +#define JH8100_NERST_I2S0_STEREO_APB 43 +#define JH8100_NERST_PDM 44 +#define JH8100_NERST_CAN0 45 +#define JH8100_NERST_CAN1 46 +#define JH8100_NERST_SMBUS0 47 +#define JH8100_NERST_SYS_IOMUX_E 48 +#define JH8100_NERST_DUBHE_TVSENSOR 49 + #endif /* __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ */ From patchwork Tue Dec 26 05:38:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: JeeHeng Sia X-Patchwork-Id: 758433 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70A354E1B8; Tue, 26 Dec 2023 05:40:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=starfivetech.com Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id C7AC4807C; Tue, 26 Dec 2023 13:40:15 +0800 (CST) Received: from EXMBX066.cuchost.com (172.16.7.66) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 26 Dec 2023 13:40:15 +0800 Received: from jsia-virtual-machine.localdomain (202.188.176.82) by EXMBX066.cuchost.com (172.16.6.66) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 26 Dec 2023 13:40:09 +0800 From: Sia Jee Heng To: , , , , , , , , , , , , CC: , , , , , Subject: [RFC 11/16] dt-bindings: clock: Add StarFive JH8100 South-West clock and reset generator Date: Tue, 26 Dec 2023 13:38:43 +0800 Message-ID: <20231226053848.25089-12-jeeheng.sia@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231226053848.25089-1-jeeheng.sia@starfivetech.com> References: <20231226053848.25089-1-jeeheng.sia@starfivetech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX066.cuchost.com (172.16.6.66) X-YovoleRuleAgent: yovoleflag Add bindings for the South-West clock and reset generator (SWCRG) on JH8100 SoC. Signed-off-by: Sia Jee Heng Reviewed-by: Ley Foon Tan --- .../bindings/clock/starfive,jh8100-swcrg.yaml | 64 +++++++++++++++++++ .../dt-bindings/clock/starfive,jh8100-crg.h | 12 ++++ .../dt-bindings/reset/starfive,jh8100-crg.h | 8 +++ 3 files changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-swcrg.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jh8100-swcrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh8100-swcrg.yaml new file mode 100644 index 000000000000..287dff7e91e3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh8100-swcrg.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh8100-swcrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH8100 South-West Clock And Reset Generator + +maintainers: + - Sia Jee Heng + +properties: + compatible: + const: starfive,jh8100-swcrg + + reg: + maxItems: 1 + + clocks: + items: + - description: APB_BUS clock from SYSCRG + - description: VDEC_ROOT clock from SYSCRG + - description: FLEXNOC1 clock from SYSCRG + + clock-names: + items: + - const: apb_bus + - const: vdec_root + - const: flexnoc1 + + '#clock-cells': + const: 1 + description: + See for valid indices. + + '#reset-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@12720000 { + compatible = "starfive,jh8100-swcrg"; + reg = <0x12720000 0x10000>; + clocks = <&syscrg JH8100_SYSCLK_APB_BUS>, + <&syscrg JH8100_SYSCLK_VDEC_ROOT>, + <&syscrg JH8100_SYSCLK_FLEXNOC1>; + clock-names = "apb_bus", "vdec_root", "flexnoc1"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jh8100-crg.h b/include/dt-bindings/clock/starfive,jh8100-crg.h index c37b42f3eacd..7b337c1495be 100644 --- a/include/dt-bindings/clock/starfive,jh8100-crg.h +++ b/include/dt-bindings/clock/starfive,jh8100-crg.h @@ -339,4 +339,16 @@ #define JH8100_NECLK_CAN1_ICG_EN 173 #define JH8100_NECLK_SMBUS0_ICG_EN 174 +/* SWCRG clocks */ +#define JH8100_SWCLK_JPEG_AXI 0 +#define JH8100_SWCLK_VC9000DJ_AXI 1 +#define JH8100_SWCLK_VC9000DJ_VDEC 2 +#define JH8100_SWCLK_VC9000DJ_APB 3 +#define JH8100_SWCLK_VDEC_AXI 4 +#define JH8100_SWCLK_VC9000D_AXI 5 +#define JH8100_SWCLK_VC9000D_VDEC 6 +#define JH8100_SWCLK_VC9000D_APB 7 +#define JH8100_SWCLK_JPEG_ICG_EN 8 +#define JH8100_SWCLK_VDEC_ICG_EN 9 + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */ diff --git a/include/dt-bindings/reset/starfive,jh8100-crg.h b/include/dt-bindings/reset/starfive,jh8100-crg.h index 30a99c78341a..de4f25dc301d 100644 --- a/include/dt-bindings/reset/starfive,jh8100-crg.h +++ b/include/dt-bindings/reset/starfive,jh8100-crg.h @@ -91,4 +91,12 @@ #define JH8100_NERST_SYS_IOMUX_E 48 #define JH8100_NERST_DUBHE_TVSENSOR 49 +/* + * SWCRG resets: assert0 + */ +#define JH8100_SWRST_PRESETN 0 +#define JH8100_SWRST_VC9000DJ 1 +#define JH8100_SWRST_VC9000D 2 +#define JH8100_SWRST_DDR_TVSENSOR 3 + #endif /* __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ */ From patchwork Tue Dec 26 05:38:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: JeeHeng Sia X-Patchwork-Id: 758432 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9817E4E60B; Tue, 26 Dec 2023 05:40:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=starfivetech.com Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id D7B6224E03E; Tue, 26 Dec 2023 13:40:28 +0800 (CST) Received: from EXMBX066.cuchost.com (172.16.7.66) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 26 Dec 2023 13:40:28 +0800 Received: from jsia-virtual-machine.localdomain (202.188.176.82) by EXMBX066.cuchost.com (172.16.6.66) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 26 Dec 2023 13:40:22 +0800 From: Sia Jee Heng To: , , , , , , , , , , , , CC: , , , , , Subject: [RFC 13/16] dt-bindings: clock: Add StarFive JH8100 Always-On clock and reset generator Date: Tue, 26 Dec 2023 13:38:45 +0800 Message-ID: <20231226053848.25089-14-jeeheng.sia@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231226053848.25089-1-jeeheng.sia@starfivetech.com> References: <20231226053848.25089-1-jeeheng.sia@starfivetech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX066.cuchost.com (172.16.6.66) X-YovoleRuleAgent: yovoleflag Add bindings for the Always-On clock and reset generator (AONCRG) on JH8100 SoC. Signed-off-by: Sia Jee Heng Reviewed-by: Ley Foon Tan --- .../clock/starfive,jh8100-aoncrg.yaml | 74 +++++++++++++++++++ .../dt-bindings/clock/starfive,jh8100-crg.h | 67 +++++++++++++++++ .../dt-bindings/reset/starfive,jh8100-crg.h | 16 ++++ 3 files changed, 157 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-aoncrg.yaml diff --git a/Documentation/devicetree/bindings/clock/starfive,jh8100-aoncrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh8100-aoncrg.yaml new file mode 100644 index 000000000000..4ae1ef827fc9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jh8100-aoncrg.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jh8100-aoncrg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH8100 Always-On Clock and Reset Generator + +maintainers: + - Sia Jee Heng + +properties: + compatible: + const: starfive,jh8100-aoncrg + + reg: + maxItems: 1 + + clocks: + items: + - description: Main Oscillator (24 MHz) + - description: GMAC0 RMII func + - description: GMAC0 RGMII func + - description: AON 125MHz clock + - description: AON 2000MHz clock + - description: AON 200MHz clock + - description: AON 667MHz clock + - description: RTC clock + + clock-names: + items: + - const: osc + - const: gmac0-rmii-func + - const: gmac0-rgmii-func + - const: aon125 + - const: aon2000 + - const: aon200 + - const: aon667 + - const: rtc + + '#clock-cells': + const: 1 + description: + See for valid indices. + + '#reset-cells': + const: 1 + description: + See for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + + clock-controller@1f310000 { + compatible = "starfive,jh8100-aoncrg"; + reg = <0x1f310000 0x10000>; + clocks = <&osc>, <&gmac0_rmii_func>, <&gmac0_rgmii_func>, <&aon125>, + <&aon2000>, <&aon200>, <&aon667>, <&rtc>; + clock-names = "osc", "gmac0-rmii-func", "gmac0-rgmii-func", "aon125", + "aon2000", "aon200", "aon667", "rtc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/starfive,jh8100-crg.h b/include/dt-bindings/clock/starfive,jh8100-crg.h index 7b337c1495be..8207d5a2f4b3 100644 --- a/include/dt-bindings/clock/starfive,jh8100-crg.h +++ b/include/dt-bindings/clock/starfive,jh8100-crg.h @@ -351,4 +351,71 @@ #define JH8100_SWCLK_JPEG_ICG_EN 8 #define JH8100_SWCLK_VDEC_ICG_EN 9 +/* AONCRG clocks */ +#define JH8100_AONCLK_GMAC0_RMII_REFIN 0 +#define JH8100_AONCLK_GMAC0_RGMII_RXIN 1 +#define JH8100_AONCLK_GMAC0_GTXCLK 2 +#define JH8100_AONCLK_AON_1000 3 +#define JH8100_AONCLK_AON_400 4 +#define JH8100_AONCLK_AON_400_POSTOSC 5 +#define JH8100_AONCLK_AON_500 6 +#define JH8100_AONCLK_AON_500_POSTOSC 7 +#define JH8100_AONCLK_XSPI_PHY 8 +#define JH8100_AONCLK_AON_100 9 +#define JH8100_AONCLK_AON_100_POSTOSC 10 +#define JH8100_AONCLK_AON_50_POSTOSC 11 +#define JH8100_AONCLK_DDR50_POSTOCC_ICG 12 +#define JH8100_AONCLK_DDR100_POSTOCC_ICG 13 +#define JH8100_AONCLK_PUFRT_APB 14 +#define JH8100_AONCLK_RTC_HMS_APB 15 +#define JH8100_AONCLK_RTC_INTERNAL 16 +#define JH8100_AONCLK_RTC_HMS_OSC32K 17 +#define JH8100_AONCLK_RTC_HMS_CAL 18 +#define JH8100_AONCLK_GMAC0_AXI128_AHB 19 +#define JH8100_AONCLK_GMAC0_AXI128_MSTRCLK 20 +#define JH8100_AONCLK_GMAC0_AXI128_AXI 21 +#define JH8100_AONCLK_GMAC0_RMII_RTX 22 +#define JH8100_AONCLK_GMAC0_AXI128_TX 23 +#define JH8100_AONCLK_GMAC0_AXI128_TX_INV 24 +#define JH8100_AONCLK_GMAC0_AXI128_RX 25 +#define JH8100_AONCLK_GMAC0_AXI128_RX_INV 26 +#define JH8100_AONCLK_GMAC0_GTXC 27 +#define JH8100_AONCLK_XSPI_AXI 28 +#define JH8100_AONCLK_XSPI_APB 29 +#define JH8100_AONCLK_XSPI_XSPI_PHY 30 +#define JH8100_AONCLK_TVSENSOR_PCLK 31 +#define JH8100_AONCLK_TVSENSOR_TSADC 32 +#define JH8100_AONCLK_TVSENSOR_BG 33 +#define JH8100_AONCLK_MEU_PCLK_AP 34 +#define JH8100_AONCLK_MEU_PCLK_SCP 35 +#define JH8100_AONCLK_MEU_MEM_AXI 36 +#define JH8100_AONCLK_AXIMEM_128B_ACLK 37 +#define JH8100_AONCLK_APB2BISR_APB 38 +#define JH8100_AONCLK_APB2BISR_BISR 39 +#define JH8100_AONCLK_EMMC_S_PCLK 40 +#define JH8100_AONCLK_EMMC_MSTRCLK 41 +#define JH8100_AONCLK_EMMC 42 +#define JH8100_AONCLK_EMMC_SDMCLK 43 +#define JH8100_AONCLK_EMMC_SDPHY_PCLK 44 +#define JH8100_AONCLK_SDIO0_PCLK 45 +#define JH8100_AONCLK_SDIO0_MSTRCLK 46 +#define JH8100_AONCLK_SDIO0 47 +#define JH8100_AONCLK_SDIO0_SDMCLK 48 +#define JH8100_AONCLK_SDIO0_SDPHY_PCLK 49 +#define JH8100_AONCLK_HCLK 50 +#define JH8100_AONCLK_ACLK 51 +#define JH8100_AONCLK_PERF_MSTRCLK 52 +#define JH8100_AONCLK_PERF_SLVCLK 53 +#define JH8100_AONCLK_GCLK0 54 +#define JH8100_AONCLK_GCLK_OSC 55 +#define JH8100_AONCLK_RTC_ICG_EN 56 +#define JH8100_AONCLK_GMAC0_ICG_EN 57 +#define JH8100_AONCLK_XSPI_ICG_EN 58 +#define JH8100_AONCLK_TVSENSOR0_ICG_EN 59 +#define JH8100_AONCLK_MEU_ICG_EN 60 +#define JH8100_AONCLK_APB2BISR_ICG_EN 61 +#define JH8100_AONCLK_EMMC_ICG_EN 62 +#define JH8100_AONCLK_SDIO0_ICG_EN 63 +#define JH8100_AONCLK_TOP_ICG_EN 64 + #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH8100_H__ */ diff --git a/include/dt-bindings/reset/starfive,jh8100-crg.h b/include/dt-bindings/reset/starfive,jh8100-crg.h index de4f25dc301d..23f15d4be22f 100644 --- a/include/dt-bindings/reset/starfive,jh8100-crg.h +++ b/include/dt-bindings/reset/starfive,jh8100-crg.h @@ -99,4 +99,20 @@ #define JH8100_SWRST_VC9000D 2 #define JH8100_SWRST_DDR_TVSENSOR 3 +/* + * AONCRG resets: assert0 + */ +#define JH8100_AONRST_AON_IOMUX_PRESETN 0 +#define JH8100_AONRST_RTC 1 +#define JH8100_AONRST_GMAC0 2 +#define JH8100_AONRST_XSPI 3 +#define JH8100_AONRST_TVSENSOR 4 +#define JH8100_AONRST_MEU 5 +#define JH8100_AONRST_AXIMEM_128B_ARESET 6 +#define JH8100_AONRST_DFT_APB2BISR_APB 7 +#define JH8100_AONRST_SDIO0 8 +#define JH8100_AONRST_EMMC 9 +#define JH8100_AONRST_TOP 10 +#define JH8100_AONRST_IRQ_CTRL 11 + #endif /* __DT_BINDINGS_RESET_STARFIVE_JH8100_H__ */ From patchwork Tue Dec 26 05:38:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: JeeHeng Sia X-Patchwork-Id: 758431 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96B4B4EB25; Tue, 26 Dec 2023 05:40:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=starfivetech.com Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 140FD8022; Tue, 26 Dec 2023 13:40:42 +0800 (CST) Received: from EXMBX066.cuchost.com (172.16.7.66) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 26 Dec 2023 13:40:41 +0800 Received: from jsia-virtual-machine.localdomain (202.188.176.82) by EXMBX066.cuchost.com (172.16.6.66) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 26 Dec 2023 13:40:35 +0800 From: Sia Jee Heng To: , , , , , , , , , , , , CC: , , , , , , Joshua Yeong Subject: [RFC 15/16] reset: starfive: Add StarFive JH8100 reset driver Date: Tue, 26 Dec 2023 13:38:47 +0800 Message-ID: <20231226053848.25089-16-jeeheng.sia@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231226053848.25089-1-jeeheng.sia@starfivetech.com> References: <20231226053848.25089-1-jeeheng.sia@starfivetech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX066.cuchost.com (172.16.6.66) X-YovoleRuleAgent: yovoleflag Add auxiliary reset driver to support StarFive JH8100 SoC. Co-developed-by: Joshua Yeong Signed-off-by: Joshua Yeong Signed-off-by: Sia Jee Heng Reviewed-by: Ley Foon Tan --- MAINTAINERS | 7 ++ drivers/reset/starfive/Kconfig | 8 ++ drivers/reset/starfive/Makefile | 2 + .../reset/starfive/reset-starfive-jh8100.c | 108 ++++++++++++++++++ 4 files changed, 125 insertions(+) create mode 100644 drivers/reset/starfive/reset-starfive-jh8100.c diff --git a/MAINTAINERS b/MAINTAINERS index 1ea4a694ed31..96fbe3259356 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20692,6 +20692,13 @@ F: Documentation/devicetree/bindings/clock/starfive,jh81*.yaml F: drivers/clk/starfive/clk-starfive-jh81* F: include/dt-bindings/clock/starfive?jh81*.h +STARFIVE JH8100 RESET CONTROLLER DRIVERS +M: Sia Jee Heng +M: Ley Foon Tan +S: Maintained +F: drivers/reset/starfive/reset-starfive-jh81* +F: include/dt-bindings/reset/starfive?jh81*.h + STATIC BRANCH/CALL M: Peter Zijlstra M: Josh Poimboeuf diff --git a/drivers/reset/starfive/Kconfig b/drivers/reset/starfive/Kconfig index 29fbcf1a7d83..88d050044d52 100644 --- a/drivers/reset/starfive/Kconfig +++ b/drivers/reset/starfive/Kconfig @@ -19,3 +19,11 @@ config RESET_STARFIVE_JH7110 default ARCH_STARFIVE help This enables the reset controller driver for the StarFive JH7110 SoC. + +config RESET_STARFIVE_JH8100 + bool "StarFive JH8100 Reset Driver" + depends on AUXILIARY_BUS && CLK_STARFIVE_JH8100_SYS + select RESET_STARFIVE_COMMON + default ARCH_STARFIVE + help + This enables the reset controller driver for the StarFive JH8100 SoC. diff --git a/drivers/reset/starfive/Makefile b/drivers/reset/starfive/Makefile index 582e4c160bd4..ede1fc1c9601 100644 --- a/drivers/reset/starfive/Makefile +++ b/drivers/reset/starfive/Makefile @@ -3,3 +3,5 @@ obj-$(CONFIG_RESET_STARFIVE_COMMON) += reset-starfive-common.o obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o obj-$(CONFIG_RESET_STARFIVE_JH7110) += reset-starfive-jh7110.o + +obj-$(CONFIG_RESET_STARFIVE_JH8100) += reset-starfive-jh8100.o diff --git a/drivers/reset/starfive/reset-starfive-jh8100.c b/drivers/reset/starfive/reset-starfive-jh8100.c new file mode 100644 index 000000000000..a14418653608 --- /dev/null +++ b/drivers/reset/starfive/reset-starfive-jh8100.c @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Reset driver for the StarFive JH8100 SoC + * + * Copyright (C) 2023 StarFive Technology Co., Ltd. + */ + +#include +#include +#include + +#include "reset-starfive-common.h" + +#define JH8100_SYSRST_NUM_RESETS (JH8100_SYSRST_HD_AUDIO + 1) +#define JH8100_NWRST_NUM_RESETS (JH8100_NWRST_MERAK1_TVSENSOR + 1) +#define JH8100_NERST_NUM_RESETS (JH8100_NERST_DUBHE_TVSENSOR + 1) +#define JH8100_SWRST_NUM_RESETS (JH8100_SWRST_DDR_TVSENSOR + 1) +#define JH8100_AONRST_NUM_RESETS (JH8100_AONRST_IRQ_CTRL + 1) + +struct jh8100_reset_info { + unsigned int nr_resets; + unsigned int assert_offset; + unsigned int status_offset; +}; + +static const struct jh8100_reset_info jh8100_sys_info = { + .nr_resets = JH8100_SYSRST_NUM_RESETS, + .assert_offset = 0x1B4, + .status_offset = 0x1B8, +}; + +static const struct jh8100_reset_info jh8100_sys_nw_info = { + .nr_resets = JH8100_NWRST_NUM_RESETS, + .assert_offset = 0xA4, + .status_offset = 0xA8, +}; + +static const struct jh8100_reset_info jh8100_sys_ne_info = { + .nr_resets = JH8100_NERST_NUM_RESETS, + .assert_offset = 0x2BC, + .status_offset = 0x2C4, +}; + +static const struct jh8100_reset_info jh8100_sys_sw_info = { + .nr_resets = JH8100_SWRST_NUM_RESETS, + .assert_offset = 0x28, + .status_offset = 0x2C, +}; + +static const struct jh8100_reset_info jh8100_aon_info = { + .nr_resets = JH8100_AONRST_NUM_RESETS, + .assert_offset = 0x104, + .status_offset = 0x108, +}; + +static int jh8100_reset_probe(struct auxiliary_device *adev, + const struct auxiliary_device_id *id) +{ + struct jh8100_reset_info *info = (struct jh8100_reset_info *) + (id->driver_data); + struct starfive_reset_adev *rdev = to_starfive_reset_adev(adev); + void __iomem *base = rdev->base; + + if (!info || !base) + return -ENODEV; + + return reset_starfive_register(&adev->dev, + adev->dev.parent->of_node, + base + info->assert_offset, + base + info->status_offset, NULL, + info->nr_resets, NULL); +} + +static const struct auxiliary_device_id jh8100_reset_ids[] = { + { + .name = "clk_starfive_jh8100_sys.rst-sys", + .driver_data = (kernel_ulong_t)&jh8100_sys_info, + }, + { + .name = "clk_starfive_jh8100_sys.rst-nw", + .driver_data = (kernel_ulong_t)&jh8100_sys_nw_info, + }, + { + .name = "clk_starfive_jh8100_sys.rst-ne", + .driver_data = (kernel_ulong_t)&jh8100_sys_ne_info, + }, + { + .name = "clk_starfive_jh8100_sys.rst-sw", + .driver_data = (kernel_ulong_t)&jh8100_sys_sw_info, + }, + { + .name = "clk_starfive_jh8100_sys.rst-aon", + .driver_data = (kernel_ulong_t)&jh8100_aon_info, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(auxiliary, jh8100_reset_ids); + +static struct auxiliary_driver jh8100_reset_driver = { + .probe = jh8100_reset_probe, + .id_table = jh8100_reset_ids, +}; +module_auxiliary_driver(jh8100_reset_driver); + +MODULE_AUTHOR("Joshua Yeong "); +MODULE_AUTHOR("Sia Jee Heng "); +MODULE_DESCRIPTION("StarFive JH8100 reset driver"); +MODULE_LICENSE("GPL");