From patchwork Mon Dec 25 10:32:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu Chien Peter Lin X-Patchwork-Id: 758267 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B75115466C; Mon, 25 Dec 2023 10:49:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from Atcsqr.andestech.com (localhost [127.0.0.2] (may be forged)) by Atcsqr.andestech.com with ESMTP id 3BPAZimB094857; Mon, 25 Dec 2023 18:35:44 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BPAXRJF093129; Mon, 25 Dec 2023 18:33:27 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Mon, 25 Dec 2023 18:33:24 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: Randolph Subject: [PATCH v6 03/16] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Date: Mon, 25 Dec 2023 18:32:55 +0800 Message-ID: <20231225103308.1557548-4-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231225103308.1557548-1-peterlin@andestech.com> References: <20231225103308.1557548-1-peterlin@andestech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 3BPAZimB094857 Add support for the Andes hart-level interrupt controller. This controller provides interrupt mask/unmask functions to access the custom register (SLIE) where the non-standard S-mode local interrupt enable bits are located. The base of custom interrupt number is set to 256. To share the riscv_intc_domain_map() with the generic RISC-V INTC and ACPI, add a chip parameter to riscv_intc_init_common(), so it can be passed to the irq_domain_set_info() as a private data. Andes hart-level interrupt controller requires the "andestech,cpu-intc" compatible string to be present in interrupt-controller of cpu node to enable the use of custom local interrupt source. e.g., cpu0: cpu@0 { compatible = "andestech,ax45mp", "riscv"; ... cpu0-intc: interrupt-controller { #interrupt-cells = <0x01>; compatible = "andestech,cpu-intc", "riscv,cpu-intc"; interrupt-controller; }; }; Signed-off-by: Yu Chien Peter Lin Reviewed-by: Randolph --- Changes v1 -> v2: - New patch Changes v2 -> v3: - Return -ENXIO if no valid compatible INTC found - Allow falling back to generic RISC-V INTC Changes v3 -> v4: (Suggested by Thomas [1]) - Add comment to andes irq chip function - Refine code flow to share with generic RISC-V INTC and ACPI - Move Andes specific definitions to include/linux/soc/andes/irq.h Changes v4 -> v5: (Suggested by Thomas) - Fix commit message - Subtract ANDES_SLI_CAUSE_BASE from d->hwirq to calculate the value of mask - Do not set chip_data to the chip itself with irq_domain_set_info() - Follow reverse fir tree order variable declarations Changes v5 -> v6: - To follow the naming on datasheet, rename ANDES_RV_IRQ_PMU to ANDES_RV_IRQ_PMOVI - Initialize the riscv_intc_* global variables for Andes INTC (Suggested by Anup) - Use BITS_PER_LONG to compute the bit mask of SIE/SLIE as they are 64-bit registers (32-bit for RV32) [1] https://patchwork.kernel.org/project/linux-riscv/patch/20231019135723.3657156-1-peterlin@andestech.com/ --- drivers/irqchip/irq-riscv-intc.c | 66 +++++++++++++++++++++++++++----- include/linux/soc/andes/irq.h | 18 +++++++++ 2 files changed, 74 insertions(+), 10 deletions(-) create mode 100644 include/linux/soc/andes/irq.h diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index e1d80cb0020e..977664b5639e 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -17,6 +17,7 @@ #include #include #include +#include static struct irq_domain *intc_domain; static unsigned int riscv_intc_nr_irqs __ro_after_init; @@ -49,6 +50,31 @@ static void riscv_intc_irq_unmask(struct irq_data *d) csr_set(CSR_IE, BIT(d->hwirq)); } +static void andes_intc_irq_mask(struct irq_data *d) +{ + /* + * Andes specific S-mode local interrupt causes (hwirq) + * are defined as (256 + n) and controlled by n-th bit + * of SLIE. + */ + unsigned int mask = BIT(d->hwirq % BITS_PER_LONG); + + if (d->hwirq < ANDES_SLI_CAUSE_BASE) + csr_clear(CSR_IE, mask); + else + csr_clear(ANDES_CSR_SLIE, mask); +} + +static void andes_intc_irq_unmask(struct irq_data *d) +{ + unsigned int mask = BIT(d->hwirq % BITS_PER_LONG); + + if (d->hwirq < ANDES_SLI_CAUSE_BASE) + csr_set(CSR_IE, mask); + else + csr_set(ANDES_CSR_SLIE, mask); +} + static void riscv_intc_irq_eoi(struct irq_data *d) { /* @@ -72,12 +98,21 @@ static struct irq_chip riscv_intc_chip = { .irq_eoi = riscv_intc_irq_eoi, }; +static struct irq_chip andes_intc_chip = { + .name = "RISC-V INTC", + .irq_mask = andes_intc_irq_mask, + .irq_unmask = andes_intc_irq_unmask, + .irq_eoi = riscv_intc_irq_eoi, +}; + static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq) { + struct irq_chip *chip = d->host_data; + irq_set_percpu_devid(irq); - irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data, - handle_percpu_devid_irq, NULL, NULL); + irq_domain_set_info(d, irq, hwirq, chip, NULL, handle_percpu_devid_irq, + NULL, NULL); return 0; } @@ -123,11 +158,12 @@ static struct fwnode_handle *riscv_intc_hwnode(void) return intc_domain->fwnode; } -static int __init riscv_intc_init_common(struct fwnode_handle *fn) +static int __init riscv_intc_init_common(struct fwnode_handle *fn, + struct irq_chip *chip) { int rc; - intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL); + intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, chip); if (!intc_domain) { pr_err("unable to add IRQ domain\n"); return -ENXIO; @@ -153,8 +189,9 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn) static int __init riscv_intc_init(struct device_node *node, struct device_node *parent) { - int rc; + struct irq_chip *chip; unsigned long hartid; + int rc; rc = riscv_of_parent_hartid(node, &hartid); if (rc < 0) { @@ -179,14 +216,23 @@ static int __init riscv_intc_init(struct device_node *node, return 0; } - riscv_intc_nr_irqs = BITS_PER_LONG; - riscv_intc_custom_base = riscv_intc_nr_irqs; - riscv_intc_custom_nr_irqs = 0; + if (of_device_is_compatible(node, "andestech,cpu-intc")) { + riscv_intc_nr_irqs = BITS_PER_LONG; + riscv_intc_custom_base = ANDES_SLI_CAUSE_BASE; + riscv_intc_custom_nr_irqs = ANDES_RV_IRQ_LAST; + chip = &andes_intc_chip; + } else { + riscv_intc_nr_irqs = BITS_PER_LONG; + riscv_intc_custom_base = riscv_intc_nr_irqs; + riscv_intc_custom_nr_irqs = 0; + chip = &riscv_intc_chip; + } - return riscv_intc_init_common(of_node_to_fwnode(node)); + return riscv_intc_init_common(of_node_to_fwnode(node), chip); } IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init); +IRQCHIP_DECLARE(andes, "andestech,cpu-intc", riscv_intc_init); #ifdef CONFIG_ACPI @@ -213,7 +259,7 @@ static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header, return -ENOMEM; } - return riscv_intc_init_common(fn); + return riscv_intc_init_common(fn, &riscv_intc_chip); } IRQCHIP_ACPI_DECLARE(riscv_intc, ACPI_MADT_TYPE_RINTC, NULL, diff --git a/include/linux/soc/andes/irq.h b/include/linux/soc/andes/irq.h new file mode 100644 index 000000000000..edc3182d6e66 --- /dev/null +++ b/include/linux/soc/andes/irq.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023 Andes Technology Corporation + */ +#ifndef __ANDES_IRQ_H +#define __ANDES_IRQ_H + +/* Andes PMU irq number */ +#define ANDES_RV_IRQ_PMOVI 18 +#define ANDES_RV_IRQ_LAST ANDES_RV_IRQ_PMOVI +#define ANDES_SLI_CAUSE_BASE 256 + +/* Andes PMU related registers */ +#define ANDES_CSR_SLIE 0x9c4 +#define ANDES_CSR_SLIP 0x9c5 +#define ANDES_CSR_SCOUNTEROF 0x9d4 + +#endif /* __ANDES_IRQ_H */ From patchwork Mon Dec 25 10:32:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu Chien Peter Lin X-Patchwork-Id: 758268 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 33FF353E17; Mon, 25 Dec 2023 10:49:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from Atcsqr.andestech.com (localhost [127.0.0.2] (may be forged)) by Atcsqr.andestech.com with ESMTP id 3BPAZhJ6094822; Mon, 25 Dec 2023 18:35:43 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BPAXcE2093172; Mon, 25 Dec 2023 18:33:38 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Mon, 25 Dec 2023 18:33:34 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v6 05/16] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Date: Mon, 25 Dec 2023 18:32:57 +0800 Message-ID: <20231225103308.1557548-6-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231225103308.1557548-1-peterlin@andestech.com> References: <20231225103308.1557548-1-peterlin@andestech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 3BPAZhJ6094822 The Andes hart-level interrupt controller (Andes INTC) allows AX45MP cores to handle custom local interrupts, such as the performance counter overflow interrupt. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Geert Uytterhoeven Reviewed-by: Lad Prabhakar Tested-by: Lad Prabhakar --- Changes v1 -> v2: - New patch Changes v2 -> v3: - Fixed possible compatibles for Andes INTC Changes v3 -> v4: - No change Changes v4 -> v5: - Include Geert's Reviewed-by - Include Prabhakar's Reviewed/Tested-by Changes v5 -> v6: - No change --- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi index eb301d8eb2b0..78072e80793d 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -38,7 +38,7 @@ cpu0: cpu@0 { cpu0_intc: interrupt-controller { #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; + compatible = "andestech,cpu-intc", "riscv,cpu-intc"; interrupt-controller; }; }; From patchwork Mon Dec 25 10:32:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu Chien Peter Lin X-Patchwork-Id: 758271 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C6FE524B1; Mon, 25 Dec 2023 10:48:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from Atcsqr.andestech.com (localhost [127.0.0.2] (may be forged)) by Atcsqr.andestech.com with ESMTP id 3BPAZfLO094816; Mon, 25 Dec 2023 18:35:41 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BPAXhhR093193; Mon, 25 Dec 2023 18:33:43 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Mon, 25 Dec 2023 18:33:39 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v6 06/16] perf: RISC-V: Eliminate redundant interrupt enable/disable operations Date: Mon, 25 Dec 2023 18:32:58 +0800 Message-ID: <20231225103308.1557548-7-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231225103308.1557548-1-peterlin@andestech.com> References: <20231225103308.1557548-1-peterlin@andestech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 3BPAZfLO094816 The interrupt enable/disable operations are already performed by the IRQ chip functions riscv_intc_irq_unmask()/riscv_intc_irq_mask() during enable_percpu_irq()/disable_percpu_irq(). It can be done only once. Signed-off-by: Yu Chien Peter Lin --- This patch allows us to drop unnecessary ALT_SBI_PMU_OVF_{DISABLE,ENABLE} in the initial PATCH3 [1]. [1] https://patchwork.kernel.org/project/linux-riscv/patch/20230907021635.1002738-4-peterlin@andestech.com/ Changes v1 -> v2: - New patch Changes v2 -> v3: - No change Changes v3 -> v4: - No change Changes v4 -> v5: - No change Changes v5 -> v6: - No change --- drivers/perf/riscv_pmu_sbi.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 16acd4dcdb96..2edbc37abadf 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -781,7 +781,6 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node) if (riscv_pmu_use_irq) { cpu_hw_evt->irq = riscv_pmu_irq; csr_clear(CSR_IP, BIT(riscv_pmu_irq_num)); - csr_set(CSR_IE, BIT(riscv_pmu_irq_num)); enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE); } @@ -792,7 +791,6 @@ static int pmu_sbi_dying_cpu(unsigned int cpu, struct hlist_node *node) { if (riscv_pmu_use_irq) { disable_percpu_irq(riscv_pmu_irq); - csr_clear(CSR_IE, BIT(riscv_pmu_irq_num)); } /* Disable all counters access for user mode now */ From patchwork Mon Dec 25 10:33:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu Chien Peter Lin X-Patchwork-Id: 758269 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85E6550277; Mon, 25 Dec 2023 10:49:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from Atcsqr.andestech.com (localhost [127.0.0.2] (may be forged)) by Atcsqr.andestech.com with ESMTP id 3BPAZhdw094820; Mon, 25 Dec 2023 18:35:43 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BPAXwfW093257; Mon, 25 Dec 2023 18:33:58 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Mon, 25 Dec 2023 18:33:55 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v6 09/16] dt-bindings: riscv: Add T-Head PMU extension description Date: Mon, 25 Dec 2023 18:33:01 +0800 Message-ID: <20231225103308.1557548-10-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231225103308.1557548-1-peterlin@andestech.com> References: <20231225103308.1557548-1-peterlin@andestech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 3BPAZhdw094820 Document the ISA string for T-Head performance monitor extension which provides counter overflow interrupt mechanism. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Guo Ren Reviewed-by: Inochi Amaoto Acked-by: Conor Dooley --- Changes v2 -> v3: - New patch Changes v3 -> v4: - No change Changes v4 -> v5: - Include Guo's Reviewed-by - Include Inochi's Reviewed-by - Update to C910 documentation with its commit hash Changes v5 -> v6: - Include Conor's Acked-by --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index c91ab0e46648..b5cb8ac7ac80 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -258,5 +258,11 @@ properties: in commit 2e5236 ("Ztso is now ratified.") of the riscv-isa-manual. + - const: xtheadpmu + description: + The T-Head performance monitor extension for counter overflow, as ratified + in commit 4c4981 ("Initial commit") of Xuantie C910 user manual. + https://github.com/T-head-Semi/openc910/tree/main/doc + additionalProperties: true ... From patchwork Mon Dec 25 10:33:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu Chien Peter Lin X-Patchwork-Id: 758272 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C09951C29; Mon, 25 Dec 2023 10:48:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from Atcsqr.andestech.com (localhost [127.0.0.2] (may be forged)) by Atcsqr.andestech.com with ESMTP id 3BPAZeao094771; Mon, 25 Dec 2023 18:35:40 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BPAY3Y6093300; Mon, 25 Dec 2023 18:34:03 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Mon, 25 Dec 2023 18:34:00 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v6 10/16] dt-bindings: riscv: Add Andes PMU extension description Date: Mon, 25 Dec 2023 18:33:02 +0800 Message-ID: <20231225103308.1557548-11-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231225103308.1557548-1-peterlin@andestech.com> References: <20231225103308.1557548-1-peterlin@andestech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 3BPAZeao094771 Document the ISA string for Andes Technology performance monitor extension which provides counter overflow interrupt and mode filtering mechanisms. Signed-off-by: Yu Chien Peter Lin Acked-by: Conor Dooley Reviewed-by: Lad Prabhakar --- Changes v2 -> v3: - New patch Changes v3 -> v4: - Include Conor's Acked-by Changes v4 -> v5: - Include Prabhakar's Reviewed-by Changes v5 -> v6: - No change --- Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index b5cb8ac7ac80..daef6c3b1580 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -258,6 +258,13 @@ properties: in commit 2e5236 ("Ztso is now ratified.") of the riscv-isa-manual. + - const: xandespmu + description: + The Andes Technology performance monitor extension for counter overflow + and privilege mode filtering. For more details, see Counter Related + Registers in the AX45MP datasheet. + https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf + - const: xtheadpmu description: The T-Head performance monitor extension for counter overflow, as ratified From patchwork Mon Dec 25 10:33:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu Chien Peter Lin X-Patchwork-Id: 758270 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A0CE52F81; Mon, 25 Dec 2023 10:49:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from Atcsqr.andestech.com (localhost [127.0.0.2] (may be forged)) by Atcsqr.andestech.com with ESMTP id 3BPAZfDQ094779; Mon, 25 Dec 2023 18:35:41 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BPAY8cF093321; Mon, 25 Dec 2023 18:34:08 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Mon, 25 Dec 2023 18:34:05 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v6 11/16] riscv: dts: allwinner: Add T-Head PMU extension for sun20i-d1s Date: Mon, 25 Dec 2023 18:33:03 +0800 Message-ID: <20231225103308.1557548-12-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231225103308.1557548-1-peterlin@andestech.com> References: <20231225103308.1557548-1-peterlin@andestech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 3BPAZfDQ094779 xtheadpmu stands for T-Head Performance Monitor Unit extension. Based on the added T-Head PMU ISA string, the SBI PMU driver will make use of the non-standard irq source. Signed-off-by: Yu Chien Peter Lin Reviewed-by: Guo Ren --- Changes v2 -> v3: - New patch Changes v3 -> v4: - No change Changes v4 -> v5: - Include Guo's Reviewed-by Changes v5 -> v6: - No change --- arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi index 64c3c2e6cbe0..7dcba86cfdd0 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi @@ -27,7 +27,7 @@ cpu0: cpu@0 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + "zifencei", "zihpm", "xtheadpmu"; #cooling-cells = <2>; cpu0_intc: interrupt-controller { From patchwork Mon Dec 25 10:33:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu Chien Peter Lin X-Patchwork-Id: 758273 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E109E3D74; Mon, 25 Dec 2023 10:48:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from Atcsqr.andestech.com (localhost [127.0.0.2] (may be forged)) by Atcsqr.andestech.com with ESMTP id 3BPAZeYv094770; Mon, 25 Dec 2023 18:35:40 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BPAYDlm093342; Mon, 25 Dec 2023 18:34:13 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Mon, 25 Dec 2023 18:34:10 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v6 12/16] riscv: dts: sophgo: Add T-Head PMU extension for cv1800b Date: Mon, 25 Dec 2023 18:33:04 +0800 Message-ID: <20231225103308.1557548-13-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231225103308.1557548-1-peterlin@andestech.com> References: <20231225103308.1557548-1-peterlin@andestech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 3BPAZeYv094770 xtheadpmu stands for T-Head Performance Monitor Unit extension. Based on the added T-Head PMU ISA string, the SBI PMU driver will make use of the non-standard irq source. Signed-off-by: Yu Chien Peter Lin Acked-by: Conor Dooley --- Changes v4 -> v5: - New patch Changes v5 -> v6: - Include Conor's Acked-by --- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi index aec6401a467b..8c0143f0a01b 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -29,7 +29,7 @@ cpu0: cpu@0 { riscv,isa = "rv64imafdc"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; + "zifencei", "zihpm", "xtheadpmu"; cpu0_intc: interrupt-controller { compatible = "riscv,cpu-intc"; From patchwork Mon Dec 25 10:33:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu Chien Peter Lin X-Patchwork-Id: 758266 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AE95454BDF; Mon, 25 Dec 2023 10:49:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from Atcsqr.andestech.com (localhost [127.0.0.2] (may be forged)) by Atcsqr.andestech.com with ESMTP id 3BPAZrms095170; Mon, 25 Dec 2023 18:35:53 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BPAYI3m093364; Mon, 25 Dec 2023 18:34:18 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Mon, 25 Dec 2023 18:34:15 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v6 13/16] riscv: dts: sophgo: Add T-Head PMU extension for sg2042 Date: Mon, 25 Dec 2023 18:33:05 +0800 Message-ID: <20231225103308.1557548-14-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231225103308.1557548-1-peterlin@andestech.com> References: <20231225103308.1557548-1-peterlin@andestech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 3BPAZrms095170 xtheadpmu stands for T-Head Performance Monitor Unit extension. Based on the added T-Head PMU ISA string, the SBI PMU driver will make use of the non-standard irq source. Signed-off-by: Yu Chien Peter Lin Acked-by: Conor Dooley --- Changes v4 -> v5: - New patch Changes v5 -> v6: - Include Conor's Acked-by --- arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 128 ++++++++++---------- 1 file changed, 64 insertions(+), 64 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi index b136b6c4128c..1d0b236f2e7a 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi @@ -260,7 +260,7 @@ cpu0: cpu@0 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <0>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -285,7 +285,7 @@ cpu1: cpu@1 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <1>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -310,7 +310,7 @@ cpu2: cpu@2 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <2>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -335,7 +335,7 @@ cpu3: cpu@3 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <3>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -360,7 +360,7 @@ cpu4: cpu@4 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <4>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -385,7 +385,7 @@ cpu5: cpu@5 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <5>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -410,7 +410,7 @@ cpu6: cpu@6 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <6>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -435,7 +435,7 @@ cpu7: cpu@7 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <7>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -460,7 +460,7 @@ cpu8: cpu@8 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <8>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -485,7 +485,7 @@ cpu9: cpu@9 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <9>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -510,7 +510,7 @@ cpu10: cpu@10 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <10>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -535,7 +535,7 @@ cpu11: cpu@11 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <11>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -560,7 +560,7 @@ cpu12: cpu@12 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <12>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -585,7 +585,7 @@ cpu13: cpu@13 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <13>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -610,7 +610,7 @@ cpu14: cpu@14 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <14>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -635,7 +635,7 @@ cpu15: cpu@15 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <15>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -660,7 +660,7 @@ cpu16: cpu@16 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <16>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -685,7 +685,7 @@ cpu17: cpu@17 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <17>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -710,7 +710,7 @@ cpu18: cpu@18 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <18>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -735,7 +735,7 @@ cpu19: cpu@19 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <19>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -760,7 +760,7 @@ cpu20: cpu@20 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <20>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -785,7 +785,7 @@ cpu21: cpu@21 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <21>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -810,7 +810,7 @@ cpu22: cpu@22 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <22>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -835,7 +835,7 @@ cpu23: cpu@23 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <23>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -860,7 +860,7 @@ cpu24: cpu@24 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <24>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -885,7 +885,7 @@ cpu25: cpu@25 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <25>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -910,7 +910,7 @@ cpu26: cpu@26 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <26>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -935,7 +935,7 @@ cpu27: cpu@27 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <27>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -960,7 +960,7 @@ cpu28: cpu@28 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <28>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -985,7 +985,7 @@ cpu29: cpu@29 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <29>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1010,7 +1010,7 @@ cpu30: cpu@30 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <30>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1035,7 +1035,7 @@ cpu31: cpu@31 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <31>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1060,7 +1060,7 @@ cpu32: cpu@32 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <32>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1085,7 +1085,7 @@ cpu33: cpu@33 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <33>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1110,7 +1110,7 @@ cpu34: cpu@34 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <34>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1135,7 +1135,7 @@ cpu35: cpu@35 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <35>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1160,7 +1160,7 @@ cpu36: cpu@36 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <36>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1185,7 +1185,7 @@ cpu37: cpu@37 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <37>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1210,7 +1210,7 @@ cpu38: cpu@38 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <38>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1235,7 +1235,7 @@ cpu39: cpu@39 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <39>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1260,7 +1260,7 @@ cpu40: cpu@40 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <40>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1285,7 +1285,7 @@ cpu41: cpu@41 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <41>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1310,7 +1310,7 @@ cpu42: cpu@42 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <42>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1335,7 +1335,7 @@ cpu43: cpu@43 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <43>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1360,7 +1360,7 @@ cpu44: cpu@44 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <44>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1385,7 +1385,7 @@ cpu45: cpu@45 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <45>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1410,7 +1410,7 @@ cpu46: cpu@46 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <46>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1435,7 +1435,7 @@ cpu47: cpu@47 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <47>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1460,7 +1460,7 @@ cpu48: cpu@48 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <48>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1485,7 +1485,7 @@ cpu49: cpu@49 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <49>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1510,7 +1510,7 @@ cpu50: cpu@50 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <50>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1535,7 +1535,7 @@ cpu51: cpu@51 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <51>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1560,7 +1560,7 @@ cpu52: cpu@52 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <52>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1585,7 +1585,7 @@ cpu53: cpu@53 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <53>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1610,7 +1610,7 @@ cpu54: cpu@54 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <54>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1635,7 +1635,7 @@ cpu55: cpu@55 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <55>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1660,7 +1660,7 @@ cpu56: cpu@56 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <56>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1685,7 +1685,7 @@ cpu57: cpu@57 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <57>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1710,7 +1710,7 @@ cpu58: cpu@58 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <58>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1735,7 +1735,7 @@ cpu59: cpu@59 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <59>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1760,7 +1760,7 @@ cpu60: cpu@60 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <60>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1785,7 +1785,7 @@ cpu61: cpu@61 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <61>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1810,7 +1810,7 @@ cpu62: cpu@62 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <62>; i-cache-block-size = <64>; i-cache-size = <65536>; @@ -1835,7 +1835,7 @@ cpu63: cpu@63 { riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", "zifencei", - "zihpm"; + "zihpm", "xtheadpmu"; reg = <63>; i-cache-block-size = <64>; i-cache-size = <65536>; From patchwork Mon Dec 25 10:33:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yu Chien Peter Lin X-Patchwork-Id: 758265 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CC5E54F88; Mon, 25 Dec 2023 10:49:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from Atcsqr.andestech.com (localhost [127.0.0.2] (may be forged)) by Atcsqr.andestech.com with ESMTP id 3BPAa37f095473; Mon, 25 Dec 2023 18:36:03 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from mail.andestech.com (ATCPCS16.andestech.com [10.0.1.222]) by Atcsqr.andestech.com with ESMTP id 3BPAYXgL093428; Mon, 25 Dec 2023 18:34:33 +0800 (+08) (envelope-from peterlin@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.498.0; Mon, 25 Dec 2023 18:34:30 +0800 From: Yu Chien Peter Lin To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v6 16/16] riscv: andes: Support specifying symbolic firmware and hardware raw events Date: Mon, 25 Dec 2023 18:33:08 +0800 Message-ID: <20231225103308.1557548-17-peterlin@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231225103308.1557548-1-peterlin@andestech.com> References: <20231225103308.1557548-1-peterlin@andestech.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 3BPAa37f095473 From: Locus Wei-Han Chen Add the Andes AX45 JSON files that allows specifying symbolic event names for the raw PMU events. Signed-off-by: Locus Wei-Han Chen Reviewed-by: Yu Chien Peter Lin Reviewed-by: Charles Ci-Jyun Wu Reviewed-by: Leo Yu-Chi Liang Tested-by: Lad Prabhakar --- Changes v1 -> v2: - No change Changes v2 -> v3: - No change Changes v3 -> v4: - No change Changes v4 -> v5: - Include Prabhakar's Tested-by Changes v5 -> v6: - No change --- .../arch/riscv/andes/ax45/firmware.json | 68 ++++++++++ .../arch/riscv/andes/ax45/instructions.json | 127 ++++++++++++++++++ .../arch/riscv/andes/ax45/memory.json | 57 ++++++++ .../arch/riscv/andes/ax45/microarch.json | 77 +++++++++++ tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 + 5 files changed, 330 insertions(+) create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json b/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json new file mode 100644 index 000000000000..9b4a032186a7 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/firmware.json @@ -0,0 +1,68 @@ +[ + { + "ArchStdEvent": "FW_MISALIGNED_LOAD" + }, + { + "ArchStdEvent": "FW_MISALIGNED_STORE" + }, + { + "ArchStdEvent": "FW_ACCESS_LOAD" + }, + { + "ArchStdEvent": "FW_ACCESS_STORE" + }, + { + "ArchStdEvent": "FW_ILLEGAL_INSN" + }, + { + "ArchStdEvent": "FW_SET_TIMER" + }, + { + "ArchStdEvent": "FW_IPI_SENT" + }, + { + "ArchStdEvent": "FW_IPI_RECEIVED" + }, + { + "ArchStdEvent": "FW_FENCE_I_SENT" + }, + { + "ArchStdEvent": "FW_FENCE_I_RECEIVED" + }, + { + "ArchStdEvent": "FW_SFENCE_VMA_SENT" + }, + { + "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" + }, + { + "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED" + }, + { + "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED" + }, + { + "ArchStdEvent": "FW_HFENCE_GVMA_SENT" + }, + { + "ArchStdEvent": "FW_HFENCE_GVMA_RECEIVED" + }, + { + "ArchStdEvent": "FW_HFENCE_GVMA_VMID_SENT" + }, + { + "ArchStdEvent": "FW_HFENCE_GVMA_VMID_RECEIVED" + }, + { + "ArchStdEvent": "FW_HFENCE_VVMA_SENT" + }, + { + "ArchStdEvent": "FW_HFENCE_VVMA_RECEIVED" + }, + { + "ArchStdEvent": "FW_HFENCE_VVMA_ASID_SENT" + }, + { + "ArchStdEvent": "FW_HFENCE_VVMA_ASID_RECEIVED" + } +] diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json b/tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json new file mode 100644 index 000000000000..713a08c1a40f --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json @@ -0,0 +1,127 @@ +[ + { + "EventCode": "0x10", + "EventName": "cycle_count", + "BriefDescription": "Cycle count" + }, + { + "EventCode": "0x20", + "EventName": "inst_count", + "BriefDescription": "Retired instruction count" + }, + { + "EventCode": "0x30", + "EventName": "int_load_inst", + "BriefDescription": "Integer load instruction count" + }, + { + "EventCode": "0x40", + "EventName": "int_store_inst", + "BriefDescription": "Integer store instruction count" + }, + { + "EventCode": "0x50", + "EventName": "atomic_inst", + "BriefDescription": "Atomic instruction count" + }, + { + "EventCode": "0x60", + "EventName": "sys_inst", + "BriefDescription": "System instruction count" + }, + { + "EventCode": "0x70", + "EventName": "int_compute_inst", + "BriefDescription": "Integer computational instruction count" + }, + { + "EventCode": "0x80", + "EventName": "condition_br", + "BriefDescription": "Conditional branch instruction count" + }, + { + "EventCode": "0x90", + "EventName": "taken_condition_br", + "BriefDescription": "Taken conditional branch instruction count" + }, + { + "EventCode": "0xA0", + "EventName": "jal_inst", + "BriefDescription": "JAL instruction count" + }, + { + "EventCode": "0xB0", + "EventName": "jalr_inst", + "BriefDescription": "JALR instruction count" + }, + { + "EventCode": "0xC0", + "EventName": "ret_inst", + "BriefDescription": "Return instruction count" + }, + { + "EventCode": "0xD0", + "EventName": "control_trans_inst", + "BriefDescription": "Control transfer instruction count" + }, + { + "EventCode": "0xE0", + "EventName": "ex9_inst", + "BriefDescription": "EXEC.IT instruction count" + }, + { + "EventCode": "0xF0", + "EventName": "int_mul_inst", + "BriefDescription": "Integer multiplication instruction count" + }, + { + "EventCode": "0x100", + "EventName": "int_div_rem_inst", + "BriefDescription": "Integer division/remainder instruction count" + }, + { + "EventCode": "0x110", + "EventName": "float_load_inst", + "BriefDescription": "Floating-point load instruction count" + }, + { + "EventCode": "0x120", + "EventName": "float_store_inst", + "BriefDescription": "Floating-point store instruction count" + }, + { + "EventCode": "0x130", + "EventName": "float_add_sub_inst", + "BriefDescription": "Floating-point addition/subtraction instruction count" + }, + { + "EventCode": "0x140", + "EventName": "float_mul_inst", + "BriefDescription": "Floating-point multiplication instruction count" + }, + { + "EventCode": "0x150", + "EventName": "float_fused_muladd_inst", + "BriefDescription": "Floating-point fused multiply-add instruction count" + }, + { + "EventCode": "0x160", + "EventName": "float_div_sqrt_inst", + "BriefDescription": "Floating-point division or square-root instruction count" + }, + { + "EventCode": "0x170", + "EventName": "other_float_inst", + "BriefDescription": "Other floating-point instruction count" + }, + { + "EventCode": "0x180", + "EventName": "int_mul_add_sub_inst", + "BriefDescription": "Integer multiplication and add/sub instruction count" + }, + { + "EventCode": "0x190", + "EventName": "retired_ops", + "BriefDescription": "Retired operation count" + } +] diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json b/tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json new file mode 100644 index 000000000000..c7401b526c77 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json @@ -0,0 +1,57 @@ +[ + { + "EventCode": "0x01", + "EventName": "ilm_access", + "BriefDescription": "ILM access" + }, + { + "EventCode": "0x11", + "EventName": "dlm_access", + "BriefDescription": "DLM access" + }, + { + "EventCode": "0x21", + "EventName": "icache_access", + "BriefDescription": "ICACHE access" + }, + { + "EventCode": "0x31", + "EventName": "icache_miss", + "BriefDescription": "ICACHE miss" + }, + { + "EventCode": "0x41", + "EventName": "dcache_access", + "BriefDescription": "DCACHE access" + }, + { + "EventCode": "0x51", + "EventName": "dcache_miss", + "BriefDescription": "DCACHE miss" + }, + { + "EventCode": "0x61", + "EventName": "dcache_load_access", + "BriefDescription": "DCACHE load access" + }, + { + "EventCode": "0x71", + "EventName": "dcache_load_miss", + "BriefDescription": "DCACHE load miss" + }, + { + "EventCode": "0x81", + "EventName": "dcache_store_access", + "BriefDescription": "DCACHE store access" + }, + { + "EventCode": "0x91", + "EventName": "dcache_store_miss", + "BriefDescription": "DCACHE store miss" + }, + { + "EventCode": "0xA1", + "EventName": "dcache_wb", + "BriefDescription": "DCACHE writeback" + } +] diff --git a/tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json b/tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json new file mode 100644 index 000000000000..a6d378cbaa74 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json @@ -0,0 +1,77 @@ +[ + { + "EventCode": "0xB1", + "EventName": "cycle_wait_icache_fill", + "BriefDescription": "Cycles waiting for ICACHE fill data" + }, + { + "EventCode": "0xC1", + "EventName": "cycle_wait_dcache_fill", + "BriefDescription": "Cycles waiting for DCACHE fill data" + }, + { + "EventCode": "0xD1", + "EventName": "uncached_ifetch_from_bus", + "BriefDescription": "Uncached ifetch data access from bus" + }, + { + "EventCode": "0xE1", + "EventName": "uncached_load_from_bus", + "BriefDescription": "Uncached load data access from bus" + }, + { + "EventCode": "0xF1", + "EventName": "cycle_wait_uncached_ifetch", + "BriefDescription": "Cycles waiting for uncached ifetch data from bus" + }, + { + "EventCode": "0x101", + "EventName": "cycle_wait_uncached_load", + "BriefDescription": "Cycles waiting for uncached load data from bus" + }, + { + "EventCode": "0x111", + "EventName": "main_itlb_access", + "BriefDescription": "Main ITLB access" + }, + { + "EventCode": "0x121", + "EventName": "main_itlb_miss", + "BriefDescription": "Main ITLB miss" + }, + { + "EventCode": "0x131", + "EventName": "main_dtlb_access", + "BriefDescription": "Main DTLB access" + }, + { + "EventCode": "0x141", + "EventName": "main_dtlb_miss", + "BriefDescription": "Main DTLB miss" + }, + { + "EventCode": "0x151", + "EventName": "cycle_wait_itlb_fill", + "BriefDescription": "Cycles waiting for Main ITLB fill data" + }, + { + "EventCode": "0x161", + "EventName": "pipe_stall_cycle_dtlb_miss", + "BriefDescription": "Pipeline stall cycles caused by Main DTLB miss" + }, + { + "EventCode": "0x02", + "EventName": "mispredict_condition_br", + "BriefDescription": "Misprediction of conditional branches" + }, + { + "EventCode": "0x12", + "EventName": "mispredict_take_condition_br", + "BriefDescription": "Misprediction of taken conditional branches" + }, + { + "EventCode": "0x22", + "EventName": "mispredict_target_ret_inst", + "BriefDescription": "Misprediction of targets of Return instructions" + } +] diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv index c61b3d6ef616..5bf09af14c1b 100644 --- a/tools/perf/pmu-events/arch/riscv/mapfile.csv +++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv @@ -15,3 +15,4 @@ # #MVENDORID-MARCHID-MIMPID,Version,Filename,EventType 0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core +0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core