From patchwork Wed Sep 4 10:08:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 172915 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp1023011ily; Wed, 4 Sep 2019 03:10:24 -0700 (PDT) X-Google-Smtp-Source: APXvYqxaMNTAq32ffDQ41oBJnnod++8I3Rh0U/NpCQSn9rD79OltNHP+mf3z8oNWHNW+vtpKsFq/ X-Received: by 2002:a17:902:74c3:: with SMTP id f3mr5631655plt.325.1567591823684; Wed, 04 Sep 2019 03:10:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567591823; cv=none; d=google.com; s=arc-20160816; b=Y8BbMu9XPVz/JwgPMxa3R9zNl3y9qW7aH23LIsxjdritXtvQ5QQzjez5ofn3owLo8a x3cns2PtplxNK5yDzKU2R6DSKEkqdFJI2cg7ekIyRyMcJTi7AAgBdnCEdfMN40rZr0LR XE5joodA5Lric/qiwktcxYERzicWdIJE6M4WaZSr5zPurItNzuVPLK+uwxWoBVfixgup eTFqvmR9b0KUx7GdnyUIDa2a1FT191SawMqlg4E6xJIuEUjcjVdTJ+nhLTR6X9XZmlM1 vkCNcw5qbB4OniBmHOe6TwXLxwSlB1QTfuseAXfxGnh+5Q8vr8wWtWU4fXS0QGPYxWpm YHww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=kf4SVDpOL9bxQn5hKtUjyOSOI6vzV6LxKt1E4w6YqR0=; b=HNPoRvUWIQ8IDHhUuDQfY5PejgSChlm+pbe2z42+Enx2N7BjYZhvD0dao+MFkVguAU uP/sdgEiIOzTao96S9237m9ElYbAfWg6mh/OYF9YwPCl3IB7f12aAqZ5XJn5rCrekGrt CxXftMq4hn35uWcF/FFUUOek5qK4Uzzl6FdJVNEEF1UPIwDuQ4+VehTmE08aacFlD/R6 8FvJ+crlqMGhva4lOPqU75imfkUp1CpujjhijoZ3ngIuS9aGEo4rm3Iz6NKrNoPpu0SC d0QNHqVPIPdENRWhOUaMycTZ8Ad4X06bmdbS85z2Qo3Eq5b2tYrwRoPha5QP54X6TnZ5 CnyQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=kDp3Ks5r; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f59si16899654plf.220.2019.09.04.03.10.22; Wed, 04 Sep 2019 03:10:23 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=kDp3Ks5r; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729384AbfIDKKW (ORCPT + 8 others); Wed, 4 Sep 2019 06:10:22 -0400 Received: from mail.kernel.org ([198.145.29.99]:40418 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726528AbfIDKKV (ORCPT ); Wed, 4 Sep 2019 06:10:21 -0400 Received: from localhost.localdomain (unknown [122.182.201.156]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id B32AC233A1; Wed, 4 Sep 2019 10:10:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1567591820; bh=kZtJo0KapTONfrxJjZzeyUaYd5qO0HV428i3J/RotIU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kDp3Ks5rtdnF3T8wXfe4iEeFogNasI3PzC7flDRM6F45YJaMSnHfcq5EJL1EE9L1W s+Tw0ZqQAKulW4GpDaLgMsmSNqD58z2OMsvZ58S/whshNbklXjodVRKDJNPYXOGZ0C cL9uq1a4vmQQf/s9h/foZU+ijKjWHkRntptGQnkM= From: Vinod Koul To: Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Andy Gross , Rob Herring , Mark Rutland , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Vinod Koul Subject: [PATCH 2/3] dt-bindings: phy-qcom-qmp: Add sm8150 UFS phy compatible string Date: Wed, 4 Sep 2019 15:38:34 +0530 Message-Id: <20190904100835.6099-3-vkoul@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190904100835.6099-1-vkoul@kernel.org> References: <20190904100835.6099-1-vkoul@kernel.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document "qcom,sdm845-qmp-ufs-phy" compatible string for QMP UFS PHY found on SM8150. Signed-off-by: Vinod Koul --- Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) -- 2.20.1 Reviewed-by: Stephen Boyd diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt index 085fbd676cfc..eac9ad3cbbc8 100644 --- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt @@ -14,7 +14,8 @@ Required properties: "qcom,msm8998-qmp-pcie-phy" for PCIe QMP phy on msm8998, "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845, "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845, - "qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845. + "qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845, + "qcom,sm8150-qmp-ufs-phy" for UFS QMP phy on sm8150. - reg: - index 0: address and length of register set for PHY's common @@ -57,6 +58,8 @@ Required properties: "aux", "cfg_ahb", "ref", "com_aux". For "qcom,sdm845-qmp-ufs-phy" must contain: "ref", "ref_aux". + For "qcom,sm8150-qmp-ufs-phy" must contain: + "ref", "ref_aux". - resets: a list of phandles and reset controller specifier pairs, one for each entry in reset-names. @@ -83,6 +86,8 @@ Required properties: "phy", "common". For "qcom,sdm845-qmp-ufs-phy": must contain: "ufsphy". + For "qcom,sm8150-qmp-ufs-phy": must contain: + "ufsphy". - vdda-phy-supply: Phandle to a regulator supply to PHY core block. - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block. From patchwork Wed Sep 4 10:08:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 172916 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp1023067ily; Wed, 4 Sep 2019 03:10:27 -0700 (PDT) X-Google-Smtp-Source: APXvYqyc6F5CThdXH7jpneILTiQRYVj5yPH4gg28Oc86eM9nCt9h91t4TXQzczF3lufS7RkDyMr/ X-Received: by 2002:a17:902:d717:: with SMTP id w23mr40515551ply.321.1567591827631; Wed, 04 Sep 2019 03:10:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567591827; cv=none; d=google.com; s=arc-20160816; b=HTDY9vN0+tnO9wfGsv3ZiEgYgY+V/x06zh4wodZ38g9Q0T8bgwTORLgt/eSDAIedev D5TCmr4MQhKaIBHC5e5SGG0HgHe7qZJjnHH4cE/xeAG4ASTxw0R8Wb+DJSlYqIw5eMaz Yqr1Qe8nX2pfttTVeMjUVCTmIxPyrOlDb8UGMBX7c92w/QC9RUG5j4WNB1OLBO53whj1 cyQDY/uHWnuuV4/EfzZ+RtPByCS7Ku7d+jCrurfuX+M2/6vkvKkJvvZwC94ka6efaqw9 QsOdqoHheByYFHvdBp3005mjVr9ucDBRajPPVwhE7NrLM7rn+xuBPWt4ITh7JHtir1cU igdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=9OH68dWUscJB3YnFOpgI6UrArMz35QsA+9fIlFoUS3c=; b=EGdy1IzzIzleQmXLqvdE+ostVs5DEWdXECCSmYNbnbTrj9+RyWhESDA23w4QRsFhCw lZjZgH48GLsqy4P/Uv2017sgcVGlS+aIuOTbGxjWIbIpJM1PQFEnlkFiOD1JNq5+etWP FNizzAvnMGCAOdz/sUj2GB1yU4EPVHO07cD1j2qMJq1V1nbdaYNU17SjZnKG6fdEVzWA 8psPMYSyNdvCKaIjmkxuhcT5Npz6CwPwSHmfWXY3a8UmfgAyH2vJ6j3JaxMw40FuZedk 5YvCqPIzbIrIJjaKaXAI5+xu1/BPBQU1wBDb7aN0U0jrcLrgNBBLyssi4R8/bGj2VCOu J+TA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=qUedy1yy; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q19si1935662pjp.99.2019.09.04.03.10.27; Wed, 04 Sep 2019 03:10:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=qUedy1yy; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729525AbfIDKK0 (ORCPT + 8 others); Wed, 4 Sep 2019 06:10:26 -0400 Received: from mail.kernel.org ([198.145.29.99]:40496 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727929AbfIDKK0 (ORCPT ); Wed, 4 Sep 2019 06:10:26 -0400 Received: from localhost.localdomain (unknown [122.182.201.156]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 88D9421881; Wed, 4 Sep 2019 10:10:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1567591825; bh=6TfIHMUIYpjr+DIYWliKQcGstOjAulhKafsCQxsQ7IE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qUedy1yy5qwkcS4BD2Tah6P1jWC83FhhDRiWMWTK7AI9YL5RhmgvKLZZuk2ktaEwn v8NkHit5rholWcF6gUFy1OgkCd+jODLAhcAJ9PWgkx2q9wQUU/A71PW55VW2o2RXF8 BO+ewny2rkR8MbPpTGFxgP4C1n8YhbzUC3ZkIReI= From: Vinod Koul To: Kishon Vijay Abraham I Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , Andy Gross , Rob Herring , Mark Rutland , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 3/3] phy: qcom-qmp: Add SM8150 QMP UFS PHY support Date: Wed, 4 Sep 2019 15:38:35 +0530 Message-Id: <20190904100835.6099-4-vkoul@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190904100835.6099-1-vkoul@kernel.org> References: <20190904100835.6099-1-vkoul@kernel.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org SM8150 UFS PHY is v4 of QMP phy. Add support for V4 QMP phy register defines and support for SM8150 QMP UFS PHY. Signed-off-by: Vinod Koul --- drivers/phy/qualcomm/phy-qcom-qmp.c | 125 ++++++++++++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.h | 96 +++++++++++++++++++++ 2 files changed, 221 insertions(+) -- 2.20.1 Reviewed-by: Bjorn Andersson diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c index 34ff6434da8f..0dd49a22d72c 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c @@ -164,6 +164,11 @@ static const unsigned int sdm845_ufsphy_regs_layout[] = { [QPHY_PCS_READY_STATUS] = 0x160, }; +static const unsigned int sm8150_ufsphy_regs_layout[] = { + [QPHY_START_CTRL] = 0x00, + [QPHY_PCS_READY_STATUS] = 0x180, +}; + static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c), QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10), @@ -878,6 +883,93 @@ static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = { QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), }; +static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_V4_SYSCLK_EN_SEL, 0xD9), + QMP_PHY_INIT_CFG(QSERDES_COM_V4_HSCLK_SEL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_COM_V4_HSCLK_HS_SWITCH_SEL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_V4_LOCK_CMP_EN, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_V4_VCO_TUNE_MAP, 0x02), + QMP_PHY_INIT_CFG(QSERDES_COM_V4_PLL_IVCO, 0x0F), + QMP_PHY_INIT_CFG(QSERDES_COM_V4_VCO_TUNE_INITVAL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_V4_BIN_VCOCAL_HSCLK_SEL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_COM_V4_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_COM_V4_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_COM_V4_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_COM_V4_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_COM_V4_LOCK_CMP1_MODE0, 0xFF), + QMP_PHY_INIT_CFG(QSERDES_COM_V4_LOCK_CMP2_MODE0, 0x0C), + QMP_PHY_INIT_CFG(QSERDES_COM_V4_BIN_VCOCAL_CMP_CODE1_MODE0, 0xAC), + QMP_PHY_INIT_CFG(QSERDES_COM_V4_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1E), + QMP_PHY_INIT_CFG(QSERDES_COM_V4_DEC_START_MODE1, 0x98), + QMP_PHY_INIT_CFG(QSERDES_COM_V4_CP_CTRL_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_COM_V4_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_COM_V4_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_COM_V4_LOCK_CMP1_MODE1, 0x32), + QMP_PHY_INIT_CFG(QSERDES_COM_V4_LOCK_CMP2_MODE1, 0x0F), + QMP_PHY_INIT_CFG(QSERDES_COM_V4_BIN_VCOCAL_CMP_CODE1_MODE1, 0xDD), + QMP_PHY_INIT_CFG(QSERDES_COM_V4_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), + + /* Rate B */ + QMP_PHY_INIT_CFG(QSERDES_COM_V4_VCO_TUNE_MAP, 0x06), +}; + +static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0C), +}; + +static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = { + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0F), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1E), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0A), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4B), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xF1), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0C), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1B), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1D), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xC0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xF6), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3B), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3D), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xE0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xC8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xC8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3B), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xB1), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xE0), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xC8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xC8), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3B), + QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xB1), + +}; + +static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = { + QMP_PHY_INIT_CFG(QPHY_V4_RX_SIGDET_CTRL2, 0x6D), + QMP_PHY_INIT_CFG(QPHY_V4_TX_LARGE_AMP_DRV_LVL, 0x0A), + QMP_PHY_INIT_CFG(QPHY_V4_TX_SMALL_AMP_DRV_LVL, 0x02), + QMP_PHY_INIT_CFG(QPHY_V4_TX_MID_TERM_CTRL1, 0x43), + QMP_PHY_INIT_CFG(QPHY_V4_DEBUG_BUS_CLKSEL, 0x1F), + QMP_PHY_INIT_CFG(QPHY_V4_RX_MIN_HIBERN8_TIME, 0xFF), + QMP_PHY_INIT_CFG(QPHY_V4_MULTI_LANE_CTRL1, 0x02), +}; /* struct qmp_phy_cfg - per-PHY initialization config */ struct qmp_phy_cfg { @@ -1038,6 +1130,10 @@ static const char * const sdm845_ufs_phy_clk_l[] = { "ref", "ref_aux", }; +static const char * const sm8150_ufs_phy_clk_l[] = { + "ref", "ref_aux", +}; + /* list of resets */ static const char * const msm8996_pciephy_reset_l[] = { "phy", "common", "cfg", @@ -1284,6 +1380,32 @@ static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { .is_dual_lane_phy = true, }; +static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { + .type = PHY_TYPE_UFS, + .nlanes = 2, + + .serdes_tbl = sm8150_ufsphy_serdes_tbl, + .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl), + .tx_tbl = sm8150_ufsphy_tx_tbl, + .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl), + .rx_tbl = sm8150_ufsphy_rx_tbl, + .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl), + .pcs_tbl = sm8150_ufsphy_pcs_tbl, + .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl), + .clk_list = sm8150_ufs_phy_clk_l, + .num_clks = ARRAY_SIZE(sm8150_ufs_phy_clk_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .regs = sm8150_ufsphy_regs_layout, + + .start_ctrl = SERDES_START, + .pwrdn_ctrl = SW_PWRDN, + .mask_pcs_ready = PCS_READY, + + .is_dual_lane_phy = true, + .no_pcs_sw_reset = true, +}; + static void qcom_qmp_phy_configure(void __iomem *base, const unsigned int *regs, const struct qmp_phy_init_tbl tbl[], @@ -1999,6 +2121,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { }, { .compatible = "qcom,msm8998-qmp-usb3-phy", .data = &msm8998_usb3phy_cfg, + }, { + .compatible = "qcom,sm8150-qmp-ufs-phy", + .data = &sm8150_ufsphy_cfg, }, { }, }; diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index 335ea5d7ef40..0eefd8621669 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -313,4 +313,100 @@ #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60 +/* Only for QMP V4 PHY - QSERDES COM registers */ +#define QSERDES_COM_V4_SYSCLK_EN_SEL 0x094 +#define QSERDES_COM_V4_HSCLK_SEL 0x158 +#define QSERDES_COM_V4_HSCLK_HS_SWITCH_SEL 0x15C +#define QSERDES_COM_V4_LOCK_CMP_EN 0x0A4 +#define QSERDES_COM_V4_VCO_TUNE_MAP 0x10C +#define QSERDES_COM_V4_PLL_IVCO 0x058 +#define QSERDES_COM_V4_VCO_TUNE_INITVAL2 0x124 +#define QSERDES_COM_V4_BIN_VCOCAL_HSCLK_SEL 0x1BC +#define QSERDES_COM_V4_DEC_START_MODE0 0x0BC +#define QSERDES_COM_V4_CP_CTRL_MODE0 0x074 +#define QSERDES_COM_V4_PLL_RCTRL_MODE0 0x07C +#define QSERDES_COM_V4_PLL_CCTRL_MODE0 0x084 +#define QSERDES_COM_V4_LOCK_CMP1_MODE0 0x0AC +#define QSERDES_COM_V4_LOCK_CMP2_MODE0 0x0B0 +#define QSERDES_COM_V4_BIN_VCOCAL_CMP_CODE1_MODE0 0x1AC +#define QSERDES_COM_V4_BIN_VCOCAL_CMP_CODE2_MODE0 0x1B0 +#define QSERDES_COM_V4_DEC_START_MODE1 0x0C4 +#define QSERDES_COM_V4_CP_CTRL_MODE1 0x078 +#define QSERDES_COM_V4_PLL_RCTRL_MODE1 0x080 +#define QSERDES_COM_V4_PLL_CCTRL_MODE1 0x088 +#define QSERDES_COM_V4_LOCK_CMP1_MODE1 0x0B4 +#define QSERDES_COM_V4_LOCK_CMP2_MODE1 0x0B8 +#define QSERDES_COM_V4_BIN_VCOCAL_CMP_CODE1_MODE1 0x1B4 +#define QSERDES_COM_V4_BIN_VCOCAL_CMP_CODE2_MODE1 0x1B8 +#define QSERDES_COM_V4_CMN_IPTRIM 0x060 + +/* Only for QMP V4 PHY - TX registers */ +#define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xD8 +#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xDC +#define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0xE0 +#define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0xE4 +#define QSERDES_V4_TX_LANE_MODE_1 0x84 +#define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xB8 + +/* Only for QMP V4 PHY - RX registers */ +#define QSERDES_V4_RX_SIGDET_LVL 0x120 +#define QSERDES_V4_RX_SIGDET_CNTRL 0x11C +#define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124 +#define QSERDES_V4_RX_RX_BAND 0x128 +#define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030 +#define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 +#define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044 +#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03C +#define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048 +#define QSERDES_V4_RX_RX_TERM_BW 0x080 +#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0EC +#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0F0 +#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0F4 +#define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 +#define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100 +#define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0F8 +#define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0FC +#define QSERDES_V4_RX_RX_MODE_00_LOW 0x170 +#define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174 +#define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178 +#define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17C +#define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180 +#define QSERDES_V4_RX_RX_MODE_01_LOW 0x184 +#define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188 +#define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18C +#define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190 +#define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194 +#define QSERDES_V4_RX_RX_MODE_10_LOW 0x198 +#define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19C +#define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1A0 +#define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1A4 +#define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1A8 +#define QSERDES_V4_RX_DCC_CTRL1 0x1BC +#define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068 +#define QSERDES_V4_RX_UCDR_FO_GAIN 0x008 +#define QSERDES_V4_RX_UCDR_SO_GAIN 0x014 +#define QSERDES_V4_RX_AC_JTAG_MODE 0x078 + +/* Only for QMP V4 PHY - PCS registers */ +#define QPHY_V4_PHY_START 0x000 +#define QPHY_V4_POWER_DOWN_CONTROL 0x004 +#define QPHY_V4_SW_RESET 0x008 +#define QPHY_V4_PCS_READY_STATUS 0x180 +#define QPHY_V4_LINECFG_DISABLE 0x148 +#define QPHY_V4_MULTI_LANE_CTRL1 0x1E0 +#define QPHY_V4_RX_SIGDET_CTRL2 0x158 +#define QPHY_V4_TX_LARGE_AMP_DRV_LVL 0x030 +#define QPHY_V4_TX_SMALL_AMP_DRV_LVL 0x038 +#define QPHY_V4_TX_MID_TERM_CTRL1 0x1D8 +#define QPHY_V4_DEBUG_BUS_CLKSEL 0x124 +#define QPHY_V4_PLL_CNTL 0x02C +#define QPHY_V4_TIMER_20US_CORECLK_STEPS_MSB 0x00C +#define QPHY_V4_TIMER_20US_CORECLK_STEPS_LSB 0x010 +#define QPHY_V4_TX_PWM_GEAR_BAND 0x160 +#define QPHY_V4_TX_HS_GEAR_BAND 0x168 +#define QPHY_V4_TX_HSGEAR_CAPABILITY 0x074 +#define QPHY_V4_RX_HSGEAR_CAPABILITY 0x0B4 +#define QPHY_V4_RX_MIN_HIBERN8_TIME 0x150 +#define QPHY_V4_BIST_FIXED_PAT_CTRL 0x060 + #endif