From patchwork Fri Dec 22 05:44:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Swee, Leong Ching" X-Patchwork-Id: 757590 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F3C939444; Fri, 22 Dec 2023 05:45:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="UNrdF7cC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703223956; x=1734759956; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Wc3WOZrrvj/mfsHMCsBQFT+YmKFZV9lPnzebZ6PYOJs=; b=UNrdF7cCXjYda8grtfUrDYXcE+jeUHPAAq6HoKyubD9WXoPkHpgAbjF1 xssNockvRuM3ZkOwqHalBjjqeonX73zfPWDZhqjGMmFs4rFq0n6A/6cJv Vt8r9TwIQydUGzm0d4jcnoEP7sJb2qwHVjec17ennywNEI1Y1qzJkItGv HMd2kHroTD32TuszvDDBq3VDSb5SduAKanc3ePz547sqrAUrtqTABgqdh YcFQibwdu+t9G2KPCvRnkVcCtnfZ2xUN54Ii1S6OW1B5ub6D4Scnyru/H 7frwEpumHUaUdmAOmcRjoCopl8FlgbYRSVDm3cFZN0OKSh1XATyEkm5XV w==; X-IronPort-AV: E=McAfee;i="6600,9927,10931"; a="9470527" X-IronPort-AV: E=Sophos;i="6.04,294,1695711600"; d="scan'208";a="9470527" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2023 21:45:55 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10931"; a="900324186" X-IronPort-AV: E=Sophos;i="6.04,294,1695711600"; d="scan'208";a="900324186" Received: from pg-esw-build.png.intel.com ([10.226.214.57]) by orsmga004.jf.intel.com with ESMTP; 21 Dec 2023 21:45:50 -0800 From: Leong Ching Swee To: Maxime Coquelin , Alexandre Torgue , Jose Abreu , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Giuseppe Cavallaro Cc: linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, Swee Leong Ching , Rohan G Thomas Subject: [PATCH net-next v1 1/4] dt-bindings: net: snps, dwmac: per channel irq Date: Fri, 22 Dec 2023 13:44:48 +0800 Message-Id: <20231222054451.2683242-2-leong.ching.swee@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231222054451.2683242-1-leong.ching.swee@intel.com> References: <20231222054451.2683242-1-leong.ching.swee@intel.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Swee Leong Ching Add dt-bindings for per channel irq. Signed-off-by: Rohan G Thomas Signed-off-by: Swee Leong Ching --- .../devicetree/bindings/net/snps,dwmac.yaml | 24 +++++++++++++------ 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index 5c2769dc689a..e72dded824f4 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -103,17 +103,27 @@ properties: interrupts: minItems: 1 - items: - - description: Combined signal for various interrupt events - - description: The interrupt to manage the remote wake-up packet detection - - description: The interrupt that occurs when Rx exits the LPI state + maxItems: 19 interrupt-names: minItems: 1 + maxItems: 19 items: - - const: macirq - - enum: [eth_wake_irq, eth_lpi] - - const: eth_lpi + oneOf: + - description: Combined signal for various interrupt events + const: macirq + - description: The interrupt to manage the remote wake-up packet detection + const: eth_wake_irq + - description: The interrupt that occurs when Rx exits the LPI state + const: eth_lpi + - description: DMA Tx per-channel interrupt + pattern: '^dma_tx[0-7]?$' + - description: DMA Rx per-channel interrupt + pattern: '^dma_rx[0-7]?$' + + allOf: + - contains: + const: macirq clocks: minItems: 1 From patchwork Fri Dec 22 05:44:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Swee, Leong Ching" X-Patchwork-Id: 757952 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA729BE53; Fri, 22 Dec 2023 05:46:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ZQaL31hG" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703223967; x=1734759967; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pNSWH3cGb8jQjk1sGpH5wFxIWXQ+eiKLajT6kOJrQF8=; b=ZQaL31hGfkSlC6enpAurWuXrdg8H/EY4VtLfoUB07lgUOU6xq82fXbrU mQpB15GUvzoWOM3XnNHBd9zMmRDFA7iZNxBEL3EJF0/gIdXrf+Ykmb6Aw 2JaKuGLvjpalXguUpILsuyuwJljWzEPDUSaKn/WEK/xW8HmTmNZYvGa3N n2epkNj1E8RTAeFoP4b+g+nFNh4gdE6JsSaDLFz2NKIAwO18pel+aVlsn C4EGJFaasrbfIUjSbqufwXwMDcwRypwRjLLU/6QrRWbR98nbRsUQxgNAD iG3tULXjB+pAao2DKOA8ZKBGt2QoMYAjG1bUfoD+CBLRnnd8bew6BNRfT A==; X-IronPort-AV: E=McAfee;i="6600,9927,10931"; a="9470553" X-IronPort-AV: E=Sophos;i="6.04,294,1695711600"; d="scan'208";a="9470553" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2023 21:46:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10931"; a="900324214" X-IronPort-AV: E=Sophos;i="6.04,294,1695711600"; d="scan'208";a="900324214" Received: from pg-esw-build.png.intel.com ([10.226.214.57]) by orsmga004.jf.intel.com with ESMTP; 21 Dec 2023 21:46:01 -0800 From: Leong Ching Swee To: Maxime Coquelin , Alexandre Torgue , Jose Abreu , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Giuseppe Cavallaro Cc: linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, Swee Leong Ching , Teoh Ji Sheng Subject: [PATCH net-next v1 2/4] net: stmmac: Make MSI interrupt routine generic Date: Fri, 22 Dec 2023 13:44:49 +0800 Message-Id: <20231222054451.2683242-3-leong.ching.swee@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231222054451.2683242-1-leong.ching.swee@intel.com> References: <20231222054451.2683242-1-leong.ching.swee@intel.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Swee Leong Ching There is no support for per DMA channel interrupt for non-MSI platform, where the MAC's per channel interrupt hooks up to interrupt controller(GIC) through shared peripheral interrupt(SPI) to handle interrupt from TX/RX transmit channel. This patch generalize the existing MSI ISR to also support non-MSI platform. Signed-off-by: Teoh Ji Sheng Signed-off-by: Swee Leong Ching --- .../net/ethernet/stmicro/stmmac/dwmac-intel.c | 4 +-- .../net/ethernet/stmicro/stmmac/dwmac4_dma.c | 2 +- .../net/ethernet/stmicro/stmmac/stmmac_main.c | 29 ++++++++++--------- include/linux/stmmac.h | 4 +-- 4 files changed, 21 insertions(+), 18 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c index 60283543ffc8..f0ec69af96c9 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c @@ -952,7 +952,7 @@ static int stmmac_config_single_msi(struct pci_dev *pdev, res->irq = pci_irq_vector(pdev, 0); res->wol_irq = res->irq; - plat->flags &= ~STMMAC_FLAG_MULTI_MSI_EN; + plat->flags &= ~STMMAC_FLAG_MULTI_IRQ_EN; dev_info(&pdev->dev, "%s: Single IRQ enablement successful\n", __func__); @@ -1004,7 +1004,7 @@ static int stmmac_config_multi_msi(struct pci_dev *pdev, if (plat->msi_sfty_ue_vec < STMMAC_MSI_VEC_MAX) res->sfty_ue_irq = pci_irq_vector(pdev, plat->msi_sfty_ue_vec); - plat->flags |= STMMAC_FLAG_MULTI_MSI_EN; + plat->flags |= STMMAC_FLAG_MULTI_IRQ_EN; dev_info(&pdev->dev, "%s: multi MSI enablement successful\n", __func__); return 0; diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c index 84d3a8551b03..5f649106ffcd 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c @@ -175,7 +175,7 @@ static void dwmac4_dma_init(void __iomem *ioaddr, value = readl(ioaddr + DMA_BUS_MODE); - if (dma_cfg->multi_msi_en) { + if (dma_cfg->multi_irq_en) { value &= ~DMA_BUS_MODE_INTM_MASK; value |= (DMA_BUS_MODE_INTM_MODE1 << DMA_BUS_MODE_INTM_SHIFT); } diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 47de466e432c..30cc9edb4198 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -129,8 +129,8 @@ static irqreturn_t stmmac_interrupt(int irq, void *dev_id); /* For MSI interrupts handling */ static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id); static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id); -static irqreturn_t stmmac_msi_intr_tx(int irq, void *data); -static irqreturn_t stmmac_msi_intr_rx(int irq, void *data); +static irqreturn_t stmmac_tx_queue_interrupt(int irq, void *data); +static irqreturn_t stmmac_rx_queue_interrupt(int irq, void *data); static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue); static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue); static void stmmac_reset_queues_param(struct stmmac_priv *priv); @@ -3602,7 +3602,7 @@ static void stmmac_free_irq(struct net_device *dev, } } -static int stmmac_request_irq_multi_msi(struct net_device *dev) +static int stmmac_request_irq_multi(struct net_device *dev) { struct stmmac_priv *priv = netdev_priv(dev); enum request_irq_err irq_err; @@ -3701,13 +3701,13 @@ static int stmmac_request_irq_multi_msi(struct net_device *dev) for (i = 0; i < priv->plat->rx_queues_to_use; i++) { if (i >= MTL_MAX_RX_QUEUES) break; - if (priv->rx_irq[i] == 0) + if (priv->rx_irq[i] <= 0) continue; int_name = priv->int_name_rx_irq[i]; sprintf(int_name, "%s:%s-%d", dev->name, "rx", i); ret = request_irq(priv->rx_irq[i], - stmmac_msi_intr_rx, + stmmac_rx_queue_interrupt, 0, int_name, &priv->dma_conf.rx_queue[i]); if (unlikely(ret < 0)) { netdev_err(priv->dev, @@ -3726,13 +3726,13 @@ static int stmmac_request_irq_multi_msi(struct net_device *dev) for (i = 0; i < priv->plat->tx_queues_to_use; i++) { if (i >= MTL_MAX_TX_QUEUES) break; - if (priv->tx_irq[i] == 0) + if (priv->tx_irq[i] <= 0) continue; int_name = priv->int_name_tx_irq[i]; sprintf(int_name, "%s:%s-%d", dev->name, "tx", i); ret = request_irq(priv->tx_irq[i], - stmmac_msi_intr_tx, + stmmac_tx_queue_interrupt, 0, int_name, &priv->dma_conf.tx_queue[i]); if (unlikely(ret < 0)) { netdev_err(priv->dev, @@ -3811,8 +3811,8 @@ static int stmmac_request_irq(struct net_device *dev) int ret; /* Request the IRQ lines */ - if (priv->plat->flags & STMMAC_FLAG_MULTI_MSI_EN) - ret = stmmac_request_irq_multi_msi(dev); + if (priv->plat->flags & STMMAC_FLAG_MULTI_IRQ_EN) + ret = stmmac_request_irq_multi(dev); else ret = stmmac_request_irq_single(dev); @@ -6075,7 +6075,7 @@ static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static irqreturn_t stmmac_msi_intr_tx(int irq, void *data) +static irqreturn_t stmmac_tx_queue_interrupt(int irq, void *data) { struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data; struct stmmac_dma_conf *dma_conf; @@ -6107,7 +6107,7 @@ static irqreturn_t stmmac_msi_intr_tx(int irq, void *data) return IRQ_HANDLED; } -static irqreturn_t stmmac_msi_intr_rx(int irq, void *data) +static irqreturn_t stmmac_rx_queue_interrupt(int irq, void *data) { struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data; struct stmmac_dma_conf *dma_conf; @@ -7456,8 +7456,11 @@ int stmmac_dvr_probe(struct device *device, priv->plat = plat_dat; priv->ioaddr = res->addr; priv->dev->base_addr = (unsigned long)res->addr; - priv->plat->dma_cfg->multi_msi_en = - (priv->plat->flags & STMMAC_FLAG_MULTI_MSI_EN); + + if (res->rx_irq[0] > 0 && res->tx_irq[0] > 0) { + priv->plat->flags |= STMMAC_FLAG_MULTI_IRQ_EN; + priv->plat->dma_cfg->multi_irq_en = true; + } priv->dev->irq = res->irq; priv->wol_irq = res->wol_irq; diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index dee5ad6e48c5..b950e6f9761d 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -98,7 +98,7 @@ struct stmmac_dma_cfg { int mixed_burst; bool aal; bool eame; - bool multi_msi_en; + bool multi_irq_en; bool dche; }; @@ -215,7 +215,7 @@ struct dwmac4_addrs { #define STMMAC_FLAG_TSO_EN BIT(4) #define STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP BIT(5) #define STMMAC_FLAG_VLAN_FAIL_Q_EN BIT(6) -#define STMMAC_FLAG_MULTI_MSI_EN BIT(7) +#define STMMAC_FLAG_MULTI_IRQ_EN BIT(7) #define STMMAC_FLAG_EXT_SNAPSHOT_EN BIT(8) #define STMMAC_FLAG_INT_SNAPSHOT_EN BIT(9) #define STMMAC_FLAG_RX_CLK_RUNS_IN_LPI BIT(10) From patchwork Fri Dec 22 05:44:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Swee, Leong Ching" X-Patchwork-Id: 757589 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2F1F0C2DA; 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a="9470574" X-IronPort-AV: E=Sophos;i="6.04,294,1695711600"; d="scan'208";a="9470574" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2023 21:46:14 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10931"; a="900324224" X-IronPort-AV: E=Sophos;i="6.04,294,1695711600"; d="scan'208";a="900324224" Received: from pg-esw-build.png.intel.com ([10.226.214.57]) by orsmga004.jf.intel.com with ESMTP; 21 Dec 2023 21:46:09 -0800 From: Leong Ching Swee To: Maxime Coquelin , Alexandre Torgue , Jose Abreu , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Giuseppe Cavallaro Cc: linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, Swee Leong Ching , Teoh Ji Sheng Subject: [PATCH net-next v1 3/4] net: stmmac: Add support for TX/RX channel interrupt Date: Fri, 22 Dec 2023 13:44:50 +0800 Message-Id: <20231222054451.2683242-4-leong.ching.swee@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231222054451.2683242-1-leong.ching.swee@intel.com> References: <20231222054451.2683242-1-leong.ching.swee@intel.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Swee Leong Ching Enable TX/RX channel interrupt registration for MAC that interrupts CPU through shared peripheral interrupt (SPI). Per channel interrupts and interrupt-names are registered through, Eg: 4 tx and 4 rx channels: interrupts = , , , ; ; ; ; ; interrupt-names = "dma_tx0", "dma_tx1", "dma_tx2", "dma_tx3", "dma_rx0", "dma_rx1", "dma_rx2", "dma_rx3"; Signed-off-by: Teoh Ji Sheng Signed-off-by: Swee Leong Ching --- .../ethernet/stmicro/stmmac/stmmac_platform.c | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c index 70eadc83ca68..f857907f13a0 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c @@ -710,6 +710,8 @@ EXPORT_SYMBOL_GPL(devm_stmmac_probe_config_dt); int stmmac_get_platform_resources(struct platform_device *pdev, struct stmmac_resources *stmmac_res) { + char irq_name[8]; + int i; memset(stmmac_res, 0, sizeof(*stmmac_res)); /* Get IRQ information early to have an ability to ask for deferred @@ -719,6 +721,28 @@ int stmmac_get_platform_resources(struct platform_device *pdev, if (stmmac_res->irq < 0) return stmmac_res->irq; + /* For RX Channel */ + for (i = 0; i < MTL_MAX_RX_QUEUES; i++) { + snprintf(irq_name, sizeof(irq_name), "dma_rx%i", i); + stmmac_res->rx_irq[i] = platform_get_irq_byname_optional(pdev, irq_name); + if (stmmac_res->rx_irq[i] < 0) { + if (stmmac_res->rx_irq[i] == -EPROBE_DEFER) + return -EPROBE_DEFER; + break; + } + } + + /* For TX Channel */ + for (i = 0; i < MTL_MAX_TX_QUEUES; i++) { + snprintf(irq_name, sizeof(irq_name), "dma_tx%i", i); + stmmac_res->tx_irq[i] = platform_get_irq_byname_optional(pdev, irq_name); + if (stmmac_res->tx_irq[i] < 0) { + if (stmmac_res->rx_irq[i] == -EPROBE_DEFER) + return -EPROBE_DEFER; + break; + } + } + /* On some platforms e.g. SPEAr the wake up irq differs from the mac irq * The external wake up irq can be passed through the platform code * named as "eth_wake_irq" From patchwork Fri Dec 22 05:44:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Swee, Leong Ching" X-Patchwork-Id: 757951 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D40BD530; Fri, 22 Dec 2023 05:46:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="dY98KLm9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1703223986; x=1734759986; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jKRp9iRvAm9GuBLgpwNJYxVqDu1ubCTAkbYv82hvvk0=; b=dY98KLm9GcJddDdUEzvEZ6nxPLnhxeJK88g56ZM5qFJuwB2fmfdSM9Wp JTU+ph/CNMCA1MC+hdOz866tnWcOe/UVzJy3JBgc6IzTSBY0r62lnjErX NabGus/LaLVAuEOONaB/9+4S51xUJgu4whyMBfWO9a3SC//zrIbwSniH3 GM6RxAseGCNVkPH4RbAc0geIsRXgP2u4Y9WqH99Gc6IlgRL6+NiqzHMBf 0554amnJO4UiBBo8Gw86cpG812+epFU5ySW+VvVFZhbPzkyWQvKgCTh+T 82puphggOLGKbz3xxCZ02kJPikPjMkyUTbzVywOHpy3y8KPkFvckumwPq Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10931"; a="9470609" X-IronPort-AV: E=Sophos;i="6.04,294,1695711600"; d="scan'208";a="9470609" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2023 21:46:26 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10931"; a="900324247" X-IronPort-AV: E=Sophos;i="6.04,294,1695711600"; d="scan'208";a="900324247" Received: from pg-esw-build.png.intel.com ([10.226.214.57]) by orsmga004.jf.intel.com with ESMTP; 21 Dec 2023 21:46:21 -0800 From: Leong Ching Swee To: Maxime Coquelin , Alexandre Torgue , Jose Abreu , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Giuseppe Cavallaro Cc: linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, Swee Leong Ching , Teoh Ji Sheng Subject: [PATCH net-next v1 4/4] net: stmmac: Use interrupt mode INTM=1 for per channel irq Date: Fri, 22 Dec 2023 13:44:51 +0800 Message-Id: <20231222054451.2683242-5-leong.ching.swee@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231222054451.2683242-1-leong.ching.swee@intel.com> References: <20231222054451.2683242-1-leong.ching.swee@intel.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Swee Leong Ching Enable per DMA channel interrupt that uses shared peripheral interrupt (SPI), so only per channel TX and RX intr (TI/RI) are handled by TX/RX ISR without calling common interrupt ISR. Signed-off-by: Teoh Ji Sheng Signed-off-by: Swee Leong Ching --- .../net/ethernet/stmicro/stmmac/dwxgmac2.h | 3 ++ .../ethernet/stmicro/stmmac/dwxgmac2_dma.c | 32 +++++++++++-------- 2 files changed, 22 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h index 207ff1799f2c..04bf731cb7ea 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h @@ -346,6 +346,9 @@ /* DMA Registers */ #define XGMAC_DMA_MODE 0x00003000 #define XGMAC_SWR BIT(0) +#define XGMAC_DMA_MODE_INTM_MASK GENMASK(13, 12) +#define XGMAC_DMA_MODE_INTM_SHIFT 12 +#define XGMAC_DMA_MODE_INTM_MODE1 0x1 #define XGMAC_DMA_SYSBUS_MODE 0x00003004 #define XGMAC_WR_OSR_LMT GENMASK(29, 24) #define XGMAC_WR_OSR_LMT_SHIFT 24 diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c index 3cde695fec91..dcb9f094415d 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c @@ -31,6 +31,13 @@ static void dwxgmac2_dma_init(void __iomem *ioaddr, value |= XGMAC_EAME; writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); + + if (dma_cfg->multi_irq_en) { + value = readl(ioaddr + XGMAC_DMA_MODE); + value &= ~XGMAC_DMA_MODE_INTM_MASK; + value |= (XGMAC_DMA_MODE_INTM_MODE1 << XGMAC_DMA_MODE_INTM_SHIFT); + writel(value, ioaddr + XGMAC_DMA_MODE); + } } static void dwxgmac2_dma_init_chan(struct stmmac_priv *priv, @@ -365,19 +372,18 @@ static int dwxgmac2_dma_interrupt(struct stmmac_priv *priv, } /* TX/RX NORMAL interrupts */ - if (likely(intr_status & XGMAC_NIS)) { - if (likely(intr_status & XGMAC_RI)) { - u64_stats_update_begin(&rxq_stats->syncp); - rxq_stats->rx_normal_irq_n++; - u64_stats_update_end(&rxq_stats->syncp); - ret |= handle_rx; - } - if (likely(intr_status & (XGMAC_TI | XGMAC_TBU))) { - u64_stats_update_begin(&txq_stats->syncp); - txq_stats->tx_normal_irq_n++; - u64_stats_update_end(&txq_stats->syncp); - ret |= handle_tx; - } + if (likely(intr_status & XGMAC_RI)) { + u64_stats_update_begin(&rxq_stats->syncp); + rxq_stats->rx_normal_irq_n++; + u64_stats_update_end(&rxq_stats->syncp); + ret |= handle_rx; + } + + if (likely(intr_status & (XGMAC_TI | XGMAC_TBU))) { + u64_stats_update_begin(&txq_stats->syncp); + txq_stats->tx_normal_irq_n++; + u64_stats_update_end(&txq_stats->syncp); + ret |= handle_tx; } /* Clear interrupts */