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[178.235.179.206]) by smtp.gmail.com with ESMTPSA id i11-20020a056512340b00b0050e4db10fbfsm26603lfr.254.2023.12.19.05.05.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 05:05:11 -0800 (PST) From: Konrad Dybcio Date: Tue, 19 Dec 2023 14:05:06 +0100 Subject: [PATCH] arm64: dts: qcom: sc8180x: Fix up PCIe nodes Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20231219-topic-8180_pcie-v1-1-c2acbba4723c@linaro.org> X-B4-Tracking: v=1; b=H4sIAAGVgWUC/x2N0QqDMAwAf0XybMDWFau/IkPaLM6A1NJuYyD++ 8Ie7+C4EyoX4QpTc0Lhj1Q5koJpG6AtpCejPJTBdrY31oz4OrIQeuO7JZMw+uhubqXBDZFBqxg qYywh0aZdeu+7ylx4le9/M9+v6wfW0g7hdgAAAA== To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vinod Koul Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Manivannan Sadhasivam , Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1702991110; l=1644; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=3qURocdV9JugtB3wzqN3xIUL65Cs1IGJ54XSfyLP3cM=; b=EdFJ2UfVugCsBHSXT4uh/4OBbUAwmzOAQRTget26RZRfwzkVVbAI13MEaPV3MVVo1A46qX0kQ jv30Y6QvwEQBpNG7L3Ha/qYEqsFEhl8FNAaxaPMV7AyNzc5jU+NbZUD X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Duplicated clock output names cause probe errors and wrong clocks cause hardware not to work. Fix such issues. Fixes: d20b6c84f56a ("arm64: dts: qcom: sc8180x: Add PCIe instances") Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc8180x.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) --- base-commit: aa4db8324c4d0e67aa4670356df4e9fae14b4d37 change-id: 20231219-topic-8180_pcie-8b545fc757be Best regards, diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi index fe761d6d0dd3..acae2652a0f6 100644 --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi @@ -1761,7 +1761,7 @@ pcie0_phy: phy@1c06000 { clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, <&gcc GCC_PCIE_0_CLKREF_CLK>, - <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, <&gcc GCC_PCIE_0_PIPE_CLK>; clock-names = "aux", "cfg_ahb", @@ -1857,7 +1857,7 @@ pcie3_phy: phy@1c0c000 { clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, <&gcc GCC_PCIE_3_CFG_AHB_CLK>, <&gcc GCC_PCIE_3_CLKREF_CLK>, - <&gcc GCC_PCIE2_PHY_REFGEN_CLK>, + <&gcc GCC_PCIE3_PHY_REFGEN_CLK>, <&gcc GCC_PCIE_3_PIPE_CLK>; clock-names = "aux", "cfg_ahb", @@ -2059,7 +2059,7 @@ pcie2_phy: phy@1c1c000 { "refgen", "pipe"; #clock-cells = <0>; - clock-output-names = "pcie_3_pipe_clk"; + clock-output-names = "pcie_2_pipe_clk"; #phy-cells = <0>;