From patchwork Wed Dec 20 10:18:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 756750 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 62BEF20DCC; Wed, 20 Dec 2023 10:18:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="Rn+3v8GG" X-UUID: 253c17409f2111eea5db2bebc7c28f94-20231220 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=mRmkEoGzC/2ZuTRSrQxg+RXzdvtGyoRr9TXd9zrr4SE=; b=Rn+3v8GGENlT3BVvPoWekCbnAs+GK6xKsgBOS1Sfl6FrYsiZjN14wemLXOTfVSIWQ64Ea8uqnTNhu7p6gsUdHXVgvfANAncE3J8VJrVOGS3/JL+Z/PjXtjCDJ4V9qPuiBP8a7FtVd+tLVbKet63YNVwE92DFT25o+V74I53YRUY=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35, REQID:380917d7-eecb-4439-a820-4f3dade42c13, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5d391d7, CLOUDID:e48ffa81-8d4f-477b-89d2-1e3bdbef96d1, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 253c17409f2111eea5db2bebc7c28f94-20231220 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1892059634; Wed, 20 Dec 2023 18:18:40 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n2.mediatek.inc (172.21.101.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 20 Dec 2023 18:18:39 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 20 Dec 2023 18:18:39 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , Moudy Ho Subject: [PATCH v9 01/12] media: platform: mtk-mdp3: add support second sets of MMSYS Date: Wed, 20 Dec 2023 18:18:27 +0800 Message-ID: <20231220101838.21510-2-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231220101838.21510-1-moudy.ho@mediatek.com> References: <20231220101838.21510-1-moudy.ho@mediatek.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N The MT8195 chipset features two MMSYS subsets: VPPSYS0 and VPPSYS1. These subsets coordinate and control the clock, power, and register settings required for the components of MDP3. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno --- .../platform/mediatek/mdp3/mdp_cfg_data.c | 44 ++++++------- .../platform/mediatek/mdp3/mtk-mdp3-comp.h | 1 + .../platform/mediatek/mdp3/mtk-mdp3-core.c | 61 ++++++++++++++++--- .../platform/mediatek/mdp3/mtk-mdp3-core.h | 18 +++++- 4 files changed, 92 insertions(+), 32 deletions(-) diff --git a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c index 502eeae0bfdc..fcc582292b77 100644 --- a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c +++ b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c @@ -73,75 +73,75 @@ static const u32 mt8183_mutex_idx[MDP_MAX_COMP_COUNT] = { static const struct mdp_comp_data mt8183_mdp_comp_data[MDP_MAX_COMP_COUNT] = { [MDP_COMP_WPEI] = { - {MDP_COMP_TYPE_WPEI, 0, MT8183_MDP_COMP_WPEI}, + {MDP_COMP_TYPE_WPEI, 0, MT8183_MDP_COMP_WPEI, MDP_MM_SUBSYS_0}, {0, 0, 0} }, [MDP_COMP_WPEO] = { - {MDP_COMP_TYPE_EXTO, 2, MT8183_MDP_COMP_WPEO}, + {MDP_COMP_TYPE_EXTO, 2, MT8183_MDP_COMP_WPEO, MDP_MM_SUBSYS_0}, {0, 0, 0} }, [MDP_COMP_WPEI2] = { - {MDP_COMP_TYPE_WPEI, 1, MT8183_MDP_COMP_WPEI2}, + {MDP_COMP_TYPE_WPEI, 1, MT8183_MDP_COMP_WPEI2, MDP_MM_SUBSYS_0}, {0, 0, 0} }, [MDP_COMP_WPEO2] = { - {MDP_COMP_TYPE_EXTO, 3, MT8183_MDP_COMP_WPEO2}, + {MDP_COMP_TYPE_EXTO, 3, MT8183_MDP_COMP_WPEO2, MDP_MM_SUBSYS_0}, {0, 0, 0} }, [MDP_COMP_ISP_IMGI] = { - {MDP_COMP_TYPE_IMGI, 0, MT8183_MDP_COMP_ISP_IMGI}, + {MDP_COMP_TYPE_IMGI, 0, MT8183_MDP_COMP_ISP_IMGI, MDP_MM_SUBSYS_0}, {0, 0, 4} }, [MDP_COMP_ISP_IMGO] = { - {MDP_COMP_TYPE_EXTO, 0, MT8183_MDP_COMP_ISP_IMGO}, + {MDP_COMP_TYPE_EXTO, 0, MT8183_MDP_COMP_ISP_IMGO, MDP_MM_SUBSYS_0}, {0, 0, 4} }, [MDP_COMP_ISP_IMG2O] = { - {MDP_COMP_TYPE_EXTO, 1, MT8183_MDP_COMP_ISP_IMG2O}, + {MDP_COMP_TYPE_EXTO, 1, MT8183_MDP_COMP_ISP_IMG2O, MDP_MM_SUBSYS_0}, {0, 0, 0} }, [MDP_COMP_CAMIN] = { - {MDP_COMP_TYPE_DL_PATH, 0, MT8183_MDP_COMP_CAMIN}, + {MDP_COMP_TYPE_DL_PATH, 0, MT8183_MDP_COMP_CAMIN, MDP_MM_SUBSYS_0}, {2, 2, 1} }, [MDP_COMP_CAMIN2] = { - {MDP_COMP_TYPE_DL_PATH, 1, MT8183_MDP_COMP_CAMIN2}, + {MDP_COMP_TYPE_DL_PATH, 1, MT8183_MDP_COMP_CAMIN2, MDP_MM_SUBSYS_0}, {2, 4, 1} }, [MDP_COMP_RDMA0] = { - {MDP_COMP_TYPE_RDMA, 0, MT8183_MDP_COMP_RDMA0}, + {MDP_COMP_TYPE_RDMA, 0, MT8183_MDP_COMP_RDMA0, MDP_MM_SUBSYS_0}, {2, 0, 0} }, [MDP_COMP_CCORR0] = { - {MDP_COMP_TYPE_CCORR, 0, MT8183_MDP_COMP_CCORR0}, + {MDP_COMP_TYPE_CCORR, 0, MT8183_MDP_COMP_CCORR0, MDP_MM_SUBSYS_0}, {1, 0, 0} }, [MDP_COMP_RSZ0] = { - {MDP_COMP_TYPE_RSZ, 0, MT8183_MDP_COMP_RSZ0}, + {MDP_COMP_TYPE_RSZ, 0, MT8183_MDP_COMP_RSZ0, MDP_MM_SUBSYS_0}, {1, 0, 0} }, [MDP_COMP_RSZ1] = { - {MDP_COMP_TYPE_RSZ, 1, MT8183_MDP_COMP_RSZ1}, + {MDP_COMP_TYPE_RSZ, 1, MT8183_MDP_COMP_RSZ1, MDP_MM_SUBSYS_0}, {1, 0, 0} }, [MDP_COMP_TDSHP0] = { - {MDP_COMP_TYPE_TDSHP, 0, MT8183_MDP_COMP_TDSHP0}, + {MDP_COMP_TYPE_TDSHP, 0, MT8183_MDP_COMP_TDSHP0, MDP_MM_SUBSYS_0}, {0, 0, 0} }, [MDP_COMP_PATH0_SOUT] = { - {MDP_COMP_TYPE_PATH, 0, MT8183_MDP_COMP_PATH0_SOUT}, + {MDP_COMP_TYPE_PATH, 0, MT8183_MDP_COMP_PATH0_SOUT, MDP_MM_SUBSYS_0}, {0, 0, 0} }, [MDP_COMP_PATH1_SOUT] = { - {MDP_COMP_TYPE_PATH, 1, MT8183_MDP_COMP_PATH1_SOUT}, + {MDP_COMP_TYPE_PATH, 1, MT8183_MDP_COMP_PATH1_SOUT, MDP_MM_SUBSYS_0}, {0, 0, 0} }, [MDP_COMP_WROT0] = { - {MDP_COMP_TYPE_WROT, 0, MT8183_MDP_COMP_WROT0}, + {MDP_COMP_TYPE_WROT, 0, MT8183_MDP_COMP_WROT0, MDP_MM_SUBSYS_0}, {1, 0, 0} }, [MDP_COMP_WDMA] = { - {MDP_COMP_TYPE_WDMA, 0, MT8183_MDP_COMP_WDMA}, + {MDP_COMP_TYPE_WDMA, 0, MT8183_MDP_COMP_WDMA, MDP_MM_SUBSYS_0}, {1, 0, 0} }, }; @@ -402,10 +402,10 @@ static const struct mdp_limit mt8183_mdp_def_limit = { }; static const struct mdp_pipe_info mt8183_pipe_info[] = { - [MDP_PIPE_WPEI] = {MDP_PIPE_WPEI, 0}, - [MDP_PIPE_WPEI2] = {MDP_PIPE_WPEI2, 1}, - [MDP_PIPE_IMGI] = {MDP_PIPE_IMGI, 2}, - [MDP_PIPE_RDMA0] = {MDP_PIPE_RDMA0, 3} + [MDP_PIPE_WPEI] = {MDP_PIPE_WPEI, MDP_MM_SUBSYS_0, 0}, + [MDP_PIPE_WPEI2] = {MDP_PIPE_WPEI2, MDP_MM_SUBSYS_0, 1}, + [MDP_PIPE_IMGI] = {MDP_PIPE_IMGI, MDP_MM_SUBSYS_0, 2}, + [MDP_PIPE_RDMA0] = {MDP_PIPE_RDMA0, MDP_MM_SUBSYS_0, 3} }; const struct mtk_mdp_driver_data mt8183_mdp_driver_data = { diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h index 20d2bcb77ef9..e89c51e1edb7 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h @@ -138,6 +138,7 @@ struct mdp_comp_match { enum mdp_comp_type type; u32 alias_id; s32 inner_id; + s32 subsys_id; }; /* Used to describe the item order in MDP property */ diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c index 94f4ed78523b..8cd0f11fc290 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c @@ -26,9 +26,10 @@ static const struct of_device_id mdp_of_ids[] = { MODULE_DEVICE_TABLE(of, mdp_of_ids); static struct platform_device *__get_pdev_by_id(struct platform_device *pdev, + struct platform_device *from, enum mdp_infra_id id) { - struct device_node *node; + struct device_node *node, *f = NULL; struct platform_device *mdp_pdev = NULL; const struct mtk_mdp_driver_data *mdp_data; const char *compat; @@ -46,9 +47,14 @@ static struct platform_device *__get_pdev_by_id(struct platform_device *pdev, dev_err(&pdev->dev, "have no driver data to find node\n"); return NULL; } + compat = mdp_data->mdp_probe_infra[id].compatible; + if (strlen(compat) == 0) + return NULL; - node = of_find_compatible_node(NULL, NULL, compat); + if (from) + f = from->dev.of_node; + node = of_find_compatible_node(f, NULL, compat); if (WARN_ON(!node)) { dev_err(&pdev->dev, "find node from id %d failed\n", id); return NULL; @@ -148,6 +154,46 @@ void mdp_video_device_release(struct video_device *vdev) kfree(mdp); } +static int mdp_mm_subsys_deploy(struct mdp_dev *mdp, enum mdp_infra_id id) +{ + struct platform_device *mm_pdev = NULL; + struct device **dev; + int i; + + if (!mdp) + return -EINVAL; + + for (i = 0; i < MDP_MM_SUBSYS_MAX; i++) { + const char *compat; + enum mdp_infra_id sub_id = id + i; + + switch (id) { + case MDP_INFRA_MMSYS: + dev = &mdp->mm_subsys[i].mmsys; + break; + default: + dev_err(&mdp->pdev->dev, "Unknown infra id %d", id); + return -EINVAL; + } + + /* + * Not every chip has multiple multimedia subsystems, so + * the config may be null. + */ + compat = mdp->mdp_data->mdp_probe_infra[sub_id].compatible; + if (strlen(compat) == 0) + continue; + + mm_pdev = __get_pdev_by_id(mdp->pdev, mm_pdev, sub_id); + if (WARN_ON(!mm_pdev)) + return -ENODEV; + + *dev = &mm_pdev->dev; + } + + return 0; +} + static int mdp_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -164,14 +210,11 @@ static int mdp_probe(struct platform_device *pdev) mdp->pdev = pdev; mdp->mdp_data = of_device_get_match_data(&pdev->dev); - mm_pdev = __get_pdev_by_id(pdev, MDP_INFRA_MMSYS); - if (!mm_pdev) { - ret = -ENODEV; + ret = mdp_mm_subsys_deploy(mdp, MDP_INFRA_MMSYS); + if (ret) goto err_destroy_device; - } - mdp->mdp_mmsys = &mm_pdev->dev; - mm_pdev = __get_pdev_by_id(pdev, MDP_INFRA_MUTEX); + mm_pdev = __get_pdev_by_id(pdev, NULL, MDP_INFRA_MUTEX); if (WARN_ON(!mm_pdev)) { ret = -ENODEV; goto err_destroy_device; @@ -210,7 +253,7 @@ static int mdp_probe(struct platform_device *pdev) mdp->scp = scp_get(pdev); if (!mdp->scp) { - mm_pdev = __get_pdev_by_id(pdev, MDP_INFRA_SCP); + mm_pdev = __get_pdev_by_id(pdev, NULL, MDP_INFRA_SCP); if (WARN_ON(!mm_pdev)) { dev_err(&pdev->dev, "Could not get scp device\n"); ret = -ENODEV; diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h index 7e21d226ceb8..7a7cdd0ce968 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h @@ -19,12 +19,23 @@ #define MDP_PHANDLE_NAME "mediatek,mdp3" enum mdp_infra_id { + /* + * Due to the sequential nature of function "mdp_mm_subsys_deploy", + * adding new enum. necessitates careful consideration. + */ MDP_INFRA_MMSYS, + MDP_INFRA_MMSYS2, MDP_INFRA_MUTEX, MDP_INFRA_SCP, MDP_INFRA_MAX }; +enum mdp_mm_subsys_id { + MDP_MM_SUBSYS_0, + MDP_MM_SUBSYS_1, + MDP_MM_SUBSYS_MAX, +}; + enum mdp_buffer_usage { MDP_BUFFER_USAGE_HW_READ, MDP_BUFFER_USAGE_MDP, @@ -65,9 +76,13 @@ struct mtk_mdp_driver_data { unsigned int pipe_info_len; }; +struct mdp_mm_subsys { + struct device *mmsys; +}; + struct mdp_dev { struct platform_device *pdev; - struct device *mdp_mmsys; + struct mdp_mm_subsys mm_subsys[MDP_MM_SUBSYS_MAX]; struct mtk_mutex *mdp_mutex[MDP_PIPE_MAX]; struct mdp_comp *comp[MDP_MAX_COMP_COUNT]; const struct mtk_mdp_driver_data *mdp_data; @@ -96,6 +111,7 @@ struct mdp_dev { struct mdp_pipe_info { enum mdp_pipe_id pipe_id; + enum mdp_mm_subsys_id sub_id; u32 mutex_id; }; From patchwork Wed Dec 20 10:18:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 756751 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76628208BB; 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Wed, 20 Dec 2023 18:18:40 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 20 Dec 2023 18:18:39 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 20 Dec 2023 18:18:39 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , Moudy Ho Subject: [PATCH v9 02/12] media: platform: mtk-mdp3: add support second sets of MUTEX Date: Wed, 20 Dec 2023 18:18:28 +0800 Message-ID: <20231220101838.21510-3-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231220101838.21510-1-moudy.ho@mediatek.com> References: <20231220101838.21510-1-moudy.ho@mediatek.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--10.127700-8.000000 X-TMASE-MatchedRID: SxnEO+JKTxoMiTNbd7AZSUD6z8N1m1ALTJDl9FKHbrk1LB46LFAAkhfB mF7pasJaoB9KLeioyTVJoFXIuzqlwbhzq4QWtOF2dXz3l78F3Ym4vBuE2X0HlX5h6y4KCSJc2Us WvUfe8jwEtgPPYjUPdQGZLfTlpw3f2lUnG4pY3Gy+dJWHbg4ITl67veYUroY0DpCUEeEFm7Ar3f toV0Xlc0vuLUFcu0MoDXWbDjwr3eyBiU7YV+klbrdQIb8hCnY+GSqdEmeD/nVdlUpKWB7xbyMOu GtF4L1EhbjW39vH2+ihJHMXPR4MEInYeNMpd8GQHcQQBuf4ZFu8n1e+HkKZPpsoi2XrUn/JUTdY /mdfTXtJKW4mDlJsMcK21zBg2Klf/KO2LNTSuGPThaXiooN2SiUxa5Q5Zp8IrCXtvBhfHxyMHk2 CQj0Dow== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--10.127700-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: DCF63A903E5918F825EF2A8437E109DF45429268DD93F3CEB80FB6F22D6473232000:8 X-MTK: N After setting up the second set of MMSYS (VPPSYS1), it is necessary to have a corresponding second set of MUTEX (MUTEX2) to assist in handling SOF/EOF. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno --- .../platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 57 +++++++++++-------- .../platform/mediatek/mdp3/mtk-mdp3-core.c | 51 ++++++++++++----- .../platform/mediatek/mdp3/mtk-mdp3-core.h | 4 +- 3 files changed, 74 insertions(+), 38 deletions(-) diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c index 6adac857a477..67c8fcc3eda9 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c @@ -44,15 +44,21 @@ static bool is_output_disabled(int p_id, const struct img_compparam *param, u32 return (count < num) ? (dis_output || dis_tile) : true; } +static struct mtk_mutex *__get_mutex(const struct mdp_dev *mdp_dev, + const struct mdp_pipe_info *p) +{ + return mdp_dev->mm_subsys[p->sub_id].mdp_mutex[p->mutex_id]; +} + static int mdp_path_subfrm_require(const struct mdp_path *path, struct mdp_cmdq_cmd *cmd, - s32 *mutex_id, u32 count) + struct mdp_pipe_info *p, u32 count) { const int p_id = path->mdp_dev->mdp_data->mdp_plat_id; const struct mdp_comp_ctx *ctx; const struct mtk_mdp_driver_data *data = path->mdp_dev->mdp_data; struct device *dev = &path->mdp_dev->pdev->dev; - struct mtk_mutex **mutex = path->mdp_dev->mdp_mutex; + struct mtk_mutex *mutex; int id, index; u32 num_comp = 0; @@ -77,7 +83,8 @@ static int mdp_path_subfrm_require(const struct mdp_path *path, dev_err(dev, "Unknown pipeline and no mutex is assigned"); return -EINVAL; } - *mutex_id = data->pipe_info[index].mutex_id; + memcpy(p, &data->pipe_info[index], sizeof(struct mdp_pipe_info)); + mutex = __get_mutex(path->mdp_dev, p); /* Set mutex mod */ for (index = 0; index < num_comp; index++) { @@ -85,29 +92,28 @@ static int mdp_path_subfrm_require(const struct mdp_path *path, if (is_output_disabled(p_id, ctx->param, count)) continue; id = ctx->comp->public_id; - mtk_mutex_write_mod(mutex[*mutex_id], - data->mdp_mutex_table_idx[id], false); + mtk_mutex_write_mod(mutex, data->mdp_mutex_table_idx[id], false); + } - mtk_mutex_write_sof(mutex[*mutex_id], - MUTEX_SOF_IDX_SINGLE_MODE); + mtk_mutex_write_sof(mutex, MUTEX_SOF_IDX_SINGLE_MODE); return 0; } static int mdp_path_subfrm_run(const struct mdp_path *path, struct mdp_cmdq_cmd *cmd, - s32 *mutex_id, u32 count) + struct mdp_pipe_info *p, u32 count) { const int p_id = path->mdp_dev->mdp_data->mdp_plat_id; const struct mdp_comp_ctx *ctx; struct device *dev = &path->mdp_dev->pdev->dev; - struct mtk_mutex **mutex = path->mdp_dev->mdp_mutex; + struct mtk_mutex *mutex; int index; u32 num_comp = 0; s32 event; - if (-1 == *mutex_id) { + if (-1 == p->mutex_id) { dev_err(dev, "Incorrect mutex id"); return -EINVAL; } @@ -127,7 +133,8 @@ static int mdp_path_subfrm_run(const struct mdp_path *path, } /* Enable the mutex */ - mtk_mutex_enable_by_cmdq(mutex[*mutex_id], (void *)&cmd->pkt); + mutex = __get_mutex(path->mdp_dev, p); + mtk_mutex_enable_by_cmdq(mutex, (void *)&cmd->pkt); /* Wait SOF events and clear mutex modules (optional) */ for (index = 0; index < num_comp; index++) { @@ -174,7 +181,7 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd, const struct img_mmsys_ctrl *ctrl = NULL; const struct img_mux *set; struct mdp_comp_ctx *ctx; - s32 mutex_id; + struct mdp_pipe_info pipe; int index, ret; u32 num_comp = 0; @@ -185,7 +192,7 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd, ctrl = CFG_ADDR(MT8183, path->config, ctrls[count]); /* Acquire components */ - ret = mdp_path_subfrm_require(path, cmd, &mutex_id, count); + ret = mdp_path_subfrm_require(path, cmd, &pipe, count); if (ret) return ret; /* Enable mux settings */ @@ -204,7 +211,7 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd, return ret; } /* Run components */ - ret = mdp_path_subfrm_run(path, cmd, &mutex_id, count); + ret = mdp_path_subfrm_run(path, cmd, &pipe, count); if (ret) return ret; /* Wait components done */ @@ -328,13 +335,13 @@ static void mdp_auto_release_work(struct work_struct *work) { struct mdp_cmdq_cmd *cmd; struct mdp_dev *mdp; - int id; + struct mtk_mutex *mutex; cmd = container_of(work, struct mdp_cmdq_cmd, auto_release_work); mdp = cmd->mdp; - id = mdp->mdp_data->pipe_info[MDP_PIPE_RDMA0].mutex_id; - mtk_mutex_unprepare(mdp->mdp_mutex[id]); + mutex = __get_mutex(mdp, &mdp->mdp_data->pipe_info[MDP_PIPE_RDMA0]); + mtk_mutex_unprepare(mutex); mdp_comp_clocks_off(&mdp->pdev->dev, cmd->comps, cmd->num_comps); @@ -354,7 +361,6 @@ static void mdp_handle_cmdq_callback(struct mbox_client *cl, void *mssg) struct cmdq_cb_data *data; struct mdp_dev *mdp; struct device *dev; - int id; if (!mssg) { pr_info("%s:no callback data\n", __func__); @@ -379,9 +385,11 @@ static void mdp_handle_cmdq_callback(struct mbox_client *cl, void *mssg) INIT_WORK(&cmd->auto_release_work, mdp_auto_release_work); if (!queue_work(mdp->clock_wq, &cmd->auto_release_work)) { + struct mtk_mutex *mutex; + dev_err(dev, "%s:queue_work fail!\n", __func__); - id = mdp->mdp_data->pipe_info[MDP_PIPE_RDMA0].mutex_id; - mtk_mutex_unprepare(mdp->mdp_mutex[id]); + mutex = __get_mutex(mdp, &mdp->mdp_data->pipe_info[MDP_PIPE_RDMA0]); + mtk_mutex_unprepare(mutex); mdp_comp_clocks_off(&mdp->pdev->dev, cmd->comps, cmd->num_comps); @@ -403,6 +411,7 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) struct mdp_comp *comps = NULL; struct device *dev = &mdp->pdev->dev; const int p_id = mdp->mdp_data->mdp_plat_id; + struct mtk_mutex *mutex = NULL; int i, ret; u32 num_comp = 0; @@ -440,8 +449,8 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) goto err_free_comps; } - i = mdp->mdp_data->pipe_info[MDP_PIPE_RDMA0].mutex_id; - ret = mtk_mutex_prepare(mdp->mdp_mutex[i]); + mutex = __get_mutex(mdp, &mdp->mdp_data->pipe_info[MDP_PIPE_RDMA0]); + ret = mtk_mutex_prepare(mutex); if (ret) { dev_err(dev, "Fail to enable mutex clk\n"); goto err_free_path; @@ -506,8 +515,8 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) mdp_comp_clocks_off(&mdp->pdev->dev, cmd->comps, cmd->num_comps); err_free_path: - i = mdp->mdp_data->pipe_info[MDP_PIPE_RDMA0].mutex_id; - mtk_mutex_unprepare(mdp->mdp_mutex[i]); + if (mutex) + mtk_mutex_unprepare(mutex); kfree(path); err_free_comps: kfree(comps); diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c index 8cd0f11fc290..4802b20d7f20 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c @@ -146,8 +146,17 @@ void mdp_video_device_release(struct video_device *vdev) vb2_dma_contig_clear_max_seg_size(&mdp->pdev->dev); mdp_comp_destroy(mdp); - for (i = 0; i < MDP_PIPE_MAX; i++) - mtk_mutex_put(mdp->mdp_mutex[i]); + for (i = 0; i < mdp->mdp_data->pipe_info_len; i++) { + enum mdp_mm_subsys_id idx; + struct mtk_mutex *m; + u32 m_id; + + idx = mdp->mdp_data->pipe_info[i].sub_id; + m_id = mdp->mdp_data->pipe_info[i].mutex_id; + m = mdp->mm_subsys[idx].mdp_mutex[m_id]; + if (!IS_ERR_OR_NULL(m)) + mtk_mutex_put(m); + } mdp_vpu_shared_mem_free(&mdp->vpu); v4l2_m2m_release(mdp->m2m_dev); @@ -171,6 +180,9 @@ static int mdp_mm_subsys_deploy(struct mdp_dev *mdp, enum mdp_infra_id id) case MDP_INFRA_MMSYS: dev = &mdp->mm_subsys[i].mmsys; break; + case MDP_INFRA_MUTEX: + dev = &mdp->mm_subsys[i].mutex; + break; default: dev_err(&mdp->pdev->dev, "Unknown infra id %d", id); return -EINVAL; @@ -214,18 +226,24 @@ static int mdp_probe(struct platform_device *pdev) if (ret) goto err_destroy_device; - mm_pdev = __get_pdev_by_id(pdev, NULL, MDP_INFRA_MUTEX); - if (WARN_ON(!mm_pdev)) { - ret = -ENODEV; + ret = mdp_mm_subsys_deploy(mdp, MDP_INFRA_MUTEX); + if (ret) goto err_destroy_device; - } + for (i = 0; i < mdp->mdp_data->pipe_info_len; i++) { + enum mdp_mm_subsys_id idx; + struct mtk_mutex **m; + + idx = mdp->mdp_data->pipe_info[i].sub_id; mutex_id = mdp->mdp_data->pipe_info[i].mutex_id; - if (!IS_ERR_OR_NULL(mdp->mdp_mutex[mutex_id])) + m = &mdp->mm_subsys[idx].mdp_mutex[mutex_id]; + + if (!IS_ERR_OR_NULL(*m)) continue; - mdp->mdp_mutex[mutex_id] = mtk_mutex_get(&mm_pdev->dev); - if (IS_ERR(mdp->mdp_mutex[mutex_id])) { - ret = PTR_ERR(mdp->mdp_mutex[mutex_id]); + + *m = mtk_mutex_get(mdp->mm_subsys[idx].mutex); + if (IS_ERR(*m)) { + ret = PTR_ERR(*m); goto err_free_mutex; } } @@ -309,9 +327,16 @@ static int mdp_probe(struct platform_device *pdev) err_deinit_comp: mdp_comp_destroy(mdp); err_free_mutex: - for (i = 0; i < mdp->mdp_data->pipe_info_len; i++) - if (!IS_ERR_OR_NULL(mdp->mdp_mutex[i])) - mtk_mutex_put(mdp->mdp_mutex[i]); + for (i = 0; i < mdp->mdp_data->pipe_info_len; i++) { + enum mdp_mm_subsys_id idx; + struct mtk_mutex *m; + + idx = mdp->mdp_data->pipe_info[i].sub_id; + mutex_id = mdp->mdp_data->pipe_info[i].mutex_id; + m = mdp->mm_subsys[idx].mdp_mutex[mutex_id]; + if (!IS_ERR_OR_NULL(m)) + mtk_mutex_put(m); + } err_destroy_device: kfree(mdp); err_return: diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h index 7a7cdd0ce968..fde2c0b95def 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h @@ -26,6 +26,7 @@ enum mdp_infra_id { MDP_INFRA_MMSYS, MDP_INFRA_MMSYS2, MDP_INFRA_MUTEX, + MDP_INFRA_MUTEX2, MDP_INFRA_SCP, MDP_INFRA_MAX }; @@ -78,12 +79,13 @@ struct mtk_mdp_driver_data { struct mdp_mm_subsys { struct device *mmsys; + struct device *mutex; + struct mtk_mutex *mdp_mutex[MDP_PIPE_MAX]; }; struct mdp_dev { struct platform_device *pdev; struct mdp_mm_subsys mm_subsys[MDP_MM_SUBSYS_MAX]; - struct mtk_mutex *mdp_mutex[MDP_PIPE_MAX]; struct mdp_comp *comp[MDP_MAX_COMP_COUNT]; const struct mtk_mdp_driver_data *mdp_data; From patchwork Wed Dec 20 10:18:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 756752 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A12E3200B9; Wed, 20 Dec 2023 10:18:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; 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Wed, 20 Dec 2023 18:18:41 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 20 Dec 2023 18:18:39 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 20 Dec 2023 18:18:39 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , Moudy Ho Subject: [PATCH v9 04/12] media: platform: mtk-mdp3: introduce more MDP3 components Date: Wed, 20 Dec 2023 18:18:30 +0800 Message-ID: <20231220101838.21510-5-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231220101838.21510-1-moudy.ho@mediatek.com> References: <20231220101838.21510-1-moudy.ho@mediatek.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--8.442300-8.000000 X-TMASE-MatchedRID: iEpXmf/25Q0s6cxI7W6yCGNW0DAjL5p++OI6XsK3BWHfUZT83lbkEH3q 33AN90RFqlMyex6rdQlDkFqK5u4Dd6o77AcuQhw7uIwLnB3Aqp2WHGENdT+VP8SiwizsgluQa2r VL+hQbq7qUsdAyq21W29HdIY9j4IIdPbgWSDbLa4HtOpEBhWiFlg3VqSTJ7So+5+93dPb6/cM6X BtKTGUp6ruib+oAEoqvN07RWVDbwH4OiVTWoD8RPPA28sXrr0yFk73i4rVVIFh7WbOnt2TB+pQB fxI8G3CjDVGmIXGRKA+v1uiXBkw6lxxDx5qbkR9FEUknJ/kEl7dB/CxWTRRu9bFCwAgdKkSEEnJ n2dNeWAAoKWkfD7VZDIMREml/SEFWe4oCiEpyu9tOTO0U3fpy5RMZUCEHkRt X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--8.442300-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 334B2591586EF155A93688245655AFD25F0B338FA1E51992A1FC605BA38ECC452000:8 X-MTK: N Add configuration of more components in MT8195 MDP3. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno --- .../platform/mediatek/mdp3/mdp_reg_aal.h | 25 ++++++ .../platform/mediatek/mdp3/mdp_reg_color.h | 31 +++++++ .../media/platform/mediatek/mdp3/mdp_reg_fg.h | 23 +++++ .../platform/mediatek/mdp3/mdp_reg_hdr.h | 31 +++++++ .../platform/mediatek/mdp3/mdp_reg_merge.h | 25 ++++++ .../platform/mediatek/mdp3/mdp_reg_ovl.h | 25 ++++++ .../platform/mediatek/mdp3/mdp_reg_pad.h | 21 +++++ .../platform/mediatek/mdp3/mdp_reg_rdma.h | 24 ++++++ .../platform/mediatek/mdp3/mdp_reg_rsz.h | 2 + .../platform/mediatek/mdp3/mdp_reg_tdshp.h | 34 ++++++++ .../platform/mediatek/mdp3/mdp_reg_wrot.h | 8 ++ .../platform/mediatek/mdp3/mtk-mdp3-comp.h | 85 +++++++++++++++---- 12 files changed, 318 insertions(+), 16 deletions(-) create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_aal.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_color.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_fg.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_hdr.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_merge.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_ovl.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_pad.h create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_tdshp.h diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_aal.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_aal.h new file mode 100644 index 000000000000..4b9513e54543 --- /dev/null +++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_aal.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MDP_REG_AAL_H__ +#define __MDP_REG_AAL_H__ + +#define MDP_AAL_EN (0x000) +#define MDP_AAL_CFG (0x020) +#define MDP_AAL_SIZE (0x030) +#define MDP_AAL_OUTPUT_SIZE (0x034) +#define MDP_AAL_OUTPUT_OFFSET (0x038) +#define MDP_AAL_CFG_MAIN (0x200) + +/* MASK */ +#define MDP_AAL_EN_MASK (0x01) +#define MDP_AAL_CFG_MASK (0x70FF00B3) +#define MDP_AAL_SIZE_MASK (0x1FFF1FFF) +#define MDP_AAL_OUTPUT_SIZE_MASK (0x1FFF1FFF) +#define MDP_AAL_OUTPUT_OFFSET_MASK (0x0FF00FF) +#define MDP_AAL_CFG_MAIN_MASK (0x0FE) + +#endif // __MDP_REG_AAL_H__ diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_color.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_color.h new file mode 100644 index 000000000000..f72503975b24 --- /dev/null +++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_color.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MDP_REG_COLOR_H__ +#define __MDP_REG_COLOR_H__ + +#define MDP_COLOR_WIN_X_MAIN (0x40C) +#define MDP_COLOR_WIN_Y_MAIN (0x410) +#define MDP_COLOR_START (0xC00) +#define MDP_COLOR_INTEN (0xC04) +#define MDP_COLOR_OUT_SEL (0xC0C) +#define MDP_COLOR_INTERNAL_IP_WIDTH (0xC50) +#define MDP_COLOR_INTERNAL_IP_HEIGHT (0xC54) +#define MDP_COLOR_CM1_EN (0xC60) +#define MDP_COLOR_CM2_EN (0xCA0) + +/* MASK */ +#define MDP_COLOR_WIN_X_MAIN_MASK (0xFFFFFFFF) +#define MDP_COLOR_WIN_Y_MAIN_MASK (0xFFFFFFFF) +#define MDP_COLOR_START_MASK (0x0FF013F) +#define MDP_COLOR_INTEN_MASK (0x07) +#define MDP_COLOR_OUT_SEL_MASK (0x0777) +#define MDP_COLOR_INTERNAL_IP_WIDTH_MASK (0x03FFF) +#define MDP_COLOR_INTERNAL_IP_HEIGHT_MASK (0x03FFF) +#define MDP_COLOR_CM1_EN_MASK (0x03) +#define MDP_COLOR_CM2_EN_MASK (0x017) + +#endif // __MDP_REG_COLOR_H__ diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_fg.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_fg.h new file mode 100644 index 000000000000..d90bcad33a59 --- /dev/null +++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_fg.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MDP_REG_FG_H__ +#define __MDP_REG_FG_H__ + +#define MDP_FG_TRIGGER (0x0) +#define MDP_FG_FG_CTRL_0 (0x20) +#define MDP_FG_FG_CK_EN (0x24) +#define MDP_FG_TILE_INFO_0 (0x418) +#define MDP_FG_TILE_INFO_1 (0x41c) + +/* MASK */ +#define MDP_FG_TRIGGER_MASK (0x00000007) +#define MDP_FG_FG_CTRL_0_MASK (0x00000033) +#define MDP_FG_FG_CK_EN_MASK (0x0000000F) +#define MDP_FG_TILE_INFO_0_MASK (0xFFFFFFFF) +#define MDP_FG_TILE_INFO_1_MASK (0xFFFFFFFF) + +#endif //__MDP_REG_FG_H__ diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_hdr.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_hdr.h new file mode 100644 index 000000000000..c19fbba39fc0 --- /dev/null +++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_hdr.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MDP_REG_HDR_H__ +#define __MDP_REG_HDR_H__ + +#define MDP_HDR_TOP (0x000) +#define MDP_HDR_RELAY (0x004) +#define MDP_HDR_SIZE_0 (0x014) +#define MDP_HDR_SIZE_1 (0x018) +#define MDP_HDR_SIZE_2 (0x01C) +#define MDP_HDR_HIST_CTRL_0 (0x020) +#define MDP_HDR_HIST_CTRL_1 (0x024) +#define MDP_HDR_HIST_ADDR (0x0DC) +#define MDP_HDR_TILE_POS (0x118) + +/* MASK */ +#define MDP_HDR_RELAY_MASK (0x01) +#define MDP_HDR_TOP_MASK (0xFF0FEB6D) +#define MDP_HDR_SIZE_0_MASK (0x1FFF1FFF) +#define MDP_HDR_SIZE_1_MASK (0x1FFF1FFF) +#define MDP_HDR_SIZE_2_MASK (0x1FFF1FFF) +#define MDP_HDR_HIST_CTRL_0_MASK (0x1FFF1FFF) +#define MDP_HDR_HIST_CTRL_1_MASK (0x1FFF1FFF) +#define MDP_HDR_HIST_ADDR_MASK (0xBF3F2F3F) +#define MDP_HDR_TILE_POS_MASK (0x1FFF1FFF) + +#endif // __MDP_REG_HDR_H__ diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_merge.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_merge.h new file mode 100644 index 000000000000..46be27e2a656 --- /dev/null +++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_merge.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MDP_REG_MERGE_H__ +#define __MDP_REG_MERGE_H__ + +#define MDP_MERGE_ENABLE (0x000) +#define MDP_MERGE_CFG_0 (0x010) +#define MDP_MERGE_CFG_4 (0x020) +#define MDP_MERGE_CFG_12 (0x040) +#define MDP_MERGE_CFG_24 (0x070) +#define MDP_MERGE_CFG_25 (0x074) + +/* MASK */ +#define MDP_MERGE_ENABLE_MASK (0xFFFFFFFF) +#define MDP_MERGE_CFG_0_MASK (0xFFFFFFFF) +#define MDP_MERGE_CFG_4_MASK (0xFFFFFFFF) +#define MDP_MERGE_CFG_12_MASK (0xFFFFFFFF) +#define MDP_MERGE_CFG_24_MASK (0xFFFFFFFF) +#define MDP_MERGE_CFG_25_MASK (0xFFFFFFFF) + +#endif //__MDP_REG_MERGE_H__ diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_ovl.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_ovl.h new file mode 100644 index 000000000000..21d2d0323293 --- /dev/null +++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_ovl.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MDP_REG_OVL_H__ +#define __MDP_REG_OVL_H__ + +#define MDP_OVL_EN (0x00c) +#define MDP_OVL_ROI_SIZE (0x020) +#define MDP_OVL_DP_CON (0x024) +#define MDP_OVL_SRC_CON (0x02c) +#define MDP_OVL_L0_CON (0x030) +#define MDP_OVL_L0_SRC_SIZE (0x038) + +/* MASK */ +#define MDP_OVL_DP_CON_MASK (0x0FFFFFFF) +#define MDP_OVL_EN_MASK (0xB07D07B1) +#define MDP_OVL_L0_CON_MASK (0xFFFFFFFF) +#define MDP_OVL_L0_SRC_SIZE_MASK (0x1FFF1FFF) +#define MDP_OVL_ROI_SIZE_MASK (0x1FFF1FFF) +#define MDP_OVL_SRC_CON_MASK (0x0000031F) + +#endif //__MDP_REG_OVL_H__ diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_pad.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_pad.h new file mode 100644 index 000000000000..0e89f1db19ed --- /dev/null +++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_pad.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MDP_REG_PAD_H__ +#define __MDP_REG_PAD_H__ + +#define MDP_PAD_CON (0x000) +#define MDP_PAD_PIC_SIZE (0x004) +#define MDP_PAD_W_SIZE (0x008) +#define MDP_PAD_H_SIZE (0x00c) + +/* MASK */ +#define MDP_PAD_CON_MASK (0x00000007) +#define MDP_PAD_PIC_SIZE_MASK (0xFFFFFFFF) +#define MDP_PAD_W_SIZE_MASK (0x1FFF1FFF) +#define MDP_PAD_H_SIZE_MASK (0x1FFF1FFF) + +#endif // __MDP_REG_PAD_H__ diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_rdma.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_rdma.h index be4065e252d3..0affb2a3b958 100644 --- a/drivers/media/platform/mediatek/mdp3/mdp_reg_rdma.h +++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_rdma.h @@ -26,6 +26,18 @@ #define MDP_RDMA_SRC_OFFSET_2 0x128 #define MDP_RDMA_SRC_OFFSET_0_P 0x148 #define MDP_RDMA_TRANSFORM_0 0x200 +#define MDP_RDMA_DMABUF_CON_0 0x240 +#define MDP_RDMA_ULTRA_TH_HIGH_CON_0 0x248 +#define MDP_RDMA_ULTRA_TH_LOW_CON_0 0x250 +#define MDP_RDMA_DMABUF_CON_1 0x258 +#define MDP_RDMA_ULTRA_TH_HIGH_CON_1 0x260 +#define MDP_RDMA_ULTRA_TH_LOW_CON_1 0x268 +#define MDP_RDMA_DMABUF_CON_2 0x270 +#define MDP_RDMA_ULTRA_TH_HIGH_CON_2 0x278 +#define MDP_RDMA_ULTRA_TH_LOW_CON_2 0x280 +#define MDP_RDMA_DMABUF_CON_3 0x288 +#define MDP_RDMA_ULTRA_TH_HIGH_CON_3 0x290 +#define MDP_RDMA_ULTRA_TH_LOW_CON_3 0x298 #define MDP_RDMA_RESV_DUMMY_0 0x2a0 #define MDP_RDMA_MON_STA_1 0x408 #define MDP_RDMA_SRC_BASE_0 0xf00 @@ -54,6 +66,18 @@ #define MDP_RDMA_SRC_OFFSET_2_MASK 0xffffffff #define MDP_RDMA_SRC_OFFSET_0_P_MASK 0xffffffff #define MDP_RDMA_TRANSFORM_0_MASK 0xff110777 +#define MDP_RDMA_DMABUF_CON_0_MASK 0x0fff00ff +#define MDP_RDMA_ULTRA_TH_HIGH_CON_0_MASK 0x3fffffff +#define MDP_RDMA_ULTRA_TH_LOW_CON_0_MASK 0x3fffffff +#define MDP_RDMA_DMABUF_CON_1_MASK 0x0f7f007f +#define MDP_RDMA_ULTRA_TH_HIGH_CON_1_MASK 0x3fffffff +#define MDP_RDMA_ULTRA_TH_LOW_CON_1_MASK 0x3fffffff +#define MDP_RDMA_DMABUF_CON_2_MASK 0x0f3f003f +#define MDP_RDMA_ULTRA_TH_HIGH_CON_2_MASK 0x3fffffff +#define MDP_RDMA_ULTRA_TH_LOW_CON_2_MASK 0x3fffffff +#define MDP_RDMA_DMABUF_CON_3_MASK 0x0f3f003f +#define MDP_RDMA_ULTRA_TH_HIGH_CON_3_MASK 0x3fffffff +#define MDP_RDMA_ULTRA_TH_LOW_CON_3_MASK 0x3fffffff #define MDP_RDMA_RESV_DUMMY_0_MASK 0xffffffff #define MDP_RDMA_MON_STA_1_MASK 0xffffffff #define MDP_RDMA_SRC_BASE_0_MASK 0xffffffff diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_rsz.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_rsz.h index 484f6d60641f..187531db8e3b 100644 --- a/drivers/media/platform/mediatek/mdp3/mdp_reg_rsz.h +++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_rsz.h @@ -20,6 +20,7 @@ #define PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET 0x02c #define PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET 0x030 #define PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET 0x034 +#define RSZ_ETC_CONTROL 0x22c /* MASK */ #define PRZ_ENABLE_MASK 0x00010001 @@ -35,5 +36,6 @@ #define PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET_MASK 0x001fffff #define PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET_MASK 0x0000ffff #define PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET_MASK 0x001fffff +#define RSZ_ETC_CONTROL_MASK 0xff770000 #endif // __MDP_REG_RSZ_H__ diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_tdshp.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_tdshp.h new file mode 100644 index 000000000000..83b5f9b432d8 --- /dev/null +++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_tdshp.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + * Author: Ping-Hsun Wu + */ + +#ifndef __MDP_REG_TDSHP_H__ +#define __MDP_REG_TDSHP_H__ + +#define MDP_HIST_CFG_00 (0x064) +#define MDP_HIST_CFG_01 (0x068) +#define MDP_TDSHP_CTRL (0x100) +#define MDP_TDSHP_CFG (0x110) +#define MDP_TDSHP_INPUT_SIZE (0x120) +#define MDP_TDSHP_OUTPUT_OFFSET (0x124) +#define MDP_TDSHP_OUTPUT_SIZE (0x128) +#define MDP_LUMA_HIST_INIT (0x200) +#define MDP_DC_TWO_D_W1_RESULT_INIT (0x260) +#define MDP_CONTOUR_HIST_INIT (0x398) + +/* MASK */ +#define MDP_HIST_CFG_00_MASK (0xFFFFFFFF) +#define MDP_HIST_CFG_01_MASK (0xFFFFFFFF) +#define MDP_LUMA_HIST_MASK (0xFFFFFFFF) +#define MDP_TDSHP_CTRL_MASK (0x07) +#define MDP_TDSHP_CFG_MASK (0x03F7) +#define MDP_TDSHP_INPUT_SIZE_MASK (0x1FFF1FFF) +#define MDP_TDSHP_OUTPUT_OFFSET_MASK (0x0FF00FF) +#define MDP_TDSHP_OUTPUT_SIZE_MASK (0x1FFF1FFF) +#define MDP_LUMA_HIST_INIT_MASK (0xFFFFFFFF) +#define MDP_DC_TWO_D_W1_RESULT_INIT_MASK (0x007FFFFF) +#define MDP_CONTOUR_HIST_INIT_MASK (0xFFFFFFFF) + +#endif // __MDP_REG_TDSHP_H__ diff --git a/drivers/media/platform/mediatek/mdp3/mdp_reg_wrot.h b/drivers/media/platform/mediatek/mdp3/mdp_reg_wrot.h index 6d3ff0e2b672..b6f016d2c29d 100644 --- a/drivers/media/platform/mediatek/mdp3/mdp_reg_wrot.h +++ b/drivers/media/platform/mediatek/mdp3/mdp_reg_wrot.h @@ -17,14 +17,18 @@ #define VIDO_STRIDE 0x030 #define VIDO_OFST_ADDR_C 0x038 #define VIDO_STRIDE_C 0x03c +#define VIDO_CTRL_2 0x048 #define VIDO_DITHER 0x054 #define VIDO_STRIDE_V 0x06c #define VIDO_OFST_ADDR_V 0x068 #define VIDO_RSV_1 0x070 +#define VIDO_DMA_PREULTRA 0x074 #define VIDO_IN_SIZE 0x078 #define VIDO_ROT_EN 0x07c #define VIDO_FIFO_TEST 0x080 #define VIDO_MAT_CTRL 0x084 +#define VIDO_SCAN_10BIT 0x0dc +#define VIDO_PENDING_ZERO 0x0e0 #define VIDO_BASE_ADDR 0xf00 #define VIDO_BASE_ADDR_C 0xf04 #define VIDO_BASE_ADDR_V 0xf08 @@ -40,14 +44,18 @@ #define VIDO_STRIDE_MASK 0x0000ffff #define VIDO_OFST_ADDR_C_MASK 0x0fffffff #define VIDO_STRIDE_C_MASK 0x0000ffff +#define VIDO_CTRL_2_MASK 0x0000000f #define VIDO_DITHER_MASK 0xff000001 #define VIDO_STRIDE_V_MASK 0x0000ffff #define VIDO_OFST_ADDR_V_MASK 0x0fffffff #define VIDO_RSV_1_MASK 0xffffffff +#define VIDO_DMA_PREULTRA_MASK 0x00ffffff #define VIDO_IN_SIZE_MASK 0x1fff1fff #define VIDO_ROT_EN_MASK 0x00000001 #define VIDO_FIFO_TEST_MASK 0x00000fff #define VIDO_MAT_CTRL_MASK 0x000000f3 +#define VIDO_SCAN_10BIT_MASK 0x0000000f +#define VIDO_PENDING_ZERO_MASK 0x07ffffff #define VIDO_BASE_ADDR_MASK 0xffffffff #define VIDO_BASE_ADDR_C_MASK 0xffffffff #define VIDO_BASE_ADDR_V_MASK 0xffffffff diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h index e89c51e1edb7..e6cbc6ab6bae 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h @@ -84,22 +84,66 @@ enum mtk_mdp_comp_id { MDP_COMP_CAMIN, /* 9 */ MDP_COMP_CAMIN2, /* 10 */ MDP_COMP_RDMA0, /* 11 */ - MDP_COMP_AAL0, /* 12 */ - MDP_COMP_CCORR0, /* 13 */ - MDP_COMP_RSZ0, /* 14 */ - MDP_COMP_RSZ1, /* 15 */ - MDP_COMP_TDSHP0, /* 16 */ - MDP_COMP_COLOR0, /* 17 */ - MDP_COMP_PATH0_SOUT, /* 18 */ - MDP_COMP_PATH1_SOUT, /* 19 */ - MDP_COMP_WROT0, /* 20 */ - MDP_COMP_WDMA, /* 21 */ - - /* Dummy Engine */ - MDP_COMP_RDMA1, /* 22 */ - MDP_COMP_RSZ2, /* 23 */ - MDP_COMP_TDSHP1, /* 24 */ - MDP_COMP_WROT1, /* 25 */ + MDP_COMP_RDMA1, /* 12 */ + MDP_COMP_RDMA2, /* 13 */ + MDP_COMP_RDMA3, /* 14 */ + MDP_COMP_AAL0, /* 15 */ + MDP_COMP_AAL1, /* 16 */ + MDP_COMP_AAL2, /* 17 */ + MDP_COMP_AAL3, /* 18 */ + MDP_COMP_CCORR0, /* 19 */ + MDP_COMP_RSZ0, /* 20 */ + MDP_COMP_RSZ1, /* 21 */ + MDP_COMP_RSZ2, /* 22 */ + MDP_COMP_RSZ3, /* 23 */ + MDP_COMP_TDSHP0, /* 24 */ + MDP_COMP_TDSHP1, /* 25 */ + MDP_COMP_TDSHP2, /* 26 */ + MDP_COMP_TDSHP3, /* 27 */ + MDP_COMP_COLOR0, /* 28 */ + MDP_COMP_COLOR1, /* 29 */ + MDP_COMP_COLOR2, /* 30 */ + MDP_COMP_COLOR3, /* 31 */ + MDP_COMP_PATH0_SOUT, /* 32 */ + MDP_COMP_PATH1_SOUT, /* 33 */ + MDP_COMP_WROT0, /* 34 */ + MDP_COMP_WROT1, /* 35 */ + MDP_COMP_WROT2, /* 36 */ + MDP_COMP_WROT3, /* 37 */ + MDP_COMP_WDMA, /* 38 */ + MDP_COMP_SPLIT, /* 39 */ + MDP_COMP_SPLIT2, /* 40 */ + MDP_COMP_STITCH, /* 41 */ + MDP_COMP_FG0, /* 42 */ + MDP_COMP_FG1, /* 43 */ + MDP_COMP_FG2, /* 44 */ + MDP_COMP_FG3, /* 45 */ + MDP_COMP_TO_SVPP2MOUT, /* 46 */ + MDP_COMP_TO_SVPP3MOUT, /* 47 */ + MDP_COMP_TO_WARP0MOUT, /* 48 */ + MDP_COMP_TO_WARP1MOUT, /* 49 */ + MDP_COMP_VPP0_SOUT, /* 50 */ + MDP_COMP_VPP1_SOUT, /* 51 */ + MDP_COMP_PQ0_SOUT, /* 52 */ + MDP_COMP_PQ1_SOUT, /* 53 */ + MDP_COMP_HDR0, /* 54 */ + MDP_COMP_HDR1, /* 55 */ + MDP_COMP_HDR2, /* 56 */ + MDP_COMP_HDR3, /* 57 */ + MDP_COMP_OVL0, /* 58 */ + MDP_COMP_OVL1, /* 59 */ + MDP_COMP_PAD0, /* 60 */ + MDP_COMP_PAD1, /* 61 */ + MDP_COMP_PAD2, /* 62 */ + MDP_COMP_PAD3, /* 63 */ + MDP_COMP_TCC0, /* 64 */ + MDP_COMP_TCC1, /* 65 */ + MDP_COMP_MERGE2, /* 66 */ + MDP_COMP_MERGE3, /* 67 */ + MDP_COMP_VDO0DL0, /* 68 */ + MDP_COMP_VDO1DL0, /* 69 */ + MDP_COMP_VDO0DL1, /* 70 */ + MDP_COMP_VDO1DL1, /* 71 */ MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */ }; @@ -117,12 +161,21 @@ enum mdp_comp_type { MDP_COMP_TYPE_COLOR, MDP_COMP_TYPE_DRE, MDP_COMP_TYPE_CCORR, + MDP_COMP_TYPE_AAL, + MDP_COMP_TYPE_TCC, MDP_COMP_TYPE_HDR, + MDP_COMP_TYPE_SPLIT, + MDP_COMP_TYPE_STITCH, + MDP_COMP_TYPE_FG, + MDP_COMP_TYPE_OVL, + MDP_COMP_TYPE_PAD, + MDP_COMP_TYPE_MERGE, MDP_COMP_TYPE_IMGI, MDP_COMP_TYPE_WPEI, MDP_COMP_TYPE_EXTO, /* External path */ MDP_COMP_TYPE_DL_PATH, /* Direct-link path */ + MDP_COMP_TYPE_DUMMY, MDP_COMP_TYPE_COUNT /* ALWAYS keep at the end */ }; From patchwork Wed Dec 20 10:18:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 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(172.21.101.193) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 20 Dec 2023 18:18:39 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 20 Dec 2023 18:18:39 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , Moudy Ho Subject: [PATCH v9 05/12] media: platform: mtk-mdp3: add checks for dummy components Date: Wed, 20 Dec 2023 18:18:31 +0800 Message-ID: <20231220101838.21510-6-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231220101838.21510-1-moudy.ho@mediatek.com> References: <20231220101838.21510-1-moudy.ho@mediatek.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--3.872600-8.000000 X-TMASE-MatchedRID: wjXr8BNNQ6gBiF1BcicujnV895e/Bd2J1KoSW5Ji1Xv/evmlVf9xZpeS PuHyHNrhlTJXKqh1ne2tsViygrLz2i2W7Y+Npd9R4pdq9sdj8LXbKTxp3+WtIF4ZlrnygRdkH+9 NxCXWsGghV3ms47WK7+B+gRoSa3oDFGDwHFCuATSWLCkl1lq7B5FLUnnvueyBEB/Asc4oaYEOgZ RjdFiqzQQyWbFmlWkxJAM20RFs/ZvVFtf7bVfns3TnOygHVQpOF7+vaWTP+FMD68pdUls5ss+cJ FTrDBt4RcK0DrBkisuAMuqetGVetksDkkP3zIjq3QfwsVk0UbswamAE0joFowYTMJo9dgTIRkwE Q8Bln+DRs0WnPjdeHdJBtxJYSqVYc+OKqv5cBQz+ooybmJZW2plPG6tTzRZavoNxQ/8+qOwOAWC Aw3j1SYCE5xpCtDRTUbJFyh4XXyqYo/TPOlMB4bCh3zE4wqa8wIE77PEBbml+3BndfXUhXQ== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--3.872600-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 6430B74F991D337D0D74B4FE9483499BD92786DF81C9284614415CD961E801EF2000:8 X-MTK: N Some components act as bridges only and do not require full configuration. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno --- .../platform/mediatek/mdp3/mdp_cfg_data.c | 8 +++ .../platform/mediatek/mdp3/mtk-mdp3-cfg.h | 1 + .../platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 58 ++++++++++++++++++- .../platform/mediatek/mdp3/mtk-mdp3-comp.c | 9 ++- 4 files changed, 74 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c index fcc582292b77..fe92c0474bfa 100644 --- a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c +++ b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c @@ -451,3 +451,11 @@ enum mtk_mdp_comp_id mdp_cfg_get_id_public(struct mdp_dev *mdp_dev, s32 inner_id err_public_id: return public_id; } + +bool mdp_cfg_comp_is_dummy(struct mdp_dev *mdp_dev, s32 inner_id) +{ + enum mtk_mdp_comp_id id = mdp_cfg_get_id_public(mdp_dev, inner_id); + enum mdp_comp_type type = mdp_dev->mdp_data->comp_data[id].match.type; + + return (type == MDP_COMP_TYPE_DUMMY); +} diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cfg.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cfg.h index dee57cc4a954..dfffc72868e4 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cfg.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cfg.h @@ -16,5 +16,6 @@ enum mtk_mdp_comp_id; s32 mdp_cfg_get_id_inner(struct mdp_dev *mdp_dev, enum mtk_mdp_comp_id id); enum mtk_mdp_comp_id mdp_cfg_get_id_public(struct mdp_dev *mdp_dev, s32 id); +bool mdp_cfg_comp_is_dummy(struct mdp_dev *mdp_dev, s32 inner_id); #endif /* __MTK_MDP3_CFG_H__ */ diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c index 31930ddbc828..a81caf5f472c 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c @@ -6,6 +6,7 @@ #include #include +#include "mtk-mdp3-cfg.h" #include "mtk-mdp3-cmdq.h" #include "mtk-mdp3-comp.h" #include "mtk-mdp3-core.h" @@ -108,6 +109,12 @@ static int mdp_path_subfrm_require(const struct mdp_path *path, /* Set mutex mod */ for (index = 0; index < num_comp; index++) { + s32 inner_id = MDP_COMP_NONE; + + if (CFG_CHECK(MT8183, p_id)) + inner_id = CFG_GET(MT8183, path->config, components[index].type); + if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) + continue; ctx = &path->comps[index]; if (is_output_disabled(p_id, ctx->param, count)) continue; @@ -132,6 +139,7 @@ static int mdp_path_subfrm_run(const struct mdp_path *path, int index; u32 num_comp = 0; s32 event; + s32 inner_id = MDP_COMP_NONE; if (-1 == p->mutex_id) { dev_err(dev, "Incorrect mutex id"); @@ -144,6 +152,10 @@ static int mdp_path_subfrm_run(const struct mdp_path *path, /* Wait WROT SRAM shared to DISP RDMA */ /* Clear SOF event for each engine */ for (index = 0; index < num_comp; index++) { + if (CFG_CHECK(MT8183, p_id)) + inner_id = CFG_GET(MT8183, path->config, components[index].type); + if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) + continue; ctx = &path->comps[index]; if (is_output_disabled(p_id, ctx->param, count)) continue; @@ -158,6 +170,10 @@ static int mdp_path_subfrm_run(const struct mdp_path *path, /* Wait SOF events and clear mutex modules (optional) */ for (index = 0; index < num_comp; index++) { + if (CFG_CHECK(MT8183, p_id)) + inner_id = CFG_GET(MT8183, path->config, components[index].type); + if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) + continue; ctx = &path->comps[index]; if (is_output_disabled(p_id, ctx->param, count)) continue; @@ -183,6 +199,12 @@ static int mdp_path_ctx_init(struct mdp_dev *mdp, struct mdp_path *path) return -EINVAL; for (index = 0; index < num_comp; index++) { + s32 inner_id = MDP_COMP_NONE; + + if (CFG_CHECK(MT8183, p_id)) + inner_id = CFG_GET(MT8183, path->config, components[index].type); + if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) + continue; if (CFG_CHECK(MT8183, p_id)) param = (void *)CFG_ADDR(MT8183, path->config, components[index]); ret = mdp_comp_ctx_config(mdp, &path->comps[index], @@ -204,6 +226,7 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd, struct mdp_pipe_info pipe; int index, ret; u32 num_comp = 0; + s32 inner_id = MDP_COMP_NONE; if (CFG_CHECK(MT8183, p_id)) num_comp = CFG_GET(MT8183, path->config, num_components); @@ -223,6 +246,10 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd, } /* Config sub-frame information */ for (index = (num_comp - 1); index >= 0; index--) { + if (CFG_CHECK(MT8183, p_id)) + inner_id = CFG_GET(MT8183, path->config, components[index].type); + if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) + continue; ctx = &path->comps[index]; if (is_output_disabled(p_id, ctx->param, count)) continue; @@ -236,6 +263,10 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd, return ret; /* Wait components done */ for (index = 0; index < num_comp; index++) { + if (CFG_CHECK(MT8183, p_id)) + inner_id = CFG_GET(MT8183, path->config, components[index].type); + if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) + continue; ctx = &path->comps[index]; if (is_output_disabled(p_id, ctx->param, count)) continue; @@ -245,6 +276,10 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd, } /* Advance to the next sub-frame */ for (index = 0; index < num_comp; index++) { + if (CFG_CHECK(MT8183, p_id)) + inner_id = CFG_GET(MT8183, path->config, components[index].type); + if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) + continue; ctx = &path->comps[index]; ret = call_op(ctx, advance_subfrm, cmd, count); if (ret) @@ -268,6 +303,7 @@ static int mdp_path_config(struct mdp_dev *mdp, struct mdp_cmdq_cmd *cmd, int index, count, ret; u32 num_comp = 0; u32 num_sub = 0; + s32 inner_id = MDP_COMP_NONE; if (CFG_CHECK(MT8183, p_id)) num_comp = CFG_GET(MT8183, path->config, num_components); @@ -278,6 +314,10 @@ static int mdp_path_config(struct mdp_dev *mdp, struct mdp_cmdq_cmd *cmd, /* Config path frame */ /* Reset components */ for (index = 0; index < num_comp; index++) { + if (CFG_CHECK(MT8183, p_id)) + inner_id = CFG_GET(MT8183, path->config, components[index].type); + if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) + continue; ctx = &path->comps[index]; ret = call_op(ctx, init_comp, cmd); if (ret) @@ -289,6 +329,11 @@ static int mdp_path_config(struct mdp_dev *mdp, struct mdp_cmdq_cmd *cmd, u32 out = 0; ctx = &path->comps[index]; + if (CFG_CHECK(MT8183, p_id)) + inner_id = CFG_GET(MT8183, path->config, components[index].type); + if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) + continue; + if (CFG_CHECK(MT8183, p_id)) out = CFG_COMP(MT8183, ctx->param, outputs[0]); @@ -306,6 +351,10 @@ static int mdp_path_config(struct mdp_dev *mdp, struct mdp_cmdq_cmd *cmd, } /* Post processing information */ for (index = 0; index < num_comp; index++) { + if (CFG_CHECK(MT8183, p_id)) + inner_id = CFG_GET(MT8183, path->config, components[index].type); + if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) + continue; ctx = &path->comps[index]; ret = call_op(ctx, post_process, cmd); if (ret) @@ -508,9 +557,16 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) } cmdq_pkt_finalize(&cmd->pkt); - for (i = 0; i < num_comp; i++) + for (i = 0; i < num_comp; i++) { + s32 inner_id = MDP_COMP_NONE; + + if (CFG_CHECK(MT8183, p_id)) + inner_id = CFG_GET(MT8183, path->config, components[i].type); + if (mdp_cfg_comp_is_dummy(mdp, inner_id)) + continue; memcpy(&comps[i], path->comps[i].comp, sizeof(struct mdp_comp)); + } mdp->cmdq_clt->client.rx_callback = mdp_handle_cmdq_callback; cmd->mdp = mdp; diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c index 575c8d52acd1..93df2e013438 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c @@ -853,6 +853,9 @@ int mdp_comp_clocks_on(struct device *dev, struct mdp_comp *comps, int num) int i, ret; for (i = 0; i < num; i++) { + /* Bypass the dummy component*/ + if (!comps[i].mdp_dev) + continue; ret = mdp_comp_clock_on(dev, &comps[i]); if (ret) return ret; @@ -865,8 +868,12 @@ void mdp_comp_clocks_off(struct device *dev, struct mdp_comp *comps, int num) { int i; - for (i = 0; i < num; i++) + for (i = 0; i < num; i++) { + /* Bypass the dummy component*/ + if (!comps[i].mdp_dev) + continue; mdp_comp_clock_off(dev, &comps[i]); + } } static int mdp_get_subsys_id(struct mdp_dev *mdp, struct device *dev, From patchwork Wed Dec 20 10:18:32 2023 Content-Type: text/plain; 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Wed, 20 Dec 2023 18:18:39 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 20 Dec 2023 18:18:39 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , Moudy Ho Subject: [PATCH v9 06/12] media: platform: mtk-mdp3: avoid multiple driver registrations Date: Wed, 20 Dec 2023 18:18:32 +0800 Message-ID: <20231220101838.21510-7-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231220101838.21510-1-moudy.ho@mediatek.com> References: <20231220101838.21510-1-moudy.ho@mediatek.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N The amount of MDP3 driver probes is determined by the registered clocks of MMSYS. Since MT8195 MDP3 utilizes VPPSYS0 and VPPSYS1, it's necessary to prevent multiple driver registrations. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno --- drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c | 1 + drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c | 8 ++++++++ drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h | 1 + 3 files changed, 10 insertions(+) diff --git a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c index fe92c0474bfa..6f77c33074ec 100644 --- a/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c +++ b/drivers/media/platform/mediatek/mdp3/mdp_cfg_data.c @@ -410,6 +410,7 @@ static const struct mdp_pipe_info mt8183_pipe_info[] = { const struct mtk_mdp_driver_data mt8183_mdp_driver_data = { .mdp_plat_id = MT8183, + .mdp_con_res = 0x14001000, .mdp_probe_infra = mt8183_mdp_probe_infra, .mdp_cfg = &mt8183_plat_cfg, .mdp_mutex_table_idx = mt8183_mutex_idx, diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c index 4802b20d7f20..6ddb5e075f5d 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c @@ -211,6 +211,7 @@ static int mdp_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct mdp_dev *mdp; struct platform_device *mm_pdev; + struct resource *res; int ret, i, mutex_id; mdp = kzalloc(sizeof(*mdp), GFP_KERNEL); @@ -222,6 +223,12 @@ static int mdp_probe(struct platform_device *pdev) mdp->pdev = pdev; mdp->mdp_data = of_device_get_match_data(&pdev->dev); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (res->start != mdp->mdp_data->mdp_con_res) { + platform_set_drvdata(pdev, mdp); + goto success_return; + } + ret = mdp_mm_subsys_deploy(mdp, MDP_INFRA_MMSYS); if (ret) goto err_destroy_device; @@ -311,6 +318,7 @@ static int mdp_probe(struct platform_device *pdev) goto err_unregister_device; } +success_return: dev_dbg(dev, "mdp-%d registered successfully\n", pdev->id); return 0; diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h index ece6509666fd..22d1b17ef2fc 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h @@ -71,6 +71,7 @@ enum mdp_pipe_id { struct mtk_mdp_driver_data { const int mdp_plat_id; + const resource_size_t mdp_con_res; const struct of_device_id *mdp_probe_infra; const struct mdp_platform_config *mdp_cfg; const u32 *mdp_mutex_table_idx; From patchwork Wed Dec 20 10:18:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 756753 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 439BF2031D; Wed, 20 Dec 2023 10:18:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="qHDUzL5/" X-UUID: 259193f09f2111eea5db2bebc7c28f94-20231220 DKIM-Signature: v=1; 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Wed, 20 Dec 2023 18:18:40 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 20 Dec 2023 18:18:40 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 20 Dec 2023 18:18:40 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , Moudy Ho Subject: [PATCH v9 08/12] media: platform: mtk-mdp3: add support for blending multiple components Date: Wed, 20 Dec 2023 18:18:34 +0800 Message-ID: <20231220101838.21510-9-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231220101838.21510-1-moudy.ho@mediatek.com> References: <20231220101838.21510-1-moudy.ho@mediatek.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--2.879000-8.000000 X-TMASE-MatchedRID: KlFhDc9v5J5ILSVPxvZJcHV895e/Bd2J1KoSW5Ji1Xv/evmlVf9xZpeS PuHyHNrhlTJXKqh1ne29cOdjc/43len2wHlv5vGudXu122+iJtoEa8g1x8eqF08vg1FXaj1omPw bEvJgAefCFUdoPtcptMfW2dzExL8C/16F1o/rJO7hG1IOMb7PsH0tCKdnhB58I/9UW5M5dRN3A3 6JhZ4tNfcUt5lc1lLgjMejjvPkBr7EKputfZBfQMUedzTwMFPo5ATKJjWFuPBd9A+8AE1s3zMr+ lwPT/UeRAKRId7FA5h8TTcKUOgXlBcaD2m2fFe6RBRiZYZplB95lSmbrC6fdtr/To2FgNrjDLMI OOVTHz2nbLeYgH6K31Zca9RSYo/b X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--2.879000-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 09D00D7E8EFE7674FAFAE6BB8D6E4A00D9443F2C780E5841E18C2F853C72CA532000:8 X-MTK: N Certain chips can combine several components to form complex virtual units with advanced functions. These components require simultaneous configuration of their MODs and clocks. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno --- .../platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 10 ++++++- .../platform/mediatek/mdp3/mtk-mdp3-comp.c | 29 +++++++++++++++++-- .../platform/mediatek/mdp3/mtk-mdp3-comp.h | 7 +++++ 3 files changed, 43 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c index a81caf5f472c..f0c5f5abeb23 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c @@ -110,17 +110,25 @@ static int mdp_path_subfrm_require(const struct mdp_path *path, /* Set mutex mod */ for (index = 0; index < num_comp; index++) { s32 inner_id = MDP_COMP_NONE; + const u32 *mutex_idx; + const struct mdp_comp_blend *b; if (CFG_CHECK(MT8183, p_id)) inner_id = CFG_GET(MT8183, path->config, components[index].type); if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) continue; + ctx = &path->comps[index]; if (is_output_disabled(p_id, ctx->param, count)) continue; + + mutex_idx = data->mdp_mutex_table_idx; id = ctx->comp->public_id; - mtk_mutex_write_mod(mutex, data->mdp_mutex_table_idx[id], false); + mtk_mutex_write_mod(mutex, mutex_idx[id], false); + b = &data->comp_data[id].blend; + if (b && b->aid_mod) + mtk_mutex_write_mod(mutex, mutex_idx[b->b_id], false); } mtk_mutex_write_sof(mutex, MUTEX_SOF_IDX_SINGLE_MODE); diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c index ed6092e1666f..e97630b7867c 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c @@ -864,12 +864,26 @@ int mdp_comp_clocks_on(struct device *dev, struct mdp_comp *comps, int num) int i, ret; for (i = 0; i < num; i++) { + struct mdp_dev *m = comps[i].mdp_dev; + enum mtk_mdp_comp_id id; + const struct mdp_comp_blend *b; + /* Bypass the dummy component*/ - if (!comps[i].mdp_dev) + if (!m) continue; + ret = mdp_comp_clock_on(dev, &comps[i]); if (ret) return ret; + + id = comps[i].public_id; + b = &m->mdp_data->comp_data[id].blend; + + if (b && b->aid_clk) { + ret = mdp_comp_clock_on(dev, m->comp[b->b_id]); + if (ret) + return ret; + } } return 0; @@ -880,10 +894,21 @@ void mdp_comp_clocks_off(struct device *dev, struct mdp_comp *comps, int num) int i; for (i = 0; i < num; i++) { + struct mdp_dev *m = comps[i].mdp_dev; + enum mtk_mdp_comp_id id; + const struct mdp_comp_blend *b; + /* Bypass the dummy component*/ - if (!comps[i].mdp_dev) + if (!m) continue; + mdp_comp_clock_off(dev, &comps[i]); + + id = comps[i].public_id; + b = &m->mdp_data->comp_data[id].blend; + + if (b && b->aid_clk) + mdp_comp_clock_off(dev, m->comp[b->b_id]); } } diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h index e6cbc6ab6bae..3e5d2da1c807 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h @@ -201,9 +201,16 @@ struct mdp_comp_info { u32 dts_reg_ofst; }; +struct mdp_comp_blend { + enum mtk_mdp_comp_id b_id; + bool aid_mod; + bool aid_clk; +}; + struct mdp_comp_data { struct mdp_comp_match match; struct mdp_comp_info info; + struct mdp_comp_blend blend; }; struct mdp_comp_ops; From patchwork Wed Dec 20 10:18:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 756749 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4481D21112; Wed, 20 Dec 2023 10:18:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="CguI752+" X-UUID: 261f0a969f2111eea5db2bebc7c28f94-20231220 DKIM-Signature: v=1; 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Wed, 20 Dec 2023 18:18:41 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 20 Dec 2023 18:18:40 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 20 Dec 2023 18:18:40 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , Moudy Ho Subject: [PATCH v9 11/12] media: platform: mtk-mdp3: add mt8195 MDP3 component settings Date: Wed, 20 Dec 2023 18:18:37 +0800 Message-ID: <20231220101838.21510-12-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231220101838.21510-1-moudy.ho@mediatek.com> References: <20231220101838.21510-1-moudy.ho@mediatek.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Extend the component settings used in MT8195 MDP3. Additionally, it is crucial to read all component settings in a specific manner to ensure that shared memory data structure lengths are aligned across different platforms. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno --- .../platform/mediatek/mdp3/mtk-mdp3-cmdq.c | 57 ++ .../platform/mediatek/mdp3/mtk-mdp3-comp.c | 798 +++++++++++++++++- 2 files changed, 851 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c index f0c5f5abeb23..8114c288da9c 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c @@ -40,6 +40,10 @@ static bool is_output_disabled(int p_id, const struct img_compparam *param, u32 num = CFG_COMP(MT8183, param, num_subfrms); dis_output = CFG_COMP(MT8183, param, frame.output_disable); dis_tile = CFG_COMP(MT8183, param, frame.output_disable); + } else if (CFG_CHECK(MT8195, p_id)) { + num = CFG_COMP(MT8195, param, num_subfrms); + dis_output = CFG_COMP(MT8195, param, frame.output_disable); + dis_tile = CFG_COMP(MT8195, param, frame.output_disable); } return (count < num) ? (dis_output || dis_tile) : true; @@ -101,6 +105,8 @@ static int mdp_path_subfrm_require(const struct mdp_path *path, if (CFG_CHECK(MT8183, p_id)) num_comp = CFG_GET(MT8183, path->config, num_components); + else if (CFG_CHECK(MT8195, p_id)) + num_comp = CFG_GET(MT8195, path->config, num_components); /* Decide which mutex to use based on the current pipeline */ index = __get_pipe(path->mdp_dev, path->comps[0].comp->public_id); @@ -115,6 +121,9 @@ static int mdp_path_subfrm_require(const struct mdp_path *path, if (CFG_CHECK(MT8183, p_id)) inner_id = CFG_GET(MT8183, path->config, components[index].type); + else if (CFG_CHECK(MT8195, p_id)) + inner_id = CFG_GET(MT8195, path->config, components[index].type); + if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) continue; @@ -156,12 +165,17 @@ static int mdp_path_subfrm_run(const struct mdp_path *path, if (CFG_CHECK(MT8183, p_id)) num_comp = CFG_GET(MT8183, path->config, num_components); + else if (CFG_CHECK(MT8195, p_id)) + num_comp = CFG_GET(MT8195, path->config, num_components); /* Wait WROT SRAM shared to DISP RDMA */ /* Clear SOF event for each engine */ for (index = 0; index < num_comp; index++) { if (CFG_CHECK(MT8183, p_id)) inner_id = CFG_GET(MT8183, path->config, components[index].type); + else if (CFG_CHECK(MT8195, p_id)) + inner_id = CFG_GET(MT8195, path->config, components[index].type); + if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) continue; ctx = &path->comps[index]; @@ -180,6 +194,9 @@ static int mdp_path_subfrm_run(const struct mdp_path *path, for (index = 0; index < num_comp; index++) { if (CFG_CHECK(MT8183, p_id)) inner_id = CFG_GET(MT8183, path->config, components[index].type); + else if (CFG_CHECK(MT8195, p_id)) + inner_id = CFG_GET(MT8195, path->config, components[index].type); + if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) continue; ctx = &path->comps[index]; @@ -202,6 +219,8 @@ static int mdp_path_ctx_init(struct mdp_dev *mdp, struct mdp_path *path) if (CFG_CHECK(MT8183, p_id)) num_comp = CFG_GET(MT8183, path->config, num_components); + else if (CFG_CHECK(MT8195, p_id)) + num_comp = CFG_GET(MT8195, path->config, num_components); if (num_comp < 1) return -EINVAL; @@ -211,10 +230,15 @@ static int mdp_path_ctx_init(struct mdp_dev *mdp, struct mdp_path *path) if (CFG_CHECK(MT8183, p_id)) inner_id = CFG_GET(MT8183, path->config, components[index].type); + else if (CFG_CHECK(MT8195, p_id)) + inner_id = CFG_GET(MT8195, path->config, components[index].type); + if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) continue; if (CFG_CHECK(MT8183, p_id)) param = (void *)CFG_ADDR(MT8183, path->config, components[index]); + else if (CFG_CHECK(MT8195, p_id)) + param = (void *)CFG_ADDR(MT8195, path->config, components[index]); ret = mdp_comp_ctx_config(mdp, &path->comps[index], param, path->param); if (ret) @@ -238,9 +262,13 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd, if (CFG_CHECK(MT8183, p_id)) num_comp = CFG_GET(MT8183, path->config, num_components); + else if (CFG_CHECK(MT8195, p_id)) + num_comp = CFG_GET(MT8195, path->config, num_components); if (CFG_CHECK(MT8183, p_id)) ctrl = CFG_ADDR(MT8183, path->config, ctrls[count]); + else if (CFG_CHECK(MT8195, p_id)) + ctrl = CFG_ADDR(MT8195, path->config, ctrls[count]); /* Acquire components */ ret = mdp_path_subfrm_require(path, cmd, &pipe, count); @@ -256,6 +284,9 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd, for (index = (num_comp - 1); index >= 0; index--) { if (CFG_CHECK(MT8183, p_id)) inner_id = CFG_GET(MT8183, path->config, components[index].type); + else if (CFG_CHECK(MT8195, p_id)) + inner_id = CFG_GET(MT8195, path->config, components[index].type); + if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) continue; ctx = &path->comps[index]; @@ -273,6 +304,9 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd, for (index = 0; index < num_comp; index++) { if (CFG_CHECK(MT8183, p_id)) inner_id = CFG_GET(MT8183, path->config, components[index].type); + else if (CFG_CHECK(MT8195, p_id)) + inner_id = CFG_GET(MT8195, path->config, components[index].type); + if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) continue; ctx = &path->comps[index]; @@ -286,6 +320,9 @@ static int mdp_path_config_subfrm(struct mdp_cmdq_cmd *cmd, for (index = 0; index < num_comp; index++) { if (CFG_CHECK(MT8183, p_id)) inner_id = CFG_GET(MT8183, path->config, components[index].type); + else if (CFG_CHECK(MT8195, p_id)) + inner_id = CFG_GET(MT8195, path->config, components[index].type); + if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) continue; ctx = &path->comps[index]; @@ -315,15 +352,22 @@ static int mdp_path_config(struct mdp_dev *mdp, struct mdp_cmdq_cmd *cmd, if (CFG_CHECK(MT8183, p_id)) num_comp = CFG_GET(MT8183, path->config, num_components); + else if (CFG_CHECK(MT8195, p_id)) + num_comp = CFG_GET(MT8195, path->config, num_components); if (CFG_CHECK(MT8183, p_id)) num_sub = CFG_GET(MT8183, path->config, num_subfrms); + else if (CFG_CHECK(MT8195, p_id)) + num_sub = CFG_GET(MT8195, path->config, num_subfrms); /* Config path frame */ /* Reset components */ for (index = 0; index < num_comp; index++) { if (CFG_CHECK(MT8183, p_id)) inner_id = CFG_GET(MT8183, path->config, components[index].type); + else if (CFG_CHECK(MT8195, p_id)) + inner_id = CFG_GET(MT8195, path->config, components[index].type); + if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) continue; ctx = &path->comps[index]; @@ -339,11 +383,16 @@ static int mdp_path_config(struct mdp_dev *mdp, struct mdp_cmdq_cmd *cmd, ctx = &path->comps[index]; if (CFG_CHECK(MT8183, p_id)) inner_id = CFG_GET(MT8183, path->config, components[index].type); + else if (CFG_CHECK(MT8195, p_id)) + inner_id = CFG_GET(MT8195, path->config, components[index].type); + if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) continue; if (CFG_CHECK(MT8183, p_id)) out = CFG_COMP(MT8183, ctx->param, outputs[0]); + else if (CFG_CHECK(MT8195, p_id)) + out = CFG_COMP(MT8195, ctx->param, outputs[0]); compose = path->composes[out]; ret = call_op(ctx, config_frame, cmd, compose); @@ -361,6 +410,9 @@ static int mdp_path_config(struct mdp_dev *mdp, struct mdp_cmdq_cmd *cmd, for (index = 0; index < num_comp; index++) { if (CFG_CHECK(MT8183, p_id)) inner_id = CFG_GET(MT8183, path->config, components[index].type); + else if (CFG_CHECK(MT8195, p_id)) + inner_id = CFG_GET(MT8195, path->config, components[index].type); + if (mdp_cfg_comp_is_dummy(path->mdp_dev, inner_id)) continue; ctx = &path->comps[index]; @@ -515,6 +567,8 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) if (CFG_CHECK(MT8183, p_id)) { num_comp = CFG_GET(MT8183, param->config, num_components); + } else if (CFG_CHECK(MT8195, p_id)) { + num_comp = CFG_GET(MT8195, param->config, num_components); } else { ret = -EINVAL; goto err_destroy_pkt; @@ -570,6 +624,9 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param) if (CFG_CHECK(MT8183, p_id)) inner_id = CFG_GET(MT8183, path->config, components[i].type); + else if (CFG_CHECK(MT8195, p_id)) + inner_id = CFG_GET(MT8195, path->config, components[i].type); + if (mdp_cfg_comp_is_dummy(mdp, inner_id)) continue; memcpy(&comps[i], path->comps[i].comp, diff --git a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c index 600fec7d2f7f..8f62fb167156 100644 --- a/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c +++ b/drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c @@ -13,11 +13,19 @@ #include "mtk-mdp3-core.h" #include "mtk-mdp3-regs.h" -#include "mdp_reg_rdma.h" +#include "mdp_reg_aal.h" #include "mdp_reg_ccorr.h" +#include "mdp_reg_color.h" +#include "mdp_reg_fg.h" +#include "mdp_reg_hdr.h" +#include "mdp_reg_merge.h" +#include "mdp_reg_ovl.h" +#include "mdp_reg_pad.h" +#include "mdp_reg_rdma.h" #include "mdp_reg_rsz.h" -#include "mdp_reg_wrot.h" +#include "mdp_reg_tdshp.h" #include "mdp_reg_wdma.h" +#include "mdp_reg_wrot.h" static u32 mdp_comp_alias_id[MDP_COMP_TYPE_COUNT]; static int p_id; @@ -85,6 +93,7 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx, bool en_ufo = MDP_COLOR_IS_UFP(colorformat); phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; + u32 rdma_con_mask = 0; u32 reg = 0; if (mdp_cfg && mdp_cfg->rdma_support_10bit) { @@ -105,6 +114,8 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx, /* Setup source frame info */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.src_ctrl); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.src_ctrl); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_CON, reg, 0x03C8FE0F); @@ -113,69 +124,163 @@ static int config_rdma_frame(struct mdp_comp_ctx *ctx, /* Setup source buffer base */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.ufo_dec_y); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.ufo_dec_y); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_UFO_DEC_LENGTH_BASE_Y, reg, 0xFFFFFFFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.ufo_dec_c); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.ufo_dec_c); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_UFO_DEC_LENGTH_BASE_C, reg, 0xFFFFFFFF); + /* Set 10bit source frame pitch */ if (block10bit) { if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.mf_bkgd_in_pxl); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.mf_bkgd_in_pxl); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_BKGD_SIZE_IN_PXL, reg, 0x001FFFFF); } } - if (CFG_CHECK(MT8183, p_id)) + if (CFG_CHECK(MT8183, p_id)) { reg = CFG_COMP(MT8183, ctx->param, rdma.control); + rdma_con_mask = 0x1110; + } else if (CFG_CHECK(MT8195, p_id)) { + reg = CFG_COMP(MT8195, ctx->param, rdma.control); + rdma_con_mask = 0x1130; + } MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_CON, reg, - 0x1110); + rdma_con_mask); + /* Setup source buffer base */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.iova[0]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.iova[0]); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_0, reg, 0xFFFFFFFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.iova[1]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.iova[1]); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_1, reg, 0xFFFFFFFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.iova[2]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.iova[2]); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_BASE_2, reg, 0xFFFFFFFF); + /* Setup source buffer end */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[0]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.iova_end[0]); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_0, reg, 0xFFFFFFFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[1]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.iova_end[1]); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_1, reg, 0xFFFFFFFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[2]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.iova_end[2]); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_END_2, reg, 0xFFFFFFFF); + /* Setup source frame pitch */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.mf_bkgd); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.mf_bkgd); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_BKGD_SIZE_IN_BYTE, reg, 0x001FFFFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.sf_bkgd); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.sf_bkgd); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SF_BKGD_SIZE_IN_BYTE, reg, 0x001FFFFF); + /* Setup color transform */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.transform); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.transform); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_TRANSFORM_0, reg, 0x0F110000); + if (!mdp_cfg || !mdp_cfg->rdma_esl_setting) + goto rdma_config_done; + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con0); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_0, + reg, 0x0FFF00FF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_high_con0); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_0, + reg, 0x3FFFFFFF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_low_con0); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_0, + reg, 0x3FFFFFFF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con1); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_1, + reg, 0x0F7F007F); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_high_con1); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_1, + reg, 0x3FFFFFFF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_low_con1); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_1, + reg, 0x3FFFFFFF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con2); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_2, + reg, 0x0F3F003F); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_high_con2); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_HIGH_CON_2, + reg, 0x3FFFFFFF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.ultra_th_low_con2); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_ULTRA_TH_LOW_CON_2, + reg, 0x3FFFFFFF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.dmabuf_con3); + MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_DMABUF_CON_3, + reg, 0x0F3F003F); + +rdma_config_done: return 0; } @@ -197,6 +302,8 @@ static int config_rdma_subfrm(struct mdp_comp_ctx *ctx, /* Set Y pixel offset */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[0]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset[0]); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_0, reg, 0xFFFFFFFF); @@ -205,6 +312,8 @@ static int config_rdma_subfrm(struct mdp_comp_ctx *ctx, if (mdp_cfg->rdma_support_10bit && block10bit && en_ufo) { if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset_0_p); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset_0_p); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_0_P, reg, 0xFFFFFFFF); @@ -214,32 +323,49 @@ static int config_rdma_subfrm(struct mdp_comp_ctx *ctx, /* Set U pixel offset */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[1]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset[1]); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_1, reg, 0xFFFFFFFF); + /* Set V pixel offset */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[2]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].offset[2]); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_SRC_OFFSET_2, reg, 0xFFFFFFFF); + /* Set source size */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].src); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].src); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_SRC_SIZE, reg, 0x1FFF1FFF); + /* Set target size */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].clip); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].clip); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_CLIP_SIZE, reg, 0x1FFF1FFF); + /* Set crop offset */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].clip_ofst); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rdma.subfrms[index].clip_ofst); MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_MF_OFFSET_1, reg, 0x003F001F); if (CFG_CHECK(MT8183, p_id)) { csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right); + } else if (CFG_CHECK(MT8195, p_id)) { + csf_l = CFG_COMP(MT8195, ctx->param, subfrms[index].in.left); + csf_r = CFG_COMP(MT8195, ctx->param, subfrms[index].in.right); } if (mdp_cfg && mdp_cfg->rdma_upsample_repeat_only) if ((csf_r - csf_l + 1) > 320) @@ -289,6 +415,14 @@ static int init_rsz(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x0, BIT(16)); /* Enable RSZ */ MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, BIT(0), BIT(0)); + + if (CFG_CHECK(MT8195, p_id)) { + struct device *dev; + + dev = ctx->comp->mdp_dev->mm_subsys[MDP_MM_SUBSYS_1].mmsys; + mtk_mmsys_vpp_rsz_dcm_config(dev, true, NULL); + } + return 0; } @@ -296,13 +430,19 @@ static int config_rsz_frame(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd, const struct v4l2_rect *compose) { + const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx); phys_addr_t base = ctx->comp->reg_base; u8 subsys_id = ctx->comp->subsys_id; bool bypass = FALSE; u32 reg = 0; + if (mdp_cfg && mdp_cfg->rsz_etc_control) + MM_REG_WRITE(cmd, subsys_id, base, RSZ_ETC_CONTROL, 0x0, 0xFFFFFFFF); + if (CFG_CHECK(MT8183, p_id)) bypass = CFG_COMP(MT8183, ctx->param, frame.bypass); + else if (CFG_CHECK(MT8195, p_id)) + bypass = CFG_COMP(MT8195, ctx->param, frame.bypass); if (bypass) { /* Disable RSZ */ @@ -312,20 +452,32 @@ static int config_rsz_frame(struct mdp_comp_ctx *ctx, if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rsz.control1); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rsz.control1); MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_1, reg, 0x03FFFDF3); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rsz.control2); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rsz.control2); MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_2, reg, 0x0FFFC290); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rsz.coeff_step_x); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rsz.coeff_step_x); MM_REG_WRITE(cmd, subsys_id, base, PRZ_HORIZONTAL_COEFF_STEP, reg, 0x007FFFFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rsz.coeff_step_y); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rsz.coeff_step_y); MM_REG_WRITE(cmd, subsys_id, base, PRZ_VERTICAL_COEFF_STEP, reg, 0x007FFFFF); + return 0; } @@ -337,19 +489,28 @@ static int config_rsz_subfrm(struct mdp_comp_ctx *ctx, u8 subsys_id = ctx->comp->subsys_id; u32 csf_l = 0, csf_r = 0; u32 reg = 0; + u32 id; if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].control2); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].control2); MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_2, reg, 0x00003800); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].src); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].src); MM_REG_WRITE(cmd, subsys_id, base, PRZ_INPUT_IMAGE, reg, 0xFFFFFFFF); if (CFG_CHECK(MT8183, p_id)) { csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right); + } else if (CFG_CHECK(MT8195, p_id)) { + csf_l = CFG_COMP(MT8195, ctx->param, subfrms[index].in.left); + csf_r = CFG_COMP(MT8195, ctx->param, subfrms[index].in.right); } if (mdp_cfg && mdp_cfg->rsz_disable_dcm_small_sample) if ((csf_r - csf_l + 1) <= 16) @@ -358,37 +519,99 @@ static int config_rsz_subfrm(struct mdp_comp_ctx *ctx, if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.left); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.left); MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_HORIZONTAL_INTEGER_OFFSET, reg, 0xFFFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.left_subpix); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.left_subpix); MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_HORIZONTAL_SUBPIXEL_OFFSET, reg, 0x1FFFFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.top); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.top); MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_VERTICAL_INTEGER_OFFSET, reg, 0xFFFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.top_subpix); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, subfrms[index].luma.top_subpix); MM_REG_WRITE(cmd, subsys_id, base, PRZ_LUMA_VERTICAL_SUBPIXEL_OFFSET, reg, 0x1FFFFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, subfrms[index].chroma.left); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, subfrms[index].chroma.left); MM_REG_WRITE(cmd, subsys_id, base, PRZ_CHROMA_HORIZONTAL_INTEGER_OFFSET, reg, 0xFFFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, subfrms[index].chroma.left_subpix); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, subfrms[index].chroma.left_subpix); MM_REG_WRITE(cmd, subsys_id, base, PRZ_CHROMA_HORIZONTAL_SUBPIXEL_OFFSET, reg, 0x1FFFFF); if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].clip); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].clip); MM_REG_WRITE(cmd, subsys_id, base, PRZ_OUTPUT_IMAGE, reg, 0xFFFFFFFF); + if (CFG_CHECK(MT8195, p_id)) { + struct device *dev; + struct mdp_comp *merge; + const struct mtk_mdp_driver_data *data = ctx->comp->mdp_dev->mdp_data; + enum mtk_mdp_comp_id public_id = ctx->comp->public_id; + + switch (public_id) { + case MDP_COMP_RSZ2: + merge = ctx->comp->mdp_dev->comp[MDP_COMP_MERGE2]; + break; + case MDP_COMP_RSZ3: + merge = ctx->comp->mdp_dev->comp[MDP_COMP_MERGE3]; + break; + default: + goto rsz_subfrm_done; + } + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].rsz_switch); + + id = data->comp_data[public_id].match.alias_id; + dev = ctx->comp->mdp_dev->mm_subsys[MDP_MM_SUBSYS_1].mmsys; + mtk_mmsys_vpp_rsz_merge_config(dev, id, reg, NULL); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, rsz.subfrms[index].merge_cfg); + MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, + MDP_MERGE_CFG_0, reg, 0xFFFFFFFF); + MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, + MDP_MERGE_CFG_4, reg, 0xFFFFFFFF); + MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, + MDP_MERGE_CFG_24, reg, 0xFFFFFFFF); + MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, + MDP_MERGE_CFG_25, reg, 0xFFFFFFFF); + + /* Bypass mode */ + MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, + MDP_MERGE_CFG_12, BIT(0), 0xFFFFFFFF); + MM_REG_WRITE(cmd, merge->subsys_id, merge->reg_base, + MDP_MERGE_ENABLE, BIT(0), 0xFFFFFFFF); + } + +rsz_subfrm_done: return 0; } @@ -405,6 +628,9 @@ static int advance_rsz_subfrm(struct mdp_comp_ctx *ctx, if (CFG_CHECK(MT8183, p_id)) { csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right); + } else if (CFG_CHECK(MT8195, p_id)) { + csf_l = CFG_COMP(MT8195, ctx->param, subfrms[index].in.left); + csf_r = CFG_COMP(MT8195, ctx->param, subfrms[index].in.right); } if ((csf_r - csf_l + 1) <= 16) @@ -431,6 +657,11 @@ static int init_wrot(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) /* Reset WROT */ MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST, BIT(0), BIT(0)); MM_REG_POLL(cmd, subsys_id, base, VIDO_SOFT_RST_STAT, BIT(0), BIT(0)); + + /* Reset setting */ + if (CFG_CHECK(MT8195, p_id)) + MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL, 0x0, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST, 0x0, BIT(0)); MM_REG_POLL(cmd, subsys_id, base, VIDO_SOFT_RST_STAT, 0x0, BIT(0)); return 0; @@ -448,57 +679,118 @@ static int config_wrot_frame(struct mdp_comp_ctx *ctx, /* Write frame base address */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.iova[0]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.iova[0]); MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR, reg, 0xFFFFFFFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.iova[1]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.iova[1]); MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_C, reg, 0xFFFFFFFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.iova[2]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.iova[2]); MM_REG_WRITE(cmd, subsys_id, base, VIDO_BASE_ADDR_V, reg, 0xFFFFFFFF); + + if (mdp_cfg && mdp_cfg->wrot_support_10bit) { + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.scan_10bit); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_SCAN_10BIT, + reg, 0x0000000F); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.pending_zero); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_PENDING_ZERO, + reg, 0x04000000); + } + + if (CFG_CHECK(MT8195, p_id)) { + reg = CFG_COMP(MT8195, ctx->param, wrot.bit_number); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL_2, + reg, 0x00000007); + } + /* Write frame related registers */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.control); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.control); MM_REG_WRITE(cmd, subsys_id, base, VIDO_CTRL, reg, 0xF131510F); + + /* Write pre-ultra threshold */ + if (CFG_CHECK(MT8195, p_id)) { + reg = CFG_COMP(MT8195, ctx->param, wrot.pre_ultra); + MM_REG_WRITE(cmd, subsys_id, base, VIDO_DMA_PREULTRA, reg, + 0x00FFFFFF); + } + /* Write frame Y pitch */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.stride[0]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.stride[0]); MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE, reg, 0x0000FFFF); + /* Write frame UV pitch */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.stride[1]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.stride[1]); MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_C, reg, 0xFFFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.stride[2]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.stride[2]); MM_REG_WRITE(cmd, subsys_id, base, VIDO_STRIDE_V, reg, 0xFFFF); + /* Write matrix control */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.mat_ctrl); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.mat_ctrl); MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAT_CTRL, reg, 0xF3); /* Set the fixed ALPHA as 0xFF */ MM_REG_WRITE(cmd, subsys_id, base, VIDO_DITHER, 0xFF000000, 0xFF000000); + /* Set VIDO_EOL_SEL */ MM_REG_WRITE(cmd, subsys_id, base, VIDO_RSV_1, BIT(31), BIT(31)); + /* Set VIDO_FIFO_TEST */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.fifo_test); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.fifo_test); + if (reg != 0) MM_REG_WRITE(cmd, subsys_id, base, VIDO_FIFO_TEST, reg, 0xFFF); + /* Filter enable */ if (mdp_cfg && mdp_cfg->wrot_filter_constraint) { if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.filter); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.filter); MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, reg, 0x77); + + /* Turn off WROT DMA DCM */ + if (CFG_CHECK(MT8195, p_id)) + MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, + (0x1 << 23) + (0x1 << 20), 0x900000); } return 0; @@ -514,35 +806,54 @@ static int config_wrot_subfrm(struct mdp_comp_ctx *ctx, /* Write Y pixel offset */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[0]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].offset[0]); MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR, reg, 0x0FFFFFFF); + /* Write U pixel offset */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[1]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].offset[1]); MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR_C, reg, 0x0FFFFFFF); + /* Write V pixel offset */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[2]); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].offset[2]); MM_REG_WRITE(cmd, subsys_id, base, VIDO_OFST_ADDR_V, reg, 0x0FFFFFFF); + /* Write source size */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].src); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].src); MM_REG_WRITE(cmd, subsys_id, base, VIDO_IN_SIZE, reg, 0x1FFF1FFF); + /* Write target size */ if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].clip); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].clip); MM_REG_WRITE(cmd, subsys_id, base, VIDO_TAR_SIZE, reg, 0x1FFF1FFF); + if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].clip_ofst); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].clip_ofst); MM_REG_WRITE(cmd, subsys_id, base, VIDO_CROP_OFST, reg, 0x1FFF1FFF); if (CFG_CHECK(MT8183, p_id)) reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].main_buf); + else if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, wrot.subfrms[index].main_buf); MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, reg, 0x1FFF7F00); @@ -708,6 +1019,171 @@ static const struct mdp_comp_ops wdma_ops = { .wait_comp_event = wait_wdma_event, }; +static int reset_luma_hist(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) +{ + const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx); + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + u32 hist_num, i; + + if (!mdp_cfg) + return -EINVAL; + + hist_num = mdp_cfg->tdshp_hist_num; + + /* Reset histogram */ + for (i = 0; i <= hist_num; i++) + MM_REG_WRITE_MASK(cmd, subsys_id, base, + (MDP_LUMA_HIST_INIT + (i << 2)), + 0, 0xFFFFFFFF); + + if (mdp_cfg->tdshp_constrain) + MM_REG_WRITE(cmd, subsys_id, base, + MDP_DC_TWO_D_W1_RESULT_INIT, 0, 0xFFFFFFFF); + + if (mdp_cfg->tdshp_contour) + for (i = 0; i < hist_num; i++) + MM_REG_WRITE_MASK(cmd, subsys_id, base, + (MDP_CONTOUR_HIST_INIT + (i << 2)), + 0, 0xFFFFFFFF); + + return 0; +} + +static int init_tdshp(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_CTRL, BIT(0), BIT(0)); + /* Enable FIFO */ + MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_CFG, BIT(1), BIT(1)); + + return reset_luma_hist(ctx, cmd); +} + +static int config_tdshp_frame(struct mdp_comp_ctx *ctx, + struct mdp_cmdq_cmd *cmd, + const struct v4l2_rect *compose) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, tdshp.cfg); + MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_CFG, reg, BIT(0)); + + return 0; +} + +static int config_tdshp_subfrm(struct mdp_comp_ctx *ctx, + struct mdp_cmdq_cmd *cmd, u32 index) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].src); + MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_INPUT_SIZE, + reg, MDP_TDSHP_INPUT_SIZE_MASK); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].clip_ofst); + MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_OUTPUT_OFFSET, + reg, 0x00FF00FF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].clip); + MM_REG_WRITE(cmd, subsys_id, base, MDP_TDSHP_OUTPUT_SIZE, + reg, MDP_TDSHP_OUTPUT_SIZE_MASK); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].hist_cfg_0); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HIST_CFG_00, reg, 0xFFFFFFFF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, tdshp.subfrms[index].hist_cfg_1); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HIST_CFG_01, reg, 0xFFFFFFFF); + + return 0; +} + +static const struct mdp_comp_ops tdshp_ops = { + .get_comp_flag = get_comp_flag, + .init_comp = init_tdshp, + .config_frame = config_tdshp_frame, + .config_subfrm = config_tdshp_subfrm, +}; + +static int init_color(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + MM_REG_WRITE(cmd, subsys_id, base, + MDP_COLOR_START, 0x1, BIT(1) | BIT(0)); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_COLOR_WIN_X_MAIN, 0xFFFF0000, 0xFFFFFFFF); + MM_REG_WRITE(cmd, subsys_id, base, + MDP_COLOR_WIN_Y_MAIN, 0xFFFF0000, 0xFFFFFFFF); + + /* Reset color matrix */ + MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_CM1_EN, 0x0, BIT(0)); + MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_CM2_EN, 0x0, BIT(0)); + + /* Enable interrupt */ + MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_INTEN, 0x7, 0x7); + + MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_OUT_SEL, 0x333, 0x333); + + return 0; +} + +static int config_color_frame(struct mdp_comp_ctx *ctx, + struct mdp_cmdq_cmd *cmd, + const struct v4l2_rect *compose) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, color.start); + MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_START, + reg, MDP_COLOR_START_MASK); + + return 0; +} + +static int config_color_subfrm(struct mdp_comp_ctx *ctx, + struct mdp_cmdq_cmd *cmd, u32 index) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, color.subfrms[index].in_hsize); + MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_INTERNAL_IP_WIDTH, + reg, 0x00003FFF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, color.subfrms[index].in_vsize); + MM_REG_WRITE(cmd, subsys_id, base, MDP_COLOR_INTERNAL_IP_HEIGHT, + reg, 0x00003FFF); + + return 0; +} + +static const struct mdp_comp_ops color_ops = { + .get_comp_flag = get_comp_flag, + .init_comp = init_color, + .config_frame = config_color_frame, + .config_subfrm = config_color_subfrm, +}; + static int init_ccorr(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) { phys_addr_t base = ctx->comp->reg_base; @@ -749,12 +1225,318 @@ static const struct mdp_comp_ops ccorr_ops = { .config_subfrm = config_ccorr_subfrm, }; +static int init_aal(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + /* Always set MDP_AAL enable to 1 */ + MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_EN, BIT(0), BIT(0)); + + return 0; +} + +static int config_aal_frame(struct mdp_comp_ctx *ctx, + struct mdp_cmdq_cmd *cmd, + const struct v4l2_rect *compose) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, aal.cfg_main); + MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_CFG_MAIN, reg, BIT(7)); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, aal.cfg); + MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_CFG, reg, BIT(0)); + + return 0; +} + +static int config_aal_subfrm(struct mdp_comp_ctx *ctx, + struct mdp_cmdq_cmd *cmd, u32 index) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, aal.subfrms[index].src); + MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_SIZE, + reg, MDP_AAL_SIZE_MASK); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, aal.subfrms[index].clip_ofst); + MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_OUTPUT_OFFSET, + reg, 0x00FF00FF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, aal.subfrms[index].clip); + MM_REG_WRITE(cmd, subsys_id, base, MDP_AAL_OUTPUT_SIZE, + reg, MDP_AAL_OUTPUT_SIZE_MASK); + + return 0; +} + +static const struct mdp_comp_ops aal_ops = { + .get_comp_flag = get_comp_flag, + .init_comp = init_aal, + .config_frame = config_aal_frame, + .config_subfrm = config_aal_subfrm, +}; + +static int init_hdr(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + /* Always set MDP_HDR enable to 1 */ + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TOP, BIT(0), BIT(0)); + + return 0; +} + +static int config_hdr_frame(struct mdp_comp_ctx *ctx, + struct mdp_cmdq_cmd *cmd, + const struct v4l2_rect *compose) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, hdr.top); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TOP, reg, BIT(29) | BIT(28)); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, hdr.relay); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_RELAY, reg, BIT(0)); + + return 0; +} + +static int config_hdr_subfrm(struct mdp_comp_ctx *ctx, + struct mdp_cmdq_cmd *cmd, u32 index) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].win_size); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TILE_POS, + reg, MDP_HDR_TILE_POS_MASK); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].src); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_SIZE_0, reg, 0x1FFF1FFF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].clip_ofst0); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_SIZE_1, reg, 0x1FFF1FFF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].clip_ofst1); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_SIZE_2, reg, 0x1FFF1FFF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hist_ctrl_0); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_HIST_CTRL_0, reg, 0x00003FFF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hist_ctrl_1); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_HIST_CTRL_1, reg, 0x00003FFF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hdr_top); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_TOP, reg, BIT(6) | BIT(5)); + + /* Enable histogram */ + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, hdr.subfrms[index].hist_addr); + MM_REG_WRITE(cmd, subsys_id, base, MDP_HDR_HIST_ADDR, reg, BIT(9)); + + return 0; +} + +static const struct mdp_comp_ops hdr_ops = { + .get_comp_flag = get_comp_flag, + .init_comp = init_hdr, + .config_frame = config_hdr_frame, + .config_subfrm = config_hdr_subfrm, +}; + +static int init_fg(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TRIGGER, BIT(2), BIT(2)); + MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TRIGGER, 0x0, BIT(2)); + + return 0; +} + +static int config_fg_frame(struct mdp_comp_ctx *ctx, + struct mdp_cmdq_cmd *cmd, + const struct v4l2_rect *compose) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, fg.ctrl_0); + MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_FG_CTRL_0, reg, BIT(0)); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, fg.ck_en); + MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_FG_CK_EN, reg, 0x7); + + return 0; +} + +static int config_fg_subfrm(struct mdp_comp_ctx *ctx, + struct mdp_cmdq_cmd *cmd, u32 index) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, fg.subfrms[index].info_0); + MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TILE_INFO_0, reg, 0xFFFFFFFF); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, fg.subfrms[index].info_1); + MM_REG_WRITE(cmd, subsys_id, base, MDP_FG_TILE_INFO_1, reg, 0xFFFFFFFF); + + return 0; +} + +static const struct mdp_comp_ops fg_ops = { + .get_comp_flag = get_comp_flag, + .init_comp = init_fg, + .config_frame = config_fg_frame, + .config_subfrm = config_fg_subfrm, +}; + +static int init_ovl(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_EN, + BIT(0), MDP_OVL_EN_MASK); + + /* Set to relay mode */ + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_SRC_CON, + BIT(9), MDP_OVL_SRC_CON_MASK); + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_DP_CON, + BIT(0), MDP_OVL_DP_CON_MASK); + + return 0; +} + +static int config_ovl_frame(struct mdp_comp_ctx *ctx, + struct mdp_cmdq_cmd *cmd, + const struct v4l2_rect *compose) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, ovl.L0_con); + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_L0_CON, reg, BIT(29) | BIT(28)); + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, ovl.src_con); + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_SRC_CON, reg, BIT(0)); + + return 0; +} + +static int config_ovl_subfrm(struct mdp_comp_ctx *ctx, + struct mdp_cmdq_cmd *cmd, u32 index) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, ovl.subfrms[index].L0_src_size); + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_L0_SRC_SIZE, + reg, MDP_OVL_L0_SRC_SIZE_MASK); + + /* Setup output size */ + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, ovl.subfrms[index].roi_size); + MM_REG_WRITE(cmd, subsys_id, base, MDP_OVL_ROI_SIZE, + reg, MDP_OVL_ROI_SIZE_MASK); + + return 0; +} + +static const struct mdp_comp_ops ovl_ops = { + .get_comp_flag = get_comp_flag, + .init_comp = init_ovl, + .config_frame = config_ovl_frame, + .config_subfrm = config_ovl_subfrm, +}; + +static int init_pad(struct mdp_comp_ctx *ctx, struct mdp_cmdq_cmd *cmd) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + + MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_CON, + BIT(1), MDP_PAD_CON_MASK); + /* Reset */ + MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_W_SIZE, + 0, MDP_PAD_W_SIZE_MASK); + MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_H_SIZE, + 0, MDP_PAD_H_SIZE_MASK); + + return 0; +} + +static int config_pad_subfrm(struct mdp_comp_ctx *ctx, + struct mdp_cmdq_cmd *cmd, u32 index) +{ + phys_addr_t base = ctx->comp->reg_base; + u16 subsys_id = ctx->comp->subsys_id; + u32 reg = 0; + + if (CFG_CHECK(MT8195, p_id)) + reg = CFG_COMP(MT8195, ctx->param, pad.subfrms[index].pic_size); + MM_REG_WRITE(cmd, subsys_id, base, MDP_PAD_PIC_SIZE, + reg, MDP_PAD_PIC_SIZE_MASK); + + return 0; +} + +static const struct mdp_comp_ops pad_ops = { + .get_comp_flag = get_comp_flag, + .init_comp = init_pad, + .config_subfrm = config_pad_subfrm, +}; + static const struct mdp_comp_ops *mdp_comp_ops[MDP_COMP_TYPE_COUNT] = { [MDP_COMP_TYPE_RDMA] = &rdma_ops, [MDP_COMP_TYPE_RSZ] = &rsz_ops, [MDP_COMP_TYPE_WROT] = &wrot_ops, [MDP_COMP_TYPE_WDMA] = &wdma_ops, + [MDP_COMP_TYPE_TDSHP] = &tdshp_ops, + [MDP_COMP_TYPE_COLOR] = &color_ops, [MDP_COMP_TYPE_CCORR] = &ccorr_ops, + [MDP_COMP_TYPE_AAL] = &aal_ops, + [MDP_COMP_TYPE_HDR] = &hdr_ops, + [MDP_COMP_TYPE_FG] = &fg_ops, + [MDP_COMP_TYPE_OVL] = &ovl_ops, + [MDP_COMP_TYPE_PAD] = &pad_ops, }; static const struct of_device_id mdp_comp_dt_ids[] __maybe_unused = { @@ -1253,6 +2035,8 @@ int mdp_comp_ctx_config(struct mdp_dev *mdp, struct mdp_comp_ctx *ctx, if (CFG_CHECK(MT8183, p_id)) arg = CFG_COMP(MT8183, param, type); + else if (CFG_CHECK(MT8195, p_id)) + arg = CFG_COMP(MT8195, param, type); else return -EINVAL; public_id = mdp_cfg_get_id_public(mdp, arg); @@ -1270,16 +2054,22 @@ int mdp_comp_ctx_config(struct mdp_dev *mdp, struct mdp_comp_ctx *ctx, ctx->param = param; if (CFG_CHECK(MT8183, p_id)) arg = CFG_COMP(MT8183, param, input); + else if (CFG_CHECK(MT8195, p_id)) + arg = CFG_COMP(MT8195, param, input); else return -EINVAL; ctx->input = &frame->inputs[arg]; if (CFG_CHECK(MT8183, p_id)) idx = CFG_COMP(MT8183, param, num_outputs); + else if (CFG_CHECK(MT8195, p_id)) + idx = CFG_COMP(MT8195, param, num_outputs); else return -EINVAL; for (i = 0; i < idx; i++) { if (CFG_CHECK(MT8183, p_id)) arg = CFG_COMP(MT8183, param, outputs[i]); + else if (CFG_CHECK(MT8195, p_id)) + arg = CFG_COMP(MT8195, param, outputs[i]); else return -EINVAL; ctx->outputs[i] = &frame->outputs[arg];