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([2a01:e0a:999:a3a0:3eae:b70:f27f:7aa1]) by smtp.gmail.com with ESMTPSA id h18-20020adffd52000000b003366af9d611sm7279693wrs.22.2023.12.20.07.57.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Dec 2023 07:57:41 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Robbin Ehn , Gianluca Guida Subject: [PATCH v2 2/6] riscv: hwprobe: export Ztso ISA extension Date: Wed, 20 Dec 2023 16:57:18 +0100 Message-ID: <20231220155723.684081-3-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231220155723.684081-1-cleger@rivosinc.com> References: <20231220155723.684081-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Export the Ztso extension to userspace. Signed-off-by: Clément Léger --- Documentation/arch/riscv/hwprobe.rst | 4 ++++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_riscv.c | 1 + 3 files changed, 6 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index 41463b932268..10bd7b170118 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -161,6 +161,10 @@ The following keys are defined: defined in the RISC-V ISA manual starting from commit 056b6ff467c7 ("Zfa is ratified"). + * :c:macro:`RISCV_HWPROBE_EXT_ZTSO`: The Ztso extension is supported as + defined in the RISC-V ISA manual starting from commit 5618fb5a216b + ("Ztso is now ratified.") + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index 91fbe1a7f2e2..01ac3dc196e5 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -56,6 +56,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZVFH (1 << 30) #define RISCV_HWPROBE_EXT_ZVFHMIN (1 << 31) #define RISCV_HWPROBE_EXT_ZFA (1ULL << 32) +#define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index f0bd7b480b7f..6564fa9e7a7f 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -174,6 +174,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZKSH); EXT_KEY(ZKT); EXT_KEY(ZIHINTNTL); + EXT_KEY(ZTSO); if (has_vector()) { EXT_KEY(ZVBB); From patchwork Wed Dec 20 15:57:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 756617 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 384814653E for ; Wed, 20 Dec 2023 15:57:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="Z6iYwN3I" Received: by mail-wr1-f43.google.com with SMTP id ffacd0b85a97d-3367659c42aso56510f8f.0 for ; Wed, 20 Dec 2023 07:57:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1703087864; x=1703692664; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oZT3AkmSaqumQ97ecuZBaz7B+rLb1J+xdw7pERlw1ck=; b=Z6iYwN3I37Qg/yMkxLLrsXU9Lc6aPdB6HSwmf6Sj+FcrCaOyiRLYpRlSyzDWEit8GD PfKcIJ4IIXvs2Kt/TvtH/u0xhg7dkXkvnqV98aSqRY02e40zClOqAIIw0klXQB13Hjh/ /4tYyNCyfrq1IgHA6E8+G8dLUH/dIDySzFVYNKW48hxXNaRIK/R5jvph7qASCEJduP0W 4hgHwPb6C/z2yy7SoOKw5iSdfXjxTg8Ev+p0M2BxrrDc0tFV/4EAJk4/csXZBCH0Tjmt iaMLIGKxwYXrh0JPQk4+Xm7BL7DZgOQYgvHWAd2dj9xKhkzopmF/CwGVlF8CBiyQj0/X KNUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703087864; x=1703692664; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oZT3AkmSaqumQ97ecuZBaz7B+rLb1J+xdw7pERlw1ck=; b=BAHWG8oZKtbyF7q3PEP1ActKibWr1Lt+pUjlV1CpfndB+irRihgejl2MFPOcOQisGX Z+ezotOO3y37BpPznaNYxveuzLhR65DFhtP0bVflMUx0EQKVRqvLI9Zw9t9mJ5cm5kFj ym/N9yWBzcQJi4Af+UVeMNWrGOOkdxKIrmQj/KuWWgqXo4QdpXAEirEQlq+/Q8fs8zuX UFFBF+Hbm+U10NArY4jjpnP4AbI/K3DKyDYAscF28WmCG3mRZVWMRrEjqXEfMIAfoqAN VCg50HyZaFNjOjpm6ArIbww/NCdQrUiV1PSjYhsB8HBUJ1t3aHNHZyfpSFLGM44ewR2g jXeg== X-Gm-Message-State: AOJu0YxxDpOaZw6JNhe0ZbVor2m1V4VRniJJe8YgmqQSEw/iTjld8i83 7ATVj9MgbT5xlY+XxHfwOvqu0Q== X-Google-Smtp-Source: AGHT+IEAqrHN3Za66t0NZjui8EhChki4mQcTMIh6RZgm58ClLt3lfkny0M8iVRzoKzGcB9ZORNH4uw== X-Received: by 2002:a05:6000:18c9:b0:336:5c96:a3c7 with SMTP id w9-20020a05600018c900b003365c96a3c7mr7715482wrq.0.1703087864600; Wed, 20 Dec 2023 07:57:44 -0800 (PST) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:3eae:b70:f27f:7aa1]) by smtp.gmail.com with ESMTPSA id h18-20020adffd52000000b003366af9d611sm7279693wrs.22.2023.12.20.07.57.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Dec 2023 07:57:43 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Robbin Ehn , Gianluca Guida Subject: [PATCH v2 4/6] riscv: add ISA extension parsing for Zacas Date: Wed, 20 Dec 2023 16:57:20 +0100 Message-ID: <20231220155723.684081-5-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231220155723.684081-1-cleger@rivosinc.com> References: <20231220155723.684081-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add parsing for Zacas ISA extension which was ratified recently in the riscv-zacas manual. Signed-off-by: Clément Léger --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 3b31efe2f716..34f86424d743 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -85,6 +85,7 @@ #define RISCV_ISA_EXT_ZVFHMIN 70 #define RISCV_ISA_EXT_ZFA 71 #define RISCV_ISA_EXT_ZTSO 72 +#define RISCV_ISA_EXT_ZACAS 73 #define RISCV_ISA_EXT_MAX 128 #define RISCV_ISA_EXT_INVALID U32_MAX diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 3eb48a0eecb3..9a9d915b5bb2 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -259,6 +259,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL), __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), + __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS), __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), __RISCV_ISA_EXT_DATA(zfhmin, RISCV_ISA_EXT_ZFHMIN), From patchwork Wed Dec 20 15:57:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 756616 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B046047A74 for ; Wed, 20 Dec 2023 15:57:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="fDYzBUSL" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-40c317ba572so13868645e9.0 for ; Wed, 20 Dec 2023 07:57:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1703087867; x=1703692667; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TXiIygoI2xfoAtWyxNJaEZbhAX2C42esk/G1o5mFVH8=; b=fDYzBUSLvR2PzV2deSxttD8JpjEI3lHd1RYNM1OAnvZjSDm9fzRHOdb2RE3BnzbbVE nFmjtTmnynnCMZ0jGtXncqEff5/6dGf/CJLED1klg4ukqF5dLN7XfDZVG5CM+js2CwKY LmraTAcKYf2xmG0BN6OFgBi3l4Jaj5hRFF19Tr6SzplWuLJ2YJ+OY2xSjglqKOXud8Rz d5QURqcciZ34J8XoTfmMph6eiQTyOpag8YOLULbUGcWocG2edn15xvuzWYwHSWwS0CVh uSDnztPFX+UWcy+5k7cr3OjZgUHZAF3huqGAj4zFpKQVdPFHV8wojykglUyRNfkkxd4W 1DKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1703087867; x=1703692667; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TXiIygoI2xfoAtWyxNJaEZbhAX2C42esk/G1o5mFVH8=; b=g/m9Y5SkIkv8snSyWv39fY9eRNyAk1xLxcO4Hw09bpELyF6pXHcxbjoFyXA7Ww/M8I e9V7S6tFhLtE20BOnX1GYErETNLGD6iTfDgTwyZ3wzlm8WIGShDJ65R480aDeUGgeA/s yODypRNDcTML+Xu6VUkOzv+9Twy5mQrT0YMe2Iz/LpztepAt6eP/vRd2g4xMDdqmq5lI OyC6nqMD9EEwUC5vayPpwB7CbwDVCnY0y0pr55RvlbNm7/JpHJL82I08QwaKRbdozNlj ixDmgJ82/HYoz1qkDGbmH+uHzdUcgsOhUsP/Uct5oIV2yl9EKx8jjuP/HMfBI8kgKK9d LW0A== X-Gm-Message-State: AOJu0Yy1JcLxZBskIW1TQLhQO0laJUR335vCTpMKfTeUdNobuaTKT3yw 1u+bmTNsc189hFkqLPuBMaeebQ== X-Google-Smtp-Source: AGHT+IEpr+96oxZFiK4cxomHHqE/jg1PvdGozQiMvvlQ4NTHaFlfmPa9ipv0kbSLSizkLF3AkktCuw== X-Received: by 2002:adf:e2c4:0:b0:336:4a0e:4284 with SMTP id d4-20020adfe2c4000000b003364a0e4284mr12246378wrj.6.1703087867017; Wed, 20 Dec 2023 07:57:47 -0800 (PST) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:3eae:b70:f27f:7aa1]) by smtp.gmail.com with ESMTPSA id h18-20020adffd52000000b003366af9d611sm7279693wrs.22.2023.12.20.07.57.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Dec 2023 07:57:46 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Robbin Ehn , Gianluca Guida Subject: [PATCH v2 6/6] riscv: hwprobe: export Zicond extension Date: Wed, 20 Dec 2023 16:57:22 +0100 Message-ID: <20231220155723.684081-7-cleger@rivosinc.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231220155723.684081-1-cleger@rivosinc.com> References: <20231220155723.684081-1-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Export the zicond extension to userspace using hwprobe. Signed-off-by: Clément Léger --- Documentation/arch/riscv/hwprobe.rst | 5 +++++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_riscv.c | 1 + 3 files changed, 7 insertions(+) diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index bff68004ad43..ee320fe7581b 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -169,6 +169,11 @@ The following keys are defined: defined in the Atomic Compare-and-Swap (CAS) instructions manual starting from commit 5059e0ca641c ("update to ratified"). + * :c:macro:`RISCV_HWPROBE_EXT_ZICOND`: The Zicond extension is supported as + defined in the RISC-V Integer Conditional (Zicond) operations extension + manual starting from commit 95cf1f9 ("Add changes requested by Ved + during signoff") + * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance information about the selected set of processors. diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h index ac65bb43c8e7..fd7af0dddb12 100644 --- a/arch/riscv/include/uapi/asm/hwprobe.h +++ b/arch/riscv/include/uapi/asm/hwprobe.h @@ -58,6 +58,7 @@ struct riscv_hwprobe { #define RISCV_HWPROBE_EXT_ZFA (1ULL << 32) #define RISCV_HWPROBE_EXT_ZTSO (1ULL << 33) #define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34) +#define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35) #define RISCV_HWPROBE_KEY_CPUPERF_0 5 #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c index 6c680c75ac0d..cca9b1e35647 100644 --- a/arch/riscv/kernel/sys_riscv.c +++ b/arch/riscv/kernel/sys_riscv.c @@ -176,6 +176,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, EXT_KEY(ZIHINTNTL); EXT_KEY(ZTSO); EXT_KEY(ZACAS); + EXT_KEY(ZICOND); if (has_vector()) { EXT_KEY(ZVBB);