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[82.149.12.148]) by smtp.gmail.com with ESMTPSA id v14-20020a05600c444e00b0040c58e410a3sm8703224wmn.14.2023.12.20.12.36.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Dec 2023 12:36:12 -0800 (PST) From: Jernej Skrabec To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, wens@csie.org, samuel@sholland.org, andrew@lunn.ch, hkallweit1@gmail.com, linux@armlinux.org.uk, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, Ondrej Jirman , Corentin Labbe , Jernej Skrabec Subject: [PATCH v5 2/3] arm64: dts: allwinner: orange-pi-3: Enable ethernet Date: Wed, 20 Dec 2023 21:35:36 +0100 Message-ID: <20231220203537.83479-3-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231220203537.83479-1-jernej.skrabec@gmail.com> References: <20231220203537.83479-1-jernej.skrabec@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Ondrej Jirman Orange Pi 3 has two regulators that power the Realtek RTL8211E PHY. According to the datasheet, both regulators need to be enabled at the same time, or that "phy-io" should be enabled slightly earlier than "ephy" regulator. RTL8211E/RTL8211EG datasheet says: Note 4: 2.5V (or 1.8/1.5V) RGMII power should be risen simultaneously or slightly earlier than 3.3V power. Rising 2.5V (or 1.8/1.5V) power later than 3.3V power may lead to errors. Signed-off-by: Ondrej Jirman Signed-off-by: Corentin Labbe Signed-off-by: Jernej Skrabec --- .../dts/allwinner/sun50i-h6-orangepi-3.dts | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts index 6fc65e8db220..6ed8613a3169 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts @@ -13,6 +13,7 @@ / { compatible = "xunlong,orangepi-3", "allwinner,sun50i-h6"; aliases { + ethernet0 = &emac; serial0 = &uart0; serial1 = &uart1; }; @@ -55,6 +56,17 @@ led-1 { }; }; + reg_gmac_2v5: gmac-2v5 { + compatible = "regulator-fixed"; + regulator-name = "gmac-2v5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ + off-on-delay-us = <100000>; + vin-supply = <®_vcc5v>; + }; + reg_vcc5v: vcc5v { /* board wide 5V supply directly from the DC jack */ compatible = "regulator-fixed"; @@ -113,6 +125,33 @@ &ehci3 { status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&ext_rgmii_pins>; + phy-mode = "rgmii-id"; + phy-handle = <&ext_rgmii_phy>; + status = "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + /* + * The board uses 2.5V RGMII signalling. Power sequence to enable + * the phy is to enable GMAC-2V5 and GMAC-3V (aldo2) power rails + * at the same time and to wait 100ms. The driver enables phy-io + * first. Delay is achieved with enable-ramp-delay on reg_aldo2. + */ + phy-io-supply = <®_gmac_2v5>; + ephy-supply = <®_aldo2>; + + reset-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */ + reset-assert-us = <15000>; + reset-deassert-us = <40000>; + }; +}; + &gpu { mali-supply = <®_dcdcc>; status = "okay"; @@ -211,6 +250,7 @@ reg_aldo2: aldo2 { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-name = "vcc33-audio-tv-ephy-mac"; + regulator-enable-ramp-delay = <100000>; }; /* ALDO3 is shorted to CLDO1 */