From patchwork Fri Aug 30 12:18:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 172685 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp543287ily; Fri, 30 Aug 2019 05:18:37 -0700 (PDT) X-Google-Smtp-Source: APXvYqxVexFXVg6RcZTv+W+ydW0dDkLDgmVleZGMArOpNf1wSBEiT/dEZqcCerrh2ajwNJhfhxek X-Received: by 2002:a17:902:b70b:: with SMTP id d11mr8032744pls.238.1567167517394; Fri, 30 Aug 2019 05:18:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567167517; cv=none; d=google.com; s=arc-20160816; b=oTESrn0b3jCbFeCpF0pwZRXsVW23kLJuuKDOzZQw+q3Ny1V7ATD5xRcLLe4Awhh7bm T1xNmLk4hDsX6GmUfp0G1OmlxggBaSaaoSEH/CCunxI+uLPFxejvCVtspMaMs180vKFK XEZjZJ7rmHq8x+SE8WZ41f/qqPFiZ7W24IWh18nUuRNr364f4GK3aI+cNLtTKNklXiFs 9VSg+NIvQOoq+oCTS68CJP7iBQoWR3mAyqNg/KGK34sH5tpLLbB7sFvUm7CXIOmDyg7h TYFzxLNU6WqmXSew+pd73gmf682gTq1eF0wWuHLNQ0ISOXoxh/+6qxG5WStKcDEmyOBZ OHSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=4/vn3nShvBSwpELcXgs5bhAcnH64+34+9f0PSBWUDWs=; b=ecjYP8xy0b7B/M+EMXbTs7bbVAvRNbEX2kPV3gaH7LNQVVYJc0LTjI73cZW5IV1Z6V DzpYwYtLjLwUK/3wOaduUP2X7+3Wx6/rCdY1lJyDpbIK7g2UBFAjVOfklA5VpDzEBaE0 3gTKXfgQyeiJVHVPkdCX4l9pMqG/inTExdGFOjMmH2igjiGjm81+L37ohaww8RV/hEFY cGp2aZ4LxP8ukSXGJFLH9WnMOFlgQXDU9BL6Fic8RHGOeZffMh9kt/k7mFSIc3wj+OXs GxZ7KEN0JLr0gHWIf3Zo/Li7hv5rkJ6LlvJxY2jDGPI5a3+s2NCKETMTuVIeby1XWCpz 0llA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=vKCpcIAy; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r193si1886576pfr.27.2019.08.30.05.18.36; Fri, 30 Aug 2019 05:18:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=vKCpcIAy; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728107AbfH3MSg (ORCPT + 8 others); Fri, 30 Aug 2019 08:18:36 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:39224 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727836AbfH3MSg (ORCPT ); Fri, 30 Aug 2019 08:18:36 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7UCITBk119927; Fri, 30 Aug 2019 07:18:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1567167509; bh=4/vn3nShvBSwpELcXgs5bhAcnH64+34+9f0PSBWUDWs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=vKCpcIAyEkJESMs644fWa33gtNE9MfFDoF9MN72X2e80u9A+0N6TBt/Nz2jy0fS8h FEEYYXwF90TVyG/UruM97wB+se4jErIjGkcjKTcT+WTwjU74rlr4OTlE5O2SYjn+eB HOKyn4Go4TODtyRrtNnL2Oy9bH2ZlCZcMd6hQq3k= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7UCITeG016147 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 30 Aug 2019 07:18:29 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 30 Aug 2019 07:18:29 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 30 Aug 2019 07:18:29 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7UCIP6H083824; Fri, 30 Aug 2019 07:18:27 -0500 From: Tero Kristo To: , , , , CC: , Subject: [PATCHv3 01/10] dt-bindings: omap: add new binding for PRM instances Date: Fri, 30 Aug 2019 15:18:07 +0300 Message-ID: <20190830121816.30034-2-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190830121816.30034-1-t-kristo@ti.com> References: <20190830121816.30034-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add new binding for OMAP PRM (Power and Reset Manager) instances. Each of these will act as a power domain controller and potentially as a reset provider. Signed-off-by: Tero Kristo --- .../devicetree/bindings/arm/omap/prm-inst.txt | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/omap/prm-inst.txt -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/Documentation/devicetree/bindings/arm/omap/prm-inst.txt b/Documentation/devicetree/bindings/arm/omap/prm-inst.txt new file mode 100644 index 000000000000..7c7527c37734 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/prm-inst.txt @@ -0,0 +1,31 @@ +OMAP PRM instance bindings + +Power and Reset Manager is an IP block on OMAP family of devices which +handle the power domains and their current state, and provide reset +handling for the domains and/or separate IP blocks under the power domain +hierarchy. + +Required properties: +- compatible: Must be one of: + "ti,am3-prm-inst" + "ti,am4-prm-inst" + "ti,omap4-prm-inst" + "ti,omap5-prm-inst" + "ti,dra7-prm-inst" +- reg: Contains PRM instance register address range + (base address and length) + +Optional properties: +- #reset-cells: Should be 1 if the PRM instance in question supports resets. +- clocks: Associated clocks for the reset signals if any. Certain reset + signals can't be toggled properly without functional clock + being active for them. + +Example: + +prm_dsp2: prm@1b00 { + compatible = "ti,dra7-prm-inst"; + reg = <0x1b00 0x40>; + #reset-cells = <1>; + clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>; +}; From patchwork Fri Aug 30 12:18:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 172690 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp543502ily; Fri, 30 Aug 2019 05:18:47 -0700 (PDT) X-Google-Smtp-Source: APXvYqwIl1ZgTz7a+/0VdhTcmTgBSdq6j5jWrcBCxl2Ef2TY3RTpsaOaFxtTyJ6h/CN4sdgrn6PI X-Received: by 2002:a63:7c0d:: with SMTP id x13mr12682997pgc.360.1567167526920; Fri, 30 Aug 2019 05:18:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567167526; cv=none; d=google.com; s=arc-20160816; b=mb6SAK5siX0d1yCH+51C2Gonew9ByfgCLPRVJ5WIc/KpVox+i4vRUkHeuyeFB5HUQw V6Jq1Ohfa7BBs1U0FnJYUEgCkoL5S7fe+9krmsDRgDbL2CQP1R4Xyc7B2il7yxsVefO+ d//HieTZD/jddK6jXUNZh61a0F9sl7cNcJoJIwdt1hTuFxV5uhHhJg6lHXxHdlwnk30p Qr7gRqJ+aEWA1hqcUUaiwEFgFUDLhy8lY51T0rOOkJUd6H4PfifKZ4o1lS95rnL79Gxw PdVnhYu03HB2Cgr3eNCzXiPkZGUYPi5qGBfTnWgubBsoU+j1/bQ8CbOB8/RSe0g4ADwI MVBg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=K9LpAnsvt5fDkmnzHyF3/44QnoabSzy0pl7C59SB404=; b=zS4fiS0G4ePJNNpugZyF5Uw4jjR/HwhrZxQbhs7t6N++KXCvgz5Q06jGdVWb41eUpA 2BNSBOvZcPZEHLtsrFnzgZCPap3xpjgm0miOFoH6PmbMybY9zj/sMSUnUbGuA+KR8wex GS4IU3rKPJP2khL5JuL/t9CwVH7n+6edwWq4NypT6/syqOis9YSmIJ1VYt74274fVTKv 9Tbicf7vqD9nIFQNM7Fmz0Z/xHt1/ra5J/NLF+aKzOdipFGFZD8N87Brl2GxnRalJ8// odWFdjTIR0UhrnlsJetmZML6cUifJN3e1KVbaTDqka3xZOXEm6Q9/x3VJahcD+n5JPy/ FB4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=x3GXxq8X; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r193si1886576pfr.27.2019.08.30.05.18.46; Fri, 30 Aug 2019 05:18:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=x3GXxq8X; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728148AbfH3MSp (ORCPT + 8 others); Fri, 30 Aug 2019 08:18:45 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:54996 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728117AbfH3MSp (ORCPT ); Fri, 30 Aug 2019 08:18:45 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7UCIWsh013289; Fri, 30 Aug 2019 07:18:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1567167512; bh=K9LpAnsvt5fDkmnzHyF3/44QnoabSzy0pl7C59SB404=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=x3GXxq8XbgFp/2obP1ZW2BjNeU5JSVkDEe4RMii9TSH8vXr9qckhueapp5aqZ/tNs 7efFsp2l0igB0p0I+zYgwOg9aO8kmDqmAQvYF3hRu0dAmcaLxpScHWrHM8tV8w23d8 uNuRExK12i/tEMHisE0TozZk7QJu94kGdyEZ1lFE= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7UCIVsZ128414 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 30 Aug 2019 07:18:32 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 30 Aug 2019 07:18:31 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 30 Aug 2019 07:18:31 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7UCIP6I083824; Fri, 30 Aug 2019 07:18:29 -0500 From: Tero Kristo To: , , , , CC: , Subject: [PATCHv3 02/10] soc: ti: add initial PRM driver with reset control support Date: Fri, 30 Aug 2019 15:18:08 +0300 Message-ID: <20190830121816.30034-3-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190830121816.30034-1-t-kristo@ti.com> References: <20190830121816.30034-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add initial PRM (Power and Reset Management) driver for TI OMAP class SoCs. Initially this driver only supports reset control, but can be extended to support rest of the functionality, like powerdomain control, PRCM irq support etc. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/Kconfig | 1 + drivers/soc/ti/Makefile | 1 + drivers/soc/ti/omap_prm.c | 259 ++++++++++++++++++++++++++++++++++++ 3 files changed, 261 insertions(+) create mode 100644 drivers/soc/ti/omap_prm.c -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index fdb6743760a2..ad08d470a2ca 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -109,6 +109,7 @@ config ARCH_OMAP2PLUS select TI_SYSC select OMAP_IRQCHIP select CLKSRC_TI_32K + select ARCH_HAS_RESET_CONTROLLER help Systems based on OMAP2, OMAP3, OMAP4 or OMAP5 diff --git a/drivers/soc/ti/Makefile b/drivers/soc/ti/Makefile index b3868d392d4f..788b5cd1e180 100644 --- a/drivers/soc/ti/Makefile +++ b/drivers/soc/ti/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_KEYSTONE_NAVIGATOR_QMSS) += knav_qmss.o knav_qmss-y := knav_qmss_queue.o knav_qmss_acc.o obj-$(CONFIG_KEYSTONE_NAVIGATOR_DMA) += knav_dma.o obj-$(CONFIG_AMX3_PM) += pm33xx.o +obj-$(CONFIG_ARCH_OMAP2PLUS) += omap_prm.o obj-$(CONFIG_WKUP_M3_IPC) += wkup_m3_ipc.o obj-$(CONFIG_TI_SCI_PM_DOMAINS) += ti_sci_pm_domains.o obj-$(CONFIG_TI_SCI_INTA_MSI_DOMAIN) += ti_sci_inta_msi.o diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c new file mode 100644 index 000000000000..ab0b66ad715d --- /dev/null +++ b/drivers/soc/ti/omap_prm.c @@ -0,0 +1,259 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * OMAP2+ PRM driver + * + * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ + * Tero Kristo + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct omap_rst_map { + s8 rst; + s8 st; +}; + +struct omap_prm_data { + u32 base; + const char *name; + u16 rstctrl; + u16 rstst; + const struct omap_rst_map *rstmap; + u8 flags; +}; + +struct omap_prm { + const struct omap_prm_data *data; + void __iomem *base; +}; + +struct omap_reset_data { + struct reset_controller_dev rcdev; + struct omap_prm *prm; + u32 mask; + spinlock_t lock; /* Protect register writes */ +}; + +#define to_omap_reset_data(p) container_of((p), struct omap_reset_data, rcdev) + +#define OMAP_MAX_RESETS 8 +#define OMAP_RESET_MAX_WAIT 10000 + +#define OMAP_PRM_HAS_RSTCTRL BIT(0) +#define OMAP_PRM_HAS_RSTST BIT(1) + +#define OMAP_PRM_HAS_RESETS (OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_RSTST) + +static const struct of_device_id omap_prm_id_table[] = { + { }, +}; + +static bool _is_valid_reset(struct omap_reset_data *reset, unsigned long id) +{ + if (reset->mask & BIT(id)) + return true; + + return false; +} + +static int omap_reset_get_st_bit(struct omap_reset_data *reset, + unsigned long id) +{ + const struct omap_rst_map *map = reset->prm->data->rstmap; + + while (map->rst >= 0) { + if (map->rst == id) + return map->st; + + map++; + } + + return id; +} + +static int omap_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct omap_reset_data *reset = to_omap_reset_data(rcdev); + u32 v; + int st_bit = omap_reset_get_st_bit(reset, id); + bool has_rstst = reset->prm->data->rstst || + (reset->prm->data->flags & OMAP_PRM_HAS_RSTST); + + /* Check if we have rstst */ + if (!has_rstst) + return -ENOTSUPP; + + /* Check if hw reset line is asserted */ + v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); + if (v & BIT(id)) + return 1; + + /* + * Check reset status, high value means reset sequence has been + * completed successfully so we can return 0 here (reset deasserted) + */ + v = readl_relaxed(reset->prm->base + reset->prm->data->rstst); + v >>= st_bit; + v &= 1; + + return !v; +} + +static int omap_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct omap_reset_data *reset = to_omap_reset_data(rcdev); + u32 v; + unsigned long flags; + + /* assert the reset control line */ + spin_lock_irqsave(&reset->lock, flags); + v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); + v |= 1 << id; + writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl); + spin_unlock_irqrestore(&reset->lock, flags); + + return 0; +} + +static int omap_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct omap_reset_data *reset = to_omap_reset_data(rcdev); + u32 v; + int st_bit; + bool has_rstst; + unsigned long flags; + + has_rstst = reset->prm->data->rstst || + (reset->prm->data->flags & OMAP_PRM_HAS_RSTST); + + if (has_rstst) { + st_bit = omap_reset_get_st_bit(reset, id); + + /* Clear the reset status by writing 1 to the status bit */ + v = readl_relaxed(reset->prm->base + reset->prm->data->rstst); + v |= 1 << st_bit; + writel_relaxed(v, reset->prm->base + reset->prm->data->rstst); + } + + /* de-assert the reset control line */ + spin_lock_irqsave(&reset->lock, flags); + v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); + v &= ~(1 << id); + writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl); + spin_unlock_irqrestore(&reset->lock, flags); + + return 0; +} + +static const struct reset_control_ops omap_reset_ops = { + .assert = omap_reset_assert, + .deassert = omap_reset_deassert, + .status = omap_reset_status, +}; + +static int omap_prm_reset_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + struct omap_reset_data *reset = to_omap_reset_data(rcdev); + + if (!_is_valid_reset(reset, reset_spec->args[0])) + return -EINVAL; + + return reset_spec->args[0]; +} + +static int omap_prm_reset_init(struct platform_device *pdev, + struct omap_prm *prm) +{ + struct omap_reset_data *reset; + const struct omap_rst_map *map; + + /* + * Check if we have controllable resets. If either rstctrl is non-zero + * or OMAP_PRM_HAS_RSTCTRL flag is set, we have reset control register + * for the domain. + */ + if (!prm->data->rstctrl && !(prm->data->flags & OMAP_PRM_HAS_RSTCTRL)) + return 0; + + map = prm->data->rstmap; + if (!map) + return -EINVAL; + + reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL); + if (!reset) + return -ENOMEM; + + reset->rcdev.owner = THIS_MODULE; + reset->rcdev.ops = &omap_reset_ops; + reset->rcdev.of_node = pdev->dev.of_node; + reset->rcdev.nr_resets = OMAP_MAX_RESETS; + reset->rcdev.of_xlate = omap_prm_reset_xlate; + reset->rcdev.of_reset_n_cells = 1; + spin_lock_init(&reset->lock); + + reset->prm = prm; + + while (map->rst >= 0) { + reset->mask |= BIT(map->rst); + map++; + } + + return devm_reset_controller_register(&pdev->dev, &reset->rcdev); +} + +static int omap_prm_probe(struct platform_device *pdev) +{ + struct resource *res; + const struct omap_prm_data *data; + struct omap_prm *prm; + const struct of_device_id *match; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + match = of_match_device(omap_prm_id_table, &pdev->dev); + if (!match) + return -ENOTSUPP; + + prm = devm_kzalloc(&pdev->dev, sizeof(*prm), GFP_KERNEL); + if (!prm) + return -ENOMEM; + + data = match->data; + + while (data->base != res->start) { + if (!data->base) + return -EINVAL; + data++; + } + + prm->data = data; + + prm->base = devm_ioremap_resource(&pdev->dev, res); + if (!prm->base) + return -ENOMEM; + + return omap_prm_reset_init(pdev, prm); +} + +static struct platform_driver omap_prm_driver = { + .probe = omap_prm_probe, + .driver = { + .name = KBUILD_MODNAME, + .of_match_table = omap_prm_id_table, + }, +}; +builtin_platform_driver(omap_prm_driver); From patchwork Fri Aug 30 12:18:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 172687 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp543367ily; Fri, 30 Aug 2019 05:18:41 -0700 (PDT) X-Google-Smtp-Source: APXvYqxlomeeiAKN741yldBwsWuQytQuGmEwhEiaPGpk8A+fDugj4LBAgiWj41i9MQ7Wx+xmpaGR X-Received: by 2002:a63:e148:: with SMTP id h8mr12789694pgk.275.1567167520987; Fri, 30 Aug 2019 05:18:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567167520; cv=none; d=google.com; s=arc-20160816; b=yQPP7eXI9kUOiSZiW18EpuImXoCVtT/OpZ2GQsV5IKx2zWAW7KyUA2nYgl8eAmDffn 4McqKeTYlhm8Hskb9KYX/jig4lxa0a5AbgxjApgdwcayZDNQgNnZ8aE0IfnJmaMmgusI ffNa0BGcARGMLN8fhn2BOz6SbK9oSE09QArLE8l66Q8y/HYRxX+NpODZfdsdDRrZuSVo mr1CKWx1iJJGCSmV7vkawiPQHyEPEmasSZJirloWzwEyCqibcSr+wE1mVLMW1UbeJQlV 4kqR80cgl4MoQTvSJoOwT/kSP4ykI5y/l1HMbFHV9O4CntHOjBnHlH31O2rU6Fm44TAA 316Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=piysbVL/wbtSd2fFes2OZDB9ILAzdFqjZ+wsv/1pBaY=; b=wNeJzvPYS2Tjr5XdT7Autgj21HuRiFYz8okpxXERAAC+Zf8cOh9MOel/vtHSd9LxTF W9D9eDCWezciXGKIklIQ2b56r8fZ6g4SxI7AcsKfzDSvIDr33JoXt/05wiFdSZSqvQsH 6suagZLj9qMCFx5wMGrhYF0YikAsGw3+wSr8n5mQX80QOfJDBnM8LpFT7Aobc85pwEhG klM6ofUVgaQ8J07JY6KMvvjzr4Zt8e1qlTAX1i7m+xhZ+OWlzngDuwmaLXm9jKrQwpPO THIuS4NLwxxEWNJPBM2NQ4BjQdgPmttGB3hekGF59S+N3bKpkYkcBfpZ5FWTKdC94LuU XoTg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=r5o3eROL; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Tero Kristo --- drivers/soc/ti/omap_prm.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index ab0b66ad715d..d70f64e7a5c8 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -153,6 +153,18 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl); spin_unlock_irqrestore(&reset->lock, flags); + if (!has_rstst) + return 0; + + /* wait for the status to be set */ + ret = readl_relaxed_poll_timeout(reset->prm->base + + reset->prm->data->rstst, + v, v & BIT(st_bit), 1, + OMAP_RESET_MAX_WAIT); + if (ret) + pr_err("%s: timedout waiting for %s:%lu\n", __func__, + dev_name(rcdev->dev), id); + return 0; } From patchwork Fri Aug 30 12:18:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 172688 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp543444ily; Fri, 30 Aug 2019 05:18:44 -0700 (PDT) X-Google-Smtp-Source: APXvYqwOOfco6NJ8bmvh7ANfvzIA79At2+d62CHKr4J7huuCS9tLt8SHbahXzbYNEZdWR0j8dlwZ X-Received: by 2002:a17:902:e592:: with SMTP id cl18mr15343204plb.291.1567167524413; Fri, 30 Aug 2019 05:18:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567167524; cv=none; d=google.com; s=arc-20160816; b=inhtQjsS5ZASXMi6QiyRQVEfz8v0ya607qJTdPc7aoecJ8Q3pP3l7UDX12iYuQkhjg NCjKr2eEEtzH/bw7Nv6NabYRGYyfX6ILa2wpPWK/ylDKmWxvYHkv5LUEp09T7T6WejB8 umigO4lVbpiYJ9h09uBcxXCqbzyvMhs/keJ0YblG8bjKK1D8JibvHSpzQesuDZ934jR9 6vjr3StJyu/Boer0EkMrGEuBbGFrgTNRA70uU5RqdXyMgQ5Am8kjzp2jqK0WmX3Ohh+q aNr4DVx+7SkH9Le1fQVxyDPCg03+wm8OU3g55h320tbGYJd60ynVZAh/RHaiC1ixtGQm yhJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=+f3IffW05cfi5yYVMC7gJ7Ll4J7LzdA5tzeGMWz+JIc=; b=KmlZgtvEQy4ikXSjP9mgoYgiQIHBacAMjJnsYR/ltdjULSDmXHHAxfu3S+sYzeXe53 UjrDpUJJn6ngSJyTwzNOeVU0cD23gRN3p4Vv+oAZd+uM7KPHzKsSrgoT2ulga/8D910M RnqpbP6yKXhd6MzLQves9QHolEtfpsy+N7seHw41S6qKqiK8LCbeu9oJ22UZUw4zkz5H k/h0qxi3NaD0W6f13NwBX7X77IwV8Mj2H4LbViwgWIFLe9CEgPxIEIGhPrUbTnY4qv3l 31Lsm8r2VTyeFR1xta/H0/kTkBRC8ynKfipU/qg+gGmgzF82KNDN/U64KiF7fIxdgX8N 2now== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=CDfSPEr4; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r193si1886576pfr.27.2019.08.30.05.18.44; Fri, 30 Aug 2019 05:18:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=CDfSPEr4; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728120AbfH3MSn (ORCPT + 8 others); Fri, 30 Aug 2019 08:18:43 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:39258 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728117AbfH3MSn (ORCPT ); Fri, 30 Aug 2019 08:18:43 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7UCIaD1119946; Fri, 30 Aug 2019 07:18:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1567167516; bh=+f3IffW05cfi5yYVMC7gJ7Ll4J7LzdA5tzeGMWz+JIc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=CDfSPEr4fSd1b2lHsLpqu7XwrM7DjHgOJS6I5vKp5EcP/jeVUuWjM5qOlWkuXSzbl 19lz0vsCIbiJmZ6mEZIm5AIfj3D/+dDiQw5f8roPuBCSDR8EPcfAJxVz2aMrDj9DCD O7WhcCIPxltbg+ETjTkrC6xbP7QwiXcr8tJfQMJA= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7UCIaw3128458 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 30 Aug 2019 07:18:36 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 30 Aug 2019 07:18:35 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 30 Aug 2019 07:18:35 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7UCIP6K083824; Fri, 30 Aug 2019 07:18:34 -0500 From: Tero Kristo To: , , , , CC: , Subject: [PATCHv3 04/10] soc: ti: omap-prm: add support for denying idle for reset clockdomain Date: Fri, 30 Aug 2019 15:18:10 +0300 Message-ID: <20190830121816.30034-5-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190830121816.30034-1-t-kristo@ti.com> References: <20190830121816.30034-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org TI SoCs hardware reset signals require the parent clockdomain to be in force wakeup mode while de-asserting the reset, otherwise it may never complete. To support this, add pdata hooks to control the clockdomain directly. Signed-off-by: Tero Kristo --- drivers/soc/ti/omap_prm.c | 36 ++++++++++++++++++++++++++-- include/linux/platform_data/ti-prm.h | 21 ++++++++++++++++ 2 files changed, 55 insertions(+), 2 deletions(-) create mode 100644 include/linux/platform_data/ti-prm.h -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index d70f64e7a5c8..0b6a300f935b 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -16,6 +16,8 @@ #include #include +#include + struct omap_rst_map { s8 rst; s8 st; @@ -24,6 +26,7 @@ struct omap_rst_map { struct omap_prm_data { u32 base; const char *name; + const char *clkdm_name; u16 rstctrl; u16 rstst; const struct omap_rst_map *rstmap; @@ -40,6 +43,8 @@ struct omap_reset_data { struct omap_prm *prm; u32 mask; spinlock_t lock; + struct clockdomain *clkdm; + struct device *dev; }; #define to_omap_reset_data(p) container_of((p), struct omap_reset_data, rcdev) @@ -49,6 +54,7 @@ struct omap_reset_data { #define OMAP_PRM_HAS_RSTCTRL BIT(0) #define OMAP_PRM_HAS_RSTST BIT(1) +#define OMAP_PRM_HAS_NO_CLKDM BIT(2) #define OMAP_PRM_HAS_RESETS (OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_RSTST) @@ -133,6 +139,8 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, int st_bit; bool has_rstst; unsigned long flags; + struct ti_prm_platform_data *pdata = dev_get_platdata(reset->dev); + int ret = 0; has_rstst = reset->prm->data->rstst || (reset->prm->data->flags & OMAP_PRM_HAS_RSTST); @@ -146,6 +154,9 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, writel_relaxed(v, reset->prm->base + reset->prm->data->rstst); } + if (reset->clkdm) + pdata->clkdm_deny_idle(reset->clkdm); + /* de-assert the reset control line */ spin_lock_irqsave(&reset->lock, flags); v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); @@ -154,7 +165,7 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, spin_unlock_irqrestore(&reset->lock, flags); if (!has_rstst) - return 0; + goto exit; /* wait for the status to be set */ ret = readl_relaxed_poll_timeout(reset->prm->base + @@ -165,7 +176,11 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, pr_err("%s: timedout waiting for %s:%lu\n", __func__, dev_name(rcdev->dev), id); - return 0; +exit: + if (reset->clkdm) + pdata->clkdm_allow_idle(reset->clkdm); + + return ret; } static const struct reset_control_ops omap_reset_ops = { @@ -190,6 +205,8 @@ static int omap_prm_reset_init(struct platform_device *pdev, { struct omap_reset_data *reset; const struct omap_rst_map *map; + struct ti_prm_platform_data *pdata = dev_get_platdata(&pdev->dev); + char buf[32]; /* * Check if we have controllable resets. If either rstctrl is non-zero @@ -199,6 +216,11 @@ static int omap_prm_reset_init(struct platform_device *pdev, if (!prm->data->rstctrl && !(prm->data->flags & OMAP_PRM_HAS_RSTCTRL)) return 0; + /* Check if we have the pdata callbacks in place */ + if (!pdata || !pdata->clkdm_lookup || !pdata->clkdm_deny_idle || + !pdata->clkdm_allow_idle) + return -EINVAL; + map = prm->data->rstmap; if (!map) return -EINVAL; @@ -213,10 +235,20 @@ static int omap_prm_reset_init(struct platform_device *pdev, reset->rcdev.nr_resets = OMAP_MAX_RESETS; reset->rcdev.of_xlate = omap_prm_reset_xlate; reset->rcdev.of_reset_n_cells = 1; + reset->dev = &pdev->dev; spin_lock_init(&reset->lock); reset->prm = prm; + sprintf(buf, "%s_clkdm", prm->data->clkdm_name ? prm->data->clkdm_name : + prm->data->name); + + if (!(prm->data->flags & OMAP_PRM_HAS_NO_CLKDM)) { + reset->clkdm = pdata->clkdm_lookup(buf); + if (!reset->clkdm) + return -EINVAL; + } + while (map->rst >= 0) { reset->mask |= BIT(map->rst); map++; diff --git a/include/linux/platform_data/ti-prm.h b/include/linux/platform_data/ti-prm.h new file mode 100644 index 000000000000..28154c3226c2 --- /dev/null +++ b/include/linux/platform_data/ti-prm.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * TI PRM (Power & Reset Manager) platform data + * + * Copyright (C) 2019 Texas Instruments, Inc. + * + * Tero Kristo + */ + +#ifndef _LINUX_PLATFORM_DATA_TI_PRM_H +#define _LINUX_PLATFORM_DATA_TI_PRM_H + +struct clockdomain; + +struct ti_prm_platform_data { + void (*clkdm_deny_idle)(struct clockdomain *clkdm); + void (*clkdm_allow_idle)(struct clockdomain *clkdm); + struct clockdomain * (*clkdm_lookup)(const char *name); +}; + +#endif /* _LINUX_PLATFORM_DATA_TI_PRM_H */ From patchwork Fri Aug 30 12:18:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 172689 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp543480ily; Fri, 30 Aug 2019 05:18:46 -0700 (PDT) X-Google-Smtp-Source: APXvYqwpcHI4e05oUclBTWpKGcgAI/Krye05Ra37qa4EkJk0sDdklwjX8vgr/uvvv7nlq77E4rSX X-Received: by 2002:a65:5289:: with SMTP id y9mr12826179pgp.445.1567167526219; Fri, 30 Aug 2019 05:18:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567167526; cv=none; d=google.com; s=arc-20160816; b=em9j2GoNVZmvCD0PRWtvtxYb74On93XWpwRoMMhmlCxIg+JGZtQet+i0pmFibjd2DZ THYwP26eCjt/SY3GMZfZc8X//o21ygMVhDGPF/IjVhNfD601kaJfA+r6efkpGhDY+2oA HqPAZln+IHtR2LsGuxlG8ngqlgUCecvF2nAqhwDXx04yzW/NvwO16SLwCb5Oe812GDA3 0Bk6TCX6KeHjGnSj1UpvFQ1/sgvdmf902O0srH1vr2A4OHrOjnd5ppMmcEvC8h9+Qmdc PXbXjDs/3eVol0YGgwhEMlOhoIzrC3YvPP5XaQCg6A+2gxjMpDxIdT704whh2PvxmvmP Uomg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=p4CR2/bpO2SmuYHCrI6BzoLr7Plewq/qhb2FSuKAUmU=; b=lz3/pdR7aLXK3raT89yNFJaNwsLnaQnE5vsPhxN4LNW7WEUZ/heg4gv+VHhnxC9qKt PqPgZTVcAGrACTyoaXUorbPvmdUHF0PqbVNJUkGaejWL3GM0KBPp1VPpvzufqXmhWz/g bKRE25sRoyi9y2+XRXfVVEmjitJnhklxeTWk8E9AhLlZq9DuUZL4etDXPRW+fMJwSueI zF1y8TwW8RRPALPIgOwUeEtmatAkSosxsWlAVfW1pOrw3r5ot84anBTGG+hybo20qpTF yXMpx1gi4vD1zue7dOacw+qWe7sFOp1P23RPXPmYoAQc9cb6AV7J0bMQASR/jRkERMGv PO/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=mJXWfTq7; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Also, disabling a clock won't fully succeed if the associated hardware resets are not asserted. Add status sync functionality between these two for TI drivers so that the situations can be handled properly without generating any timeouts. Signed-off-by: Tero Kristo --- drivers/soc/ti/omap_prm.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index 0b6a300f935b..7c8fdc5e6c50 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -15,6 +15,8 @@ #include #include #include +#include +#include #include @@ -44,6 +46,7 @@ struct omap_reset_data { u32 mask; spinlock_t lock; struct clockdomain *clkdm; + struct clk *clk; struct device *dev; }; @@ -128,6 +131,8 @@ static int omap_reset_assert(struct reset_controller_dev *rcdev, writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl); spin_unlock_irqrestore(&reset->lock, flags); + ti_clk_notify_resets(reset->clk, v == reset->mask); + return 0; } @@ -164,9 +169,19 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl); spin_unlock_irqrestore(&reset->lock, flags); + ti_clk_notify_resets(reset->clk, v == reset->mask); + if (!has_rstst) goto exit; + /* If associated clock is disabled, we can't poll completion status */ + if (reset->clk) { + struct clk_hw *hw = __clk_get_hw(reset->clk); + + if (!clk_hw_is_enabled(hw)) + return ret; + } + /* wait for the status to be set */ ret = readl_relaxed_poll_timeout(reset->prm->base + reset->prm->data->rstst, @@ -207,6 +222,7 @@ static int omap_prm_reset_init(struct platform_device *pdev, const struct omap_rst_map *map; struct ti_prm_platform_data *pdata = dev_get_platdata(&pdev->dev); char buf[32]; + u32 v; /* * Check if we have controllable resets. If either rstctrl is non-zero @@ -237,6 +253,13 @@ static int omap_prm_reset_init(struct platform_device *pdev, reset->rcdev.of_reset_n_cells = 1; reset->dev = &pdev->dev; spin_lock_init(&reset->lock); + reset->clk = of_clk_get(pdev->dev.of_node, 0); + + if (PTR_ERR(reset->clk) == -ENOENT) + reset->clk = NULL; + + if (IS_ERR(reset->clk)) + return PTR_ERR(reset->clk); reset->prm = prm; @@ -254,6 +277,11 @@ static int omap_prm_reset_init(struct platform_device *pdev, map++; } + if (reset->clk) { + v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); + ti_clk_notify_resets(reset->clk, v == reset->mask); + } + return devm_reset_controller_register(&pdev->dev, &reset->rcdev); } From patchwork Fri Aug 30 12:18:13 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 172692 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp543664ily; Fri, 30 Aug 2019 05:18:54 -0700 (PDT) X-Google-Smtp-Source: APXvYqwtb0fckEap+U83Kc0tL8d5OKwnEMZcqihV5BnOrSxcxPa7QLBxuVAIZ+0NQV8HXTAq2wjp X-Received: by 2002:a17:90a:338b:: with SMTP id n11mr642778pjb.132.1567167534333; Fri, 30 Aug 2019 05:18:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567167534; cv=none; d=google.com; s=arc-20160816; b=lxlseWmZfkg7IOHv+8Fdu6JzsS+DyWCmEbSZyEWZv9oRPnRlWo2pCgCvO2vSLFLbQy bPMjiS/t67kpvtW+jdmNypSdd4wRmGbrZdVBGCyJNSOOn5hDHzjglZROeZ6eTROYiZ9O vpfJIyhBwVcjQmUK8QC0VjsWFawJCZF/iGtb1o3Lp9Hpqsexf2Sp9GOShUoYGU84IVBM +IKi96x9GOyoScMWn3MB1gx2gyK0Nvs+4sTmo+4lSeO62W1otN0wq7mdYhKya7lnpbv3 jwJCj7eX0Sc9rrX4dpu43rTTUOMO9iPzUEj5D2Vg3Sm9sak5dnNNr+iJ72nJHT0rf7f1 Ukqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=CaSpC6veZguPG4+z+PAkEp85ogZkXYKmwl1YDntIISA=; b=J2yYI+BysWIeZoK9om9v3HP/85LbGTbDwmzKERXtLsCZSY38jB0b1ZoR+zUILjYXd9 JeBzHA/Shb3Odg/KDO7Q9rpjLGfb9KrJvLjPwkfM5oMiHKKuBqot07g5KJ0PP4AO7vS7 6McN469wY3+V1oEDLZWYEE7sOzjVk4LDLV2+EeUDkCswiM3ugg/87oZPO9OnaVG8wwVy 4ehPZFRGhawgfLliN2EFZTp1DI5M0aKUk3imxKkfh8BECi39ubO7ED+vbyf3VtbgiJGJ /44kx7ajcAgRiRkx93U/8MOSCaxuBUW9rQPya1hRN2LFE4CCnALDFS1BmWzMYJR9eBqV eyew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=QmoFg1Rz; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r193si1886576pfr.27.2019.08.30.05.18.54; Fri, 30 Aug 2019 05:18:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=QmoFg1Rz; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728117AbfH3MSx (ORCPT + 8 others); Fri, 30 Aug 2019 08:18:53 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:34694 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727739AbfH3MSx (ORCPT ); Fri, 30 Aug 2019 08:18:53 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7UCIg5o118366; Fri, 30 Aug 2019 07:18:42 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1567167522; bh=CaSpC6veZguPG4+z+PAkEp85ogZkXYKmwl1YDntIISA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=QmoFg1RzZQ3AtNoa33y3GFo9dM6pA9wY9/y+tglJUP7G9PE4quFZJYLA/J2GGktOO RQXojWRyoaaxNQDz4j1B8d1/sJtp5S7ECWA3XB7/CtU0Ntmfv2joUFRGc4Gw5Iv/B0 mfhd135/KtVoW7av1a1WcuHOumPQe4s41c6whb0I= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7UCIgMt031625 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 30 Aug 2019 07:18:42 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 30 Aug 2019 07:18:42 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 30 Aug 2019 07:18:42 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7UCIP6N083824; Fri, 30 Aug 2019 07:18:40 -0500 From: Tero Kristo To: , , , , CC: , Subject: [PATCHv3 07/10] soc: ti: omap-prm: add data for am33xx Date: Fri, 30 Aug 2019 15:18:13 +0300 Message-ID: <20190830121816.30034-8-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190830121816.30034-1-t-kristo@ti.com> References: <20190830121816.30034-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add PRM instance data for AM33xx SoC. Includes some basic register definitions and reset data for now. Signed-off-by: Tero Kristo --- drivers/soc/ti/omap_prm.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index d413e65c9b9b..bc0933315484 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -61,6 +61,11 @@ struct omap_reset_data { #define OMAP_PRM_HAS_RESETS (OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_RSTST) +static const struct omap_rst_map rst_map_0[] = { + { .rst = 0, .st = 0 }, + { .rst = -1 }, +}; + static const struct omap_rst_map rst_map_01[] = { { .rst = 0, .st = 0 }, { .rst = 1, .st = 1 }, @@ -82,8 +87,27 @@ static const struct omap_prm_data omap4_prm_data[] = { { }, }; +static const struct omap_rst_map am3_per_rst_map[] = { + { .rst = 1 }, + { .rst = -1 }, +}; + +static const struct omap_rst_map am3_wkup_rst_map[] = { + { .rst = 3, .st = 5 }, + { .rst = -1 }, +}; + +static const struct omap_prm_data am3_prm_data[] = { + { .name = "per", .base = 0x44e00c00, .rstctrl = 0x0, .rstmap = am3_per_rst_map, .flags = OMAP_PRM_HAS_RSTCTRL, .clkdm_name = "pruss_ocp" }, + { .name = "wkup", .base = 0x44e00d00, .rstctrl = 0x0, .rstst = 0xc, .rstmap = am3_wkup_rst_map, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM }, + { .name = "device", .base = 0x44e00f00, .rstctrl = 0x0, .rstst = 0x8, .rstmap = rst_map_01, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM }, + { .name = "gfx", .base = 0x44e01100, .rstctrl = 0x4, .rstst = 0x14, .rstmap = rst_map_0, .clkdm_name = "gfx_l3" }, + { }, +}; + static const struct of_device_id omap_prm_id_table[] = { { .compatible = "ti,omap4-prm-inst", .data = omap4_prm_data }, + { .compatible = "ti,am3-prm-inst", .data = am3_prm_data }, { }, }; From patchwork Fri Aug 30 12:18:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 172693 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp543690ily; Fri, 30 Aug 2019 05:18:55 -0700 (PDT) X-Google-Smtp-Source: APXvYqyNupmCIyyz79nt/zAu+ZaDL5RgSdRwegdkSsJZlE7SItxnuXjAOBJ4ISCXqbFPGPA1cskY X-Received: by 2002:a17:902:fa5:: with SMTP id 34mr15663680plz.285.1567167535425; Fri, 30 Aug 2019 05:18:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567167535; cv=none; d=google.com; s=arc-20160816; b=pc0LTIjqBD2jc9RQqezkfe0UnV22YOdZQSO6VUKagSGr7YR8vwBAylCoc7urGHbcK3 jsTl2PPa40AAqt07kUP7eEmM5n20ajAH9t7bZRsbBDBIuui4JCf6tpr2wMtLoE9FQi6z yoPHeGxDLbvDMoglimYMQPRoOk/7Fk51ilz7oX0uGgT2/VCpQKC4Fp9LFdvbf3iTmTXT eXemCEPvYvtYuFyKFnJM1gJug3qb72upXuzN9MHYYNnBEJY+70JXgvkQUJNN1xU84od9 MWyjlgjIPY8sjXM2c3W2EaOyQdznG2gX1IqNkYtWh409bn0bfupF5wXB1QIKjHSIId49 BhXQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=m5F7T0I8i9kVslFhvet0C2Cq/+ANjXtF6DL6MR2PLmI=; b=SumRGlCfXaNDYkWSYJnJPlLqKkLwTIOpFVRxXRvyyKDk24WBC2cB8c51fXbD5GbCgU HI0XIy9uwauhEUtbu4Yi8g19YPsl3MnV9gpT1i5fr05xtxvnOUp4f7R2jt4mcSWbFvsG 0R9rPkdqFhnqqGCQ+dNcL4tvgdxtIp9FwWp5/8Gx36xkjAir3v/9LbaGv6iokU0UcJmz /Rvt2iHdbPUdC//pvtlkJSU0+dFnIud/7km30YnByXcpeJ1moiD1tOH+3kDHix5I5Io1 LOZ7YceSj2hztrgF6M75895KDIJEHwM2PMuUyZ2OUjtsXxDt6CLFsRaFZ2a6iJcZ9L14 uOwA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=X4lVSZbF; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r193si1886576pfr.27.2019.08.30.05.18.55; Fri, 30 Aug 2019 05:18:55 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=X4lVSZbF; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728157AbfH3MSy (ORCPT + 8 others); Fri, 30 Aug 2019 08:18:54 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:39280 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727739AbfH3MSy (ORCPT ); Fri, 30 Aug 2019 08:18:54 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7UCIi0q119978; Fri, 30 Aug 2019 07:18:44 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1567167524; bh=m5F7T0I8i9kVslFhvet0C2Cq/+ANjXtF6DL6MR2PLmI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=X4lVSZbFHJa6bV8ehdf0y7ML+SrQVGW5w/d1sCo17kWjUasjyiWImc0dQg5r57r+K R7nwUiV79n8Vgq0u+oBbBiTfi41+GBp/yf80BISite3p1PAoyluDpZL4NY7dDWEkJz hqecFq0ZAs2tIpEExN+IiMHvyrNnkx1UtyFp3Suk= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7UCIiXS004799 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 30 Aug 2019 07:18:44 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 30 Aug 2019 07:18:44 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 30 Aug 2019 07:18:44 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7UCIP6O083824; Fri, 30 Aug 2019 07:18:42 -0500 From: Tero Kristo To: , , , , CC: , Subject: [PATCHv3 08/10] soc: ti: omap-prm: add dra7 PRM data Date: Fri, 30 Aug 2019 15:18:14 +0300 Message-ID: <20190830121816.30034-9-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190830121816.30034-1-t-kristo@ti.com> References: <20190830121816.30034-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add PRM instance data for dra7 family of SoCs. Initially this is just used to provide reset support. Signed-off-by: Tero Kristo --- drivers/soc/ti/omap_prm.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index bc0933315484..bb03afe1a95c 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -87,6 +87,19 @@ static const struct omap_prm_data omap4_prm_data[] = { { }, }; +static const struct omap_prm_data dra7_prm_data[] = { + { .name = "dsp1", .base = 0x4ae06400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, + { .name = "ipu", .base = 0x4ae06500, .rstctrl = 0x10, .rstst = 0x14, .clkdm_name = "ipu1", .rstmap = rst_map_012 }, + { .name = "core", .base = 0x4ae06700, .rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ipu2", .rstmap = rst_map_012 }, + { .name = "iva", .base = 0x4ae06f00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012 }, + { .name = "dsp2", .base = 0x4ae07b00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, + { .name = "eve1", .base = 0x4ae07b40, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, + { .name = "eve2", .base = 0x4ae07b80, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, + { .name = "eve3", .base = 0x4ae07bc0, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, + { .name = "eve4", .base = 0x4ae07c00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, + { }, +}; + static const struct omap_rst_map am3_per_rst_map[] = { { .rst = 1 }, { .rst = -1 }, @@ -107,6 +120,7 @@ static const struct omap_prm_data am3_prm_data[] = { static const struct of_device_id omap_prm_id_table[] = { { .compatible = "ti,omap4-prm-inst", .data = omap4_prm_data }, + { .compatible = "ti,dra7-prm-inst", .data = dra7_prm_data }, { .compatible = "ti,am3-prm-inst", .data = am3_prm_data }, { }, }; From patchwork Fri Aug 30 12:18:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 172694 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp543723ily; Fri, 30 Aug 2019 05:18:57 -0700 (PDT) X-Google-Smtp-Source: APXvYqwBx/PcnJvL2ItqqDys+mlCB9cvqS3YobuOyqCv5FUXHK2xGq1wYk77xPr+guczXDbMkdTy X-Received: by 2002:a17:90a:25a9:: with SMTP id k38mr1053045pje.12.1567167537109; Fri, 30 Aug 2019 05:18:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567167537; cv=none; d=google.com; s=arc-20160816; b=loKtojM2s84tAvrTmmEWYpSazHTocFahyt7N+ZymcDn8fPas0CGqnUoj4x5bfHb2b7 8o40sU7GuQKFtx70vQkPyQsBdY0os2SeU832+X2jiAgNcCAIZQjleN2roa3usrRXjMaD 3xzzCjxnOKvglWQWbyXdHKlZrMX/QVeVSC56bHzpAXfipwJwiDL9P/uddPKr76A+zhzj YkxAwhfs7TiETKQWqkFgA6hOAtlHYZhtziGq1Z2uTvtzeCQMCUYrpO0SKmhBIE5z8GyR K8vMaf7vuvKxv9SKM0sQ3nVWa3XMRfF1bGn/3t8BumqDfI10JGaOPXXgxYPbuRiL7lpl w5Aw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=QcXAIWwT6vALVIQWT9+wzZ4g0FGWezy41x40Ykr/5h8=; b=zgq4J5eo9R0nJNtG7YfEUSaieav5housqiIRpVIicuYueizNkD0U2PUCCOdBQFNo2e J3JEY3qcqjs0v3QiV8w59l8j8EQ4ohUQJ4pcawJva9O+whCgTC9HL/7qnfErcnK8jgsC qnV6mkHKclTCroOTs2AryCjiXSidy0NmKsSFgypktwpPk3ynBiOnk8g0BpIhWWDnVyUg jF2ctIr3OYFa66LwHhA3iyuezn6wVEbmJg83wz3P6d1BtOTbIYU1C+58Qtq0Q3E1eQRH pX/PjyFwhqDnCaYIqWy18uNe0yuSYL0jvc8JZTFPBt4AjSaO3T5cOzLgchBDzcaZUgV+ K3xw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="I4PG9PN/"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r193si1886576pfr.27.2019.08.30.05.18.56; Fri, 30 Aug 2019 05:18:57 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="I4PG9PN/"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728164AbfH3MS4 (ORCPT + 8 others); Fri, 30 Aug 2019 08:18:56 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:44100 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727739AbfH3MSz (ORCPT ); Fri, 30 Aug 2019 08:18:55 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7UCIkdG099668; Fri, 30 Aug 2019 07:18:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1567167526; bh=QcXAIWwT6vALVIQWT9+wzZ4g0FGWezy41x40Ykr/5h8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=I4PG9PN/uVRTBf6N2j482GBLeMSjbn/l7Bi34dQqzGnKebJRPgGg5DGLPsDk8xcOi lPo+G4fg+Kekb9B4YrVsdIPZI63LCyPK2OFOQtwtAAxDSLrKUhArXuluFvWoudIWtk +suFUmnpaaqYeIrnh6eaUzuPB1N6wfG0NTsb0hpA= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7UCIk0S031794 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 30 Aug 2019 07:18:46 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 30 Aug 2019 07:18:46 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Fri, 30 Aug 2019 07:18:46 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7UCIP6P083824; Fri, 30 Aug 2019 07:18:44 -0500 From: Tero Kristo To: , , , , CC: , Subject: [PATCHv3 09/10] soc: ti: omap-prm: add am4 PRM data Date: Fri, 30 Aug 2019 15:18:15 +0300 Message-ID: <20190830121816.30034-10-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190830121816.30034-1-t-kristo@ti.com> References: <20190830121816.30034-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add PRM instance data for am4 family of SoCs. Initially this is just used to provide reset support. Signed-off-by: Tero Kristo --- drivers/soc/ti/omap_prm.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index bb03afe1a95c..216a4b69a6c9 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -118,10 +118,30 @@ static const struct omap_prm_data am3_prm_data[] = { { }, }; +static const struct omap_rst_map am4_per_rst_map[] = { + { .rst = 1, .st = 0 }, + { .rst = -1 }, +}; + +static const struct omap_rst_map am4_device_rst_map[] = { + { .rst = 0, .st = 1 }, + { .rst = 1, .st = 0 }, + { .rst = -1 }, +}; + +static const struct omap_prm_data am4_prm_data[] = { + { .name = "gfx", .base = 0x44df0400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_0, .clkdm_name = "gfx_l3" }, + { .name = "per", .base = 0x44df0800, .rstctrl = 0x10, .rstst = 0x14, .rstmap = am4_per_rst_map, .clkdm_name = "pruss_ocp" }, + { .name = "wkup", .base = 0x44df2000, .rstctrl = 0x10, .rstst = 0x14, .rstmap = am3_wkup_rst_map, .flags = OMAP_PRM_HAS_NO_CLKDM }, + { .name = "device", .base = 0x44df4000, .rstctrl = 0x0, .rstst = 0x4, .rstmap = am4_device_rst_map, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM }, + { }, +}; + static const struct of_device_id omap_prm_id_table[] = { { .compatible = "ti,omap4-prm-inst", .data = omap4_prm_data }, { .compatible = "ti,dra7-prm-inst", .data = dra7_prm_data }, { .compatible = "ti,am3-prm-inst", .data = am3_prm_data }, + { .compatible = "ti,am4-prm-inst", .data = am4_prm_data }, { }, };