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[93.34.89.13]) by smtp.googlemail.com with ESMTPSA id a15-20020a5d508f000000b0033330846e76sm1496191wrt.86.2023.12.15.16.23.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Dec 2023 16:23:06 -0800 (PST) From: Christian Marangi To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Christian Marangi , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Tobias Waldekranz Subject: [net-next PATCH v4 1/4] dt-bindings: net: phy: Document new LEDs polarity property Date: Fri, 15 Dec 2023 22:22:41 +0100 Message-Id: <20231215212244.1658-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231215212244.1658-1-ansuelsmth@gmail.com> References: <20231215212244.1658-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Document new LEDs polarity property to define what mode the LED needs to be put to turn it on. Currently supported modes are: - active-low - active-high - active-low-tristate - active-high-tristate Mode is optional and if it's not defined, a default value is chosed by the driver. Signed-off-by: Christian Marangi --- Changes v4: - Drop support for global active-low - Rework to polarity option (for marvell10g series support) Changes v3: - Out of RFC Changes v2: - Add this patch .../devicetree/bindings/net/ethernet-phy.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml index 8fb2a6ee7e5b..282bf18f50fd 100644 --- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml @@ -225,6 +225,17 @@ properties: driver dependent and required for ports that define multiple LED for the same port. + polarity: + description: | + Electrical polarity and drive type for the LED to turn it + on. + $ref: /schemas/types.yaml#/definitions/string + enum: + - active-low + - active-high + - active-low-tristate + - active-high-tristate + required: - reg From patchwork Fri Dec 15 21:22:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 754978 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 720916FCC; Sat, 16 Dec 2023 00:23:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="WexT5Hx+" Received: by mail-wr1-f47.google.com with SMTP id ffacd0b85a97d-3363eba94ebso934945f8f.3; Fri, 15 Dec 2023 16:23:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1702686188; x=1703290988; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=fIXO+pxuufKHplD7mxtVHj98eE+3KzzT1cWSD2a1WH0=; b=WexT5Hx+2RHiSZhHk8+EQQjJe6NpR5tnISs8MFyVEWbhYASMuROqHepd4yGxrNcK0P yrsZ3GfzXEO6Tnrhz1It1T6PwWNJoPqGSTbUzYBP/Heybcin8HG9c05VYfsjshyQu3l5 uySpj7yyLpTr6Eu+Rhr1Z3IaIyNNqodXh1wQ17l8gAgHqUbcyeK5o5NRGpq/Ep96LNrL zm1S+sAY7CW8/ueB+mco9rXnMllXSncg4nR8/VQAYOZnFQlGti2KBOxtyRB+fOTrh/ME ElJA7MhbdQQG6T0bNxkQnshTuOq4052bgS9QAq2oMqnvOBGG5+VJ5qhdcnQi9Q+GFa/0 Suiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702686188; x=1703290988; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fIXO+pxuufKHplD7mxtVHj98eE+3KzzT1cWSD2a1WH0=; b=NrNs2Ybr1Z6/TKZyJOvAnCPkPuoSuVNEkC0CBJUVtoFEgEIvXv5ergw7BBfFltcIYO mZ1QTh/M9acolugpqGZ6FMgx050nEQONxo4nOhf3a9f08B7j4fvkG/DW0KIU3qziYQHT OXJx3rn5Lk9SDB7QaiDLXupAt0GLvrY8W6f71p+OtzUSO/gRV4Qjd2k6IOshTvE9R7n+ l6/Rw50jRelOSM6s6CISvoJcSw3traWmRBQoru2L70iQzBQgO7+dEE9Tca+skti2prgW AFUvv381PkRyR0JGjJPmYG7b2inVTQxzRbw3HNJ+M19tt2xxEbsAfzu42kVhdWnso+Bu w0iQ== X-Gm-Message-State: AOJu0YytedBfIXUO0CqC5VEFlRDtkbPNVrbo2AcMC0T1OO1pXI+QuNrI lsgzzATaCUICg1s8J5gPHUQ= X-Google-Smtp-Source: AGHT+IGGNAwF5C6fAi5f5M65yoR5PxJ0HKMu6Cq+CQ7xlx3zvLT6xpkIECMzGkkpva+pqlaf2lKq6Q== X-Received: by 2002:adf:fb07:0:b0:333:470f:cdf9 with SMTP id c7-20020adffb07000000b00333470fcdf9mr3190088wrr.93.1702686188487; Fri, 15 Dec 2023 16:23:08 -0800 (PST) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id a15-20020a5d508f000000b0033330846e76sm1496191wrt.86.2023.12.15.16.23.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Dec 2023 16:23:08 -0800 (PST) From: Christian Marangi To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Christian Marangi , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Tobias Waldekranz Subject: [net-next PATCH v4 2/4] net: phy: add support for PHY LEDs polarity modes Date: Fri, 15 Dec 2023 22:22:42 +0100 Message-Id: <20231215212244.1658-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231215212244.1658-1-ansuelsmth@gmail.com> References: <20231215212244.1658-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add support for PHY LEDs polarity modes. Some device might require special polarity mode for the LED to correctly work and those mode doesn't reflect what the PHY sets by default. An example is a PHY device that set LED to active high but the attached LEDs require to be active low to correctly work (and turn on when actually requested) PHY driver needs to declare .led_polarity_set() to configure LED polarity. Index of the LED is passed and the polarity mode in the enum. If a polarity is not set in DT and .led_polarity_set() is declared, PHY_LED_POLARITY_DEFAULT is passed as polarity mode to let the PHY driver decide a default polarity mode for the attached LEDs. This is needed for PHY that sets active high on reset and the common configuration is LEDs with active low polarity. Signed-off-by: Christian Marangi --- Changes v4: - Drop for global active-low - Rework to polarity option (for marvell10g series support) Changes v3: - Out of RFC Changes v2: - Add this patch drivers/net/phy/phy_device.c | 45 ++++++++++++++++++++++++++++++++++++ include/linux/phy.h | 25 ++++++++++++++++++++ 2 files changed, 70 insertions(+) diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index d8e9335d415c..b35b7a8717cc 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -43,6 +43,13 @@ MODULE_DESCRIPTION("PHY library"); MODULE_AUTHOR("Andy Fleming"); MODULE_LICENSE("GPL"); +static const char * const phy_led_polarity_mode_strings[] = { + [PHY_LED_POLARITY_ACTIVE_LOW] = "active-low", + [PHY_LED_POLARITY_ACTIVE_HIGH] = "active-high", + [PHY_LED_POLARITY_ACTIVE_LOW_TRISTATED] = "active-low-tristated", + [PHY_LED_POLARITY_ACTIVE_HIGH_TRISTATED] = "active-low-tristated", +}; + __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_basic_features) __ro_after_init; EXPORT_SYMBOL_GPL(phy_basic_features); @@ -3086,6 +3093,40 @@ static void phy_leds_unregister(struct phy_device *phydev) } } +static int of_phy_set_led_polarity(struct phy_device *phydev, + struct device_node *led, u32 index) +{ + const char *polarity_str; + int i, err; + + err = of_property_read_string(led, "polarity", &polarity_str); + if (err) { + if (err != -EINVAL) + return err; + + /* Nothing to do, polarity setting not supported */ + if (!phydev->drv->led_polarity_set) + return 0; + + /* Apply default polarity if supported */ + return phydev->drv->led_polarity_set(phydev, index, + PHY_LED_POLARITY_DEFAULT); + } + + for (i = 0; i < ARRAY_SIZE(phy_led_polarity_mode_strings); i++) + if (!strcmp(phy_led_polarity_mode_strings[i], polarity_str)) { + if (!phydev->drv->led_polarity_set) { + phydev_warn(phydev, "Ignoring LED polarity in DT. Setting polarity not supported\n"); + return 0; + } + + return phydev->drv->led_polarity_set(phydev, index, i); + } + + /* Unknown polarity mode declared */ + return -EINVAL; +} + static int of_phy_led(struct phy_device *phydev, struct device_node *led) { @@ -3109,6 +3150,10 @@ static int of_phy_led(struct phy_device *phydev, if (index > U8_MAX) return -EINVAL; + err = of_phy_set_led_polarity(phydev, led, index); + if (err) + return err; + phyled->index = index; if (phydev->drv->led_brightness_set) cdev->brightness_set_blocking = phy_led_set_brightness; diff --git a/include/linux/phy.h b/include/linux/phy.h index 6e7ebcc50b85..88ff4195bc4f 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -852,6 +852,16 @@ struct phy_plca_status { bool pst; }; +enum phy_led_polarity_modes { + PHY_LED_POLARITY_ACTIVE_LOW, + PHY_LED_POLARITY_ACTIVE_HIGH, + PHY_LED_POLARITY_ACTIVE_LOW_TRISTATED, + PHY_LED_POLARITY_ACTIVE_HIGH_TRISTATED, + + /* PHY driver apply a default value */ + PHY_LED_POLARITY_DEFAULT, +}; + /** * struct phy_led: An LED driven by the PHY * @@ -1145,6 +1155,21 @@ struct phy_driver { int (*led_hw_control_get)(struct phy_device *dev, u8 index, unsigned long *rules); + /** + * @led_polarity_set: Set the LED polarity mode + * @dev: PHY device which has the LED + * @index: Which LED of the PHY device + * @polarity_mode: LED polarity mode from enum + * + * Set PHY to requested LED polarity mode. + * + * If polarity mode PHY_LED_POLARITY_DEFAULT is passed, + * PHY driver should apply a default LED polarity mode. + * + * Returns 0, or an error code. + */ + int (*led_polarity_set)(struct phy_device *dev, int index, + enum phy_led_polarity_modes polarity_mode); }; #define to_phy_driver(d) container_of(to_mdio_common_driver(d), \ struct phy_driver, mdiodrv) From patchwork Fri Dec 15 21:22:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 755233 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8ECCEDDDE; Sat, 16 Dec 2023 00:23:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="PTNln9ZN" Received: by mail-wr1-f47.google.com with SMTP id ffacd0b85a97d-3363aa1b7d2so1031029f8f.0; Fri, 15 Dec 2023 16:23:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1702686190; x=1703290990; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=o6LKt+ontTXHu1XtoIYFtpLE+AnFf2w4c9A2s2xTblA=; b=PTNln9ZNxq47pubwHBj1zIFOaJ5+FSK4RY0IYUTONjGmDGs/cLf308TNgCs5fYsGil 1NPUk+/XYL1s1s+B5bIR6DWMP/cEgnmjDnPXzSOhXLS9Bmhf9jW1md0tmqGgQW3Uh7xc UyDbx5zkp0yJCwb52WQgA3YqaLogERLHmN3hKGZ/Z5B3q/VSz1PO7cmaNQ2pveNlC0Hf N408/Ng3jKLemY9XvaTO6pxvkm92cU5IG8sYHXjar8b4s9gJybnhAkxwYeJ+x/I+0mmF d4PgahQQ8e4xHryZ2yzVQu/7kC18QprbhIT1GDMjyeClUMDiHYnXSOS4vVGdp5a2eH/c p7dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702686190; x=1703290990; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=o6LKt+ontTXHu1XtoIYFtpLE+AnFf2w4c9A2s2xTblA=; b=bxqntpN7Qr5dh83/AI5dbVUapbfXIhaiURIcnMy3xTVXqbH4eHybb20Iav6Re8Ne55 B7Mcpvj0vhr94uwylrunbHFuLixhrAOQjWQXZODO6JN4vBiZhJZOojqX8zMlFzevVN3e 9UR8nMb5ymqR2eLQo+b4g+F9GZGOH2mp4Bc5JYi5Z627Q9v28bjRJgpueXwyaUmmFKTI BNuoYyV8vNXG5Nm02XgkL9KMsVflMg6PQ+v4a4915hOStr0yY8bCEAGbBE7+W+d2IWQ2 WfZ/iTM3uIyqSc/6RHkQCIzYQpbSJ46MPRt6P0fLo/499TG/y3tOUoXRFm3VvioTk3aB vdKQ== X-Gm-Message-State: AOJu0YyysONCggvTuAkh1sXHZCAE7QxSkObKTiCwk9g0avgcPtP8HkVg THBvc7LKsyWbG0+r/RCYYlc= X-Google-Smtp-Source: AGHT+IEO0rwiCNwmhPDW7n5j/1ISVzS6LcoZzZ9+6U11kTQWjyTepWNdOyQk42N8xD7EXAP8JAdumQ== X-Received: by 2002:adf:ffcb:0:b0:336:46bf:7d95 with SMTP id x11-20020adfffcb000000b0033646bf7d95mr1372823wrs.20.1702686189689; Fri, 15 Dec 2023 16:23:09 -0800 (PST) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id a15-20020a5d508f000000b0033330846e76sm1496191wrt.86.2023.12.15.16.23.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Dec 2023 16:23:09 -0800 (PST) From: Christian Marangi To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Christian Marangi , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Tobias Waldekranz Cc: Rob Herring Subject: [net-next PATCH v4 3/4] dt-bindings: net: Document QCA808x PHYs Date: Fri, 15 Dec 2023 22:22:43 +0100 Message-Id: <20231215212244.1658-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231215212244.1658-1-ansuelsmth@gmail.com> References: <20231215212244.1658-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add Documentation for QCA808x PHYs for the additional LED configuration for this PHY. Signed-off-by: Christian Marangi Reviewed-by: Rob Herring --- Changes v4: - Add Reviewed-by tag Changes v3: - Use compatible instead of select - Out of RFC Changes v2: - Fix License warning from checkpatch - Drop redundant Description phrase - Improve commit tile - Drop special property (generalized) .../devicetree/bindings/net/qca,qca808x.yaml | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/qca,qca808x.yaml diff --git a/Documentation/devicetree/bindings/net/qca,qca808x.yaml b/Documentation/devicetree/bindings/net/qca,qca808x.yaml new file mode 100644 index 000000000000..e2552655902a --- /dev/null +++ b/Documentation/devicetree/bindings/net/qca,qca808x.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/qca,qca808x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Atheros QCA808X PHY + +maintainers: + - Christian Marangi + +description: + QCA808X PHYs can have up to 3 LEDs attached. + All 3 LEDs are disabled by default. + 2 LEDs have dedicated pins with the 3rd LED having the + double function of Interrupt LEDs/GPIO or additional LED. + + By default this special PIN is set to LED function. + +allOf: + - $ref: ethernet-phy.yaml# + +properties: + compatible: + enum: + - ethernet-phy-id004d.d101 + +unevaluatedProperties: false + +examples: + - | + #include + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@0 { + compatible = "ethernet-phy-id004d.d101"; + reg = <0>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_WAN; + default-state = "keep"; + }; + }; + }; + }; From patchwork Fri Dec 15 21:22:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christian Marangi X-Patchwork-Id: 754977 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A775D37D2C; Sat, 16 Dec 2023 00:23:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ZCB+BQhA" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-40c517d0de5so13276035e9.0; Fri, 15 Dec 2023 16:23:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1702686191; x=1703290991; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=+8AybbXxKqnC8kXtSDfIGr8w4UB01xkSFYGdiTz7lkE=; b=ZCB+BQhAbUELe7pAmi/TDQ8J3bbAM1DhAWXZmMWDUl2ZvpYiKvIablFSu0ntbzcspb /YLrkiUtVZcpzUyvsbmIfQ95ZzTNWv6+wqIT9BOJECzL1CPXNAOcKli2+WzFs2WWlB7L Xq0DkTkApmElkEamQE3xAFCTCQuHIixMMOtAf/wTj3JVx2HlFACJPad88RD8+ttaUaFS 1rdWxVPBXmWnEyv+rPGoQr4HEx/LHnyeW1t3c56hztl16V5Gi7HKMdd2Zsvu8Vb/3Jws iaSzIwBHAojbVm87Ww+9NmZS6M7zdBUBGdDss9yeCG9gGvyvRoqFWoRypnFAQUul7vha yYjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702686191; x=1703290991; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+8AybbXxKqnC8kXtSDfIGr8w4UB01xkSFYGdiTz7lkE=; b=DbrnDi8xQ6LKpbD+WrK+bns8FoWFUQGUuzwccfxX5jUxotLmikm7o2UQfmCKcKCUvs oMqWT0FT5/CNzMlgvj5wfNF0EX12lCmBp5ZYY8FHhAkzTgwZ0MUPimG8DV8mA683ajZt NIWDh746LOGE3hSqwk2LzVnvbu1lFhVa5NjNAxALz78Z7mnc6fOe3nMEHfC+Oj8iSrJ8 JNOenQmwywM/aaRS0/cQjf/yPMU8vxVb3RthasEYNwuh4vIDQasTAtG5EziEeRrKBiNp NGuachfEmEr8QJ0DWfqB7cmmFN3Tn3jJQMUScp5k4HRstgnQMgwgRU+fe75pcok20SI1 RfNQ== X-Gm-Message-State: AOJu0Yx8WpA7Bu/kpxtqwvo1PEebEG29WcmmLSzYnYaa3V7PNTc8OL+m ZRuX+X8aJbwmHOjbLPlcdMhkgJHBWEg= X-Google-Smtp-Source: AGHT+IEUo0speA3kr6H7mvjUd5WQ49zXXeW0TH1HVM2TZqIPa1nHHjpHi5065EuexJ5T8Ht1+5PlQA== X-Received: by 2002:a7b:cbc7:0:b0:402:e68f:8896 with SMTP id n7-20020a7bcbc7000000b00402e68f8896mr6757244wmi.0.1702686190736; Fri, 15 Dec 2023 16:23:10 -0800 (PST) Received: from localhost.localdomain (93-34-89-13.ip49.fastwebnet.it. [93.34.89.13]) by smtp.googlemail.com with ESMTPSA id a15-20020a5d508f000000b0033330846e76sm1496191wrt.86.2023.12.15.16.23.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Dec 2023 16:23:10 -0800 (PST) From: Christian Marangi To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Christian Marangi , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Tobias Waldekranz Subject: [net-next PATCH v4 4/4] net: phy: at803x: add LED support for qca808x Date: Fri, 15 Dec 2023 22:22:44 +0100 Message-Id: <20231215212244.1658-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20231215212244.1658-1-ansuelsmth@gmail.com> References: <20231215212244.1658-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Add LED support for QCA8081 PHY. Documentation for this LEDs PHY is very scarce even with NDA access to Documentation for OEMs. Only the blink pattern are documented and are very confusing most of the time. No documentation is present about forcing the LED on/off or to always blink. Those settings were reversed by poking the regs and trying to find the correct bits to trigger these modes. Some bits mode are not clear and maybe the documentation option are not 100% correct. For the sake of LED support the reversed option are enough to add support for current LED APIs. Supported HW control modes are: - tx - rx - link10 - link100 - link1000 - half_duplex - full_duplex Also add support for LED polarity set to set LED polarity to active high or low. QSDK sets this value to high by default but PHY reset value doesn't have this enabled by default. QSDK also sets 2 additional bits but their usage is not clear, info about this is added in the header. It was verified that for correct function of the LED if active high is needed, only BIT 6 is needed. Signed-off-by: Christian Marangi --- Changes v4: - Rework to polarity option (for marvell10g series support) - Rework logic to enforce single PHY polarity mode Changes v3: - Out of RFC - Drop link_25000 and add TODO commends waiting for the netdev trigger thing to be merged (I will take care of sending a followup patch later) Changes v2: - Move to new led_polarity_set implementation - Drop special probe drivers/net/phy/at803x.c | 308 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 308 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index b9d3a26cf6dc..d36d3bea4739 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -272,6 +272,69 @@ #define QCA808X_CDT_STATUS_STAT_OPEN 2 #define QCA808X_CDT_STATUS_STAT_SHORT 3 +#define QCA808X_MMD7_LED2_CTRL 0x8074 +#define QCA808X_MMD7_LED2_FORCE_CTRL 0x8075 +#define QCA808X_MMD7_LED1_CTRL 0x8076 +#define QCA808X_MMD7_LED1_FORCE_CTRL 0x8077 +#define QCA808X_MMD7_LED0_CTRL 0x8078 +#define QCA808X_MMD7_LED_CTRL(x) (0x8078 - ((x) * 2)) + +/* LED hw control pattern is the same for every LED */ +#define QCA808X_LED_PATTERN_MASK GENMASK(15, 0) +#define QCA808X_LED_SPEED2500_ON BIT(15) +#define QCA808X_LED_SPEED2500_BLINK BIT(14) +/* Follow blink trigger even if duplex or speed condition doesn't match */ +#define QCA808X_LED_BLINK_CHECK_BYPASS BIT(13) +#define QCA808X_LED_FULL_DUPLEX_ON BIT(12) +#define QCA808X_LED_HALF_DUPLEX_ON BIT(11) +#define QCA808X_LED_TX_BLINK BIT(10) +#define QCA808X_LED_RX_BLINK BIT(9) +#define QCA808X_LED_TX_ON_10MS BIT(8) +#define QCA808X_LED_RX_ON_10MS BIT(7) +#define QCA808X_LED_SPEED1000_ON BIT(6) +#define QCA808X_LED_SPEED100_ON BIT(5) +#define QCA808X_LED_SPEED10_ON BIT(4) +#define QCA808X_LED_COLLISION_BLINK BIT(3) +#define QCA808X_LED_SPEED1000_BLINK BIT(2) +#define QCA808X_LED_SPEED100_BLINK BIT(1) +#define QCA808X_LED_SPEED10_BLINK BIT(0) + +#define QCA808X_MMD7_LED0_FORCE_CTRL 0x8079 +#define QCA808X_MMD7_LED_FORCE_CTRL(x) (0x8079 - ((x) * 2)) + +/* LED force ctrl is the same for every LED + * No documentation exist for this, not even internal one + * with NDA as QCOM gives only info about configuring + * hw control pattern rules and doesn't indicate any way + * to force the LED to specific mode. + * These define comes from reverse and testing and maybe + * lack of some info or some info are not entirely correct. + * For the basic LED control and hw control these finding + * are enough to support LED control in all the required APIs. + */ +#define QCA808X_LED_FORCE_MASK GENMASK(15, 13) +#define QCA808X_LED_FORCE_BLINK_8HZ FIELD_PREP(QCA808X_LED_FORCE_MASK, 0x7) +#define QCA808X_LED_FORCE_BLINK_4HZ FIELD_PREP(QCA808X_LED_FORCE_MASK, 0x6) +#define QCA808X_LED_FORCE_ON FIELD_PREP(QCA808X_LED_FORCE_MASK, 0x5) +#define QCA808X_LED_FORCE_OFF FIELD_PREP(QCA808X_LED_FORCE_MASK, 0x4) +/* HW control option are confusing: + * - 0x3 is 50% on 50% off at 4hz + * - 0x2 is 75% on 25% off at 4hz + * - 0x1 is 25% on 75% off at 4hz + * - 0x0 is 50% on 50% off at 8hz and is set by default + * This comes from visual check and may not be 100% correct. + */ +#define QCA808X_LED_HW_CONTROL_50_50_4HZ FIELD_PREP(QCA808X_LED_FORCE_MASK, 0x3) +#define QCA808X_LED_HW_CONTROL_75_25 FIELD_PREP(QCA808X_LED_FORCE_MASK, 0x2) +#define QCA808X_LED_HW_CONTROL_25_75 FIELD_PREP(QCA808X_LED_FORCE_MASK, 0x1) +#define QCA808X_LED_HW_CONTROL_50_50_8HZ FIELD_PREP(QCA808X_LED_FORCE_MASK, 0x0) + +#define QCA808X_MMD7_LED_POLARITY_CTRL 0x901a +/* QSDK sets by default 0x46 to this reg that sets BIT 6 for + * LED to active high. It's not clear what BIT 3 and BIT 4 does. + */ +#define QCA808X_LED_ACTIVE_HIGH BIT(6) + /* QCA808X 1G chip type */ #define QCA808X_PHY_MMD7_CHIP_TYPE 0x901d #define QCA808X_PHY_CHIP_TYPE_1G BIT(0) @@ -312,6 +375,7 @@ struct at803x_priv { struct regulator_dev *vddio_rdev; struct regulator_dev *vddh_rdev; u64 stats[ARRAY_SIZE(qca83xx_hw_stats)]; + int led_polarity_mode; }; struct at803x_context { @@ -672,6 +736,9 @@ static int at803x_probe(struct phy_device *phydev) if (!priv) return -ENOMEM; + /* Init LED polarity mode to -1 */ + priv->led_polarity_mode = -1; + phydev->priv = priv; ret = at803x_parse_dt(phydev); @@ -2128,6 +2195,241 @@ static void qca808x_link_change_notify(struct phy_device *phydev) QCA8081_PHY_FIFO_RSTN, phydev->link ? QCA8081_PHY_FIFO_RSTN : 0); } +static int qca808x_led_parse_netdev(struct phy_device *phydev, unsigned long rules, + u16 *offload_trigger) +{ + /* TODO: add link_2500 when added to netdev trigger */ + /* Parsing specific to netdev trigger */ + if (test_bit(TRIGGER_NETDEV_TX, &rules)) + *offload_trigger |= QCA808X_LED_TX_BLINK; + if (test_bit(TRIGGER_NETDEV_RX, &rules)) + *offload_trigger |= QCA808X_LED_RX_BLINK; + if (test_bit(TRIGGER_NETDEV_LINK_10, &rules)) + *offload_trigger |= QCA808X_LED_SPEED10_ON; + if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) + *offload_trigger |= QCA808X_LED_SPEED100_ON; + if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) + *offload_trigger |= QCA808X_LED_SPEED1000_ON; + if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules)) + *offload_trigger |= QCA808X_LED_HALF_DUPLEX_ON; + if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules)) + *offload_trigger |= QCA808X_LED_FULL_DUPLEX_ON; + + if (rules && !*offload_trigger) + return -EOPNOTSUPP; + + /* Enable BLINK_CHECK_BYPASS by default to make the LED + * blink even with duplex or speed mode not enabled. + */ + *offload_trigger |= QCA808X_LED_BLINK_CHECK_BYPASS; + + return 0; +} + +static int qca808x_led_hw_control_enable(struct phy_device *phydev, u8 index) +{ + u16 reg; + + if (index > 2) + return -EINVAL; + + reg = QCA808X_MMD7_LED_FORCE_CTRL(index); + + return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, + QCA808X_LED_FORCE_MASK); +} + +static int qca808x_led_hw_is_supported(struct phy_device *phydev, u8 index, + unsigned long rules) +{ + u16 offload_trigger = 0; + + if (index > 2) + return -EINVAL; + + return qca808x_led_parse_netdev(phydev, rules, &offload_trigger); +} + +static int qca808x_led_hw_control_set(struct phy_device *phydev, u8 index, + unsigned long rules) +{ + u16 reg, offload_trigger = 0; + int ret; + + if (index > 2) + return -EINVAL; + + reg = QCA808X_MMD7_LED_CTRL(index); + + ret = qca808x_led_parse_netdev(phydev, rules, &offload_trigger); + if (ret) + return ret; + + ret = qca808x_led_hw_control_enable(phydev, index); + if (ret) + return ret; + + return phy_modify_mmd(phydev, MDIO_MMD_AN, reg, + QCA808X_LED_PATTERN_MASK, + offload_trigger); +} + +static bool qca808x_led_hw_control_status(struct phy_device *phydev, u8 index) +{ + u16 reg; + int val; + + if (index > 2) + return false; + + reg = QCA808X_MMD7_LED_FORCE_CTRL(index); + + val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); + + return !(val & QCA808X_LED_FORCE_MASK); +} + +static int qca808x_led_hw_control_get(struct phy_device *phydev, u8 index, + unsigned long *rules) +{ + u16 reg; + int val; + + if (index > 2) + return -EINVAL; + + /* Check if we have hw control enabled */ + if (qca808x_led_hw_control_status(phydev, index)) + return -EINVAL; + + reg = QCA808X_MMD7_LED_CTRL(index); + + /* TODO: add link_2500 when added to netdev trigger */ + val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); + if (val & QCA808X_LED_TX_BLINK) + set_bit(TRIGGER_NETDEV_TX, rules); + if (val & QCA808X_LED_RX_BLINK) + set_bit(TRIGGER_NETDEV_RX, rules); + if (val & QCA808X_LED_SPEED10_ON) + set_bit(TRIGGER_NETDEV_LINK_10, rules); + if (val & QCA808X_LED_SPEED100_ON) + set_bit(TRIGGER_NETDEV_LINK_100, rules); + if (val & QCA808X_LED_SPEED1000_ON) + set_bit(TRIGGER_NETDEV_LINK_1000, rules); + if (val & QCA808X_LED_HALF_DUPLEX_ON) + set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules); + if (val & QCA808X_LED_FULL_DUPLEX_ON) + set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules); + + return 0; +} + +static int qca808x_led_hw_control_reset(struct phy_device *phydev, u8 index) +{ + u16 reg; + + if (index > 2) + return -EINVAL; + + reg = QCA808X_MMD7_LED_CTRL(index); + + return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, + QCA808X_LED_PATTERN_MASK); +} + +static int qca808x_led_brightness_set(struct phy_device *phydev, + u8 index, enum led_brightness value) +{ + u16 reg; + int ret; + + if (index > 2) + return -EINVAL; + + if (!value) { + ret = qca808x_led_hw_control_reset(phydev, index); + if (ret) + return ret; + } + + reg = QCA808X_MMD7_LED_FORCE_CTRL(index); + + return phy_modify_mmd(phydev, MDIO_MMD_AN, reg, + QCA808X_LED_FORCE_MASK, + value ? QCA808X_LED_FORCE_ON : + QCA808X_LED_FORCE_OFF); +} + +static int qca808x_led_blink_set(struct phy_device *phydev, u8 index, + unsigned long *delay_on, + unsigned long *delay_off) +{ + u16 reg; + int ret; + + if (index > 2) + return -EINVAL; + + reg = QCA808X_MMD7_LED_FORCE_CTRL(index); + + ret = phy_modify_mmd(phydev, MDIO_MMD_AN, reg, + QCA808X_LED_FORCE_MASK, + QCA808X_LED_FORCE_BLINK_4HZ); + if (ret) + return ret; + + /* We set blink to 4Hz, aka 250ms */ + *delay_on = 250 / 2; + *delay_off = 250 / 2; + + return 0; +} + +static int qca808x_led_polarity_set(struct phy_device *phydev, int index, + enum phy_led_polarity_modes polarity_mode) +{ + struct at803x_priv *priv = phydev->priv; + bool active_low; + int ret; + + switch (polarity_mode) { + case PHY_LED_POLARITY_ACTIVE_LOW: + active_low = true; + break; + case PHY_LED_POLARITY_ACTIVE_HIGH: + case PHY_LED_POLARITY_DEFAULT: + active_low = false; + break; + default: + return -EINVAL; + } + + /* PHY polarity is global and can't be set per LED. + * To detect this, check if last requested polarity mode + * match the new one. + */ + if (priv->led_polarity_mode >= 0 && + priv->led_polarity_mode != active_low) { + phydev_err(phydev, "PHY polarity is global. Mismatched polarity on different LED\n"); + return -EINVAL; + } + + /* Save the last PHY polarity mode */ + priv->led_polarity_mode = active_low; + + if (active_low) { + ret = phy_clear_bits_mmd(phydev, MDIO_MMD_AN, + QCA808X_MMD7_LED_POLARITY_CTRL, + QCA808X_LED_ACTIVE_HIGH); + } else { + ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, + QCA808X_MMD7_LED_POLARITY_CTRL, + QCA808X_LED_ACTIVE_HIGH); + } + + return ret; +} + static struct phy_driver at803x_driver[] = { { /* Qualcomm Atheros AR8035 */ @@ -2304,6 +2606,12 @@ static struct phy_driver at803x_driver[] = { .cable_test_start = qca808x_cable_test_start, .cable_test_get_status = qca808x_cable_test_get_status, .link_change_notify = qca808x_link_change_notify, + .led_brightness_set = qca808x_led_brightness_set, + .led_blink_set = qca808x_led_blink_set, + .led_hw_is_supported = qca808x_led_hw_is_supported, + .led_hw_control_set = qca808x_led_hw_control_set, + .led_hw_control_get = qca808x_led_hw_control_get, + .led_polarity_set = qca808x_led_polarity_set, }, }; module_phy_driver(at803x_driver);