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[45.79.221.244]) by smtp.gmail.com with ESMTPSA id r193sm976784ywe.8.2019.08.29.23.24.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Aug 2019 23:24:48 -0700 (PDT) From: Leo Yan To: Arnaldo Carvalho de Melo , Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Jiri Olsa , Namhyung Kim , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mike Leach , Robert Walker , Adrian Hunter Cc: Leo Yan Subject: [PATCH v1 1/3] perf cs-etm: Refactor instruction size handling Date: Fri, 30 Aug 2019 14:24:19 +0800 Message-Id: <20190830062421.31275-2-leo.yan@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190830062421.31275-1-leo.yan@linaro.org> References: <20190830062421.31275-1-leo.yan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org There has several code pieces need to know the instruction size, but now every place calculates the instruction size separately. This patch refactors to create a new function cs_etm__instr_size() as a central place to analyze the instruction length based on ISA type and instruction value. Signed-off-by: Leo Yan --- tools/perf/util/cs-etm.c | 44 +++++++++++++++++++++++++++------------- 1 file changed, 30 insertions(+), 14 deletions(-) -- 2.17.1 diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index b3a5daaf1a8f..882a0718033d 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -914,6 +914,26 @@ static inline int cs_etm__t32_instr_size(struct cs_etm_queue *etmq, return ((instrBytes[1] & 0xF8) >= 0xE8) ? 4 : 2; } +static inline int cs_etm__instr_size(struct cs_etm_queue *etmq, + u8 trace_chan_id, + enum cs_etm_isa isa, + u64 addr) +{ + int insn_len; + + /* + * T32 instruction size might be 32-bit or 16-bit, decide by calling + * cs_etm__t32_instr_size(). + */ + if (isa == CS_ETM_ISA_T32) + insn_len = cs_etm__t32_instr_size(etmq, trace_chan_id, addr); + /* Otherwise, A64 and A32 instruction size are always 32-bit. */ + else + insn_len = 4; + + return insn_len; +} + static inline u64 cs_etm__first_executed_instr(struct cs_etm_packet *packet) { /* Returns 0 for the CS_ETM_DISCONTINUITY packet */ @@ -938,19 +958,23 @@ static inline u64 cs_etm__instr_addr(struct cs_etm_queue *etmq, const struct cs_etm_packet *packet, u64 offset) { + int insn_len; + if (packet->isa == CS_ETM_ISA_T32) { u64 addr = packet->start_addr; while (offset > 0) { - addr += cs_etm__t32_instr_size(etmq, - trace_chan_id, addr); + addr += cs_etm__instr_size(etmq, trace_chan_id, + packet->isa, addr); offset--; } return addr; } - /* Assume a 4 byte instruction size (A32/A64) */ - return packet->start_addr + offset * 4; + /* Return instruction size for A32/A64 */ + insn_len = cs_etm__instr_size(etmq, trace_chan_id, + packet->isa, packet->start_addr); + return packet->start_addr + offset * insn_len; } static void cs_etm__update_last_branch_rb(struct cs_etm_queue *etmq, @@ -1090,16 +1114,8 @@ static void cs_etm__copy_insn(struct cs_etm_queue *etmq, return; } - /* - * T32 instruction size might be 32-bit or 16-bit, decide by calling - * cs_etm__t32_instr_size(). - */ - if (packet->isa == CS_ETM_ISA_T32) - sample->insn_len = cs_etm__t32_instr_size(etmq, trace_chan_id, - sample->ip); - /* Otherwise, A64 and A32 instruction size are always 32-bit. */ - else - sample->insn_len = 4; + sample->insn_len = cs_etm__instr_size(etmq, trace_chan_id, + packet->isa, sample->ip); cs_etm__mem_access(etmq, trace_chan_id, sample->ip, sample->insn_len, (void *)sample->insn); From patchwork Fri Aug 30 06:24:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 172676 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp187569ily; Thu, 29 Aug 2019 23:24:57 -0700 (PDT) X-Google-Smtp-Source: APXvYqwi1XtpMppLT+/8b8YwkjzRXKQife0qNFJIiCBi4U3PuXMivwcGKWzdtIGhN7MjxqYAk+Hc X-Received: by 2002:a17:902:e613:: with SMTP id cm19mr13113262plb.299.1567146296926; Thu, 29 Aug 2019 23:24:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567146296; cv=none; d=google.com; s=arc-20160816; b=Rv0jB/PL2OTqCkHN3M2nMG8P5klLOET83SDiUbk/qrwgmSkwLQcCKtTnpuQojwiCsy mht1Gkqo2aihaPBn/cjX/f73rM15J5Ug/46A/PG7Vi4VU2ISteHVsAlPHaMk4AaEpCAp V9VjgfN2xuSGYnjjGBy+zu3XszBrc4yJ6EtLEqDbSSr75Nxj6OtOpqLMoWn4ld07yycT CuaO+zupi8exwldcDnUhjMABLNH0eAfV+5cSJryBxOit6hJ75h7Yp33mbd0+J7cJQUB6 OrJexDq1KYU6H0hohYar2UsV5050luFWD9w3pr+uFiSNmAj1EEs7laRtlecSILwBnn76 cB4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=ELhnXlXvAFpwCV+V+b16yA2Nld0gK9Jz+4VNmTdBWdw=; b=UcSTv7av6+69ZIWWcAP8E9G1JQFul3XG5N2iIJBQyZT550+PYvw/FSuaPOlSZMQdgD lXFgihRp8RZ+ayU4z4m5t47H5jd9kI+iymaAhYSs3q19vsNSnLGqmi0nC0D07vDicTHM YMYaS2+WosTkKtpk1Mm5J1VswUsKVGTKwYcXpF1qFwSE7uOQ/p3AQxEIC4cfoR9Q7jAd OELYkuMbf6QQcCMaGuNHpCFn/7MTmUJ3jniQquCeWAMiYW6mF6t11ALBXaWRxq57tH5F Cixh10zjiOrLj3gu99YWq7nOBRYG3vxGMsZyIqblaiYmevcpJR88unGgmWnLKx4BxTi/ vnYg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="wPf/U6vB"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[45.79.221.244]) by smtp.gmail.com with ESMTPSA id r193sm976784ywe.8.2019.08.29.23.24.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Aug 2019 23:24:53 -0700 (PDT) From: Leo Yan To: Arnaldo Carvalho de Melo , Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Jiri Olsa , Namhyung Kim , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mike Leach , Robert Walker , Adrian Hunter Cc: Leo Yan Subject: [PATCH v1 2/3] perf cs-etm: Add callchain to instruction sample Date: Fri, 30 Aug 2019 14:24:20 +0800 Message-Id: <20190830062421.31275-3-leo.yan@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190830062421.31275-1-leo.yan@linaro.org> References: <20190830062421.31275-1-leo.yan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Firstly, this patch adds support for the thread stack; when every branch packet is coming we will push or pop the stack based on the sample flags. Secondly, based on the thread stack we can synthesize call chain for the instruction sample, this can be used by itrace option '--itrace=g'. Signed-off-by: Leo Yan --- tools/perf/util/cs-etm.c | 74 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 73 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 882a0718033d..ad573d3bd305 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -17,6 +17,7 @@ #include #include "auxtrace.h" +#include "callchain.h" #include "color.h" #include "cs-etm.h" #include "cs-etm-decoder/cs-etm-decoder.h" @@ -69,6 +70,7 @@ struct cs_etm_traceid_queue { size_t last_branch_pos; union perf_event *event_buf; struct thread *thread; + struct ip_callchain *chain; struct branch_stack *last_branch; struct branch_stack *last_branch_rb; struct cs_etm_packet *prev_packet; @@ -246,6 +248,16 @@ static int cs_etm__init_traceid_queue(struct cs_etm_queue *etmq, if (!tidq->prev_packet) goto out_free; + if (etm->synth_opts.callchain) { + size_t sz = sizeof(struct ip_callchain); + + /* Add 1 to callchain_sz for callchain context */ + sz += (etm->synth_opts.callchain_sz + 1) * sizeof(u64); + tidq->chain = zalloc(sz); + if (!tidq->chain) + goto out_free; + } + if (etm->synth_opts.last_branch) { size_t sz = sizeof(struct branch_stack); @@ -270,6 +282,7 @@ static int cs_etm__init_traceid_queue(struct cs_etm_queue *etmq, zfree(&tidq->last_branch); zfree(&tidq->prev_packet); zfree(&tidq->packet); + zfree(&tidq->chain); out: return rc; } @@ -541,6 +554,7 @@ static void cs_etm__free_traceid_queues(struct cs_etm_queue *etmq) zfree(&tidq->last_branch_rb); zfree(&tidq->prev_packet); zfree(&tidq->packet); + zfree(&tidq->chain); zfree(&tidq); /* @@ -1121,6 +1135,41 @@ static void cs_etm__copy_insn(struct cs_etm_queue *etmq, sample->insn_len, (void *)sample->insn); } +static void cs_etm__add_stack_event(struct cs_etm_queue *etmq, + struct cs_etm_traceid_queue *tidq) +{ + struct cs_etm_auxtrace *etm = etmq->etm; + u8 trace_chan_id = tidq->trace_chan_id; + int insn_len; + u64 from_ip, to_ip; + + if (etm->synth_opts.callchain || etm->synth_opts.thread_stack) { + + from_ip = cs_etm__last_executed_instr(tidq->prev_packet); + to_ip = cs_etm__first_executed_instr(tidq->packet); + + /* + * T32 instruction size might be 32-bit or 16-bit, decide by + * calling cs_etm__t32_instr_size(). + */ + if (tidq->prev_packet->isa == CS_ETM_ISA_T32) + insn_len = cs_etm__t32_instr_size(etmq, trace_chan_id, + from_ip); + /* Otherwise, A64 and A32 instruction size are always 32-bit. */ + else + insn_len = 4; + + thread_stack__event(tidq->thread, tidq->prev_packet->cpu, + tidq->prev_packet->flags, + from_ip, to_ip, insn_len, + etmq->buffer->buffer_nr); + } else { + thread_stack__set_trace_nr(tidq->thread, + tidq->prev_packet->cpu, + etmq->buffer->buffer_nr); + } +} + static int cs_etm__synth_instruction_sample(struct cs_etm_queue *etmq, struct cs_etm_traceid_queue *tidq, u64 addr, u64 period) @@ -1146,6 +1195,14 @@ static int cs_etm__synth_instruction_sample(struct cs_etm_queue *etmq, cs_etm__copy_insn(etmq, tidq->trace_chan_id, tidq->packet, &sample); + if (etm->synth_opts.callchain) { + thread_stack__sample(tidq->thread, tidq->packet->cpu, + tidq->chain, + etm->synth_opts.callchain_sz + 1, + sample.ip, etm->kernel_start); + sample.callchain = tidq->chain; + } + if (etm->synth_opts.last_branch) { cs_etm__copy_last_branch_rb(etmq, tidq); sample.branch_stack = tidq->last_branch; @@ -1329,6 +1386,8 @@ static int cs_etm__synth_events(struct cs_etm_auxtrace *etm, attr.sample_type &= ~(u64)PERF_SAMPLE_ADDR; } + if (etm->synth_opts.callchain) + attr.sample_type |= PERF_SAMPLE_CALLCHAIN; if (etm->synth_opts.last_branch) attr.sample_type |= PERF_SAMPLE_BRANCH_STACK; @@ -1397,6 +1456,9 @@ static int cs_etm__sample(struct cs_etm_queue *etmq, tidq->period_instructions = instrs_over; } + if (tidq->prev_packet->last_instr_taken_branch) + cs_etm__add_stack_event(etmq, tidq); + if (etm->sample_branches) { bool generate_sample = false; @@ -2596,7 +2658,17 @@ int cs_etm__process_auxtrace_info(union perf_event *event, } else { itrace_synth_opts__set_default(&etm->synth_opts, session->itrace_synth_opts->default_no_sample); - etm->synth_opts.callchain = false; + + etm->synth_opts.thread_stack = + session->itrace_synth_opts->thread_stack; + } + + if (etm->synth_opts.callchain && !symbol_conf.use_callchain) { + symbol_conf.use_callchain = true; + if (callchain_register_param(&callchain_param) < 0) { + symbol_conf.use_callchain = false; + etm->synth_opts.callchain = false; + } } err = cs_etm__synth_events(etm, session); From patchwork Fri Aug 30 06:24:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Leo Yan X-Patchwork-Id: 172677 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp187646ily; Thu, 29 Aug 2019 23:25:02 -0700 (PDT) X-Google-Smtp-Source: APXvYqxCT18qVT1dKRY7odmTfDqE+teWaQzEdhPJH+LyCnFKuAld+dqORKVZq3+EKA8VGor+vIZs X-Received: by 2002:aa7:9591:: with SMTP id z17mr16333160pfj.215.1567146302193; Thu, 29 Aug 2019 23:25:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567146302; cv=none; d=google.com; s=arc-20160816; b=p8fzZwvoWpydrQDEyyLh51ADjeDZUGw0aqaOFUTehByejDgnCW0hnklgCXU0Mq8BD5 hkJzmUuDDSmK7LrjVccoNsBzFiYlthEnqDxEQ6CkOglJxuYWlDlz2P4FpVrrwq+EITzS ceaRdk11HwFWE7xboBZYFiF8owyQn8aZNxxdYzpI4pUurhyu0AquZDB2C+YRH3BX5R8S szhAUbgjRtPugFdNW0hBa+AmLK+xbTp6atneYOEOXTqW+mwqPllZ0WvPY608Ft5N03VT QN13KvHnqPyGvGk0kjZPPwZY91HkD8NAopBN+MHJU8Kg+/VrTnvEOnLRgO/BVTe6lZeY 1ObA== ARC-Message-Signature: i=1; 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[45.79.221.244]) by smtp.gmail.com with ESMTPSA id r193sm976784ywe.8.2019.08.29.23.24.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Aug 2019 23:24:58 -0700 (PDT) From: Leo Yan To: Arnaldo Carvalho de Melo , Mathieu Poirier , Suzuki K Poulose , Alexander Shishkin , Jiri Olsa , Namhyung Kim , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Mike Leach , Robert Walker , Adrian Hunter Cc: Leo Yan Subject: [PATCH v1 3/3] perf cs-etm: Correct the packet usage for instruction sample Date: Fri, 30 Aug 2019 14:24:21 +0800 Message-Id: <20190830062421.31275-4-leo.yan@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190830062421.31275-1-leo.yan@linaro.org> References: <20190830062421.31275-1-leo.yan@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org It uses 'tidq->packet' rather than 'tidq->prev_packet' to generate instruction sample, comparing against the thread stack and the branch samples which are using the 'tidp->prev_packet', thus this leads the instruction sample to use one ahead packet than thread stack and branch samples. As result, the instruction's call chain can be wrongly displayed as below: main 1579 100 instructions: ffff000010214854 perf_event_update_userpage+0x4c ([kernel.kallsyms]) ffff000010214850 perf_event_update_userpage+0x48 ([kernel.kallsyms]) ffff000010219360 perf_swevent_add+0x88 ([kernel.kallsyms]) ffff0000102135f4 event_sched_in.isra.57+0xbc ([kernel.kallsyms]) ffff0000102137a0 group_sched_in+0x60 ([kernel.kallsyms]) ffff000010213b84 flexible_sched_in+0xfc ([kernel.kallsyms]) ffff00001020c0b4 visit_groups_merge+0x12c ([kernel.kallsyms]) In this log, the continuous two lines includes two functions, the up line contains the child function info and the bottom line contains its parent function, and so forth. But if review the first two lines: perf_event_update_userpage+0x4c => the sampled instruction perf_event_update_userpage+0x48 => the parent function's calling The child function and parent function is the same function perf_event_update_userpage(), but perf_event_update_userpage() isn't a recursive function, thus this calling sequence shouldn't never happen. This is caused by the instruction sample using the 'tidq->packet', but this packet is not handled yet by thread stack, the thread stack is delayed to handle one return packet for stack popping. To fix this issue, we can simply to use 'tidq->prev_packet' to generate the instruction sample, this allows the thread stack to push/pop properly for instruction sample. Finally, we can get below result: main 1579 100 instructions: ffff000010214854 perf_event_update_userpage+0x4c ([kernel.kallsyms]) ffff000010219360 perf_swevent_add+0x88 ([kernel.kallsyms]) ffff0000102135f4 event_sched_in.isra.57+0xbc ([kernel.kallsyms]) ffff0000102137a0 group_sched_in+0x60 ([kernel.kallsyms]) ffff000010213b84 flexible_sched_in+0xfc ([kernel.kallsyms]) ffff00001020c0b4 visit_groups_merge+0x12c ([kernel.kallsyms]) Signed-off-by: Leo Yan --- tools/perf/util/cs-etm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index ad573d3bd305..0bd2b3c48394 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -1414,7 +1414,7 @@ static int cs_etm__sample(struct cs_etm_queue *etmq, struct cs_etm_packet *tmp; int ret; u8 trace_chan_id = tidq->trace_chan_id; - u64 instrs_executed = tidq->packet->instr_count; + u64 instrs_executed = tidq->prev_packet->instr_count; tidq->period_instructions += instrs_executed; @@ -1445,7 +1445,7 @@ static int cs_etm__sample(struct cs_etm_queue *etmq, */ u64 offset = (instrs_executed - instrs_over - 1); u64 addr = cs_etm__instr_addr(etmq, trace_chan_id, - tidq->packet, offset); + tidq->prev_packet, offset); ret = cs_etm__synth_instruction_sample( etmq, tidq, addr, etm->instructions_sample_period);