From patchwork Fri Dec 15 08:56:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 755382 Received: from SHSQR01.spreadtrum.com (mx1.unisoc.com [222.66.158.135]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF46F17981; Fri, 15 Dec 2023 08:57:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=unisoc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=unisoc.com Received: from dlp.unisoc.com ([10.29.3.86]) by SHSQR01.spreadtrum.com with ESMTP id 3BF8upUE027909; Fri, 15 Dec 2023 16:56:51 +0800 (+08) (envelope-from Chunyan.Zhang@unisoc.com) Received: from SHDLP.spreadtrum.com (bjmbx02.spreadtrum.com [10.0.64.8]) by dlp.unisoc.com (SkyGuard) with ESMTPS id 4Ss2xL0H9zz2PfFhY; Fri, 15 Dec 2023 16:50:46 +0800 (CST) Received: from ubt.spreadtrum.com (10.0.73.88) by BJMBX02.spreadtrum.com (10.0.64.8) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Fri, 15 Dec 2023 16:56:49 +0800 From: Chunyan Zhang To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones CC: , , Baolin Wang , Orson Zhai , Chunyan Zhang , Chunyan Zhang , LKML Subject: [PATCH 1/4] dt-bindings: mfd: sprd: Add support for UMS9620 Date: Fri, 15 Dec 2023 16:56:27 +0800 Message-ID: <20231215085630.984892-2-chunyan.zhang@unisoc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231215085630.984892-1-chunyan.zhang@unisoc.com> References: <20231215085630.984892-1-chunyan.zhang@unisoc.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHCAS03.spreadtrum.com (10.0.1.207) To BJMBX02.spreadtrum.com (10.0.64.8) X-MAIL: SHSQR01.spreadtrum.com 3BF8upUE027909 Add bindings for Unisoc UMS9620 system global registers which provide register maps for clocks. Signed-off-by: Chunyan Zhang --- Documentation/devicetree/bindings/mfd/sprd,ums512-glbreg.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/sprd,ums512-glbreg.yaml b/Documentation/devicetree/bindings/mfd/sprd,ums512-glbreg.yaml index 996bd4a17ca3..a750fa23d7e7 100644 --- a/Documentation/devicetree/bindings/mfd/sprd,ums512-glbreg.yaml +++ b/Documentation/devicetree/bindings/mfd/sprd,ums512-glbreg.yaml @@ -19,7 +19,9 @@ description: properties: compatible: items: - - const: sprd,ums512-glbregs + - enum: + - sprd,ums512-glbregs + - sprd,ums9620-glbregs - const: syscon - const: simple-mfd From patchwork Fri Dec 15 08:56:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 754789 Received: from SHSQR01.spreadtrum.com (mx1.unisoc.com [222.66.158.135]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 511BE1798E; Fri, 15 Dec 2023 08:57:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=unisoc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=unisoc.com Received: from dlp.unisoc.com ([10.29.3.86]) by SHSQR01.spreadtrum.com with ESMTP id 3BF8uqDs028071; Fri, 15 Dec 2023 16:56:52 +0800 (+08) (envelope-from Chunyan.Zhang@unisoc.com) Received: from SHDLP.spreadtrum.com (bjmbx02.spreadtrum.com [10.0.64.8]) by dlp.unisoc.com (SkyGuard) with ESMTPS id 4Ss2xM29ggz2PDtHV; Fri, 15 Dec 2023 16:50:47 +0800 (CST) Received: from ubt.spreadtrum.com (10.0.73.88) by BJMBX02.spreadtrum.com (10.0.64.8) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Fri, 15 Dec 2023 16:56:50 +0800 From: Chunyan Zhang To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones CC: , , Baolin Wang , Orson Zhai , Chunyan Zhang , Chunyan Zhang , LKML Subject: [PATCH 2/4] dt-bindings: arm: Add compatible strings for Unisoc's UMS9620 Date: Fri, 15 Dec 2023 16:56:28 +0800 Message-ID: <20231215085630.984892-3-chunyan.zhang@unisoc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231215085630.984892-1-chunyan.zhang@unisoc.com> References: <20231215085630.984892-1-chunyan.zhang@unisoc.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHCAS03.spreadtrum.com (10.0.1.207) To BJMBX02.spreadtrum.com (10.0.64.8) X-MAIL: SHSQR01.spreadtrum.com 3BF8uqDs028071 Added bindings for Unisoc's UMS9620-2H10 board and UMS9620 SoC. Signed-off-by: Chunyan Zhang Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/sprd/sprd.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sprd/sprd.yaml b/Documentation/devicetree/bindings/arm/sprd/sprd.yaml index eaa67b8e0d6c..40fc3c8b9dce 100644 --- a/Documentation/devicetree/bindings/arm/sprd/sprd.yaml +++ b/Documentation/devicetree/bindings/arm/sprd/sprd.yaml @@ -35,6 +35,11 @@ properties: - sprd,ums512-1h10 - const: sprd,ums512 + - items: + - enum: + - sprd,ums9620-2h10 + - const: sprd,ums9620 + additionalProperties: true ... From patchwork Fri Dec 15 08:56:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 754788 Received: from SHSQR01.spreadtrum.com (mx1.unisoc.com [222.66.158.135]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 642BF1774C; Fri, 15 Dec 2023 08:57:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=unisoc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=unisoc.com Received: from dlp.unisoc.com ([10.29.3.86]) by SHSQR01.spreadtrum.com with ESMTP id 3BF8usLB028221; Fri, 15 Dec 2023 16:56:54 +0800 (+08) (envelope-from Chunyan.Zhang@unisoc.com) Received: from SHDLP.spreadtrum.com (bjmbx02.spreadtrum.com [10.0.64.8]) by dlp.unisoc.com (SkyGuard) with ESMTPS id 4Ss2xN3qR1z2PfHZn; Fri, 15 Dec 2023 16:50:48 +0800 (CST) Received: from ubt.spreadtrum.com (10.0.73.88) by BJMBX02.spreadtrum.com (10.0.64.8) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Fri, 15 Dec 2023 16:56:51 +0800 From: Chunyan Zhang To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones CC: , , Baolin Wang , Orson Zhai , Chunyan Zhang , Chunyan Zhang , LKML Subject: [PATCH 3/4] dt-bindings: serial: Add a new compatible string for UMS9620 Date: Fri, 15 Dec 2023 16:56:29 +0800 Message-ID: <20231215085630.984892-4-chunyan.zhang@unisoc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231215085630.984892-1-chunyan.zhang@unisoc.com> References: <20231215085630.984892-1-chunyan.zhang@unisoc.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHCAS03.spreadtrum.com (10.0.1.207) To BJMBX02.spreadtrum.com (10.0.64.8) X-MAIL: SHSQR01.spreadtrum.com 3BF8usLB028221 The UMS9620 also uses the same serial device with SC9836. Signed-off-by: Chunyan Zhang --- Documentation/devicetree/bindings/serial/sprd-uart.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/serial/sprd-uart.yaml b/Documentation/devicetree/bindings/serial/sprd-uart.yaml index 28ff77aa86c8..f4dbb6dc2b6e 100644 --- a/Documentation/devicetree/bindings/serial/sprd-uart.yaml +++ b/Documentation/devicetree/bindings/serial/sprd-uart.yaml @@ -20,6 +20,7 @@ properties: - sprd,sc9860-uart - sprd,sc9863a-uart - sprd,ums512-uart + - sprd,ums9620-uart - const: sprd,sc9836-uart - const: sprd,sc9836-uart From patchwork Fri Dec 15 08:56:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chunyan Zhang X-Patchwork-Id: 755381 Received: from SHSQR01.spreadtrum.com (mx1.unisoc.com [222.66.158.135]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B03F31798E; Fri, 15 Dec 2023 08:57:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=unisoc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=unisoc.com Received: from dlp.unisoc.com ([10.29.3.86]) by SHSQR01.spreadtrum.com with ESMTP id 3BF8ut02028363; Fri, 15 Dec 2023 16:56:55 +0800 (+08) (envelope-from Chunyan.Zhang@unisoc.com) Received: from SHDLP.spreadtrum.com (bjmbx02.spreadtrum.com [10.0.64.8]) by dlp.unisoc.com (SkyGuard) with ESMTPS id 4Ss2xP5Gp9z2PfFhY; Fri, 15 Dec 2023 16:50:49 +0800 (CST) Received: from ubt.spreadtrum.com (10.0.73.88) by BJMBX02.spreadtrum.com (10.0.64.8) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Fri, 15 Dec 2023 16:56:52 +0800 From: Chunyan Zhang To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones CC: , , Baolin Wang , Orson Zhai , Chunyan Zhang , Chunyan Zhang , LKML Subject: [PATCH 4/4] arm64: dts: sprd: Add support for Unisoc's UMS9620 Date: Fri, 15 Dec 2023 16:56:30 +0800 Message-ID: <20231215085630.984892-5-chunyan.zhang@unisoc.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231215085630.984892-1-chunyan.zhang@unisoc.com> References: <20231215085630.984892-1-chunyan.zhang@unisoc.com> Precedence: bulk X-Mailing-List: linux-serial@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SHCAS03.spreadtrum.com (10.0.1.207) To BJMBX02.spreadtrum.com (10.0.64.8) X-MAIL: SHSQR01.spreadtrum.com 3BF8ut02028363 Add basic support for Unisoc's UMS9620, with this patch, the board ums9620-2h10 can run into console. Signed-off-by: Chunyan Zhang --- arch/arm64/boot/dts/sprd/Makefile | 3 +- arch/arm64/boot/dts/sprd/ums9620-2h10.dts | 38 ++++ arch/arm64/boot/dts/sprd/ums9620.dtsi | 247 ++++++++++++++++++++++ 3 files changed, 287 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/sprd/ums9620-2h10.dts create mode 100644 arch/arm64/boot/dts/sprd/ums9620.dtsi diff --git a/arch/arm64/boot/dts/sprd/Makefile b/arch/arm64/boot/dts/sprd/Makefile index 97522fb0bf66..3ce81ad7116f 100644 --- a/arch/arm64/boot/dts/sprd/Makefile +++ b/arch/arm64/boot/dts/sprd/Makefile @@ -2,4 +2,5 @@ dtb-$(CONFIG_ARCH_SPRD) += sc9836-openphone.dtb \ sp9860g-1h10.dtb \ sp9863a-1h10.dtb \ - ums512-1h10.dtb + ums512-1h10.dtb \ + ums9620-2h10.dtb diff --git a/arch/arm64/boot/dts/sprd/ums9620-2h10.dts b/arch/arm64/boot/dts/sprd/ums9620-2h10.dts new file mode 100644 index 000000000000..b35671192a72 --- /dev/null +++ b/arch/arm64/boot/dts/sprd/ums9620-2h10.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Unisoc UMS9620-2h10 board DTS file + * + * Copyright (C) 2023, Unisoc Inc. + */ + +/dts-v1/; + +#include "ums9620.dtsi" + +/ { + model = "Unisoc UMS9620-2H10 Board"; + + compatible = "sprd,ums9620-2h10", "sprd,ums9620"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>; + }; + + chosen { + stdout-path = "serial1:921600n8"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/sprd/ums9620.dtsi b/arch/arm64/boot/dts/sprd/ums9620.dtsi new file mode 100644 index 000000000000..c63019b2fe51 --- /dev/null +++ b/arch/arm64/boot/dts/sprd/ums9620.dtsi @@ -0,0 +1,247 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Unisoc UMS9620 DTS file + * + * Copyright (C) 2023, Unisoc Inc. + */ + +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + core4 { + cpu = <&CPU4>; + }; + core5 { + cpu = <&CPU5>; + }; + core6 { + cpu = <&CPU6>; + }; + core7 { + cpu = <&CPU7>; + }; + }; + }; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + enable-method = "psci"; + cpu-idle-states = <&LIT_CORE_PD>; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + enable-method = "psci"; + cpu-idle-states = <&LIT_CORE_PD>; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; + enable-method = "psci"; + cpu-idle-states = <&LIT_CORE_PD>; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x300>; + enable-method = "psci"; + cpu-idle-states = <&LIT_CORE_PD>; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x0 0x400>; + enable-method = "psci"; + cpu-idle-states = <&BIG_CORE_PD>; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x0 0x500>; + enable-method = "psci"; + cpu-idle-states = <&BIG_CORE_PD>; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x0 0x600>; + enable-method = "psci"; + cpu-idle-states = <&BIG_CORE_PD>; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x0 0x700>; + enable-method = "psci"; + cpu-idle-states = <&BIG_CORE_PD>; + }; + }; + + idle-states { + entry-method = "psci"; + LIT_CORE_PD: cpu-pd-lit { + compatible = "arm,idle-state"; + entry-latency-us = <1000>; + exit-latency-us = <500>; + min-residency-us = <2500>; + local-timer-stop; + arm,psci-suspend-param = <0x00010000>; + }; + + BIG_CORE_PD: cpu-pd-big { + compatible = "arm,idle-state"; + entry-latency-us = <4000>; + exit-latency-us = <4000>; + min-residency-us = <10000>; + local-timer-stop; + arm,psci-suspend-param = <0x00010000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure PPI */ + , /* Physical Non-Secure PPI */ + , /* Virtual PPI */ + ; /* Hipervisor PPI */ + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = , + , + , + , + , + , + , + ; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@12000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x12000000 0 0x20000>, /* GICD */ + <0x0 0x12040000 0 0x100000>; /* GICR */ + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + redistributor-stride = <0x0 0x20000>; /* 128KB stride */ + #redistributor-regions = <1>; + interrupt-controller; + interrupts = ; + }; + + apb@20200000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x20200000 0x100000>; + + uart0: serial@0 { + compatible = "sprd,ums9620-uart", + "sprd,sc9836-uart"; + reg = <0 0x100>; + interrupts = ; + clocks = <&ext_26m>; + status = "disabled"; + }; + + uart1: serial@10000 { + compatible = "sprd,ums9620-uart", + "sprd,sc9836-uart"; + reg = <0x10000 0x100>; + interrupts = ; + clocks = <&ext_26m>; + status = "disabled"; + }; + }; + }; + + ext_26m: clk-26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "ext-26m"; + }; + + ext_4m: clk-4m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <4000000>; + clock-output-names = "ext-4m"; + }; + + ext_32k: clk-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "ext-32k"; + }; + + rco_100m: clk-100m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "rco-100m"; + }; + + dphy_312m5: dphy-312m5 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <312500000>; + clock-output-names = "dphy-312m5"; + }; + + dphy_416m7: dphy-416m7 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <416700000>; + clock-output-names = "dphy-416m7"; + }; +};