From patchwork Thu Dec 14 06:28:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 754628 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="WFEH4GWX" Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 496E3124; Wed, 13 Dec 2023 22:29:34 -0800 (PST) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BE4xHAQ021012; Thu, 14 Dec 2023 06:29:25 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=rl4RrSic2RPILQgcuXsxGN828QIT4dj5tIrRbc9tKS0=; b=WF EH4GWXGiOuNM0mEpfhxiynfU9f5S8SEofPRXzrsaigcX6gFD0TqugbZssv7n8xj9 3BIq3XRXAPjRBRPhW1Wa9OkI5aUInU3quFnoWV+j/EVAo3UdUB+BxCXPrlCvQGLG ebzx5HGAlvbqd7+7vZnfNAvXB8WSTPuWzVcv8xjbThrFfXP45G5eAMYXwtx2ijsI lRK0g4SrM3TKKXQR5e18CecRIuUY+L6wQVbgE9cRceiHPlETLVNIs4yxD4lPQYBj b4QXC5Ewi4dtpX0aU5PXKMCPA4e4TuwcRCQOBUj2PouJw8uE0/Vape8gw7y0XRnf oqO0C9T8/rWe4+s+Cw6w== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uyq9t0k72-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 06:29:24 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BE6TNPj007129 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 06:29:23 GMT Received: from hu-ipkumar-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 13 Dec 2023 22:29:16 -0800 From: Praveenkumar I To: , , , , , , , , , , , , , , , , , , , , , CC: , , , Subject: [PATCH 02/10] clk: qcom: ipq5332: Add separate clocks for PCIe and USB for Combo PHY Date: Thu, 14 Dec 2023 11:58:39 +0530 Message-ID: <20231214062847.2215542-3-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231214062847.2215542-1-quic_ipkumar@quicinc.com> References: <20231214062847.2215542-1-quic_ipkumar@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: syGSRi-2WLNyPPqr15UhKBZuG0EGVtIQ X-Proofpoint-GUID: syGSRi-2WLNyPPqr15UhKBZuG0EGVtIQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 mlxlogscore=953 suspectscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 priorityscore=1501 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140039 Qualcomm IPQ5332 has a combo PHY for PCIe and USB. Either one of the interface (PCIe/USB) can use this combo PHY and the PHY drivers are different for PCIe and USB. Hence separate the PCIe and USB pipe clock source from DT, and individual driver node can be used as a clock source separately in the gcc. Add separate enum for PCIe and USB pipe clock and change the parent in corresponding structures. Signed-off-by: Praveenkumar I --- drivers/clk/qcom/gcc-ipq5332.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c index f98591148a97..aa0f616c3b1b 100644 --- a/drivers/clk/qcom/gcc-ipq5332.c +++ b/drivers/clk/qcom/gcc-ipq5332.c @@ -25,7 +25,8 @@ enum { DT_SLEEP_CLK, DT_PCIE_2LANE_PHY_PIPE_CLK, DT_PCIE_2LANE_PHY_PIPE_CLK_X1, - DT_USB_PCIE_WRAPPER_PIPE_CLK, + DT_PCIE_WRAPPER_PIPE_CLK, + DT_USB_WRAPPER_PIPE_CLK, }; enum { @@ -728,7 +729,7 @@ static struct clk_regmap_phy_mux gcc_pcie3x1_0_pipe_clk_src = { .hw.init = &(struct clk_init_data) { .name = "gcc_pcie3x1_0_pipe_clk_src", .parent_data = &(const struct clk_parent_data) { - .index = DT_USB_PCIE_WRAPPER_PIPE_CLK, + .index = DT_PCIE_WRAPPER_PIPE_CLK, }, .num_parents = 1, .ops = &clk_regmap_phy_mux_ops, @@ -1072,7 +1073,7 @@ static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src = { .hw.init = &(struct clk_init_data) { .name = "gcc_usb0_pipe_clk_src", .parent_data = &(const struct clk_parent_data) { - .index = DT_USB_PCIE_WRAPPER_PIPE_CLK, + .index = DT_USB_WRAPPER_PIPE_CLK, }, .num_parents = 1, .ops = &clk_regmap_phy_mux_ops, From patchwork Thu Dec 14 06:28:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 754627 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Og9FCSyt" Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 35CD619D; Wed, 13 Dec 2023 22:29:48 -0800 (PST) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BE5rhmo013695; Thu, 14 Dec 2023 06:29:39 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=+bJsIiFNHY5aU+4zRAegfGTvThqxKaxMtSO0RkFserM=; b=Og 9FCSytvlaJqSJJoTEu1qxntQcJUVcxqPyXqefBw2KV3hA3DFCKxlFU7WoFvM8IhI /rgYeQEypJci0XKp1aVCCMdXejLSIajBKcfU+V0SwZ+8RdELhrCjKCqQO0khk4IV 97m43qhZhpdnISu0Xfju5UUg2wZmSXkrghuBuI/rnvD/AEFtRvoEsYdFkwaVoBMk uh9WtEspaiLBgV4nvttj8UoPWPsynCyj2noIeHKxTyfsT6xRLEul/0JAKLQKRcY8 CU/gAyqYKAuRP0/ttmJ0ycNTRTiH70MTM0dCm/R1zNx/5VuN1HEtNcL/vdvHg8yG 4pA5bfBuqsmalnrnam7w== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uyp4xgqfq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 06:29:39 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BE6TcpH021107 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 06:29:38 GMT Received: from hu-ipkumar-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 13 Dec 2023 22:29:31 -0800 From: Praveenkumar I To: , , , , , , , , , , , , , , , , , , , , , CC: , , , Subject: [PATCH 04/10] phy: qcom: Add support for Pipe clock rate from device data Date: Thu, 14 Dec 2023 11:58:41 +0530 Message-ID: <20231214062847.2215542-5-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231214062847.2215542-1-quic_ipkumar@quicinc.com> References: <20231214062847.2215542-1-quic_ipkumar@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: WPCDI7RAtvN8Ovli654D4dpVh1Nz__FM X-Proofpoint-ORIG-GUID: WPCDI7RAtvN8Ovli654D4dpVh1Nz__FM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=999 mlxscore=0 priorityscore=1501 malwarescore=0 adultscore=0 spamscore=0 suspectscore=0 phishscore=0 impostorscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140039 Qualcomm IPQ5332 has the same PCIe UNIPHY PHY with different pipe clock rate. Add support to define the pipe clock rate in device data. Signed-off-by: Praveenkumar I --- This patch depends on the below series which adds PCIe support in Qualcomm IPQ5018 https://lore.kernel.org/all/20231003120846.28626-1-quic_nsekar@quicinc.com/ drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c index 5ef6ae7276cf..9f9a03faf6fa 100644 --- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c +++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c @@ -54,6 +54,7 @@ struct uniphy_pcie_data { unsigned int phy_type; const struct uniphy_regs *init_seq; unsigned int init_seq_num; + unsigned int pipe_clk_rate; }; struct qcom_uniphy_pcie { @@ -117,6 +118,7 @@ static const struct uniphy_pcie_data ipq5018_2x2_data = { .phy_type = PHY_TYPE_PCIE_GEN2, .init_seq = ipq5018_regs, .init_seq_num = ARRAY_SIZE(ipq5018_regs), + .pipe_clk_rate = 125000000, }; static void qcom_uniphy_pcie_init(struct qcom_uniphy_pcie *phy) @@ -232,6 +234,7 @@ static int qcom_uniphy_pcie_get_resources(struct platform_device *pdev, static int phy_pipe_clk_register(struct qcom_uniphy_pcie *phy, struct device_node *np) { + const struct uniphy_pcie_data *data = phy->data; struct clk_fixed_rate *fixed; struct clk_init_data init = { }; int ret; @@ -247,7 +250,7 @@ static int phy_pipe_clk_register(struct qcom_uniphy_pcie *phy, return -ENOMEM; init.ops = &clk_fixed_rate_ops; - fixed->fixed_rate = 125000000; + fixed->fixed_rate = data->pipe_clk_rate; fixed->hw.init = &init; ret = devm_clk_hw_register(phy->dev, &fixed->hw); From patchwork Thu Dec 14 06:28:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 754626 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="ZE/b4bc7" Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3DFE4121; Wed, 13 Dec 2023 22:30:03 -0800 (PST) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BE5rRvB013098; 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Thu, 14 Dec 2023 06:29:53 GMT Received: from hu-ipkumar-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 13 Dec 2023 22:29:46 -0800 From: Praveenkumar I To: , , , , , , , , , , , , , , , , , , , , , CC: , , , Subject: [PATCH 06/10] phy: qcom: ipq5332: Add support for g3x1 and g3x2 PCIe PHYs Date: Thu, 14 Dec 2023 11:58:43 +0530 Message-ID: <20231214062847.2215542-7-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231214062847.2215542-1-quic_ipkumar@quicinc.com> References: <20231214062847.2215542-1-quic_ipkumar@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: uU5Uxie_b92n2qBO3Fv0wog4gufFbrNv X-Proofpoint-ORIG-GUID: uU5Uxie_b92n2qBO3Fv0wog4gufFbrNv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=999 mlxscore=0 priorityscore=1501 malwarescore=0 adultscore=0 spamscore=0 suspectscore=0 phishscore=0 impostorscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140039 Add support for single-lane and dual-lane PCIe UNIPHY found on Qualcomm IPQ5332 platform. This UNIPHY is similar to the one present in Qualcomm IPQ5018. Signed-off-by: Praveenkumar I --- This patch depends on the below series which adds PCIe support in Qualcomm IPQ5018 https://lore.kernel.org/all/20231003120846.28626-1-quic_nsekar@quicinc.com/ .../phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c index 9f9a03faf6fa..aa71b85eb50e 100644 --- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c +++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c @@ -34,6 +34,10 @@ #define SSCG_CTRL_REG_6 0xb0 #define PCS_INTERNAL_CONTROL_2 0x2d8 +#define PHY_CFG_PLLCFG 0x220 +#define PHY_CFG_EIOS_DTCT_REG 0x3e4 +#define PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME 0x3e8 + #define PHY_MODE_FIXED 0x1 enum qcom_uniphy_pcie_type { @@ -112,6 +116,21 @@ static const struct uniphy_regs ipq5018_regs[] = { }, }; +static const struct uniphy_regs ipq5332_regs[] = { + { + .offset = PHY_CFG_PLLCFG, + .val = 0x30, + }, + { + .offset = PHY_CFG_EIOS_DTCT_REG, + .val = 0x53ef, + }, + { + .offset = PHY_CFG_GEN3_ALIGN_HOLDOFF_TIME, + .val = 0xCf, + }, +}; + static const struct uniphy_pcie_data ipq5018_2x2_data = { .lanes = 2, .lane_offset = 0x800, @@ -121,6 +140,23 @@ static const struct uniphy_pcie_data ipq5018_2x2_data = { .pipe_clk_rate = 125000000, }; +static const struct uniphy_pcie_data ipq5332_x2_data = { + .lanes = 2, + .lane_offset = 0x800, + .phy_type = PHY_TYPE_PCIE_GEN3, + .init_seq = ipq5332_regs, + .init_seq_num = ARRAY_SIZE(ipq5332_regs), + .pipe_clk_rate = 250000000, +}; + +static const struct uniphy_pcie_data ipq5332_x1_data = { + .lanes = 1, + .phy_type = PHY_TYPE_PCIE_GEN3, + .init_seq = ipq5332_regs, + .init_seq_num = ARRAY_SIZE(ipq5332_regs), + .pipe_clk_rate = 250000000, +}; + static void qcom_uniphy_pcie_init(struct qcom_uniphy_pcie *phy) { const struct uniphy_pcie_data *data = phy->data; @@ -270,6 +306,14 @@ static const struct of_device_id qcom_uniphy_pcie_id_table[] = { .compatible = "qcom,ipq5018-uniphy-pcie-gen2x2", .data = &ipq5018_2x2_data, }, + { + .compatible = "qcom,ipq5332-uniphy-pcie-gen3x2", + .data = &ipq5332_x2_data, + }, + { + .compatible = "qcom,ipq5332-uniphy-pcie-gen3x1", + .data = &ipq5332_x1_data, + }, { /* Sentinel */ }, }; MODULE_DEVICE_TABLE(of, qcom_uniphy_pcie_id_table); From patchwork Thu Dec 14 06:28:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 754625 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="c1U2Xg+1" Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B556131; Wed, 13 Dec 2023 22:30:18 -0800 (PST) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BE1G3ii013046; Thu, 14 Dec 2023 06:30:09 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=WJr3Nkmd/Qw0LXUgVh1auTrBFZKq1cTU8dUnkpzDrVU=; b=c1 U2Xg+1F58F630Hu3p/unEOoG0oYgCeceNOMpLBTPFcAQZMeP7pkUMLAyBAnyRgWo A4OPV3z9jvC7l20095pXFT72Jmz6ewQJ8Ph0Ogj/O8ZSclp+DF0EecrNBg23IQDD 0T84zku3O4azNjLMRR1rQ7wbnKSyg+IjPcxo3iMu4bG6nmCzh4UBV3rPc8xkhDYS anRnvY85sAid4qPvJjeBQAcDdQSOsK+ON6AJuii3ZQpHGE9tXiaTypFVje8CrsUr PSFRusdy7bfqPjTSI5vGya6YwoRJzdakxbTUas4wgpG/80y3c+KuwFbL3hTYjN1I U2+ANv/dvO50VVaUJbCQ== Received: from nasanppmta05.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uyq9t0k9t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 06:30:09 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BE6U8pt006229 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 06:30:08 GMT Received: from hu-ipkumar-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 13 Dec 2023 22:30:00 -0800 From: Praveenkumar I To: , , , , , , , , , , , , , , , , , , , , , CC: , , , Subject: [PATCH 08/10] pci: qcom: Add support for IPQ5332 Date: Thu, 14 Dec 2023 11:58:45 +0530 Message-ID: <20231214062847.2215542-9-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231214062847.2215542-1-quic_ipkumar@quicinc.com> References: <20231214062847.2215542-1-quic_ipkumar@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: GUaimBjfFoMiK3fyMTlOIKmwFZNFsqnm X-Proofpoint-GUID: GUaimBjfFoMiK3fyMTlOIKmwFZNFsqnm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxscore=0 mlxlogscore=958 suspectscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 priorityscore=1501 phishscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140039 The Qualcomm IPQ5332 PCIe controller instances are based on SNPS core 5.90a with Gen3 Single-lane and Dual-lane support. The Qualcomm IP rev is 1.27.0 and hence using the 1_27_0 ops. Signed-off-by: Praveenkumar I --- This patch depends on the below series which adds PCIe support in Qualcomm IPQ9574 https://lore.kernel.org/all/20230519090219.15925-1-quic_devipriy@quicinc.com/ drivers/pci/controller/dwc/pcie-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 109df587234e..3d54de1a71df 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1642,6 +1642,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 }, { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 }, { .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 }, + { .compatible = "qcom,pcie-ipq5332", .data = &cfg_1_27_0 }, { .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 }, { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 }, { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 }, From patchwork Thu Dec 14 06:28:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 754624 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="JlpUzm31" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A4261BB; Wed, 13 Dec 2023 22:30:33 -0800 (PST) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BE6RaTm011805; Thu, 14 Dec 2023 06:30:24 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=97iArE/7fSpUEFf1nWhOfrrjPwTNcjVGC7vrxk+Z5PY=; b=Jl pUzm31S7Tc8NMcwNCtiSDsmK9h61Ll0sLrc8OuUF+mU6ZCEgB9S+ZEU8iGoSUvZC 4TzbOd/NTK64Q9tU7fYHrtBepBTTbMbMUYcusUTAm8EvA2xoqntHy/uNmkUhy3E8 /ajeO0Usc6n2SET0qhgcpnSUICW80iWVc9MczDGKrtPAtLXpzxGWyFlQxkJD9LOK mUzdqhF20654njCEvVa7fWbQxKB+RZMa0uKA3bcVXdkq8K5AQR824qirfPbIRuBG s7vEtZKH6Wx7m6Vw3Kk5v7GfqZbf9tZgzoUJqXP+1d/iYIJhDp9iQVYLVJEzDFcV 13G9HCtm8DnJGSAKnLHg== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uyqgt0jeq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 06:30:24 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BE6UNiV018007 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 06:30:23 GMT Received: from hu-ipkumar-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 13 Dec 2023 22:30:15 -0800 From: Praveenkumar I To: , , , , , , , , , , , , , , , , , , , , , CC: , , , Subject: [PATCH 10/10] arm64: dts: qcom: ipq5332: Enable PCIe phys and controllers Date: Thu, 14 Dec 2023 11:58:47 +0530 Message-ID: <20231214062847.2215542-11-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231214062847.2215542-1-quic_ipkumar@quicinc.com> References: <20231214062847.2215542-1-quic_ipkumar@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 9xfHIffaGkkmrwGB9V7CzBTBrvmfquZJ X-Proofpoint-ORIG-GUID: 9xfHIffaGkkmrwGB9V7CzBTBrvmfquZJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 mlxlogscore=827 mlxscore=0 clxscore=1015 spamscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140039 Enable the PCIe controller and PHY nodes for RDP 441. Signed-off-by: Praveenkumar I --- arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts | 74 +++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts index 846413817e9a..83eca8435cff 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts +++ b/arch/arm64/boot/dts/qcom/ipq5332-rdp441.dts @@ -62,4 +62,78 @@ data-pins { bias-pull-up; }; }; + + pcie0_default: pcie0-default-state { + clkreq-n-pins { + pins = "gpio37"; + function = "pcie0_clk"; + drive-strength = <8>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio38"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + output-low; + }; + + wake-n-pins { + pins = "gpio39"; + function = "pcie0_wake"; + drive-strength = <8>; + bias-pull-up; + }; + }; + + pcie1_default: pcie1-default-state { + clkreq-n-pins { + pins = "gpio46"; + function = "pcie1_clk"; + drive-strength = <8>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio47"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + output-low; + }; + + wake-n-pins { + pins = "gpio48"; + function = "pcie1_wake"; + drive-strength = <8>; + bias-pull-up; + }; + }; +}; + +&pcie0_phy { + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default>; + + perst-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 39 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default>; + + perst-gpios = <&tlmm 47 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 48 GPIO_ACTIVE_LOW>; + status = "okay"; };