From patchwork Thu Dec 14 09:48:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 754592 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Sjo6Lk4r" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7B335118; Thu, 14 Dec 2023 01:48:55 -0800 (PST) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BE5d0lK018068; Thu, 14 Dec 2023 09:48:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=gZ/G1pFW0dLa+8o+dWcun5klmauXu0uQjqsi4LtQX7Q=; b=Sj o6Lk4rsYuaoUSPimAUc94NrhgZqDwq+IEaFD3OG49W3DoEetkpMHS6Q1hMZCouaS aEc3fCd5RgI1XCop9qS1rRnRMXkRvtL9vr1MRJlijnKBo6JVl8ZMgcBn6H3E5UZ/ ZZb3/X7uLgaOlwjpIXhMFl5iEWlUZyBTOldodMW4dWXOmKHHOD448TDcAMAoJyYm sAmC/0Taf9FPJcaOWVa7WfitsstVbN0HCRWcqE89T1vxFeFQ8PVMoHa02Cd8UoTx DsFA4w8RBmu8/9gwhjO8OQ+ZI4Tf/WwDeLU9otxE8MBhKqKTgseTX+6SMuEdhUX4 af2sFsa0QoUl9I3uCL2Q== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uynre130q-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:48:41 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BE9me0E008508 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:48:40 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 01:48:36 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v7 03/14] net: phy: at803x: add QCA8084 ethernet phy support Date: Thu, 14 Dec 2023 17:48:02 +0800 Message-ID: <20231214094813.24690-4-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231214094813.24690-1-quic_luoj@quicinc.com> References: <20231214094813.24690-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: RhP1EfKtgo2pdt8Zq9Sf4r5t1XhGbXFR X-Proofpoint-GUID: RhP1EfKtgo2pdt8Zq9Sf4r5t1XhGbXFR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=965 suspectscore=0 impostorscore=0 phishscore=0 bulkscore=0 spamscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140065 Add qca8084 PHY support, which is four-port PHY with maximum link capability 2.5G, the features of each port is almost same as QCA8081 and slave seed config is not needed. Three kind of interface modes supported by qca8084. PHY_INTERFACE_MODE_10G_QXGMII, PHY_INTERFACE_MODE_2500BASEX and PHY_INTERFACE_MODE_SGMII. The PCS(serdes) and clock are also needed to be configured to bringup qca8084 PHY, which will be added in the pcs driver. The additional CDT configurations used for qca8084. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 49 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 37fb033e1c29..8dfdf2ff56a5 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -176,6 +176,7 @@ #define AT8030_PHY_ID_MASK 0xffffffef #define QCA8081_PHY_ID 0x004dd101 +#define QCA8084_PHY_ID 0x004dd180 #define QCA8327_A_PHY_ID 0x004dd033 #define QCA8327_B_PHY_ID 0x004dd034 @@ -1760,6 +1761,9 @@ static bool qca808x_is_prefer_master(struct phy_device *phydev) static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev) { + if (phydev_id_compare(phydev, QCA8084_PHY_ID)) + return false; + return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported); } @@ -1824,6 +1828,23 @@ static int qca808x_read_status(struct phy_device *phydev) return ret; if (phydev->link) { + /* There are two PCSs available for QCA8084, which support the + * following interface modes. + * + * 1. PHY_INTERFACE_MODE_10G_QXGMII utilizes PCS1 for all + * available 4 ports, which is for all link speeds. + * + * 2. PHY_INTERFACE_MODE_2500BASEX utilizes PCS0 for the + * fourth port, which is only for the link speed 2500M same + * as QCA8081. + * + * 3. PHY_INTERFACE_MODE_SGMII utilizes PCS0 for the fourth + * port, which is for the link speed 10M, 100M and 1000M same + * as QCA8081. + */ + if (phydev->interface == PHY_INTERFACE_MODE_10G_QXGMII) + return 0; + if (phydev->speed == SPEED_2500) phydev->interface = PHY_INTERFACE_MODE_2500BASEX; else @@ -1958,6 +1979,14 @@ static int qca808x_cable_test_start(struct phy_device *phydev) phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060); phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060); + if (phydev_id_compare(phydev, QCA8084_PHY_ID)) { + /* Adjust the positive and negative pulse thereshold of CDT */ + phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8075, 0xa060); + + /* Disable the near echo bypass */ + phy_modify_mmd(phydev, MDIO_MMD_PCS, 0x807f, BIT(15), 0); + } + return 0; } @@ -2227,6 +2256,25 @@ static struct phy_driver at803x_driver[] = { .cable_test_start = qca808x_cable_test_start, .cable_test_get_status = qca808x_cable_test_get_status, .link_change_notify = qca808x_link_change_notify, +}, { + /* Qualcomm QCA8084 */ + PHY_ID_MATCH_MODEL(QCA8084_PHY_ID), + .name = "Qualcomm QCA8084", + .flags = PHY_POLL_CABLE_TEST, + .config_intr = at803x_config_intr, + .handle_interrupt = at803x_handle_interrupt, + .get_tunable = at803x_get_tunable, + .set_tunable = at803x_set_tunable, + .set_wol = at803x_set_wol, + .get_wol = at803x_get_wol, + .get_features = qca808x_get_features, + .config_aneg = at803x_config_aneg, + .suspend = genphy_suspend, + .resume = genphy_resume, + .read_status = qca808x_read_status, + .soft_reset = qca808x_soft_reset, + .cable_test_start = qca808x_cable_test_start, + .cable_test_get_status = qca808x_cable_test_get_status, }, }; module_phy_driver(at803x_driver); @@ -2242,6 +2290,7 @@ static struct mdio_device_id __maybe_unused atheros_tbl[] = { { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) }, { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) }, + { PHY_ID_MATCH_MODEL(QCA8084_PHY_ID) }, { } }; From patchwork Thu Dec 14 09:48:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 754591 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="Q+6Kucqe" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3DDAA118; Thu, 14 Dec 2023 01:49:04 -0800 (PST) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BE8k2hR017630; Thu, 14 Dec 2023 09:48:50 GMT DKIM-Signature: v=1; a=rsa-sha256; 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Thu, 14 Dec 2023 09:48:49 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 01:48:45 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v7 05/14] net: phy: at803x: Add qca8084_config_init function Date: Thu, 14 Dec 2023 17:48:04 +0800 Message-ID: <20231214094813.24690-6-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231214094813.24690-1-quic_luoj@quicinc.com> References: <20231214094813.24690-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: QRAe3tA68AcDDTlUQBoC24ioP5h0tAK_ X-Proofpoint-ORIG-GUID: QRAe3tA68AcDDTlUQBoC24ioP5h0tAK_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 phishscore=0 mlxlogscore=999 mlxscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 bulkscore=0 impostorscore=0 adultscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140065 Configure MSE detect threshold and ADC clock edge invert. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 143f0d2e36a6..ba5d069ad351 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -280,6 +280,15 @@ #define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL 0x9072 #define QCA8081_PHY_FIFO_RSTN BIT(11) +/* QCA8084 ADC clock edge */ +#define QCA8084_ADC_CLK_SEL 0x8b80 +#define QCA8084_ADC_CLK_SEL_ACLK GENMASK(7, 4) +#define QCA8084_ADC_CLK_SEL_ACLK_FALL 0xf +#define QCA8084_ADC_CLK_SEL_ACLK_RISE 0x0 + +#define QCA8084_MSE_THRESHOLD 0x800a +#define QCA8084_MSE_THRESHOLD_2P5G_VAL 0x51c6 + MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); MODULE_AUTHOR("Matus Ujhelyi"); MODULE_LICENSE("GPL"); @@ -2085,6 +2094,26 @@ static void qca808x_link_change_notify(struct phy_device *phydev) QCA8081_PHY_FIFO_RSTN, phydev->link ? QCA8081_PHY_FIFO_RSTN : 0); } +static int qca8084_config_init(struct phy_device *phydev) +{ + int ret; + + /* Invert ADC clock edge */ + ret = at803x_debug_reg_mask(phydev, QCA8084_ADC_CLK_SEL, + QCA8084_ADC_CLK_SEL_ACLK, + FIELD_PREP(QCA8084_ADC_CLK_SEL_ACLK, + QCA8084_ADC_CLK_SEL_ACLK_FALL)); + if (ret < 0) + return ret; + + /* Adjust MSE threshold value to avoid link issue with + * some link partner. + */ + return phy_write_mmd(phydev, MDIO_MMD_PMAPMD, + QCA8084_MSE_THRESHOLD, + QCA8084_MSE_THRESHOLD_2P5G_VAL); +} + static struct phy_driver at803x_driver[] = { { /* Qualcomm Atheros AR8035 */ @@ -2281,6 +2310,7 @@ static struct phy_driver at803x_driver[] = { .soft_reset = qca808x_soft_reset, .cable_test_start = qca808x_cable_test_start, .cable_test_get_status = qca808x_cable_test_get_status, + .config_init = qca8084_config_init, }, }; module_phy_driver(at803x_driver); From patchwork Thu Dec 14 09:48:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 754590 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="hOlAVQCO" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C56E1AA; Thu, 14 Dec 2023 01:49:14 -0800 (PST) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BE5VDxc031722; Thu, 14 Dec 2023 09:49:00 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=t69PPg+jCem4K6Eo0WgGA6QNG+KxgQaYrvmj24AWmE8=; b=hO lAVQCOeP0+EFAlSzjzj63U3VKPaLC+rgRgf6hehkLrPxbNPKAlWBKRSmL4sWf4fA qLtquyAMT1/eD3X5jhVK2zxK03B9ToLujcoUmRzM0TMw/yJ65BJBO8JKFi3ycTQL C1FIbZ7rN/jw2EzkLmaP+mCWvhMGLE+E7GEqgvrep8SJwWnqltoFMFSiEmXCwWPK zZ7lYVBt5oPtTIHJuRBrIBiMR4QLfpGrBSRxtiPVns2NeISRqTrs1ThcJTxetIaf cc4mV3K3pWks1RNDgNVCGHfmAXNopoGVkRIsD69Y5QZUTz4jCtgaMxCVLbQgjcDc M9NTc2QHdaHa0rSoBrKA== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uyqgt0x70-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:48:59 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BE9mx25024099 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:48:59 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 01:48:54 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v7 07/14] net: phy: at803x: add the possible_interfaces Date: Thu, 14 Dec 2023 17:48:06 +0800 Message-ID: <20231214094813.24690-8-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231214094813.24690-1-quic_luoj@quicinc.com> References: <20231214094813.24690-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: enyKgFTJ0Q4_IgOjsAA-INSrHrCZby5p X-Proofpoint-ORIG-GUID: enyKgFTJ0Q4_IgOjsAA-INSrHrCZby5p X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 mlxlogscore=954 mlxscore=0 clxscore=1015 spamscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140065 When qca808x works on the interface mode sgmii or 2500base-x, the interface mode can be switched according to the PHY link speed. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index b6b41b1a4352..c186ef8e798f 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -2101,10 +2101,22 @@ static void qca808x_link_change_notify(struct phy_device *phydev) QCA8081_PHY_FIFO_RSTN, phydev->link ? QCA8081_PHY_FIFO_RSTN : 0); } +static void qca808x_fill_possible_interfaces(struct phy_device *phydev) +{ + unsigned long *possible = phydev->possible_interfaces; + + if (phydev->interface != PHY_INTERFACE_MODE_10G_QXGMII) { + __set_bit(PHY_INTERFACE_MODE_2500BASEX, possible); + __set_bit(PHY_INTERFACE_MODE_SGMII, possible); + } +} + static int qca8084_config_init(struct phy_device *phydev) { int ret; + qca808x_fill_possible_interfaces(phydev); + /* Invert ADC clock edge */ ret = at803x_debug_reg_mask(phydev, QCA8084_ADC_CLK_SEL, QCA8084_ADC_CLK_SEL_ACLK, From patchwork Thu Dec 14 09:48:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 754589 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="avuB8VK+" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A319B10E2; Thu, 14 Dec 2023 01:49:22 -0800 (PST) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BE5ebtr021783; Thu, 14 Dec 2023 09:49:09 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=Pv0bj9BwrtvC5bjKTWWscgwoj6oQ0HJW9ayhPrX1rpc=; b=av uB8VK+rZji8jFbuHXmSyXY5nWcKQdgZrYa3fhsrTJZfI5x18N29SlgGQPWry9Tw/ HgErdP463iQgVtyHKxZ3pVS203iiTYg6R1wCGCRKIh4gsTjkV9J7rvx8nfzELmQ8 tGUIxgg85Az4IxKQnII5pLwWkkRjCY8FLQnwOS6rRFsGES5xzQI8LL2ukmQlv9Rw Xd736LirDR3DUh8lw4w/1D93XXbGAbIpfqPn3AZ31Fwfy1hcBy9SjySyk9L6LDPN qjyee+H2eyi7VVh2WySVYW4oIcn26UUSEmRS5Hx+g1VMLrs/+wyrO010u5+vRtfL uw1fDA46r4F2SAGtpCsg== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uynre131p-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:49:09 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BE9n8WY001600 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:49:08 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 01:49:03 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v7 09/14] net: phy: at803x: set MDIO address of qca8084 PHY Date: Thu, 14 Dec 2023 17:48:08 +0800 Message-ID: <20231214094813.24690-10-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231214094813.24690-1-quic_luoj@quicinc.com> References: <20231214094813.24690-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: B344eEj8kRyMFwBGLtS16jb4hoxAoER7 X-Proofpoint-GUID: B344eEj8kRyMFwBGLtS16jb4hoxAoER7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=999 suspectscore=0 impostorscore=0 phishscore=0 bulkscore=0 spamscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140065 Program the MDIO address of qca8084 PHY and PCS device in the PHY probe function. The MDIO address of qca8084 device is configured according to the property "qcom,phy-addr-fixup" of phy node, which defines the MDIO address for 4 PHYs and 3 PCSes, each MDIO address occupies 5 bits in the config register. The MDIO address of qca8084 should be configured correctly before doing the clock initialization in the PHY probe function, so the property "reg" can't be used to configure the MDIO address of phy device one by one, the clock initialization will be configured with all 4 PHY devices in one PHY probe function. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 61 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 016e40e32982..a00c5950683c 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -303,6 +303,18 @@ #define QCA8084_HIGH_ADDR_PREFIX 0x18 #define QCA8084_LOW_ADDR_PREFIX 0x10 +#define QCA8084_PCS_CFG 0xc90f014 +#define QCA8084_PCS_ADDR0_MASK GENMASK(4, 0) +#define QCA8084_PCS_ADDR1_MASK GENMASK(9, 5) +#define QCA8084_PCS_ADDR2_MASK GENMASK(14, 10) + +#define QCA8084_EPHY_CFG 0xc90f018 +#define QCA8084_EPHY_ADDR0_MASK GENMASK(4, 0) +#define QCA8084_EPHY_ADDR1_MASK GENMASK(9, 5) +#define QCA8084_EPHY_ADDR2_MASK GENMASK(14, 10) +#define QCA8084_EPHY_ADDR3_MASK GENMASK(19, 15) +#define QCA8084_EPHY_LDO_EN GENMASK(21, 20) + MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); MODULE_AUTHOR("Matus Ujhelyi"); MODULE_LICENSE("GPL"); @@ -955,6 +967,51 @@ static int at803x_parse_dt(struct phy_device *phydev) return 0; } +static int qca8084_parse_and_set_phyaddr(struct phy_device *phydev) +{ + struct device_node *node; + u32 addr[7]; + int ret; + + node = phydev->mdio.dev.of_node; + + /* The property "qcom,phy-addr-fixup" is only defined in one + * PHY device tree node. + */ + ret = of_property_read_u32_array(node, "qcom,phy-addr-fixup", + addr, ARRAY_SIZE(addr)); + if (ret) + return ret == -EINVAL ? 0 : ret; + + /* There are 4 PHYs and 3 PCSes on qca8084 chip, each device address + * occupies 5 bits of the config register to customize the MDIO address. + */ + ret = qca8084_mii_modify(phydev, QCA8084_EPHY_CFG, + QCA8084_EPHY_ADDR0_MASK | + QCA8084_EPHY_ADDR1_MASK | + QCA8084_EPHY_ADDR2_MASK | + QCA8084_EPHY_ADDR3_MASK, + FIELD_PREP(QCA8084_EPHY_ADDR0_MASK, addr[0]) | + FIELD_PREP(QCA8084_EPHY_ADDR1_MASK, addr[1]) | + FIELD_PREP(QCA8084_EPHY_ADDR2_MASK, addr[2]) | + FIELD_PREP(QCA8084_EPHY_ADDR3_MASK, addr[3])); + if (ret) + return ret; + + return qca8084_mii_modify(phydev, QCA8084_PCS_CFG, + QCA8084_PCS_ADDR0_MASK | + QCA8084_PCS_ADDR1_MASK | + QCA8084_PCS_ADDR2_MASK, + FIELD_PREP(QCA8084_PCS_ADDR0_MASK, addr[4]) | + FIELD_PREP(QCA8084_PCS_ADDR1_MASK, addr[5]) | + FIELD_PREP(QCA8084_PCS_ADDR2_MASK, addr[6])); +} + +static int qca8084_probe(struct phy_device *phydev) +{ + return qca8084_parse_and_set_phyaddr(phydev); +} + static int at803x_probe(struct phy_device *phydev) { struct device *dev = &phydev->mdio.dev; @@ -967,6 +1024,9 @@ static int at803x_probe(struct phy_device *phydev) phydev->priv = priv; + if (phydev_id_compare(phydev, QCA8084_PHY_ID)) + return qca8084_probe(phydev); + ret = at803x_parse_dt(phydev); if (ret) return ret; @@ -2434,6 +2494,7 @@ static struct phy_driver at803x_driver[] = { PHY_ID_MATCH_MODEL(QCA8084_PHY_ID), .name = "Qualcomm QCA8084", .flags = PHY_POLL_CABLE_TEST, + .probe = at803x_probe, .config_intr = at803x_config_intr, .handle_interrupt = at803x_handle_interrupt, .get_tunable = at803x_get_tunable, From patchwork Thu Dec 14 09:48:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 754588 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="HwUP/3IY" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 74E281994; 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Thu, 14 Dec 2023 09:49:17 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BE9nHTL024433 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:49:17 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 01:49:12 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v7 11/14] net: phy: at803x: add qca808x initial config sequence Date: Thu, 14 Dec 2023 17:48:10 +0800 Message-ID: <20231214094813.24690-12-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231214094813.24690-1-quic_luoj@quicinc.com> References: <20231214094813.24690-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: WwWodg1rUzi9iUBdMCKl9kvLIYZ0l01Q X-Proofpoint-ORIG-GUID: WwWodg1rUzi9iUBdMCKl9kvLIYZ0l01Q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 phishscore=0 mlxlogscore=999 mlxscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 bulkscore=0 impostorscore=0 adultscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140065 After GPIO reset, these Ethernet clock sequence needs to be configured before reading the features of PHY, the Ethernet system clock works on 25MHZ. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 84 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 83 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 6a7a7111ff68..204f5ca6001c 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -1090,6 +1090,84 @@ static int qca8084_parse_dt(struct phy_device *phydev) return 0; } +static int qca8084_clock_config(struct phy_device *phydev) +{ + struct at803x_priv *priv; + int ret = 0; + + /* The ethernet clock IDs are only defined in one PHY device + * tree node, and these ethernet clocks only needs to be configured + * one time, which work on the clock rate 25MHZ. + */ + priv = phydev->priv; + if (!priv->clk[SRDS0_SYS_CLK]) + return 0; + + ret = clk_set_rate(priv->clk[SRDS0_SYS_CLK], 25000000); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[SRDS0_SYS_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[SRDS1_SYS_CLK]); + if (ret) + return ret; + + /* Reset PCS system clocks */ + reset_control_assert(priv->reset[SRDS0_SYS_RESET]); + reset_control_assert(priv->reset[SRDS1_SYS_RESET]); + fsleep(20000); + + reset_control_deassert(priv->reset[SRDS0_SYS_RESET]); + reset_control_deassert(priv->reset[SRDS1_SYS_RESET]); + + ret = clk_prepare_enable(priv->clk[GEPHY0_SYS_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[GEPHY1_SYS_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[GEPHY2_SYS_CLK]); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[GEPHY3_SYS_CLK]); + if (ret) + return ret; + + /* Reset ethernet system clocks */ + reset_control_assert(priv->reset[GEPHY0_SYS_RESET]); + reset_control_assert(priv->reset[GEPHY1_SYS_RESET]); + reset_control_assert(priv->reset[GEPHY2_SYS_RESET]); + reset_control_assert(priv->reset[GEPHY3_SYS_RESET]); + fsleep(20000); + + reset_control_deassert(priv->reset[GEPHY0_SYS_RESET]); + reset_control_deassert(priv->reset[GEPHY1_SYS_RESET]); + reset_control_deassert(priv->reset[GEPHY2_SYS_RESET]); + reset_control_deassert(priv->reset[GEPHY3_SYS_RESET]); + + /* Release ethernet DSP reset */ + reset_control_deassert(priv->reset[GEPHY0_RESET]); + reset_control_deassert(priv->reset[GEPHY1_RESET]); + reset_control_deassert(priv->reset[GEPHY2_RESET]); + reset_control_deassert(priv->reset[GEPHY3_RESET]); + reset_control_deassert(priv->reset[GEPHY_DSP_RESET]); + + /* Enable efuse loading into analog circuit */ + ret = qca8084_mii_modify(phydev, QCA8084_EPHY_CFG, + QCA8084_EPHY_LDO_EN, 0); + if (ret) + return ret; + + fsleep(10000); + return 0; +} + static int qca8084_probe(struct phy_device *phydev) { int ret; @@ -1098,7 +1176,11 @@ static int qca8084_probe(struct phy_device *phydev) if (ret) return ret; - return qca8084_parse_and_set_phyaddr(phydev); + ret = qca8084_parse_and_set_phyaddr(phydev); + if (ret) + return ret; + + return qca8084_clock_config(phydev); } static int at803x_probe(struct phy_device *phydev) From patchwork Thu Dec 14 09:48:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luo Jie X-Patchwork-Id: 754587 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="pUqDr1IA" Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 194F31BCD; Thu, 14 Dec 2023 01:49:39 -0800 (PST) Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 3BE9Q7hb029781; Thu, 14 Dec 2023 09:49:26 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= qcppdkim1; bh=B1iNr8ZoSL+9Nsxcj5DA5N199o4zb2A3hGCzRlJGaGY=; b=pU qDr1IAs4uZrFHYTL27NM3OUYM3gyIXR8ZKA3wuNVjZqJr3nUvtYhkoJwiX8v9Y59 ExADBYObOiIyjQsKfF5AbdWTCUqWSnnD13WphIZzNsHP0oQBWWeXbjwb8S0WAiPq Rb49NIkB5cQj1GXZD89bkroAvXIBsb/hO2/1xQPT+h4wqn4r1ZuSmLsEIdc6+D6L XraXgJxZ5xgadAB1vQfAc/NsVWrPriw+1on2Tb22DXFOqSFtk1h5WmU8GMAonWlc H5NOM5kNYHxff2yYAkTUXlN57dlaVITJ/0Z4AbJz7AsW9dn4UQUTULvnkWzsLxJk k27pEMtv54bjjT7Ke1Xg== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3uyp0p92wr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:49:26 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BE9nPBq007224 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 14 Dec 2023 09:49:25 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 14 Dec 2023 01:49:21 -0800 From: Luo Jie To: , , , , , , , , , , , , CC: , , , Subject: [PATCH v7 13/14] net: phy: at803x: configure qca8084 work mode Date: Thu, 14 Dec 2023 17:48:12 +0800 Message-ID: <20231214094813.24690-14-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231214094813.24690-1-quic_luoj@quicinc.com> References: <20231214094813.24690-1-quic_luoj@quicinc.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: JJmBKfLAsNLue1oyIUYX3IljNaKN31xX X-Proofpoint-GUID: JJmBKfLAsNLue1oyIUYX3IljNaKN31xX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_02,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxlogscore=999 mlxscore=0 priorityscore=1501 phishscore=0 impostorscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312140065 There are four kind of work modes supported by qca8084. 1. Quad PHYs work on 10g-qxgmii. 2. PHY1, PHY2, PHY3 wors on 10g-qxgmii, PHY4 works on sgmii. 3. Quad PHYs connected with internal MACs by GMII, which works on switch mode. 4. PHY1, PHY2, PHY3 connected with internal MACs by GMII, PHY4 works on sgmii. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 53 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 52 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 4499d78891d2..6bc80704949a 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -317,6 +317,13 @@ #define QCA8084_EPHY_ADDR3_MASK GENMASK(19, 15) #define QCA8084_EPHY_LDO_EN GENMASK(21, 20) +#define QCA8084_WORK_MODE_CFG 0xc90f030 +#define QCA8084_WORK_MODE_MASK GENMASK(5, 0) +#define QCA8084_WORK_MODE_QXGMII (BIT(5) | GENMASK(3, 0)) +#define QCA8084_WORK_MODE_QXGMII_PORT4_SGMII (BIT(5) | GENMASK(2, 0)) +#define QCA8084_WORK_MODE_SWITCH BIT(4) +#define QCA8084_WORK_MODE_SWITCH_PORT4_SGMII BIT(5) + MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); MODULE_AUTHOR("Matus Ujhelyi"); MODULE_LICENSE("GPL"); @@ -1231,6 +1238,46 @@ static int qca8084_common_clock_init(struct phy_device *phydev) return clk_prepare_enable(priv->clk[MDIO_MASTER_AHB_CLK]); } +static int qca8084_parse_and_set_work_mode(struct phy_device *phydev) +{ + struct device_node *node; + struct at803x_priv *priv; + u32 value, work_mode; + int ret; + + node = phydev->mdio.dev.of_node; + priv = phydev->priv; + + /* The property "qcom,phy-work-mode" is only defined in one + * PHY device tree node. + */ + ret = of_property_read_u32(node, "qcom,phy-work-mode", &value); + if (ret) + return ret == -EINVAL ? 0 : ret; + + switch (value) { + case 0: + work_mode = QCA8084_WORK_MODE_QXGMII; + break; + case 1: + work_mode = QCA8084_WORK_MODE_QXGMII_PORT4_SGMII; + break; + case 2: + work_mode = QCA8084_WORK_MODE_SWITCH; + break; + case 3: + work_mode = QCA8084_WORK_MODE_SWITCH_PORT4_SGMII; + break; + default: + phydev_err(phydev, "invalid qcom,phy-work-mode %d\n", value); + return -EINVAL; + } + + return qca8084_mii_modify(phydev, QCA8084_WORK_MODE_CFG, + QCA8084_WORK_MODE_MASK, + FIELD_PREP(QCA8084_WORK_MODE_MASK, work_mode)); +} + static int qca8084_probe(struct phy_device *phydev) { int ret; @@ -1247,7 +1294,11 @@ static int qca8084_probe(struct phy_device *phydev) if (ret) return ret; - return qca8084_common_clock_init(phydev); + ret = qca8084_common_clock_init(phydev); + if (ret) + return ret; + + return qca8084_parse_and_set_work_mode(phydev); } static int at803x_probe(struct phy_device *phydev)