From patchwork Thu Aug 29 16:16:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 172634 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2449769ily; Thu, 29 Aug 2019 09:16:44 -0700 (PDT) X-Google-Smtp-Source: APXvYqwNcsKfNVDIac2R5G/HywOWrucjBnXrEWTyS+Qgttgbdk5p5Xim14A2J0nqdl0DWkgJpdUG X-Received: by 2002:a17:90a:c503:: with SMTP id k3mr10826258pjt.134.1567095404849; Thu, 29 Aug 2019 09:16:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567095404; cv=none; d=google.com; s=arc-20160816; b=JRAQcLM3km4/u4gVnHiKBV2Oah2mtPfwPEzpoEDBXBfmMBb3vNb0HP/9HSf+5/MQh+ lzjxNQWJqszA+zZyAW7xlHo7klc9FSyWdd6WT5quo87lSrFDv5FdTEiqKNkXO5NNYVCx zM61NGpihqPlPj5I+4euSxTwTCr09uM36d4/mTNX9jxISQwmS5UU0XcgnCl+hUFuCmn3 +V3ZOziFVZCNqozcRr765/hO0+OxCBdE3ztVAGifGuLor2n+CxBarBHcVRLK6MsnPOL1 ivCjglGTfiMVq6rtVx3ziiXslFeQ9TqjbiMKkErPF4Kigi4TAdwuxTPOr7tD05AfeLis Rmrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=LRSXXM/9Hjh3g9tVzGv7Uh9K2mMpn/F7sp2YRf04TcA=; b=kkuFglFAH2a8fwyJjFxdHfHoQsmwLPjmHJy/qP/cfgIaahGGSwX41ox1VFOg+/woSq CltCqDdC7dEf8EYtf9qHLp3tEROkS4plZpP2x0ghQTpA7P343TEiK83vUN4Pz10QMCVy yA+S11Nqokg2rGV2iRaYq4F0CPNd/5zRwF529uFGpyO/gZsLRTs9FsethcuVrO0xkqIX DJdK2FXI2q85kSDATu6Givsc1RMHFtwDAkKyFWdckUOR1jC4EUDg47Cg5uJbsTXJg+AR 8cvkeZ25MIrmZeml8NCsovfBFvkMrvbD3MXGLK1VWBbwRa91x5GvKtmbzMzmPKu3nKvX jRzg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=iUy5GOB3; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id q13sm3915424wmq.30.2019.08.29.09.16.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Aug 2019 09:16:40 -0700 (PDT) From: Jerome Brunet To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Kevin Hilman Cc: Jerome Brunet , linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] dt-bindings: interrupt-controller: new binding for the meson sm1 SoCs Date: Thu, 29 Aug 2019 18:16:34 +0200 Message-Id: <20190829161635.25067-2-jbrunet@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190829161635.25067-1-jbrunet@baylibre.com> References: <20190829161635.25067-1-jbrunet@baylibre.com> MIME-Version: 1.0 X-Patchwork-Bot: notify Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update the dt-binding to add support for the sm1 SoC family in the amlogic GPIO interrupt controller driver. Signed-off-by: Jerome Brunet --- .../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt | 1 + 1 file changed, 1 insertion(+) -- 2.21.0 diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt index 7d531d5fff29..684bb1cd75ec 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt @@ -16,6 +16,7 @@ Required properties: "amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912) "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X) "amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2) + "amlogic,meson-sm1-gpio-intc" for SM1 SoCs (S905D3, S905X3, S905Y3) - reg : Specifies base physical address and size of the registers. - interrupt-controller : Identifies the node as an interrupt controller. - #interrupt-cells : Specifies the number of cells needed to encode an From patchwork Thu Aug 29 16:16:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 172635 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp2449814ily; Thu, 29 Aug 2019 09:16:47 -0700 (PDT) X-Google-Smtp-Source: APXvYqzbUiNE5/LF+DoKKCwvwp4XgpHAeaCb7g1PH2ofRo28E8EhYKCoyi2+7soineQBheqf+Dp3 X-Received: by 2002:a63:e62:: with SMTP id 34mr8882644pgo.331.1567095406792; Thu, 29 Aug 2019 09:16:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567095406; cv=none; d=google.com; s=arc-20160816; b=n2T9z/mzK7TfeBnwqADtJ9gFjm+ucS0+JLU2q2j8gHb1U8dpUYNHKRVPIvQbNPTZU8 b289iPUKG+rUNZMBEWOOwMhZRt/xGKd4vTXgNwAROgsBfkG2Qqm5170j7ZP0RJWLY8dJ Nd2ZI2lYjviUOzfG582Q9+gwV7NH/spw5i1ZR0Ace8/ykP/Z4NOclEsQcefdgEKKtMhl zkDOhBoQpDcFJ4HwY30gAOAnLvN4Vfoq0ta6m7zJ5bSiwif8uP5HSu8v1uJ2fPMLmpmB TGsFjjGR0oyGa6bOe00sFV7C+qxCywk2lh6sKuezqo5wGQtPXs3PGMxcvPgrOCpsyA4f SKLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FmQNGjfdBr23Vmw3dpbgVM+854E1+2Ni006e4CpQSgY=; b=xkk3lsGyPXed70dJzEaBS0lN19WKQ0Lf3n1Sqx00enTCe+oSQg9aeIhaFDLU8bSSH/ TqddnnfklSqA29CgT1LGAC6G0wUnq0TLzSDAJD9bxEQrQT5IPCWFKd0o/cP3MfNHwIzC +vlaUa3V9pusz335z/1O27aEaCKJO5yUH4h0dK2cVabXaSMKnCXl3hSNBYWMdA6UFs4w Nf4nqs49NV8GBN3JfaR+i2oFBuRUo7h8JuRV1BDjsKByMMr1PTk6CsCQQVP4aXiFTdJS itATBITN1G5haaF+pkr05Vw/OP9jzMWRG+pqNu7kSzaZJpTSG+TQFjtU/4LYt/GUT/wb b8NA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=CekDSk1M; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[90.63.244.31]) by smtp.googlemail.com with ESMTPSA id q13sm3915424wmq.30.2019.08.29.09.16.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Aug 2019 09:16:41 -0700 (PDT) From: Jerome Brunet To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Kevin Hilman Cc: Jerome Brunet , linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] irqchip/meson-gpio: Add support for meson sm1 SoCs Date: Thu, 29 Aug 2019 18:16:35 +0200 Message-Id: <20190829161635.25067-3-jbrunet@baylibre.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190829161635.25067-1-jbrunet@baylibre.com> References: <20190829161635.25067-1-jbrunet@baylibre.com> MIME-Version: 1.0 X-Patchwork-Bot: notify Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The meson sm1 SoCs uses the same type of GPIO interrupt controller IP block as the other meson SoCs, A total of 100 pins can be spied on: - 223:100 undefined (no interrupt) - 99:97 3 pins on bank GPIOE - 96:77 20 pins on bank GPIOX - 76:61 16 pins on bank GPIOA - 60:53 8 pins on bank GPIOC - 52:37 16 pins on bank BOOT - 36:28 9 pins on bank GPIOH - 27:12 16 pins on bank GPIOZ - 11:0 12 pins in the AO domain Mapping is the same as the g12a family but the sm1 controller allows to trig an irq on both edges of the input signal. This was not possible with the previous SoCs families Signed-off-by: Jerome Brunet --- drivers/irqchip/irq-meson-gpio.c | 52 +++++++++++++++++++++++--------- 1 file changed, 38 insertions(+), 14 deletions(-) -- 2.21.0 diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c index dcdc23b9dce6..829084b568fa 100644 --- a/drivers/irqchip/irq-meson-gpio.c +++ b/drivers/irqchip/irq-meson-gpio.c @@ -24,14 +24,25 @@ #define REG_PIN_47_SEL 0x08 #define REG_FILTER_SEL 0x0c -#define REG_EDGE_POL_MASK(x) (BIT(x) | BIT(16 + (x))) +/* + * Note: The S905X3 datasheet reports that BOTH_EDGE is controlled by + * bits 24 to 31. Tests on the actual HW show that these bits are + * stuck at 0. Bits 8 to 15 are responsive and have the expected + * effect. + */ #define REG_EDGE_POL_EDGE(x) BIT(x) #define REG_EDGE_POL_LOW(x) BIT(16 + (x)) +#define REG_BOTH_EDGE(x) BIT(8 + (x)) +#define REG_EDGE_POL_MASK(x) ( \ + REG_EDGE_POL_EDGE(x) | \ + REG_EDGE_POL_LOW(x) | \ + REG_BOTH_EDGE(x)) #define REG_PIN_SEL_SHIFT(x) (((x) % 4) * 8) #define REG_FILTER_SEL_SHIFT(x) ((x) * 4) struct meson_gpio_irq_params { unsigned int nr_hwirq; + bool support_edge_both; }; static const struct meson_gpio_irq_params meson8_params = { @@ -54,6 +65,11 @@ static const struct meson_gpio_irq_params axg_params = { .nr_hwirq = 100, }; +static const struct meson_gpio_irq_params sm1_params = { + .nr_hwirq = 100, + .support_edge_both = true, +}; + static const struct of_device_id meson_irq_gpio_matches[] = { { .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params }, { .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params }, @@ -61,11 +77,12 @@ static const struct of_device_id meson_irq_gpio_matches[] = { { .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params }, { .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params }, { .compatible = "amlogic,meson-g12a-gpio-intc", .data = &axg_params }, + { .compatible = "amlogic,meson-sm1-gpio-intc", .data = &sm1_params }, { } }; struct meson_gpio_irq_controller { - unsigned int nr_hwirq; + const struct meson_gpio_irq_params *params; void __iomem *base; u32 channel_irqs[NUM_CHANNEL]; DECLARE_BITMAP(channel_map, NUM_CHANNEL); @@ -168,14 +185,22 @@ static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl, */ type &= IRQ_TYPE_SENSE_MASK; - if (type == IRQ_TYPE_EDGE_BOTH) - return -EINVAL; + /* + * New controller support EDGE_BOTH trigger. This setting takes + * precedence over the other edge/polarity settings + */ + if (type == IRQ_TYPE_EDGE_BOTH) { + if (!ctl->params->support_edge_both) + return -EINVAL; - if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) - val |= REG_EDGE_POL_EDGE(idx); + val |= REG_BOTH_EDGE(idx); + } else { + if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) + val |= REG_EDGE_POL_EDGE(idx); - if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) - val |= REG_EDGE_POL_LOW(idx); + if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) + val |= REG_EDGE_POL_LOW(idx); + } spin_lock(&ctl->lock); @@ -199,7 +224,7 @@ static unsigned int meson_gpio_irq_type_output(unsigned int type) */ if (sense & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) type |= IRQ_TYPE_LEVEL_HIGH; - else if (sense & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) + else type |= IRQ_TYPE_EDGE_RISING; return type; @@ -328,15 +353,13 @@ static int __init meson_gpio_irq_parse_dt(struct device_node *node, struct meson_gpio_irq_controller *ctl) { const struct of_device_id *match; - const struct meson_gpio_irq_params *params; int ret; match = of_match_node(meson_irq_gpio_matches, node); if (!match) return -ENODEV; - params = match->data; - ctl->nr_hwirq = params->nr_hwirq; + ctl->params = match->data; ret = of_property_read_variable_u32_array(node, "amlogic,channel-interrupts", @@ -385,7 +408,8 @@ static int __init meson_gpio_irq_of_init(struct device_node *node, if (ret) goto free_channel_irqs; - domain = irq_domain_create_hierarchy(parent_domain, 0, ctl->nr_hwirq, + domain = irq_domain_create_hierarchy(parent_domain, 0, + ctl->params->nr_hwirq, of_node_to_fwnode(node), &meson_gpio_irq_domain_ops, ctl); @@ -396,7 +420,7 @@ static int __init meson_gpio_irq_of_init(struct device_node *node, } pr_info("%d to %d gpio interrupt mux initialized\n", - ctl->nr_hwirq, NUM_CHANNEL); + ctl->params->nr_hwirq, NUM_CHANNEL); return 0;