From patchwork Tue Dec 12 15:23:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gatien CHEVALLIER X-Patchwork-Id: 753872 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="Yn9bC0R/" Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73229DB; Tue, 12 Dec 2023 07:25:06 -0800 (PST) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3BCDNCqH030710; Tue, 12 Dec 2023 16:24:07 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=GqiIUS76/77U02ULG+zDfNo7uarUnt7rSt6USgUSPXY=; b=Yn 9bC0R/94GIy0AaLdxWUp36BFqn/C70ZkQ5egqTlffVG1E1LRRuav0s5v1wZMT39c WAcn5K3MT7RUYtvIBL6jByO0hd2cu3q1U7Cr77RAta/UGvsu1WWhMc/i0U1J3MzU LQeIab5xhaOWmvihNSd8e/NhltQAqA/O2wvtjXMgkkNHGsy0xhUVHrQrTyhXEt1Z wzv2apXRBBK3z2qSs7iLZqveiU1sMiqPrp3BPYFwjAA7rdY1pwlykL05pRbhz26H axBRi7X/o8KhMydZvhTgbWmpsIh+EkTEdOrJWe8HC5FMP96JdVfGuThynqKsMDzb k3do2bmf6ao6B9AwnFsA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3uve88uydg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Dec 2023 16:24:07 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id C1487100064; Tue, 12 Dec 2023 16:24:06 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id B4D2822F7B1; Tue, 12 Dec 2023 16:24:06 +0100 (CET) Received: from localhost (10.252.7.20) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 12 Dec 2023 16:24:06 +0100 From: Gatien Chevallier To: , , , , , , , , , , , , , , , , , , , , , , , , , Frank Rowand , , , , , CC: , , , , , , , , , , , , , , , , Gatien Chevallier Subject: [PATCH v8 02/13] dt-bindings: treewide: add access-controllers description Date: Tue, 12 Dec 2023 16:23:45 +0100 Message-ID: <20231212152356.345703-3-gatien.chevallier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231212152356.345703-1-gatien.chevallier@foss.st.com> References: <20231212152356.345703-1-gatien.chevallier@foss.st.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-12_09,2023-12-12_01,2023-05-22_02 access-controllers is an optional property that allows a peripheral to refer to one or more domain access controller(s). Description of this property is added to all peripheral binding files of the peripheral under the STM32 firewall controller. It allows an accurate representation of the hardware, where various peripherals are connected to a firewall bus. The firewall can then check the peripheral accesses before allowing its device to probe. Signed-off-by: Gatien Chevallier Acked-by: Wolfram Sang # for I2C --- Changes in V6: - Minor changes in commit message - Renamed access-controller to access-controllers Changes in V5: - Discarded review tags as the content has changed - Renamed feature-domains to access-controller Changes in V4: - Added Jonathan's tag for IIO Changes in V2: - Add missing "feature-domains" property declaration in bosch,m_can.yaml and st,stm32-cryp.yaml files Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml | 4 ++++ Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml | 4 ++++ Documentation/devicetree/bindings/dma/st,stm32-dma.yaml | 4 ++++ Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml | 4 ++++ Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml | 4 ++++ Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml | 4 ++++ .../devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml | 4 ++++ Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml | 4 ++++ Documentation/devicetree/bindings/media/cec/st,stm32-cec.yaml | 4 ++++ Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml | 4 ++++ .../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml | 4 ++++ Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml | 4 ++++ Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml | 4 ++++ Documentation/devicetree/bindings/mmc/arm,pl18x.yaml | 4 ++++ Documentation/devicetree/bindings/net/can/bosch,m_can.yaml | 4 ++++ Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 4 ++++ Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml | 4 ++++ .../devicetree/bindings/regulator/st,stm32-vrefbuf.yaml | 4 ++++ Documentation/devicetree/bindings/rng/st,stm32-rng.yaml | 4 ++++ Documentation/devicetree/bindings/serial/st,stm32-uart.yaml | 4 ++++ Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml | 4 ++++ Documentation/devicetree/bindings/sound/st,stm32-sai.yaml | 4 ++++ Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml | 4 ++++ Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml | 4 ++++ Documentation/devicetree/bindings/spi/st,stm32-spi.yaml | 4 ++++ Documentation/devicetree/bindings/usb/dwc2.yaml | 4 ++++ 26 files changed, 104 insertions(+) diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml index 0ddeb8a9a7a0..27354658d054 100644 --- a/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml +++ b/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml @@ -46,6 +46,10 @@ properties: power-domains: maxItems: 1 + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml index ac480765cde0..822318414095 100644 --- a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml +++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml @@ -51,6 +51,10 @@ properties: power-domains: maxItems: 1 + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml index 329847ef096a..ff935a0068ec 100644 --- a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml +++ b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml @@ -82,6 +82,10 @@ properties: description: if defined, it indicates that the controller supports memory-to-memory transfer + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml index e722fbcd8a5f..ddf82bf1e71a 100644 --- a/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml +++ b/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml @@ -28,6 +28,10 @@ properties: resets: maxItems: 1 + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml index 94b75d9f66cd..39fad8f7df44 100644 --- a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml @@ -99,6 +99,10 @@ properties: wakeup-source: true + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml index 995cbf8cefc6..ec34c48d4878 100644 --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml @@ -93,6 +93,10 @@ properties: '#size-cells': const: 0 + access-controllers: + minItems: 1 + maxItems: 2 + allOf: - if: properties: diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml index 1970503389aa..c1b1324fa132 100644 --- a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml @@ -59,6 +59,10 @@ properties: If not, SPI CLKOUT frequency will not be accurate. maximum: 20000000 + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml index 04045b932bd2..b15de4eb209c 100644 --- a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml +++ b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml @@ -45,6 +45,10 @@ properties: '#size-cells': const: 0 + access-controllers: + minItems: 1 + maxItems: 2 + additionalProperties: false required: diff --git a/Documentation/devicetree/bindings/media/cec/st,stm32-cec.yaml b/Documentation/devicetree/bindings/media/cec/st,stm32-cec.yaml index 2314a9a14650..1d930d9e10fd 100644 --- a/Documentation/devicetree/bindings/media/cec/st,stm32-cec.yaml +++ b/Documentation/devicetree/bindings/media/cec/st,stm32-cec.yaml @@ -29,6 +29,10 @@ properties: - const: cec - const: hdmi-cec + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml index 6b3e413cedb2..34147127192f 100644 --- a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml +++ b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml @@ -36,6 +36,10 @@ properties: resets: maxItems: 1 + access-controllers: + minItems: 1 + maxItems: 2 + port: $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml index 14f1833d37c9..deef455bfd21 100644 --- a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml @@ -45,6 +45,10 @@ properties: Reflects the memory layout with four integer values per bank. Format: 0
+ access-controllers: + minItems: 1 + maxItems: 2 + patternProperties: "^.*@[0-4],[a-f0-9]+$": additionalProperties: true diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml index 27329c5dc38e..d41308856408 100644 --- a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml +++ b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml @@ -44,6 +44,10 @@ properties: wakeup-source: true + access-controllers: + minItems: 1 + maxItems: 2 + pwm: type: object additionalProperties: false diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml index f84e09a5743b..b0e438ff4950 100644 --- a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml +++ b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml @@ -67,6 +67,10 @@ properties: "#size-cells": const: 0 + access-controllers: + minItems: 1 + maxItems: 2 + pwm: type: object additionalProperties: false diff --git a/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml b/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml index 2459a55ed540..5644927be810 100644 --- a/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml +++ b/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml @@ -79,6 +79,10 @@ properties: - const: rx - const: tx + access-controllers: + minItems: 1 + maxItems: 2 + power-domains: true resets: diff --git a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml index f9ffb963d6b1..c4887522e8fe 100644 --- a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml +++ b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml @@ -118,6 +118,10 @@ properties: phys: maxItems: 1 + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml index fc8c96b08d7d..f2714b5b6cf4 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml @@ -93,6 +93,10 @@ properties: select RCC clock instead of ETH_REF_CLK. type: boolean + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - clocks diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml index 24a3dbde223b..ceea122ae1a6 100644 --- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml +++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml @@ -55,6 +55,10 @@ properties: description: number of clock cells for ck_usbo_48m consumer const: 0 + access-controllers: + minItems: 1 + maxItems: 2 + # Required child nodes: patternProperties: diff --git a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml index 05f4ad2c7d3a..6ceaffb45dc9 100644 --- a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml +++ b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml @@ -30,6 +30,10 @@ properties: vdda-supply: description: phandle to the vdda input analog voltage. + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml b/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml index 717f6b321f88..340d01d481d1 100644 --- a/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml +++ b/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml @@ -37,6 +37,10 @@ properties: description: If set, the RNG configuration in RNG_CR, RNG_HTCR and RNG_NSCR will be locked. + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml index 1df8ffe95fc6..1de03af4ead1 100644 --- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml +++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml @@ -70,6 +70,10 @@ properties: enum: [1, 2, 4, 8, 12, 14, 16] default: 8 + access-controllers: + minItems: 1 + maxItems: 2 + allOf: - $ref: rs485.yaml# - $ref: serial.yaml# diff --git a/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml b/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml index b9111d375b93..8978f6bd63e5 100644 --- a/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml @@ -65,6 +65,10 @@ properties: $ref: audio-graph-port.yaml# unevaluatedProperties: false + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - "#sound-dai-cells" diff --git a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml index 59df8a832310..b46a4778807d 100644 --- a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml +++ b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml @@ -48,6 +48,10 @@ properties: clock-names: maxItems: 3 + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml b/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml index bc48151b9adb..3dedc81ec12f 100644 --- a/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml +++ b/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml @@ -50,6 +50,10 @@ properties: resets: maxItems: 1 + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - "#sound-dai-cells" diff --git a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml index 8bba965a9ae6..3f1a27efff80 100644 --- a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml @@ -46,6 +46,10 @@ properties: - const: tx - const: rx + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml index ae0f082bd377..0b303bf5c02c 100644 --- a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml +++ b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml @@ -50,6 +50,10 @@ properties: - const: rx - const: tx + access-controllers: + minItems: 1 + maxItems: 2 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml index 0a5c98ea711d..88c077673c8b 100644 --- a/Documentation/devicetree/bindings/usb/dwc2.yaml +++ b/Documentation/devicetree/bindings/usb/dwc2.yaml @@ -172,6 +172,10 @@ properties: tpl-support: true + access-controllers: + minItems: 1 + maxItems: 2 + dependencies: port: [ usb-role-switch ] role-switch-default-mode: [ usb-role-switch ] From patchwork Tue Dec 12 15:23:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gatien CHEVALLIER X-Patchwork-Id: 753871 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="71l+5CnO" Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 402DADB; Tue, 12 Dec 2023 07:26:05 -0800 (PST) Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 3BCCOnGn001179; Tue, 12 Dec 2023 16:25:19 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=QpG4L46teLbBYcxt3AXNM5BujFv4AEDCEiVswfgeH2s=; b=71 l+5CnOazG6/owrN9/LPpceyoq14h8BUl/wClZ6vlstNujryKkM6aDgjhcYQtywWs FrHGo/LqhoPTh783vbnHTfsaTe2FocR9mDik120YyxjrLRTz2iaBPacfIv3XlROD vK74aSPwPnapnTnj8rVvUZtCriJBABL7XM7Tu99qpBHR9SZzYONZ5agfTUE27fH2 4tQY8GEWIN5MeYee+1KHiEsqCxNlJL6X5DGnxjrijiiwZ73/+ENZxaJJZAYRxsEZ iY6gkadX2zEHIWMNQXTB+YSXUA0BLcd89So8iKQHm4y7iz2H9k4Ogdk3udACYraD vcXxT7I3wTFu7C/kJLsw== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3uvehmc8g4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Dec 2023 16:25:19 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 1D59610005A; Tue, 12 Dec 2023 16:25:19 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 12E8922D195; Tue, 12 Dec 2023 16:25:19 +0100 (CET) Received: from localhost (10.252.7.20) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 12 Dec 2023 16:25:18 +0100 From: Gatien Chevallier To: , , , , , , , , , , , , , , , , , , , , , , , , , Frank Rowand , , , , , CC: , , , , , , , , , , , , , , , , Gatien Chevallier Subject: [PATCH v8 04/13] dt-bindings: bus: document ETZPC Date: Tue, 12 Dec 2023 16:23:47 +0100 Message-ID: <20231212152356.345703-5-gatien.chevallier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231212152356.345703-1-gatien.chevallier@foss.st.com> References: <20231212152356.345703-1-gatien.chevallier@foss.st.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-12_09,2023-12-12_01,2023-05-22_02 Document ETZPC (Extended TrustZone protection controller). ETZPC is a firewall controller. Signed-off-by: Gatien Chevallier --- Changes in V6: - Renamed access-controller to access-controllers - Removal of access-control-provider property - Removal of access-controller and access-controller-names declaration in the patternProperties field. Add additionalProperties: true in this field. Changes in V5: - Renamed feature-domain* to access-control* Changes in V2: - Corrected errors highlighted by Rob's robot - No longer define the maxItems for the "feature-domains" property - Fix example (node name, status) - Declare "feature-domain-names" as an optional property for child nodes - Fix description of "feature-domains" property - Reordered the properties so it matches ETZPC - Add missing "feature-domain-controller" property .../bindings/bus/st,stm32-etzpc.yaml | 87 +++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/st,stm32-etzpc.yaml diff --git a/Documentation/devicetree/bindings/bus/st,stm32-etzpc.yaml b/Documentation/devicetree/bindings/bus/st,stm32-etzpc.yaml new file mode 100644 index 000000000000..9ca0ad39bc19 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/st,stm32-etzpc.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/st,stm32-etzpc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STM32 Extended TrustZone protection controller + +description: | + The ETZPC configures TrustZone security in a SoC having bus masters and + devices with programmable-security attributes (securable resources). + +maintainers: + - Gatien Chevallier + +properties: + compatible: + contains: + const: st,stm32-etzpc + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + + "#access-controller-cells": + const: 1 + description: + Contains the firewall ID associated to the peripheral. + +patternProperties: + "^.*@[0-9a-f]+$": + description: Peripherals + type: object + + additionalProperties: true + + required: + - access-controllers + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - "#access-controller-cells" + - ranges + +additionalProperties: false + +examples: + - | + // In this example, the usart2 device refers to rifsc as its access + // controller. + // Access rights are verified before creating devices. + + #include + #include + #include + + etzpc: bus@5c007000 { + compatible = "st,stm32-etzpc"; + reg = <0x5c007000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + #access-controller-cells = <1>; + ranges; + + usart2: serial@4c001000 { + compatible = "st,stm32h7-uart"; + reg = <0x4c001000 0x400>; + interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART2_K>; + resets = <&rcc USART2_R>; + wakeup-source; + dmas = <&dmamux1 43 0x400 0x5>, + <&dmamux1 44 0x400 0x1>; + dma-names = "rx", "tx"; + access-controllers = <&etzpc 17>; + }; + }; From patchwork Tue Dec 12 15:23:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gatien CHEVALLIER X-Patchwork-Id: 753870 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="RzLFWHBF" Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9FE14E4; Tue, 12 Dec 2023 07:26:07 -0800 (PST) Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 3BCDIrYm022629; Tue, 12 Dec 2023 16:25:20 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=Mokd495pPZuOck3VG0eOg0eI5aC2lsYI/q7r8vaJx3Y=; b=Rz LFWHBFTwQ3o3UMsoMdnEzzCgydQH4YR1KtkGkLIWX1i9r8+xzX9AgmzV9hEsTU+E PguQibj71ac1Kk7a2kRL1D2w7XfxbogGwIMNgkdluGgCo046evEEE6THNm8fr9bq wVHzzDXG95IF0B6+KGPgGZc5pk+pgO0Lpf3oiFu79B8xoMEYvTjQd3MwHPfftO4l Bbj/cALsWSYbxS6mi0jI50nCvYk2IBWm9fKVKYEubZ1nTez0Ip+D3x47bKZq/Uox pOHbKr1rlLj6WqykdZAhB2GSQWGk4AyZGy1ju5nETJT8AZFs5K5F2p1ZtEtKkJ7o kZNiYdj9PcnxM2/HMOvQ== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3uvg0gut1a-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Dec 2023 16:25:20 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id C95E9100060; Tue, 12 Dec 2023 16:25:19 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id BCEA822D195; Tue, 12 Dec 2023 16:25:19 +0100 (CET) Received: from localhost (10.252.7.20) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 12 Dec 2023 16:25:19 +0100 From: Gatien Chevallier To: , , , , , , , , , , , , , , , , , , , , , , , , , Frank Rowand , , , , , CC: , , , , , , , , , , , , , , , , Gatien Chevallier Subject: [PATCH v8 05/13] firewall: introduce stm32_firewall framework Date: Tue, 12 Dec 2023 16:23:48 +0100 Message-ID: <20231212152356.345703-6-gatien.chevallier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231212152356.345703-1-gatien.chevallier@foss.st.com> References: <20231212152356.345703-1-gatien.chevallier@foss.st.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-12_09,2023-12-12_01,2023-05-22_02 Introduce a STM32 firewall framework that offers to firewall consumers different firewall services such as the ability to check their access rights against their firewall controller(s). The STM32 firewall framework offers a generic API for STM32 firewall controllers that is defined in their drivers to best fit the specificity of each firewall. There are various types of firewalls: -Peripheral firewalls that filter accesses to peripherals -Memory firewalls that filter accesses to memories or memory regions -No type for undefined type of firewall Signed-off-by: Gatien Chevallier --- Changes in V8: - Add missing dependency on OF for OF_DYNAMIC Changes in V7: - Select OF_DYNAMIC when STM32_FIREWALL is set in order to use of_detach_node() in the firewall framework. Since the simple-bus pre-probe creates devices for all subnodes. This function is needed to detach particular nodes so that there's no match Changes in V6: - Renamed access-controller to access-controllers Changes in V5: - Rename feature-domain* to access-control* - Fix index out of range in stm32_firewall_get_firewall() - Add mising "select STM32_FIREWALL" in config ARCH_STM32 in arch/arm/mach-stm32/Kconfig Changes in V4: - Fix documentation syntax - Put node in case of error in stm32_firewall_populate_bus() - Check firewall controller presence before using it in stm32_firewall_controller_register() Changes in V2: - Support multiple entries for "feature-domains" property. Change stm32_firewall_get_firewall() to do so. - Better handle the device-tree parsing using phandle+args APIs and phandle iterator. - Remove "resource firewall" type - Rephrase STM32_FIREWALL description in the bus Kconfig and remove useless default value - Add missing EXPORT_SYMBOL_GPL - Remove useless stm32_firewall_get_id() API - Add a field for the name of the firewall entry in the stm32_firewall_controller structure - Minor fixes on some traces level (err -> debug) - Fix licenses to GPL-2.0-only - Fix stm32_firewall_get_firewall() description - Rephrase some sentences to better emphasize this is STM32-specific - Switch to list_for_each_entry() in stm32_firewall_controller_unregister() as we only expect one firewall controller instance per device. The loop just breaks when found - Do not register the firewall controller if it is already registered to the framework MAINTAINERS | 5 + arch/arm/mach-stm32/Kconfig | 1 + arch/arm64/Kconfig.platforms | 1 + drivers/bus/Kconfig | 10 + drivers/bus/Makefile | 1 + drivers/bus/stm32_firewall.c | 294 ++++++++++++++++++++++ drivers/bus/stm32_firewall.h | 83 ++++++ include/linux/bus/stm32_firewall_device.h | 141 +++++++++++ 8 files changed, 536 insertions(+) create mode 100644 drivers/bus/stm32_firewall.c create mode 100644 drivers/bus/stm32_firewall.h create mode 100644 include/linux/bus/stm32_firewall_device.h diff --git a/MAINTAINERS b/MAINTAINERS index e2c6187a3ac8..774c7e1601d8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20430,6 +20430,11 @@ T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/i2c/st,st-mipid02.yaml F: drivers/media/i2c/st-mipid02.c +ST STM32 FIREWALL +M: Gatien Chevallier +S: Maintained +F: drivers/bus/stm32_firewall.c + ST STM32 I2C/SMBUS DRIVER M: Pierre-Yves MORDRET M: Alain Volmat diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig index 98145031586f..ae21a9f78f9c 100644 --- a/arch/arm/mach-stm32/Kconfig +++ b/arch/arm/mach-stm32/Kconfig @@ -12,6 +12,7 @@ menuconfig ARCH_STM32 select PINCTRL select RESET_CONTROLLER select STM32_EXTI + select STM32_FIREWALL help Support for STMicroelectronics STM32 processors. diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 24335565bad5..13ed0a483617 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -305,6 +305,7 @@ config ARCH_STM32 select ARM_SMC_MBOX select ARM_SCMI_PROTOCOL select COMMON_CLK_SCMI + select STM32_FIREWALL help This enables support for ARMv8 based STMicroelectronics STM32 family, including: diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index e6742998f372..7d47e0005cfe 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -163,6 +163,16 @@ config QCOM_SSC_BLOCK_BUS i2c/spi/uart controllers, a hexagon core, and a clock controller which provides clocks for the above. +config STM32_FIREWALL + bool "STM32 Firewall framework" + depends on (ARCH_STM32 || COMPILE_TEST) && OF + select OF_DYNAMIC + help + Say y to enable STM32 firewall framework and its services. Firewall + controllers will be able to register to the framework. Access for + hardware resources linked to a firewall controller can be requested + through this STM32 framework. + config SUN50I_DE2_BUS bool "Allwinner A64 DE2 Bus Driver" default ARM64 diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index d90eed189a65..fc0511450ec2 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o obj-$(CONFIG_QCOM_SSC_BLOCK_BUS) += qcom-ssc-block-bus.o +obj-$(CONFIG_STM32_FIREWALL) += stm32_firewall.o obj-$(CONFIG_SUN50I_DE2_BUS) += sun50i-de2.o obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o obj-$(CONFIG_OF) += simple-pm-bus.o diff --git a/drivers/bus/stm32_firewall.c b/drivers/bus/stm32_firewall.c new file mode 100644 index 000000000000..decb79449047 --- /dev/null +++ b/drivers/bus/stm32_firewall.c @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "stm32_firewall.h" + +/* Corresponds to STM32_FIREWALL_MAX_EXTRA_ARGS + firewall ID */ +#define STM32_FIREWALL_MAX_ARGS (STM32_FIREWALL_MAX_EXTRA_ARGS + 1) + +static LIST_HEAD(firewall_controller_list); +static DEFINE_MUTEX(firewall_controller_list_lock); + +/* Firewall device API */ + +int stm32_firewall_get_firewall(struct device_node *np, struct stm32_firewall *firewall, + unsigned int nb_firewall) +{ + struct stm32_firewall_controller *ctrl; + struct of_phandle_iterator it; + unsigned int i, j = 0; + int err; + + if (!firewall || !nb_firewall) + return -EINVAL; + + /* Parse property with phandle parsed out */ + of_for_each_phandle(&it, err, np, "access-controllers", "#access-controller-cells", 0) { + struct of_phandle_args provider_args; + struct device_node *provider = it.node; + const char *fw_entry; + bool match = false; + + if (err) { + pr_err("Unable to get access-controllers property for node %s\n, err: %d", + np->full_name, err); + of_node_put(provider); + return err; + } + + if (j > nb_firewall) { + pr_err("Too many firewall controllers"); + of_node_put(provider); + return -EINVAL; + } + + provider_args.args_count = of_phandle_iterator_args(&it, provider_args.args, + STM32_FIREWALL_MAX_ARGS); + + /* Check if the parsed phandle corresponds to a registered firewall controller */ + mutex_lock(&firewall_controller_list_lock); + list_for_each_entry(ctrl, &firewall_controller_list, entry) { + if (ctrl->dev->of_node->phandle == it.phandle) { + match = true; + firewall[j].firewall_ctrl = ctrl; + break; + } + } + mutex_unlock(&firewall_controller_list_lock); + + if (!match) { + firewall[j].firewall_ctrl = NULL; + pr_err("No firewall controller registered for %s\n", np->full_name); + of_node_put(provider); + return -ENODEV; + } + + err = of_property_read_string_index(np, "access-controller-names", j, &fw_entry); + if (err == 0) + firewall[j].entry = fw_entry; + + /* Handle the case when there are no arguments given along with the phandle */ + if (provider_args.args_count < 0 || + provider_args.args_count > STM32_FIREWALL_MAX_ARGS) { + of_node_put(provider); + return -EINVAL; + } else if (provider_args.args_count == 0) { + firewall[j].extra_args_size = 0; + firewall[j].firewall_id = U32_MAX; + j++; + continue; + } + + /* The firewall ID is always the first argument */ + firewall[j].firewall_id = provider_args.args[0]; + + /* Extra args start at the second argument */ + for (i = 0; i < provider_args.args_count - 1; i++) + firewall[j].extra_args[i] = provider_args.args[i + 1]; + + /* Remove the firewall ID arg that is not an extra argument */ + firewall[j].extra_args_size = provider_args.args_count - 1; + + j++; + } + + return 0; +} +EXPORT_SYMBOL_GPL(stm32_firewall_get_firewall); + +int stm32_firewall_grant_access(struct stm32_firewall *firewall) +{ + struct stm32_firewall_controller *firewall_controller; + + if (!firewall || firewall->firewall_id == U32_MAX) + return -EINVAL; + + firewall_controller = firewall->firewall_ctrl; + + if (!firewall_controller) + return -ENODEV; + + return firewall_controller->grant_access(firewall_controller, firewall->firewall_id); +} +EXPORT_SYMBOL_GPL(stm32_firewall_grant_access); + +int stm32_firewall_grant_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{ + struct stm32_firewall_controller *firewall_controller; + + if (!firewall || subsystem_id == U32_MAX || firewall->firewall_id == U32_MAX) + return -EINVAL; + + firewall_controller = firewall->firewall_ctrl; + + if (!firewall_controller) + return -ENODEV; + + return firewall_controller->grant_access(firewall_controller, subsystem_id); +} +EXPORT_SYMBOL_GPL(stm32_firewall_grant_access_by_id); + +void stm32_firewall_release_access(struct stm32_firewall *firewall) +{ + struct stm32_firewall_controller *firewall_controller; + + if (!firewall || firewall->firewall_id == U32_MAX) { + pr_debug("Incorrect arguments when releasing a firewall access\n"); + return; + } + + firewall_controller = firewall->firewall_ctrl; + + if (!firewall_controller) { + pr_debug("No firewall controller to release\n"); + return; + } + + firewall_controller->release_access(firewall_controller, firewall->firewall_id); +} +EXPORT_SYMBOL_GPL(stm32_firewall_release_access); + +void stm32_firewall_release_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{ + struct stm32_firewall_controller *firewall_controller; + + if (!firewall || subsystem_id == U32_MAX || firewall->firewall_id == U32_MAX) { + pr_debug("Incorrect arguments when releasing a firewall access"); + return; + } + + firewall_controller = firewall->firewall_ctrl; + + if (!firewall_controller) { + pr_debug("No firewall controller to release"); + return; + } + + firewall_controller->release_access(firewall_controller, subsystem_id); +} +EXPORT_SYMBOL_GPL(stm32_firewall_release_access_by_id); + +/* Firewall controller API */ + +int stm32_firewall_controller_register(struct stm32_firewall_controller *firewall_controller) +{ + struct stm32_firewall_controller *ctrl; + + if (!firewall_controller) + return -ENODEV; + + pr_info("Registering %s firewall controller\n", firewall_controller->name); + + mutex_lock(&firewall_controller_list_lock); + list_for_each_entry(ctrl, &firewall_controller_list, entry) { + if (ctrl == firewall_controller) { + pr_debug("%s firewall controller already registered\n", + firewall_controller->name); + mutex_unlock(&firewall_controller_list_lock); + return 0; + } + } + list_add_tail(&firewall_controller->entry, &firewall_controller_list); + mutex_unlock(&firewall_controller_list_lock); + + return 0; +} +EXPORT_SYMBOL_GPL(stm32_firewall_controller_register); + +void stm32_firewall_controller_unregister(struct stm32_firewall_controller *firewall_controller) +{ + struct stm32_firewall_controller *ctrl; + bool controller_removed = false; + + if (!firewall_controller) { + pr_debug("Null reference while unregistering firewall controller\n"); + return; + } + + mutex_lock(&firewall_controller_list_lock); + list_for_each_entry(ctrl, &firewall_controller_list, entry) { + if (ctrl == firewall_controller) { + controller_removed = true; + list_del_init(&ctrl->entry); + break; + } + } + mutex_unlock(&firewall_controller_list_lock); + + if (!controller_removed) + pr_debug("There was no firewall controller named %s to unregister\n", + firewall_controller->name); +} +EXPORT_SYMBOL_GPL(stm32_firewall_controller_unregister); + +int stm32_firewall_populate_bus(struct stm32_firewall_controller *firewall_controller) +{ + struct stm32_firewall *firewalls; + struct device_node *child; + struct device *parent; + unsigned int i; + int len; + int err; + + parent = firewall_controller->dev; + + dev_dbg(parent, "Populating %s system bus\n", dev_name(firewall_controller->dev)); + + for_each_available_child_of_node(dev_of_node(parent), child) { + /* The access-controllers property is mandatory for firewall bus devices */ + len = of_count_phandle_with_args(child, "access-controllers", + "#access-controller-cells"); + if (len <= 0) { + of_node_put(child); + return -EINVAL; + } + + firewalls = kcalloc(len, sizeof(*firewalls), GFP_KERNEL); + if (!firewalls) { + of_node_put(child); + return -ENOMEM; + } + + err = stm32_firewall_get_firewall(child, firewalls, (unsigned int)len); + if (err) { + kfree(firewalls); + of_node_put(child); + return err; + } + + for (i = 0; i < len; i++) { + if (firewall_controller->grant_access(firewall_controller, + firewalls[i].firewall_id)) { + /* + * Peripheral access not allowed or not defined. + * Mark the node as populated so platform bus won't probe it + */ + of_detach_node(child); + dev_err(parent, "%s: Device driver will not be probed\n", + child->full_name); + } + } + + kfree(firewalls); + } + + return 0; +} +EXPORT_SYMBOL_GPL(stm32_firewall_populate_bus); diff --git a/drivers/bus/stm32_firewall.h b/drivers/bus/stm32_firewall.h new file mode 100644 index 000000000000..e5fac85fe346 --- /dev/null +++ b/drivers/bus/stm32_firewall.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#ifndef _STM32_FIREWALL_H +#define _STM32_FIREWALL_H + +#include +#include +#include +#include +#include + +/** + * STM32_PERIPHERAL_FIREWALL: This type of firewall protects peripherals + * STM32_MEMORY_FIREWALL: This type of firewall protects memories/subsets of memory + * zones + * STM32_NOTYPE_FIREWALL: Undefined firewall type + */ + +#define STM32_PERIPHERAL_FIREWALL BIT(1) +#define STM32_MEMORY_FIREWALL BIT(2) +#define STM32_NOTYPE_FIREWALL BIT(3) + +/** + * struct stm32_firewall_controller - Information on firewall controller supplying services + * + * @name: Name of the firewall controller + * @dev: Device reference of the firewall controller + * @mmio: Base address of the firewall controller + * @entry: List entry of the firewall controller list + * @type: Type of firewall + * @max_entries: Number of entries covered by the firewall + * @grant_access: Callback used to grant access for a device access against a + * firewall controller + * @release_access: Callback used to release resources taken by a device when access was + * granted + * @grant_memory_range_access: Callback used to grant access for a device to a given memory region + */ +struct stm32_firewall_controller { + const char *name; + struct device *dev; + void __iomem *mmio; + struct list_head entry; + unsigned int type; + unsigned int max_entries; + + int (*grant_access)(struct stm32_firewall_controller *ctrl, u32 id); + void (*release_access)(struct stm32_firewall_controller *ctrl, u32 id); + int (*grant_memory_range_access)(struct stm32_firewall_controller *ctrl, phys_addr_t paddr, + size_t size); +}; + +/** + * stm32_firewall_controller_register - Register a firewall controller to the STM32 firewall + * framework + * @firewall_controller: Firewall controller to register + * + * Returns 0 in case of success or -ENODEV if no controller was given. + */ +int stm32_firewall_controller_register(struct stm32_firewall_controller *firewall_controller); + +/** + * stm32_firewall_controller_unregister - Unregister a firewall controller from the STM32 + * firewall framework + * @firewall_controller: Firewall controller to unregister + */ +void stm32_firewall_controller_unregister(struct stm32_firewall_controller *firewall_controller); + +/** + * stm32_firewall_populate_bus - Populate device tree nodes that have a correct firewall + * configuration. This is used at boot-time only, as a sanity check + * between device tree and firewalls hardware configurations to + * prevent a kernel crash when a device driver is not granted access + * + * @firewall_controller: Firewall controller which nodes will be populated or not + * + * Returns 0 in case of success or appropriate errno code if error occurred. + */ +int stm32_firewall_populate_bus(struct stm32_firewall_controller *firewall_controller); + +#endif /* _STM32_FIREWALL_H */ diff --git a/include/linux/bus/stm32_firewall_device.h b/include/linux/bus/stm32_firewall_device.h new file mode 100644 index 000000000000..bbbee0b24ea8 --- /dev/null +++ b/include/linux/bus/stm32_firewall_device.h @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#ifndef STM32_FIREWALL_DEVICE_H +#define STM32_FIREWALL_DEVICE_H + +#include +#include +#include + +#define STM32_FIREWALL_MAX_EXTRA_ARGS 5 + +/* Opaque reference to stm32_firewall_controller */ +struct stm32_firewall_controller; + +/** + * struct stm32_firewall - Information on a device's firewall. Each device can have more than one + * firewall. + * + * @firewall_ctrl: Pointer referencing a firewall controller of the device. It is + * opaque so a device cannot manipulate the controller's ops or access + * the controller's data + * @extra_args: Extra arguments that are implementation dependent + * @entry: Name of the firewall entry + * @extra_args_size: Number of extra arguments + * @firewall_id: Firewall ID associated the device for this firewall controller + */ +struct stm32_firewall { + struct stm32_firewall_controller *firewall_ctrl; + u32 extra_args[STM32_FIREWALL_MAX_EXTRA_ARGS]; + const char *entry; + size_t extra_args_size; + u32 firewall_id; +}; + +#if IS_ENABLED(CONFIG_STM32_FIREWALL) +/** + * stm32_firewall_get_firewall - Get the firewall(s) associated to given device. + * The firewall controller reference is always the first argument + * of each of the access-controller property entries. + * The firewall ID is always the second argument of each of the + * access-controller property entries. + * If there's no argument linked to the phandle, then the firewall ID + * field is set to U32_MAX, which is an invalid ID. + * + * @np: Device node to parse + * @firewall: Array of firewall references + * @nb_firewall: Number of firewall references to get. Must be at least 1. + * + * Returns 0 on success, -ENODEV if there's no match with a firewall controller or appropriate errno + * code if error occurred. + */ +int stm32_firewall_get_firewall(struct device_node *np, struct stm32_firewall *firewall, + unsigned int nb_firewall); + +/** + * stm32_firewall_grant_access - Request firewall access rights and grant access. + * + * @firewall: Firewall reference containing the ID to check against its firewall + * controller + * + * Returns 0 if access is granted, -EACCES if access is denied, -ENODEV if firewall is null or + * appropriate errno code if error occurred + */ +int stm32_firewall_grant_access(struct stm32_firewall *firewall); + +/** + * stm32_firewall_release_access - Release access granted from a call to + * stm32_firewall_grant_access(). + * + * @firewall: Firewall reference containing the ID to check against its firewall + * controller + */ +void stm32_firewall_release_access(struct stm32_firewall *firewall); + +/** + * stm32_firewall_grant_access_by_id - Request firewall access rights of a given device + * based on a specific firewall ID + * + * Warnings: + * There is no way to ensure that the given ID will correspond to the firewall referenced in the + * device node if the ID did not come from stm32_firewall_get_firewall(). In that case, this + * function must be used with caution. + * This function should be used for subsystem resources that do not have the same firewall ID + * as their parent. + * U32_MAX is an invalid ID. + * + * @firewall: Firewall reference containing the firewall controller + * @subsystem_id: Firewall ID of the subsystem resource + * + * Returns 0 if access is granted, -EACCES if access is denied, -ENODEV if firewall is null or + * appropriate errno code if error occurred + */ +int stm32_firewall_grant_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id); + +/** + * stm32_firewall_release_access_by_id - Release access granted from a call to + * stm32_firewall_grant_access_by_id(). + * + * Warnings: + * There is no way to ensure that the given ID will correspond to the firewall referenced in the + * device node if the ID did not come from stm32_firewall_get_firewall(). In that case, this + * function must be used with caution. + * This function should be used for subsystem resources that do not have the same firewall ID + * as their parent. + * U32_MAX is an invalid ID. + * + * @firewall: Firewall reference containing the firewall controller + * @subsystem_id: Firewall ID of the subsystem resource + */ +void stm32_firewall_release_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id); + +#else /* CONFIG_STM32_FIREWALL */ + +int stm32_firewall_get_firewall(struct device_node *np, struct stm32_firewall *firewall) +{ + return -ENODEV; +} + +int stm32_firewall_grant_access(struct stm32_firewall *firewall) +{ + return -ENODEV; +} + +void stm32_firewall_release_access(struct stm32_firewall *firewall) +{ +} + +int stm32_firewall_grant_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{ + return -ENODEV; +} + +void stm32_firewall_release_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id) +{ +} + +#endif /* CONFIG_STM32_FIREWALL */ +#endif /* STM32_FIREWALL_DEVICE_H */ From patchwork Tue Dec 12 15:23:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gatien CHEVALLIER X-Patchwork-Id: 753869 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="1dFlEjsb" Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D2FD7D3; Tue, 12 Dec 2023 07:27:15 -0800 (PST) Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 3BCE3S8N028254; Tue, 12 Dec 2023 16:26:32 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=u9zWGEdFB11DbLE904eNSgCuw8Hsqkgso/LOcoqp4SU=; b=1d FlEjsbW+fdroD2XfPrhbd6FLrFhfladyWnFIpfpCN3tbTNUzEzixeuoWhznsUpPE q74DD3iwhHyKrDLJ5eA+iG1nX6o2hVEqU1I4WksNL4bNd6ZJwxcxoXuTQWtqrJ2S Z0C2dAG9wZYKTMGhix8JFas9apMnBWDtvI8StzTr0o03mAOIXE8H+sOm1PWyhctw VRX4990AagOID2vQRvrUj5GUrN3tjzyshkyW2kVomSnqkk8tzEzqe6Uiq0l7i9Ut Aaza5EzPTVzEKN9DJrsNyvYLPNPQ9NUpLojwXh3aTFwephtqQJ3s02BDf7D5v3iu f5CS3vSkpNab04wZy5fA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3uw42nht0f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Dec 2023 16:26:32 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 3D7AF100060; Tue, 12 Dec 2023 16:26:32 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 330D922F7BA; Tue, 12 Dec 2023 16:26:32 +0100 (CET) Received: from localhost (10.252.7.20) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 12 Dec 2023 16:26:31 +0100 From: Gatien Chevallier To: , , , , , , , , , , , , , , , , , , , , , , , , , Frank Rowand , , , , , CC: , , , , , , , , , , , , , , , , Gatien Chevallier Subject: [PATCH v8 09/13] bus: etzpc: introduce ETZPC firewall controller driver Date: Tue, 12 Dec 2023 16:23:52 +0100 Message-ID: <20231212152356.345703-10-gatien.chevallier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231212152356.345703-1-gatien.chevallier@foss.st.com> References: <20231212152356.345703-1-gatien.chevallier@foss.st.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-12_09,2023-12-12_01,2023-05-22_02 ETZPC is a peripheral and memory firewall controller that filter accesses based on Arm TrustZone secure state and Arm CPU privilege execution level. It handles MCU isolation as well. Signed-off-by: Gatien Chevallier --- Changes in V2: - Add controller name - Driver is now a module_platform_driver - Use error code returned by stm32_firewall_populate_bus() - Fix license MAINTAINERS | 1 + drivers/bus/Makefile | 2 +- drivers/bus/stm32_etzpc.c | 141 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 143 insertions(+), 1 deletion(-) create mode 100644 drivers/bus/stm32_etzpc.c diff --git a/MAINTAINERS b/MAINTAINERS index a1152438b52d..b83b471c8b73 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20433,6 +20433,7 @@ F: drivers/media/i2c/st-mipid02.c ST STM32 FIREWALL M: Gatien Chevallier S: Maintained +F: drivers/bus/stm32_etzpc.c F: drivers/bus/stm32_firewall.c F: drivers/bus/stm32_rifsc.c diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index e50d18e1d141..cddd4984d6af 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -26,7 +26,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o obj-$(CONFIG_QCOM_SSC_BLOCK_BUS) += qcom-ssc-block-bus.o -obj-$(CONFIG_STM32_FIREWALL) += stm32_firewall.o stm32_rifsc.o +obj-$(CONFIG_STM32_FIREWALL) += stm32_firewall.o stm32_rifsc.o stm32_etzpc.o obj-$(CONFIG_SUN50I_DE2_BUS) += sun50i-de2.o obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o obj-$(CONFIG_OF) += simple-pm-bus.o diff --git a/drivers/bus/stm32_etzpc.c b/drivers/bus/stm32_etzpc.c new file mode 100644 index 000000000000..7fc0f16960be --- /dev/null +++ b/drivers/bus/stm32_etzpc.c @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "stm32_firewall.h" + +/* + * ETZPC registers + */ +#define ETZPC_DECPROT 0x10 +#define ETZPC_HWCFGR 0x3F0 + +/* + * HWCFGR register + */ +#define ETZPC_HWCFGR_NUM_TZMA GENMASK(7, 0) +#define ETZPC_HWCFGR_NUM_PER_SEC GENMASK(15, 8) +#define ETZPC_HWCFGR_NUM_AHB_SEC GENMASK(23, 16) +#define ETZPC_HWCFGR_CHUNKS1N4 GENMASK(31, 24) + +/* + * ETZPC miscellaneous + */ +#define ETZPC_PROT_MASK GENMASK(1, 0) +#define ETZPC_PROT_A7NS 0x3 +#define ETZPC_DECPROT_SHIFT 1 + +#define IDS_PER_DECPROT_REGS 16 + +static int stm32_etzpc_grant_access(struct stm32_firewall_controller *ctrl, u32 firewall_id) +{ + u32 offset, reg_offset, sec_val; + + if (firewall_id >= ctrl->max_entries) { + dev_err(ctrl->dev, "Invalid sys bus ID %u", firewall_id); + return -EINVAL; + } + + /* Check access configuration, 16 peripherals per register */ + reg_offset = ETZPC_DECPROT + 0x4 * (firewall_id / IDS_PER_DECPROT_REGS); + offset = (firewall_id % IDS_PER_DECPROT_REGS) << ETZPC_DECPROT_SHIFT; + + /* Verify peripheral is non-secure and attributed to cortex A7 */ + sec_val = (readl(ctrl->mmio + reg_offset) >> offset) & ETZPC_PROT_MASK; + if (sec_val != ETZPC_PROT_A7NS) { + dev_dbg(ctrl->dev, "Invalid bus configuration: reg_offset %#x, value %d\n", + reg_offset, sec_val); + return -EACCES; + } + + return 0; +} + +static void stm32_etzpc_release_access(struct stm32_firewall_controller *ctrl __maybe_unused, + u32 firewall_id __maybe_unused) +{ +} + +static int stm32_etzpc_probe(struct platform_device *pdev) +{ + struct stm32_firewall_controller *etzpc_controller; + struct device_node *np = pdev->dev.of_node; + u32 nb_per, nb_master; + struct resource *res; + void __iomem *mmio; + int rc; + + etzpc_controller = devm_kzalloc(&pdev->dev, sizeof(*etzpc_controller), GFP_KERNEL); + if (!etzpc_controller) + return -ENOMEM; + + mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(mmio)) + return PTR_ERR(mmio); + + etzpc_controller->dev = &pdev->dev; + etzpc_controller->mmio = mmio; + etzpc_controller->name = dev_driver_string(etzpc_controller->dev); + etzpc_controller->type = STM32_PERIPHERAL_FIREWALL | STM32_MEMORY_FIREWALL; + etzpc_controller->grant_access = stm32_etzpc_grant_access; + etzpc_controller->release_access = stm32_etzpc_release_access; + + /* Get number of etzpc entries*/ + nb_per = FIELD_GET(ETZPC_HWCFGR_NUM_PER_SEC, + readl(etzpc_controller->mmio + ETZPC_HWCFGR)); + nb_master = FIELD_GET(ETZPC_HWCFGR_NUM_AHB_SEC, + readl(etzpc_controller->mmio + ETZPC_HWCFGR)); + etzpc_controller->max_entries = nb_per + nb_master; + + platform_set_drvdata(pdev, etzpc_controller); + + rc = stm32_firewall_controller_register(etzpc_controller); + if (rc) { + dev_err(etzpc_controller->dev, "Couldn't register as a firewall controller: %d", + rc); + return rc; + } + + rc = stm32_firewall_populate_bus(etzpc_controller); + if (rc) { + dev_err(etzpc_controller->dev, "Couldn't populate ETZPC bus: %d", + rc); + return rc; + } + + /* Populate all allowed nodes */ + return of_platform_populate(np, NULL, NULL, &pdev->dev); +} + +static const struct of_device_id stm32_etzpc_of_match[] = { + { .compatible = "st,stm32-etzpc" }, + {} +}; +MODULE_DEVICE_TABLE(of, stm32_etzpc_of_match); + +static struct platform_driver stm32_etzpc_driver = { + .probe = stm32_etzpc_probe, + .driver = { + .name = "stm32-etzpc", + .of_match_table = stm32_etzpc_of_match, + }, +}; +module_platform_driver(stm32_etzpc_driver); + +MODULE_AUTHOR("Gatien Chevallier "); +MODULE_DESCRIPTION("STMicroelectronics ETZPC driver"); +MODULE_LICENSE("GPL"); From patchwork Tue Dec 12 15:23:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gatien CHEVALLIER X-Patchwork-Id: 753868 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="xWQM+nnR" Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9DA24101; Tue, 12 Dec 2023 07:27:17 -0800 (PST) Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 3BCCtShA012700; Tue, 12 Dec 2023 16:26:34 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=d8TCOwrYxXWJWufVh9NBhZg0OCOLZiK2cnNQqkAHow8=; b=xW QM+nnRXVniMicsYJlEJKTTGYSTF47DiFt4vFgGUgYbg/I8TkhgSMvrdEMkKaEJ5g z1Ino/Dmdrv/rlGkKjEL3ZvdQgk8r6a8RYq/QUtPxEBr9HZ5Bbcz6ReHhZIQrt23 lVkv753VkOUgZWSGI/Uqlqe2Q/yYn9G+jDiRQPSpOnDdpDuDuizSKbNySYkBgR+M Vnn+SS2pwnkoXRnmAcAS3mJlvw8MDWMOKfG+Zif1BltP62K3eF2qmDOPTg+lvupF 9uETRXacCCcftIbCJQ8juyFR578BkFL6ued0iL05LeH15uwa6hcehitsuM9lA76d ddAM+ZV9tfmbdiBsOAdA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3uw42nht0k-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Dec 2023 16:26:34 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 98F8E100060; Tue, 12 Dec 2023 16:26:33 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 8D1AA22F7BA; Tue, 12 Dec 2023 16:26:33 +0100 (CET) Received: from localhost (10.252.7.20) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 12 Dec 2023 16:26:33 +0100 From: Gatien Chevallier To: , , , , , , , , , , , , , , , , , , , , , , , , , Frank Rowand , , , , , CC: , , , , , , , , , , , , , , , , Gatien Chevallier Subject: [PATCH v8 11/13] ARM: dts: stm32: put ETZPC as an access controller for STM32MP15x boards Date: Tue, 12 Dec 2023 16:23:54 +0100 Message-ID: <20231212152356.345703-12-gatien.chevallier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231212152356.345703-1-gatien.chevallier@foss.st.com> References: <20231212152356.345703-1-gatien.chevallier@foss.st.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-12_09,2023-12-12_01,2023-05-22_02 Reference ETZPC as an access-control-provider. For more information on which peripheral is securable or supports MCU isolation, please read the STM32MP13 reference manual Signed-off-by: Gatien Chevallier --- Patch not present in V6 arch/arm/boot/dts/st/stm32mp151.dtsi | 66 ++++++++++++++++++++++++++- arch/arm/boot/dts/st/stm32mp153.dtsi | 2 + arch/arm/boot/dts/st/stm32mp15xc.dtsi | 1 + 3 files changed, 68 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi index 78c0d6ccdb09..8a40df8a097b 100644 --- a/arch/arm/boot/dts/st/stm32mp151.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -330,10 +330,11 @@ ts_cal2: calib@5e { }; etzpc: bus@5c007000 { - compatible = "st,stm32-etzpc"; + compatible = "st,stm32-etzpc", "simple-bus"; reg = <0x5c007000 0x400>; #address-cells = <1>; #size-cells = <1>; + #access-controller-cells = <1>; ranges; timers2: timer@40000000 { @@ -351,6 +352,7 @@ timers2: timer@40000000 { <&dmamux1 21 0x400 0x1>, <&dmamux1 22 0x400 0x1>; dma-names = "ch1", "ch2", "ch3", "ch4", "up"; + access-controllers = <&etzpc 16>; status = "disabled"; pwm { @@ -387,6 +389,7 @@ timers3: timer@40001000 { <&dmamux1 27 0x400 0x1>, <&dmamux1 28 0x400 0x1>; dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; + access-controllers = <&etzpc 17>; status = "disabled"; pwm { @@ -421,6 +424,7 @@ timers4: timer@40002000 { <&dmamux1 31 0x400 0x1>, <&dmamux1 32 0x400 0x1>; dma-names = "ch1", "ch2", "ch3", "ch4"; + access-controllers = <&etzpc 18>; status = "disabled"; pwm { @@ -457,6 +461,7 @@ timers5: timer@40003000 { <&dmamux1 59 0x400 0x1>, <&dmamux1 60 0x400 0x1>; dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; + access-controllers = <&etzpc 19>; status = "disabled"; pwm { @@ -488,6 +493,7 @@ timers6: timer@40004000 { clock-names = "int"; dmas = <&dmamux1 69 0x400 0x1>; dma-names = "up"; + access-controllers = <&etzpc 20>; status = "disabled"; timer@5 { @@ -508,6 +514,7 @@ timers7: timer@40005000 { clock-names = "int"; dmas = <&dmamux1 70 0x400 0x1>; dma-names = "up"; + access-controllers = <&etzpc 21>; status = "disabled"; timer@6 { @@ -526,6 +533,7 @@ timers12: timer@40006000 { interrupt-names = "global"; clocks = <&rcc TIM12_K>; clock-names = "int"; + access-controllers = <&etzpc 22>; status = "disabled"; pwm { @@ -550,6 +558,7 @@ timers13: timer@40007000 { interrupt-names = "global"; clocks = <&rcc TIM13_K>; clock-names = "int"; + access-controllers = <&etzpc 23>; status = "disabled"; pwm { @@ -574,6 +583,7 @@ timers14: timer@40008000 { interrupt-names = "global"; clocks = <&rcc TIM14_K>; clock-names = "int"; + access-controllers = <&etzpc 24>; status = "disabled"; pwm { @@ -598,6 +608,7 @@ lptimer1: timer@40009000 { clocks = <&rcc LPTIM1_K>; clock-names = "mux"; wakeup-source; + access-controllers = <&etzpc 25>; status = "disabled"; pwm { @@ -626,6 +637,7 @@ i2s2: audio-controller@4000b000 { dmas = <&dmamux1 39 0x400 0x01>, <&dmamux1 40 0x400 0x01>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 27>; status = "disabled"; }; @@ -640,6 +652,7 @@ spi2: spi@4000b000 { dmas = <&dmamux1 39 0x400 0x05>, <&dmamux1 40 0x400 0x05>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 27>; status = "disabled"; }; @@ -651,6 +664,7 @@ i2s3: audio-controller@4000c000 { dmas = <&dmamux1 61 0x400 0x01>, <&dmamux1 62 0x400 0x01>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 28>; status = "disabled"; }; @@ -665,6 +679,7 @@ spi3: spi@4000c000 { dmas = <&dmamux1 61 0x400 0x05>, <&dmamux1 62 0x400 0x05>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 28>; status = "disabled"; }; @@ -678,6 +693,7 @@ spdifrx: audio-controller@4000d000 { dmas = <&dmamux1 93 0x400 0x01>, <&dmamux1 94 0x400 0x01>; dma-names = "rx", "rx-ctrl"; + access-controllers = <&etzpc 29>; status = "disabled"; }; @@ -690,6 +706,7 @@ usart2: serial@4000e000 { dmas = <&dmamux1 43 0x400 0x15>, <&dmamux1 44 0x400 0x11>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 30>; status = "disabled"; }; @@ -702,6 +719,7 @@ usart3: serial@4000f000 { dmas = <&dmamux1 45 0x400 0x15>, <&dmamux1 46 0x400 0x11>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 31>; status = "disabled"; }; @@ -714,6 +732,7 @@ uart4: serial@40010000 { dmas = <&dmamux1 63 0x400 0x15>, <&dmamux1 64 0x400 0x11>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 32>; status = "disabled"; }; @@ -726,6 +745,7 @@ uart5: serial@40011000 { dmas = <&dmamux1 65 0x400 0x15>, <&dmamux1 66 0x400 0x11>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 33>; status = "disabled"; }; @@ -742,6 +762,7 @@ i2c1: i2c@40012000 { st,syscfg-fmp = <&syscfg 0x4 0x1>; wakeup-source; i2c-analog-filter; + access-controllers = <&etzpc 34>; status = "disabled"; }; @@ -758,6 +779,7 @@ i2c2: i2c@40013000 { st,syscfg-fmp = <&syscfg 0x4 0x2>; wakeup-source; i2c-analog-filter; + access-controllers = <&etzpc 35>; status = "disabled"; }; @@ -774,6 +796,7 @@ i2c3: i2c@40014000 { st,syscfg-fmp = <&syscfg 0x4 0x4>; wakeup-source; i2c-analog-filter; + access-controllers = <&etzpc 36>; status = "disabled"; }; @@ -790,6 +813,7 @@ i2c5: i2c@40015000 { st,syscfg-fmp = <&syscfg 0x4 0x10>; wakeup-source; i2c-analog-filter; + access-controllers = <&etzpc 37>; status = "disabled"; }; @@ -799,6 +823,7 @@ cec: cec@40016000 { interrupts = ; clocks = <&rcc CEC_K>, <&rcc CEC>; clock-names = "cec", "hdmi-cec"; + access-controllers = <&etzpc 38>; status = "disabled"; }; @@ -809,6 +834,7 @@ dac: dac@40017000 { clock-names = "pclk"; #address-cells = <1>; #size-cells = <0>; + access-controllers = <&etzpc 39>; status = "disabled"; dac1: dac@1 { @@ -835,6 +861,7 @@ uart7: serial@40018000 { dmas = <&dmamux1 79 0x400 0x15>, <&dmamux1 80 0x400 0x11>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 40>; status = "disabled"; }; @@ -847,6 +874,7 @@ uart8: serial@40019000 { dmas = <&dmamux1 81 0x400 0x15>, <&dmamux1 82 0x400 0x11>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 41>; status = "disabled"; }; @@ -871,6 +899,7 @@ timers1: timer@44000000 { <&dmamux1 17 0x400 0x1>; dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig", "com"; + access-controllers = <&etzpc 48>; status = "disabled"; pwm { @@ -912,6 +941,7 @@ timers8: timer@44001000 { <&dmamux1 53 0x400 0x1>; dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig", "com"; + access-controllers = <&etzpc 49>; status = "disabled"; pwm { @@ -941,6 +971,7 @@ usart6: serial@44003000 { dmas = <&dmamux1 71 0x400 0x15>, <&dmamux1 72 0x400 0x11>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 51>; status = "disabled"; }; @@ -952,6 +983,7 @@ i2s1: audio-controller@44004000 { dmas = <&dmamux1 37 0x400 0x01>, <&dmamux1 38 0x400 0x01>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 52>; status = "disabled"; }; @@ -966,6 +998,7 @@ spi1: spi@44004000 { dmas = <&dmamux1 37 0x400 0x05>, <&dmamux1 38 0x400 0x05>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 52>; status = "disabled"; }; @@ -980,6 +1013,7 @@ spi4: spi@44005000 { dmas = <&dmamux1 83 0x400 0x05>, <&dmamux1 84 0x400 0x05>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 53>; status = "disabled"; }; @@ -997,6 +1031,7 @@ timers15: timer@44006000 { <&dmamux1 107 0x400 0x1>, <&dmamux1 108 0x400 0x1>; dma-names = "ch1", "up", "trig", "com"; + access-controllers = <&etzpc 54>; status = "disabled"; pwm { @@ -1024,6 +1059,7 @@ timers16: timer@44007000 { dmas = <&dmamux1 109 0x400 0x1>, <&dmamux1 110 0x400 0x1>; dma-names = "ch1", "up"; + access-controllers = <&etzpc 55>; status = "disabled"; pwm { @@ -1050,6 +1086,7 @@ timers17: timer@44008000 { dmas = <&dmamux1 111 0x400 0x1>, <&dmamux1 112 0x400 0x1>; dma-names = "ch1", "up"; + access-controllers = <&etzpc 56>; status = "disabled"; pwm { @@ -1076,6 +1113,7 @@ spi5: spi@44009000 { dmas = <&dmamux1 85 0x400 0x05>, <&dmamux1 86 0x400 0x05>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 57>; status = "disabled"; }; @@ -1087,6 +1125,7 @@ sai1: sai@4400a000 { reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; interrupts = ; resets = <&rcc SAI1_R>; + access-controllers = <&etzpc 58>; status = "disabled"; sai1a: audio-controller@4400a004 { @@ -1119,6 +1158,7 @@ sai2: sai@4400b000 { reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; interrupts = ; resets = <&rcc SAI2_R>; + access-controllers = <&etzpc 59>; status = "disabled"; sai2a: audio-controller@4400b004 { @@ -1150,6 +1190,7 @@ sai3: sai@4400c000 { reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; interrupts = ; resets = <&rcc SAI3_R>; + access-controllers = <&etzpc 60>; status = "disabled"; sai3a: audio-controller@4400c004 { @@ -1180,6 +1221,7 @@ dfsdm: dfsdm@4400d000 { clock-names = "dfsdm"; #address-cells = <1>; #size-cells = <0>; + access-controllers = <&etzpc 61>; status = "disabled"; dfsdm0: filter@0 { @@ -1259,6 +1301,7 @@ dma1: dma-controller@48000000 { #dma-cells = <4>; st,mem2mem; dma-requests = <8>; + access-controllers = <&etzpc 88>; }; dma2: dma-controller@48001000 { @@ -1277,6 +1320,7 @@ dma2: dma-controller@48001000 { #dma-cells = <4>; st,mem2mem; dma-requests = <8>; + access-controllers = <&etzpc 89>; }; dmamux1: dma-router@48002000 { @@ -1288,6 +1332,7 @@ dmamux1: dma-router@48002000 { dma-channels = <16>; clocks = <&rcc DMAMUX>; resets = <&rcc DMAMUX_R>; + access-controllers = <&etzpc 90>; }; adc: adc@48003000 { @@ -1302,6 +1347,7 @@ adc: adc@48003000 { #interrupt-cells = <1>; #address-cells = <1>; #size-cells = <0>; + access-controllers = <&etzpc 72>; status = "disabled"; adc1: adc@0 { @@ -1352,6 +1398,7 @@ sdmmc3: mmc@48004000 { cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <120000000>; + access-controllers = <&etzpc 86>; status = "disabled"; }; @@ -1369,6 +1416,7 @@ usbotg_hs: usb-otg@49000000 { dr_mode = "otg"; otg-rev = <0x200>; usb33d-supply = <&usb33>; + access-controllers = <&etzpc 85>; status = "disabled"; }; @@ -1381,6 +1429,7 @@ dcmi: dcmi@4c006000 { clock-names = "mclk"; dmas = <&dmamux1 75 0x400 0x01>; dma-names = "tx"; + access-controllers = <&etzpc 70>; status = "disabled"; }; @@ -1393,6 +1442,7 @@ lptimer2: timer@50021000 { clocks = <&rcc LPTIM2_K>; clock-names = "mux"; wakeup-source; + access-controllers = <&etzpc 64>; status = "disabled"; pwm { @@ -1422,6 +1472,7 @@ lptimer3: timer@50022000 { clocks = <&rcc LPTIM3_K>; clock-names = "mux"; wakeup-source; + access-controllers = <&etzpc 65>; status = "disabled"; pwm { @@ -1444,6 +1495,7 @@ lptimer4: timer@50023000 { clocks = <&rcc LPTIM4_K>; clock-names = "mux"; wakeup-source; + access-controllers = <&etzpc 66>; status = "disabled"; pwm { @@ -1460,6 +1512,7 @@ lptimer5: timer@50024000 { clocks = <&rcc LPTIM5_K>; clock-names = "mux"; wakeup-source; + access-controllers = <&etzpc 67>; status = "disabled"; pwm { @@ -1475,6 +1528,7 @@ vrefbuf: vrefbuf@50025000 { regulator-min-microvolt = <1500000>; regulator-max-microvolt = <2500000>; clocks = <&rcc VREF>; + access-controllers = <&etzpc 69>; status = "disabled"; }; @@ -1486,6 +1540,7 @@ sai4: sai@50027000 { reg = <0x50027000 0x4>, <0x500273f0 0x10>; interrupts = ; resets = <&rcc SAI4_R>; + access-controllers = <&etzpc 68>; status = "disabled"; sai4a: audio-controller@50027004 { @@ -1518,6 +1573,7 @@ hash1: hash@54002000 { dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; dma-names = "in"; dma-maxburst = <2>; + access-controllers = <&etzpc 8>; status = "disabled"; }; @@ -1526,6 +1582,7 @@ rng1: rng@54003000 { reg = <0x54003000 0x400>; clocks = <&rcc RNG1_K>; resets = <&rcc RNG1_R>; + access-controllers = <&etzpc 7>; status = "okay"; }; @@ -1536,6 +1593,7 @@ fmc: memory-controller@58002000 { reg = <0x58002000 0x1000>; clocks = <&rcc FMC_K>; resets = <&rcc FMC_R>; + access-controllers = <&etzpc 91>; status = "disabled"; ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ @@ -1575,6 +1633,7 @@ qspi: spi@58003000 { resets = <&rcc QSPI_R>; #address-cells = <1>; #size-cells = <0>; + access-controllers = <&etzpc 92>; status = "disabled"; }; @@ -1602,6 +1661,7 @@ ethernet0: ethernet@5800a000 { snps,en-tx-lpi-clockgating; snps,axi-config = <&stmmac_axi_config_0>; snps,tso; + access-controllers = <&etzpc 94>; status = "disabled"; stmmac_axi_config_0: stmmac-axi-config { @@ -1617,6 +1677,7 @@ usart1: serial@5c000000 { interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc USART1_K>; wakeup-source; + access-controllers = <&etzpc 3>; status = "disabled"; }; @@ -1630,6 +1691,7 @@ spi6: spi@5c001000 { resets = <&rcc SPI6_R>; dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, <&mdma1 35 0x0 0x40002 0x0 0x0>; + access-controllers = <&etzpc 4>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -1647,6 +1709,7 @@ i2c4: i2c@5c002000 { st,syscfg-fmp = <&syscfg 0x4 0x8>; wakeup-source; i2c-analog-filter; + access-controllers = <&etzpc 5>; status = "disabled"; }; @@ -1663,6 +1726,7 @@ i2c6: i2c@5c009000 { st,syscfg-fmp = <&syscfg 0x4 0x20>; wakeup-source; i2c-analog-filter; + access-controllers = <&etzpc 12>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/st/stm32mp153.dtsi b/arch/arm/boot/dts/st/stm32mp153.dtsi index 36e17ea0b179..4640dafb1598 100644 --- a/arch/arm/boot/dts/st/stm32mp153.dtsi +++ b/arch/arm/boot/dts/st/stm32mp153.dtsi @@ -41,6 +41,7 @@ m_can1: can@4400e000 { clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; clock-names = "hclk", "cclk"; bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; + access-controllers = <&etzpc 62>; status = "disabled"; }; @@ -54,6 +55,7 @@ m_can2: can@4400f000 { clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; clock-names = "hclk", "cclk"; bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; + access-controllers = <&etzpc 62>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/st/stm32mp15xc.dtsi b/arch/arm/boot/dts/st/stm32mp15xc.dtsi index d36c3457451a..97465717f932 100644 --- a/arch/arm/boot/dts/st/stm32mp15xc.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xc.dtsi @@ -11,6 +11,7 @@ cryp1: cryp@54001000 { interrupts = ; clocks = <&rcc CRYP1>; resets = <&rcc CRYP1_R>; + access-controllers = <&etzpc 9>; status = "disabled"; }; }; From patchwork Tue Dec 12 15:23:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gatien CHEVALLIER X-Patchwork-Id: 753867 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="t/MkDzcs" Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CED721B6; Tue, 12 Dec 2023 07:28:30 -0800 (PST) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3BCDTj5q030770; Tue, 12 Dec 2023 16:27:45 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=A5E3Yu4fIV5aU7qtI3/a6w1HvBafHrdmVAlZVmDmZf8=; b=t/ MkDzcs97RJTybMv0GdhkYCl2CsJvbP8D59E+Gc4Qn9DeoaEmlcDrsoXYd6kO9Yct 5eLkh+QwurAaviZ4O3szR7dhoVz4mBCbkCIdXFxsN5/tWK8gEs7q8Ba3hwqcf7+I R065+ObzoCVoRLMImemhjuhLNnAoquPiUHC5fQxHnLXpOaofrOwxjNDJssfUTc7M qfz09yiho6vN22qYBThkA5rCMt+Jml1ZHd6y9lKpqOoQfdR5yJUAD3cB8zKNSWtU 37DRUMA0xseOaMfsg+aAhUmc1KUFp8XggfR7w3fX9nc8t+olhrIeGM2/LVxCjQuN ZOwBDIjat23I5zfhehWA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3uve88uyxn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Dec 2023 16:27:45 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 2622C100060; Tue, 12 Dec 2023 16:27:45 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 1695522F7C8; Tue, 12 Dec 2023 16:27:45 +0100 (CET) Received: from localhost (10.252.7.20) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 12 Dec 2023 16:27:44 +0100 From: Gatien Chevallier To: , , , , , , , , , , , , , , , , , , , , , , , , , Frank Rowand , , , , , CC: , , , , , , , , , , , , , , , , Gatien Chevallier Subject: [PATCH v8 13/13] ARM: dts: stm32: put ETZPC as an access controller for STM32MP13x boards Date: Tue, 12 Dec 2023 16:23:56 +0100 Message-ID: <20231212152356.345703-14-gatien.chevallier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231212152356.345703-1-gatien.chevallier@foss.st.com> References: <20231212152356.345703-1-gatien.chevallier@foss.st.com> Precedence: bulk X-Mailing-List: linux-usb@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-12_09,2023-12-12_01,2023-05-22_02 Reference ETZPC as an access-control-provider. For more information on which peripheral is securable or supports MCU isolation, please read the STM32MP13 reference manual Signed-off-by: Gatien Chevallier --- Patch not present in V6 arch/arm/boot/dts/st/stm32mp131.dtsi | 26 ++++++++++++++++++++++++++ arch/arm/boot/dts/st/stm32mp133.dtsi | 1 + arch/arm/boot/dts/st/stm32mp13xc.dtsi | 1 + arch/arm/boot/dts/st/stm32mp13xf.dtsi | 1 + 4 files changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index 6ba8e3fd43b0..74ceece168ce 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -883,6 +883,7 @@ etzpc: bus@5c007000 { reg = <0x5c007000 0x400>; #address-cells = <1>; #size-cells = <1>; + #access-controller-cells = <1>; ranges; adc_2: adc@48004000 { @@ -895,6 +896,7 @@ adc_2: adc@48004000 { #interrupt-cells = <1>; #address-cells = <1>; #size-cells = <0>; + access-controllers = <&etzpc 33>; status = "disabled"; adc2: adc@0 { @@ -942,6 +944,7 @@ usbotg_hs: usb@49000000 { dr_mode = "otg"; otg-rev = <0x200>; usb33d-supply = <&scmi_usb33>; + access-controllers = <&etzpc 34>; status = "disabled"; }; @@ -955,6 +958,7 @@ usart1: serial@4c000000 { dmas = <&dmamux1 41 0x400 0x5>, <&dmamux1 42 0x400 0x1>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 16>; status = "disabled"; }; @@ -968,6 +972,7 @@ usart2: serial@4c001000 { dmas = <&dmamux1 43 0x400 0x5>, <&dmamux1 44 0x400 0x1>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 17>; status = "disabled"; }; @@ -979,6 +984,7 @@ i2s4: audio-controller@4c002000 { dmas = <&dmamux1 83 0x400 0x01>, <&dmamux1 84 0x400 0x01>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 13>; status = "disabled"; }; @@ -993,6 +999,7 @@ spi4: spi@4c002000 { dmas = <&dmamux1 83 0x400 0x01>, <&dmamux1 84 0x400 0x01>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 18>; status = "disabled"; }; @@ -1007,6 +1014,7 @@ spi5: spi@4c003000 { dmas = <&dmamux1 85 0x400 0x01>, <&dmamux1 86 0x400 0x01>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 19>; status = "disabled"; }; @@ -1025,6 +1033,7 @@ i2c3: i2c@4c004000 { dma-names = "rx", "tx"; st,syscfg-fmp = <&syscfg 0x4 0x4>; i2c-analog-filter; + access-controllers = <&etzpc 20>; status = "disabled"; }; @@ -1043,6 +1052,7 @@ i2c4: i2c@4c005000 { dma-names = "rx", "tx"; st,syscfg-fmp = <&syscfg 0x4 0x8>; i2c-analog-filter; + access-controllers = <&etzpc 21>; status = "disabled"; }; @@ -1061,6 +1071,7 @@ i2c5: i2c@4c006000 { dma-names = "rx", "tx"; st,syscfg-fmp = <&syscfg 0x4 0x10>; i2c-analog-filter; + access-controllers = <&etzpc 22>; status = "disabled"; }; @@ -1073,6 +1084,7 @@ timers12: timer@4c007000 { interrupt-names = "global"; clocks = <&rcc TIM12_K>; clock-names = "int"; + access-controllers = <&etzpc 23>; status = "disabled"; pwm { @@ -1097,6 +1109,7 @@ timers13: timer@4c008000 { interrupt-names = "global"; clocks = <&rcc TIM13_K>; clock-names = "int"; + access-controllers = <&etzpc 24>; status = "disabled"; pwm { @@ -1121,6 +1134,7 @@ timers14: timer@4c009000 { interrupt-names = "global"; clocks = <&rcc TIM14_K>; clock-names = "int"; + access-controllers = <&etzpc 25>; status = "disabled"; pwm { @@ -1150,6 +1164,7 @@ timers15: timer@4c00a000 { <&dmamux1 107 0x400 0x1>, <&dmamux1 108 0x400 0x1>; dma-names = "ch1", "up", "trig", "com"; + access-controllers = <&etzpc 26>; status = "disabled"; pwm { @@ -1177,6 +1192,7 @@ timers16: timer@4c00b000 { dmas = <&dmamux1 109 0x400 0x1>, <&dmamux1 110 0x400 0x1>; dma-names = "ch1", "up"; + access-controllers = <&etzpc 27>; status = "disabled"; pwm { @@ -1204,6 +1220,7 @@ timers17: timer@4c00c000 { dmas = <&dmamux1 111 0x400 0x1>, <&dmamux1 112 0x400 0x1>; dma-names = "ch1", "up"; + access-controllers = <&etzpc 28>; status = "disabled"; pwm { @@ -1228,6 +1245,7 @@ lptimer2: timer@50021000 { clocks = <&rcc LPTIM2_K>; clock-names = "mux"; wakeup-source; + access-controllers = <&etzpc 1>; status = "disabled"; pwm { @@ -1262,6 +1280,7 @@ lptimer3: timer@50022000 { clocks = <&rcc LPTIM3_K>; clock-names = "mux"; wakeup-source; + access-controllers = <&etzpc 2>; status = "disabled"; pwm { @@ -1290,6 +1309,7 @@ hash: hash@54003000 { resets = <&rcc HASH1_R>; dmas = <&mdma 30 0x2 0x1000a02 0x0 0x0>; dma-names = "in"; + access-controllers = <&etzpc 41>; }; rng: rng@54004000 { @@ -1297,6 +1317,7 @@ rng: rng@54004000 { reg = <0x54004000 0x400>; clocks = <&rcc RNG1_K>; resets = <&rcc RNG1_R>; + access-controllers = <&etzpc 40>; }; fmc: memory-controller@58002000 { @@ -1311,6 +1332,7 @@ fmc: memory-controller@58002000 { #size-cells = <1>; clocks = <&rcc FMC_K>; resets = <&rcc FMC_R>; + access-controllers = <&etzpc 54>; status = "disabled"; nand-controller@4,0 { @@ -1344,6 +1366,7 @@ qspi: spi@58003000 { dma-names = "tx", "rx"; clocks = <&rcc QSPI_K>; resets = <&rcc QSPI_R>; + access-controllers = <&etzpc 55>; status = "disabled"; }; @@ -1358,6 +1381,7 @@ sdmmc1: mmc@58005000 { cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <130000000>; + access-controllers = <&etzpc 50>; status = "disabled"; }; @@ -1372,6 +1396,7 @@ sdmmc2: mmc@58007000 { cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <130000000>; + access-controllers = <&etzpc 51>; status = "disabled"; }; @@ -1385,6 +1410,7 @@ usbphyc: usbphyc@5a006000 { resets = <&rcc USBPHY_R>; vdda1v1-supply = <&scmi_reg11>; vdda1v8-supply = <&scmi_reg18>; + access-controllers = <&etzpc 5>; status = "disabled"; usbphyc_port0: usb-phy@0 { diff --git a/arch/arm/boot/dts/st/stm32mp133.dtsi b/arch/arm/boot/dts/st/stm32mp133.dtsi index c4d3a520c14b..3e394c8e58b9 100644 --- a/arch/arm/boot/dts/st/stm32mp133.dtsi +++ b/arch/arm/boot/dts/st/stm32mp133.dtsi @@ -47,6 +47,7 @@ adc_1: adc@48003000 { #interrupt-cells = <1>; #address-cells = <1>; #size-cells = <0>; + access-controllers = <&etzpc 32>; status = "disabled"; adc1: adc@0 { diff --git a/arch/arm/boot/dts/st/stm32mp13xc.dtsi b/arch/arm/boot/dts/st/stm32mp13xc.dtsi index b9fb071a1471..a8bd5fe6536c 100644 --- a/arch/arm/boot/dts/st/stm32mp13xc.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13xc.dtsi @@ -11,6 +11,7 @@ cryp: crypto@54002000 { interrupts = ; clocks = <&rcc CRYP1>; resets = <&rcc CRYP1_R>; + access-controllers = <&etzpc 42>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/st/stm32mp13xf.dtsi b/arch/arm/boot/dts/st/stm32mp13xf.dtsi index b9fb071a1471..a8bd5fe6536c 100644 --- a/arch/arm/boot/dts/st/stm32mp13xf.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13xf.dtsi @@ -11,6 +11,7 @@ cryp: crypto@54002000 { interrupts = ; clocks = <&rcc CRYP1>; resets = <&rcc CRYP1_R>; + access-controllers = <&etzpc 42>; status = "disabled"; }; };