From patchwork Wed Dec 13 16:28:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 753663 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="EPaCDW3X" Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E3B3891 for ; Wed, 13 Dec 2023 08:29:05 -0800 (PST) Received: by mail-lf1-x12e.google.com with SMTP id 2adb3069b0e04-50be10acaf9so7005470e87.1 for ; Wed, 13 Dec 2023 08:29:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702484944; x=1703089744; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NEzLaoNa4BA2w8OvaI5sizwaYC3nqK5NDpqXu6xPo90=; b=EPaCDW3X65pt9lfhQDirUMYk6SCoBK/3UDqFB0I/I4ffRoHzcZgU/2n/oE3Y8VJ1ST 09QWKkA3NX+8kwydIeMpnuL1Tic5bu6GdW32RMYHKCTFDkhcQu/uEya/clUz9upHQG36 vmY7SPwX7Dg65keGSow7WOFAk6MRnUrywU2g0RYMuEkXCa19Ku6luR09CVKDAz1cgsOA 9VKgkj5OJgXoBwPcrcrLNIJd34Ib3aoanBKNwsO5zaczD1lzxGUP84mSLx2VaA/mG8wA UHu5Am8ufx7NHpWmsY9wskoPFxCughn9IKmGm9fGnjq2IS9gsLcWY6zSzeJ59JIRZPUV Q3Qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702484944; x=1703089744; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NEzLaoNa4BA2w8OvaI5sizwaYC3nqK5NDpqXu6xPo90=; b=L+nnNZlAHGAH72I5mr4wOO6bfU9Z5ramBRPUPY+FBn89JKBkhyUXuih9Me95R7zyZW 9etrWDGmj9hTSqLdUgEnkqONLWkGWsHg0LQLRDKZUod5zggJKrS9ns0dfN6ySV1Ajbec gqO7ukdb4gw9OQ59xCBkHXtj+BLaD6mlDDMr0KmxHlvgDs/3O0brkWIYPrCe+9KkKZ2Q pVA8LZpiIr+y5+lPgwzTPl5p2RG97V2/M0fzfbZP8V9q7h1HV/hVYtVI8tCgcyvSI8xA j+mPndu8JezrbRFJhd5ywCEQYkWBdtU6f1CypAUVBoR68TBhm1W6Pqk1OvnB3cTsAcNB l9LA== X-Gm-Message-State: AOJu0YwADHBj99FsjxOvZ5p2TU9jzYdBgw/1OmS/gW1k8+m58xU5mCrV Y4cPd/8aQ+8dCCxcN3fxL6lhCA== X-Google-Smtp-Source: AGHT+IHtY5gkQmmJhndNfLTuymBN96U+PgF076ivxPPJWBCxoTTijgt9TkViwC9hvJ0o+aI9ZxUjpA== X-Received: by 2002:a19:5e1d:0:b0:50b:f03c:1eb2 with SMTP id s29-20020a195e1d000000b0050bf03c1eb2mr3934707lfb.20.1702484944075; Wed, 13 Dec 2023 08:29:04 -0800 (PST) Received: from krzk-bin.. ([178.197.218.27]) by smtp.gmail.com with ESMTPSA id br7-20020a056512400700b0050bfe37d28asm1641026lfb.34.2023.12.13.08.29.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 08:29:03 -0800 (PST) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v2 1/4] arm64: dts: qcom: sm8450: move Soundwire pinctrl to its nodes Date: Wed, 13 Dec 2023 17:28:53 +0100 Message-Id: <20231213162856.188566-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231213162856.188566-1-krzysztof.kozlowski@linaro.org> References: <20231213162856.188566-1-krzysztof.kozlowski@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Pin configuration for Soundwire bus should be set in Soundwire controller nodes, not in the associated macro codec node. This placement change should not have big impact in general, because macro codec is a clock provider for Soundwire controller, thus its devices is probed first. However it will have impact for disabled Soundwire buses, e.g. WSA2, because after this change the pins will be left in default state. We also follow similar approach in newer SoCs, like Qualcomm SM8650. Signed-off-by: Krzysztof Kozlowski --- Not tested on HW. --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 12e55a0c7417..3b6ea9653d2a 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2160,8 +2160,6 @@ wsa2macro: codec@31e0000 { #clock-cells = <0>; clock-output-names = "wsa2-mclk"; - pinctrl-names = "default"; - pinctrl-0 = <&wsa2_swr_active>; #sound-dai-cells = <1>; }; @@ -2173,6 +2171,9 @@ swr4: soundwire-controller@31f0000 { clock-names = "iface"; label = "WSA2"; + pinctrl-0 = <&wsa2_swr_active>; + pinctrl-names = "default"; + qcom,din-ports = <2>; qcom,dout-ports = <6>; @@ -2208,8 +2209,6 @@ rxmacro: codec@3200000 { #clock-cells = <0>; clock-output-names = "mclk"; - pinctrl-names = "default"; - pinctrl-0 = <&rx_swr_active>; #sound-dai-cells = <1>; }; @@ -2223,6 +2222,9 @@ swr1: soundwire-controller@3210000 { qcom,din-ports = <0>; qcom,dout-ports = <5>; + pinctrl-0 = <&rx_swr_active>; + pinctrl-names = "default"; + qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; @@ -2254,8 +2256,6 @@ txmacro: codec@3220000 { #clock-cells = <0>; clock-output-names = "mclk"; - pinctrl-names = "default"; - pinctrl-0 = <&tx_swr_active>; #sound-dai-cells = <1>; }; @@ -2275,8 +2275,6 @@ wsamacro: codec@3240000 { #clock-cells = <0>; clock-output-names = "mclk"; - pinctrl-names = "default"; - pinctrl-0 = <&wsa_swr_active>; #sound-dai-cells = <1>; }; @@ -2288,6 +2286,9 @@ swr0: soundwire-controller@3250000 { clock-names = "iface"; label = "WSA"; + pinctrl-0 = <&wsa_swr_active>; + pinctrl-names = "default"; + qcom,din-ports = <2>; qcom,dout-ports = <6>; @@ -2318,6 +2319,9 @@ swr2: soundwire-controller@33b0000 { clock-names = "iface"; label = "TX"; + pinctrl-0 = <&tx_swr_active>; + pinctrl-names = "default"; + qcom,din-ports = <4>; qcom,dout-ports = <0>; qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; From patchwork Wed Dec 13 16:28:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 753662 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="dYnjOtpm" Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C1F6F4 for ; Wed, 13 Dec 2023 08:29:10 -0800 (PST) Received: by mail-lf1-x12f.google.com with SMTP id 2adb3069b0e04-50bf7bc38c0so8116554e87.2 for ; Wed, 13 Dec 2023 08:29:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702484948; x=1703089748; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uDQI7CGNXE5QtDrGTA7vjhneNjlnGJyq3B8Gpd+RnjY=; b=dYnjOtpmKjg4GHWhqzNDp6EKEDaiJS8Nx+2o8mHB8bhiqjDodq7dChEPR6L+dSTC1X DqI1HnyTr9MZP1mTRLaAQrb3GtFS/RvifnO61mkRcOApX/y4EZkKBO+4UexRQ5quGShJ 8TLZ13SUnU6tqagVqOWaQjaDNxkj87usGsxKTZ/ayWO7UF1eq6TIC40mfoBCLFD/XSyL jHf+1etIble+SvvrZ+2vGh+c+pH77c4cIXRPhjRgDqqQy4IYwvzJ4FQD0EHL5CpyjFP0 XU97jFXo1sVtfWg2IERRN8YXr/dZ7xL9l3OST+JrtDSCUDGm2ZN9YhiDdlPrn8zRQv8U kZ9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702484948; x=1703089748; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uDQI7CGNXE5QtDrGTA7vjhneNjlnGJyq3B8Gpd+RnjY=; b=BWBtRoCROtFUDi1aIr4nXu+v1oV2kG6kiLSWzxAXVUj4ViHG20niR+SD5jr+lmuLO2 AmoXErJy3Al24uLMVy2xemw2NyiDCE0Zl96xfmUUjDCbuakx6klTvPFTjkLgkcg0x5EM 5jhvXyrctf+9s/41PXX2S/85dh3rAiGLSsr77l/9aOhKGYFp+DVc1uY6plcpSOwJDm0s CsF5kCdWsYIIQP1r70Z3U9Q5pvB+UOH3x3hCRO+Xsmvd0OdUVEbp/8wld1CKtB/XMDO9 z6y6KuwCbmswRhzqh5lGoVrhty3OCKCmNEcABqPWdb9Cq9iqUFgjq24w7pMfOp6B2Jm5 rDwQ== X-Gm-Message-State: AOJu0YzrBxdZKEgjQl30+dx4V5xdeLeq/L19wKjSW++e/APDcvUM8wTA Iv5SKjh5L7V8YFrx3KxUa86D/A== X-Google-Smtp-Source: AGHT+IF3V4GjzyZmMwHdlCvCM9mUMLaBxXfJBCvlAZ8+rLP7Wm0ND/VzVwR6nDgB+2BRfaOBZJH5tQ== X-Received: by 2002:a19:2d5e:0:b0:50b:e6ff:e53e with SMTP id t30-20020a192d5e000000b0050be6ffe53emr3148181lft.9.1702484948105; Wed, 13 Dec 2023 08:29:08 -0800 (PST) Received: from krzk-bin.. ([178.197.218.27]) by smtp.gmail.com with ESMTPSA id br7-20020a056512400700b0050bfe37d28asm1641026lfb.34.2023.12.13.08.29.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 08:29:07 -0800 (PST) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v2 3/4] arm64: dts: qcom: sm8550: move Soundwire pinctrl to its nodes Date: Wed, 13 Dec 2023 17:28:55 +0100 Message-Id: <20231213162856.188566-4-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231213162856.188566-1-krzysztof.kozlowski@linaro.org> References: <20231213162856.188566-1-krzysztof.kozlowski@linaro.org> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Pin configuration for Soundwire bus should be set in Soundwire controller nodes, not in the associated macro codec node. This placement change should not have big impact in general, because macro codec is a clock provider for Soundwire controller, thus its devices is probed first. However it will have impact for disabled Soundwire buses, e.g. WSA2, because after this change the pins will be left in default state. We also follow similar approach in newer SoCs, like Qualcomm SM8650. Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 1f06fd33d1ce..d8f79b5895f5 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2050,8 +2050,6 @@ lpass_wsa2macro: codec@6aa0000 { #clock-cells = <0>; clock-output-names = "wsa2-mclk"; - pinctrl-names = "default"; - pinctrl-0 = <&wsa2_swr_active>; #sound-dai-cells = <1>; }; @@ -2063,6 +2061,9 @@ swr3: soundwire-controller@6ab0000 { clock-names = "iface"; label = "WSA2"; + pinctrl-0 = <&wsa2_swr_active>; + pinctrl-names = "default"; + qcom,din-ports = <4>; qcom,dout-ports = <9>; @@ -2096,8 +2097,6 @@ lpass_rxmacro: codec@6ac0000 { #clock-cells = <0>; clock-output-names = "mclk"; - pinctrl-names = "default"; - pinctrl-0 = <&rx_swr_active>; #sound-dai-cells = <1>; }; @@ -2109,6 +2108,9 @@ swr1: soundwire-controller@6ad0000 { clock-names = "iface"; label = "RX"; + pinctrl-0 = <&rx_swr_active>; + pinctrl-names = "default"; + qcom,din-ports = <1>; qcom,dout-ports = <11>; @@ -2142,8 +2144,6 @@ lpass_txmacro: codec@6ae0000 { #clock-cells = <0>; clock-output-names = "mclk"; - pinctrl-names = "default"; - pinctrl-0 = <&tx_swr_active>; #sound-dai-cells = <1>; }; @@ -2161,8 +2161,6 @@ lpass_wsamacro: codec@6b00000 { #clock-cells = <0>; clock-output-names = "mclk"; - pinctrl-names = "default"; - pinctrl-0 = <&wsa_swr_active>; #sound-dai-cells = <1>; }; @@ -2174,6 +2172,9 @@ swr0: soundwire-controller@6b10000 { clock-names = "iface"; label = "WSA"; + pinctrl-0 = <&wsa_swr_active>; + pinctrl-names = "default"; + qcom,din-ports = <4>; qcom,dout-ports = <9>; @@ -2203,6 +2204,9 @@ swr2: soundwire-controller@6d30000 { clock-names = "iface"; label = "TX"; + pinctrl-0 = <&tx_swr_active>; + pinctrl-names = "default"; + qcom,din-ports = <4>; qcom,dout-ports = <0>; qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;