From patchwork Wed Dec 13 22:36:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Cheatham X-Patchwork-Id: 753558 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="FTTmIBHZ" Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2070.outbound.protection.outlook.com [40.107.244.70]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 17DA7CD; Wed, 13 Dec 2023 14:37:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=aRs7Rz9lPv1Tk/xUJ0Ua/Wgbs+odMTv/cYb/qlUmW78iD/279L3rEVWphrrd1XCg+DSkC1zoPCPCvYgLc4A3DJYFo6PE0FTAdUpvzwoERfm0Ybsj9Z7g/AXQTap84e4fy/u6mo3bWYMXt28tMIoTcu20qNCNTanbLsDAMzElCP2IlDheLwK8gX5br1EOJ3sZ1zwSKaV3bso5yps/fI19VjEFYMgP7BnxJ3jgXmtqoXD4s673IFdtXBxOxJa4CXuEgDuUIIEn0dcJQC7nt2zZRyIUjYFF/qH7ug8l9iheB/Bro0MJEMl2v3TGirNkvzft3jCsfRNv1EnMX92z8RHa6A== ARC-Message-Signature: i=1; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SN1PEPF0002BA52.mail.protection.outlook.com (10.167.242.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7091.26 via Frontend Transport; Wed, 13 Dec 2023 22:37:27 +0000 Received: from bcheatha-HP-EliteBook-845-G8-Notebook-PC.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Wed, 13 Dec 2023 16:37:22 -0600 From: Ben Cheatham To: , , , , , , , CC: , , Subject: [PATCH v8 1/5] cxl, ACPI, APEI, EINJ: Add CXL_EINJ Kconfig option Date: Wed, 13 Dec 2023 16:36:58 -0600 Message-ID: <20231213223702.543419-2-Benjamin.Cheatham@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231213223702.543419-1-Benjamin.Cheatham@amd.com> References: <20231213223702.543419-1-Benjamin.Cheatham@amd.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA52:EE_|DS0PR12MB7802:EE_ X-MS-Office365-Filtering-Correlation-Id: 19322675-5b89-47b2-bb6f-08dbfc2c15d1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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This option will allow for the CXL core module to access helpers inside the EINJ module, while also giving users the option of disabling CXL EINJ error types at build time. Also update CONFIG_ACPI_APEI_EINJ to set CONFIG_CXL_EINJ by default. Reviewed-by: Jonathan Cameron Signed-off-by: Ben Cheatham --- drivers/acpi/apei/Kconfig | 1 + drivers/cxl/Kconfig | 12 ++++++++++++ 2 files changed, 13 insertions(+) diff --git a/drivers/acpi/apei/Kconfig b/drivers/acpi/apei/Kconfig index 6b18f8bc7be3..4c3f0ec5731e 100644 --- a/drivers/acpi/apei/Kconfig +++ b/drivers/acpi/apei/Kconfig @@ -55,6 +55,7 @@ config ACPI_APEI_MEMORY_FAILURE config ACPI_APEI_EINJ tristate "APEI Error INJection (EINJ)" depends on ACPI_APEI && DEBUG_FS + imply CXL_BUS help EINJ provides a hardware error injection mechanism, it is mainly used for debugging and testing the other parts of diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig index 8ea1d340e438..6f4adcd733e5 100644 --- a/drivers/cxl/Kconfig +++ b/drivers/cxl/Kconfig @@ -154,4 +154,16 @@ config CXL_PMU monitoring units and provide standard perf based interfaces. If unsure say 'm'. + +config CXL_EINJ + bool "CXL Error INJection Support" + default ACPI_APEI_EINJ + depends on ACPI_APEI_EINJ && ACPI_APEI_EINJ=CXL_BUS + help + Support for CXL protocol Error INJection through debugfs/cxl. + Availability and which errors are supported is dependent on + the host platform. Look to ACPI v6.5 section 18.6.4 and kernel + EINJ documentation for more information. + + If unsure say 'n' endif From patchwork Wed Dec 13 22:36:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Cheatham X-Patchwork-Id: 754363 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="YKBEB0X7" Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2064.outbound.protection.outlook.com [40.107.237.64]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B177EB7; Wed, 13 Dec 2023 14:37:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=gOGTtzGB5PcImjAaeS6VmNYu3NmHKY4/ly2j3VAOi+HcmJmA6HF21qpdUu3rTTPNVx8KISIXqEV42rb3Naqa5ywkpxnPMO2CGBz3FbG/HrGFlaPhlt2X8QwgPrNtdWpiizm3IfpPPJC3wAEEQLV1OhuR/04wyOGSEu36VEi2JDoONYWimc2uF6Arm7pdqzGjIZFPlw1H5/efqT077O3smFbLovhk9u+A9qjsU6nyWsAe7n/fss5xNM1ITL55nvXP1+BP5ncZf7r74HN1JUZwz2f1DrbidDB9r/zMEQ+xIGZE5AaFzNBgbaQmewpir7+p6n0zhNER7IHjmqWu5zl97g== ARC-Message-Signature: i=1; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SN1PEPF0002BA4F.mail.protection.outlook.com (10.167.242.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7091.26 via Frontend Transport; Wed, 13 Dec 2023 22:37:43 +0000 Received: from bcheatha-HP-EliteBook-845-G8-Notebook-PC.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Wed, 13 Dec 2023 16:37:40 -0600 From: Ben Cheatham To: , , , , , , , CC: , , Subject: [PATCH v8 2/5] ACPI, APEI, EINJ: Add wrapper __init function Date: Wed, 13 Dec 2023 16:36:59 -0600 Message-ID: <20231213223702.543419-3-Benjamin.Cheatham@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231213223702.543419-1-Benjamin.Cheatham@amd.com> References: <20231213223702.543419-1-Benjamin.Cheatham@amd.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA4F:EE_|PH0PR12MB8051:EE_ X-MS-Office365-Filtering-Correlation-Id: 026c98ec-9d0e-4f2b-d980-08dbfc2c1f46 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Instead of porting the EINJ module to a library module, add a wrapper __init function around einj_init() to pin the EINJ module even if it does not initialize correctly. This should be fine since the EINJ module is only ever unloaded manually. One note: since the CXL core will be calling into the EINJ module directly, even though it may not have initialized, all CXL helper functions *have* to check if the EINJ module is initialized before doing any work. Reviewed-by: Jonathan Cameron Signed-off-by: Ben Cheatham Signed-off-by: Dan Williams --- drivers/acpi/apei/einj.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/acpi/apei/einj.c b/drivers/acpi/apei/einj.c index 013eb621dc92..26a887d2a5cd 100644 --- a/drivers/acpi/apei/einj.c +++ b/drivers/acpi/apei/einj.c @@ -615,6 +615,8 @@ static int available_error_type_show(struct seq_file *m, void *v) DEFINE_SHOW_ATTRIBUTE(available_error_type); +static bool einj_initialized; + static int error_type_get(void *data, u64 *val) { *val = error_type; @@ -684,7 +686,7 @@ static int einj_check_table(struct acpi_table_einj *einj_tab) return 0; } -static int __init einj_init(void) +static int __init __einj_init(void) { int rc; acpi_status status; @@ -782,10 +784,31 @@ static int __init einj_init(void) return rc; } +static int __init einj_init(void) +{ + int rc = __einj_init(); + + einj_initialized = (rc == 0); + + /* + * CXL needs to be able to link and call its EINJ helpers + * regardless of whether the EINJ table is present and initialized + * correctly. CXL helpers check @einj_initialized before + * doing any work. + */ + if (IS_ENABLED(CONFIG_CXL_EINJ)) + return 0; + + return rc; +} + static void __exit einj_exit(void) { struct apei_exec_context ctx; + if (!einj_initialized) + return; + if (einj_param) { acpi_size size = (acpi5) ? sizeof(struct set_error_type_with_address) : From patchwork Wed Dec 13 22:37:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Cheatham X-Patchwork-Id: 753557 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="aqFUEwTL" Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2085.outbound.protection.outlook.com [40.107.94.85]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE5E1CD; Wed, 13 Dec 2023 14:38:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=iVIdFYvcks/CusGRxDFkUHkcWxYmhVdRxgD0YkHeEqK2UkUI7tyMNQ3uhRg9a5Vyl253dXskQmyXB7mG3AzWHuj90+fJYZaaOnMnH4MAnaqhX9k67fR7dy2GoLwnlKcKSo1ySaDrmH2EIyuLjcMzlJzTXBnCAdFmLoVDzYXjXMFUcjmokB6cbp30A1bwAcm/en8JfThkws0DSEXBLl/MCKiCt3A1WK0KJlRuhlhHb39gnVA3QUo3KIwCS8G16rxiTwDqhXCMs7Ll9qsXXepUsswM1BB5c5u94Qh/sGMWyOv/UlGFe0es5l01KeeJb+48f4paO6xzXs+aez6O0X08Vw== ARC-Message-Signature: i=1; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SN1PEPF0002BA4C.mail.protection.outlook.com (10.167.242.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7091.26 via Frontend Transport; Wed, 13 Dec 2023 22:37:59 +0000 Received: from bcheatha-HP-EliteBook-845-G8-Notebook-PC.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Wed, 13 Dec 2023 16:37:56 -0600 From: Ben Cheatham To: , , , , , , , CC: , , Subject: [PATCH v8 3/5] ACPI: Add CXL protocol error defines Date: Wed, 13 Dec 2023 16:37:00 -0600 Message-ID: <20231213223702.543419-4-Benjamin.Cheatham@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231213223702.543419-1-Benjamin.Cheatham@amd.com> References: <20231213223702.543419-1-Benjamin.Cheatham@amd.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA4C:EE_|SJ0PR12MB5439:EE_ X-MS-Office365-Filtering-Correlation-Id: a85b365f-110d-4045-c39d-08dbfc2c28eb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Reviewed-by: Jonathan Cameron Signed-off-by: Ben Cheatham --- I made a pull request for this support in the ACPICA project which has been accepted (link below), so this patch is temporary and I expect it to be dropped once the kernel updates from ACPICA. [1]: Link: https://github.com/acpica/acpica/pull/884 --- include/acpi/actbl1.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index a33375e055ad..1f58c5d86869 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h @@ -1096,6 +1096,12 @@ enum acpi_einj_command_status { #define ACPI_EINJ_PLATFORM_CORRECTABLE (1<<9) #define ACPI_EINJ_PLATFORM_UNCORRECTABLE (1<<10) #define ACPI_EINJ_PLATFORM_FATAL (1<<11) +#define ACPI_EINJ_CXL_CACHE_CORRECTABLE (1<<12) +#define ACPI_EINJ_CXL_CACHE_UNCORRECTABLE (1<<13) +#define ACPI_EINJ_CXL_CACHE_FATAL (1<<14) +#define ACPI_EINJ_CXL_MEM_CORRECTABLE (1<<15) +#define ACPI_EINJ_CXL_MEM_UNCORRECTABLE (1<<16) +#define ACPI_EINJ_CXL_MEM_FATAL (1<<17) #define ACPI_EINJ_VENDOR_DEFINED (1<<31) /******************************************************************************* From patchwork Wed Dec 13 22:37:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Cheatham X-Patchwork-Id: 754362 Authentication-Results: smtp.subspace.kernel.org; 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Wed, 13 Dec 2023 16:38:10 -0600 From: Ben Cheatham To: , , , , , , , CC: , , Subject: [PATCH v8 4/5] cxl/core, EINJ: Add CXL debugfs files and EINJ functions Date: Wed, 13 Dec 2023 16:37:01 -0600 Message-ID: <20231213223702.543419-5-Benjamin.Cheatham@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231213223702.543419-1-Benjamin.Cheatham@amd.com> References: <20231213223702.543419-1-Benjamin.Cheatham@amd.com> Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA50:EE_|CH0PR12MB5057:EE_ X-MS-Office365-Filtering-Correlation-Id: d02f6c4e-446d-4233-2581-08dbfc2c3075 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sAWMcsTdiSuY1PRv6YzwkMzTD/8Y71aze/28Yx7DRdrUaZ4dizDQzghLIXJPFLxlI5qA43HLQDJlfw3Nk+bm+L5rMvuCa9sddMBDPDR0X8Pl8SMq9vwLVi0oj+d8jzBdw06vnIhNu2V1VJi4dEw5JzDKHCs7drJZENx2e315ZpbnNApEKc9ZtKparOHjU4om/jRP855f/MNfoagA0OLyS7zYGDWyuWeVLx1c5Dd19JzYZLWkwkF9lVcBLgqPY94V4geeCiLvGLTYxK/V4C+HTFWRlf1Q+4IG22V7sVI5rTWEi7qaIMKMteWrQvX9GKodiNOdU97EacvWiNgXwyjXmxoM872OGCm6LRDUV9Ey1Q6ZKfdZs30U78BdSlSu46EsmOjnWsPL/loXMb/Oh8YfN+zsUl/tNHZdCDAoedMOKib8LuCJuAGVfsKR988n+2ssA+KanuSEQd75idfKqU7l6o05NKXWu8WvT/DuiduDIpNt6/Efgr6REvqLleSsNAEmKAaSEbfk1u4rpu691tfXW5L/gcURQpNAnyo2vMrDM6o9MV2WKFhb0AxVzpKHC/QAJhMYguO9PkfC/u1TiALFIU1W2ibueTUGP45LKVrA7LgPFuQ428Vh7v6qUo2FROm7JwWvxnAsoj7dBOI9HNGr9hYKFbZaLGPzdrGF/AfNxSA4zlyQhPxtlTwWsQ1R+SzmnqQg7nUJOwt2h3A3hVzomXLOFUw2g1T4SWvZ9Hxuhft62pJAIFZp0uOjxFCZmqilyRkHDllpmMJrvTwovCRH/WB2jWkzIOeQyRo/8/dyT4Y= X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA50.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5057 Implement CXL helper functions in the EINJ module for getting the available CXL protocol error types and injecting CXL errors and export them to sysfs under kernel/debug/cxl. The kernel/debug/cxl/einj_types file will print the available CXL protocol errors in the same format as the available_error_types file provided by the EINJ module. The kernel/debug/cxl/$dport_dev/einj_inject is functionally the same as the error_type and error_inject files provided by the EINJ module, i.e.: writing an error type into $dport_dev/einj_inject will inject said error type into the CXL dport represented by $dport_dev. Reviewed-by: Jonathan Cameron Signed-off-by: Ben Cheatham --- Documentation/ABI/testing/debugfs-cxl | 23 ++++ drivers/acpi/apei/einj.c | 144 ++++++++++++++++++++++++-- drivers/cxl/core/port.c | 33 ++++++ drivers/cxl/einj.h | 58 +++++++++++ 4 files changed, 248 insertions(+), 10 deletions(-) create mode 100644 drivers/cxl/einj.h diff --git a/Documentation/ABI/testing/debugfs-cxl b/Documentation/ABI/testing/debugfs-cxl index fe61d372e3fa..97a8684bad84 100644 --- a/Documentation/ABI/testing/debugfs-cxl +++ b/Documentation/ABI/testing/debugfs-cxl @@ -33,3 +33,26 @@ Description: device cannot clear poison from the address, -ENXIO is returned. The clear_poison attribute is only visible for devices supporting the capability. + +What: /sys/kernel/debug/cxl/einj_types +Date: November, 2023 +KernelVersion: v6.8 +Contact: linux-cxl@vger.kernel.org +Description: + (RO) Prints the CXL protocol error types made available by + the platform in the format "0x ". + The can be written to einj_inject to inject + into a chosen dport. This file is only visible if + CONFIG_CXL_EINJ is enabled. + +What: /sys/kernel/debug/cxl/$dport_dev/einj_inject +Date: November, 2023 +KernelVersion: v6.8 +Contact: linux-cxl@vger.kernel.org +Description: + (WO) Writing an integer to this file injects the corresponding + CXL protocol error into $dport_dev (integer to type mapping is + available by reading from einj_types). If the dport was + enumerated in RCH mode, a CXL 1.1 error is injected, otherwise + a CXL 2.0 error is injected. This file is only visible if + CONFIG_CXL_EINJ is enabled. diff --git a/drivers/acpi/apei/einj.c b/drivers/acpi/apei/einj.c index 26a887d2a5cd..1a2195779b52 100644 --- a/drivers/acpi/apei/einj.c +++ b/drivers/acpi/apei/einj.c @@ -24,6 +24,7 @@ #include #include "apei-internal.h" +#include "../../cxl/einj.h" #undef pr_fmt #define pr_fmt(fmt) "EINJ: " fmt @@ -36,6 +37,12 @@ #define MEM_ERROR_MASK (ACPI_EINJ_MEMORY_CORRECTABLE | \ ACPI_EINJ_MEMORY_UNCORRECTABLE | \ ACPI_EINJ_MEMORY_FATAL) +#define CXL_ERROR_MASK (ACPI_EINJ_CXL_CACHE_CORRECTABLE | \ + ACPI_EINJ_CXL_CACHE_UNCORRECTABLE | \ + ACPI_EINJ_CXL_CACHE_FATAL | \ + ACPI_EINJ_CXL_MEM_CORRECTABLE | \ + ACPI_EINJ_CXL_MEM_UNCORRECTABLE | \ + ACPI_EINJ_CXL_MEM_FATAL) /* * ACPI version 5 provides a SET_ERROR_TYPE_WITH_ADDRESS action. @@ -537,8 +544,11 @@ static int einj_error_inject(u32 type, u32 flags, u64 param1, u64 param2, if (type & ACPI5_VENDOR_BIT) { if (vendor_flags != SETWA_FLAGS_MEM) goto inject; - } else if (!(type & MEM_ERROR_MASK) && !(flags & SETWA_FLAGS_MEM)) + } else if (!(type & MEM_ERROR_MASK) && !(flags & SETWA_FLAGS_MEM)) { goto inject; + } else if ((type & CXL_ERROR_MASK) && (flags & SETWA_FLAGS_MEM)) { + goto inject; + } /* * Disallow crazy address masks that give BIOS leeway to pick @@ -590,6 +600,9 @@ static const char * const einj_error_type_string[] = { "0x00000200\tPlatform Correctable\n", "0x00000400\tPlatform Uncorrectable non-fatal\n", "0x00000800\tPlatform Uncorrectable fatal\n", +}; + +static const char * const einj_cxl_error_type_string[] = { "0x00001000\tCXL.cache Protocol Correctable\n", "0x00002000\tCXL.cache Protocol Uncorrectable non-fatal\n", "0x00004000\tCXL.cache Protocol Uncorrectable fatal\n", @@ -617,29 +630,44 @@ DEFINE_SHOW_ATTRIBUTE(available_error_type); static bool einj_initialized; -static int error_type_get(void *data, u64 *val) +int einj_cxl_available_error_type_show(struct seq_file *m, void *v) { - *val = error_type; + int cxl_err, rc; + u32 available_error_type = 0; + + if (!einj_initialized) + return -ENXIO; + + rc = einj_get_available_error_type(&available_error_type); + if (rc) + return rc; + + for (int pos = 0; pos < ARRAY_SIZE(einj_cxl_error_type_string); pos++) { + cxl_err = ACPI_EINJ_CXL_CACHE_CORRECTABLE << pos; + + if (available_error_type & cxl_err) + seq_puts(m, einj_cxl_error_type_string[pos]); + } return 0; } +EXPORT_SYMBOL_NS_GPL(einj_cxl_available_error_type_show, CXL); -static int error_type_set(void *data, u64 val) +static int validate_error_type(u64 type) { + u32 tval, vendor, available_error_type = 0; int rc; - u32 available_error_type = 0; - u32 tval, vendor; /* Only low 32 bits for error type are valid */ - if (val & GENMASK_ULL(63, 32)) + if (type & GENMASK_ULL(63, 32)) return -EINVAL; /* * Vendor defined types have 0x80000000 bit set, and * are not enumerated by ACPI_EINJ_GET_ERROR_TYPE */ - vendor = val & ACPI5_VENDOR_BIT; - tval = val & 0x7fffffff; + vendor = type & ACPI5_VENDOR_BIT; + tval = type & 0x7fffffff; /* Only one error type can be specified */ if (tval & (tval - 1)) @@ -648,9 +676,105 @@ static int error_type_set(void *data, u64 val) rc = einj_get_available_error_type(&available_error_type); if (rc) return rc; - if (!(val & available_error_type)) + if (!(type & available_error_type)) return -EINVAL; } + + return 0; +} + +static int cxl_dport_get_sbdf(struct pci_dev *dport_dev, u64 *sbdf) +{ + struct pci_bus *pbus; + struct pci_host_bridge *bridge; + u64 seg = 0, bus; + + pbus = dport_dev->bus; + bridge = pci_find_host_bridge(pbus); + + if (!bridge) + return -ENODEV; + + if (bridge->domain_nr != PCI_DOMAIN_NR_NOT_SET) + seg = bridge->domain_nr << 24; + + bus = pbus->number << 16; + *sbdf = seg | bus | dport_dev->devfn; + + return 0; +} + +int einj_cxl_inject_rch_error(u64 rcrb, u64 type) +{ + u64 param1 = 0, param2 = 0, param4 = 0; + u32 flags; + int rc; + + if (!einj_initialized) + return -ENXIO; + + /* Only CXL error types can be specified */ + if (type & ~CXL_ERROR_MASK || (type & ACPI5_VENDOR_BIT)) + return -EINVAL; + + rc = validate_error_type(type); + if (rc) + return rc; + + param1 = (u64) rcrb; + param2 = 0xfffffffffffff000; + flags = 0x2; + + return einj_error_inject(type, flags, param1, param2, 0, param4); +} +EXPORT_SYMBOL_NS_GPL(einj_cxl_inject_rch_error, CXL); + +int einj_cxl_inject_error(struct pci_dev *dport, u64 type) +{ + u64 param1 = 0, param2 = 0, param4 = 0; + u32 flags; + int rc; + + if (!einj_initialized) + return -ENXIO; + + /* Only CXL error types can be specified */ + if (type & ~CXL_ERROR_MASK || (type & ACPI5_VENDOR_BIT)) + return -EINVAL; + + rc = validate_error_type(type); + if (rc) + return rc; + + rc = cxl_dport_get_sbdf(dport, ¶m4); + if (rc) + return rc; + + flags = 0x4; + + return einj_error_inject(type, flags, param1, param2, 0, param4); +} +EXPORT_SYMBOL_NS_GPL(einj_cxl_inject_error, CXL); + +static int error_type_get(void *data, u64 *val) +{ + *val = error_type; + + return 0; +} + +static int error_type_set(void *data, u64 val) +{ + int rc; + + /* CXL error types have to be injected from cxl debugfs */ + if (val & CXL_ERROR_MASK && !(val & ACPI5_VENDOR_BIT)) + return -EINVAL; + + rc = validate_error_type(val); + if (rc) + return rc; + error_type = val; return 0; diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 38441634e4c6..4ed4a24138c3 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include "core.h" @@ -783,6 +784,32 @@ static int cxl_dport_setup_regs(struct device *host, struct cxl_dport *dport, return rc; } +DEFINE_SHOW_ATTRIBUTE(cxl_einj_available_error_type); + +static int cxl_einj_inject(void *data, u64 type) +{ + struct cxl_dport *dport = data; + + if (dport->rch) + return cxl_einj_inject_rch_error(dport->rcrb.base, type); + + if (!dev_is_pci(dport->dport_dev)) + return -EINVAL; + + return cxl_einj_inject_error(to_pci_dev(dport->dport_dev), type); +} +DEFINE_DEBUGFS_ATTRIBUTE(cxl_einj_inject_fops, NULL, cxl_einj_inject, "%llx\n"); + +static void cxl_debugfs_create_dport_dir(struct cxl_dport *dport) +{ + struct dentry *dir; + + dir = cxl_debugfs_create_dir(dev_name(dport->dport_dev)); + + debugfs_create_file("einj_inject", 0200, dir, dport, + &cxl_einj_inject_fops); +} + static struct cxl_port *__devm_cxl_add_port(struct device *host, struct device *uport_dev, resource_size_t component_reg_phys, @@ -1136,6 +1163,8 @@ struct cxl_dport *devm_cxl_add_dport(struct cxl_port *port, } else { dev_dbg(dport_dev, "dport added to %s\n", dev_name(&port->dev)); + + cxl_debugfs_create_dport_dir(dport); } return dport; @@ -1170,6 +1199,8 @@ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, } else { dev_dbg(dport_dev, "RCH dport added to %s\n", dev_name(&port->dev)); + + cxl_debugfs_create_dport_dir(dport); } return dport; @@ -2109,6 +2140,8 @@ static __init int cxl_core_init(void) int rc; cxl_debugfs = debugfs_create_dir("cxl", NULL); + debugfs_create_file("einj_types", 0400, cxl_debugfs, NULL, + &cxl_einj_available_error_type_fops); cxl_mbox_init(); diff --git a/drivers/cxl/einj.h b/drivers/cxl/einj.h new file mode 100644 index 000000000000..b913763c3238 --- /dev/null +++ b/drivers/cxl/einj.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * CXL protocol Error INJection support. + * + * Copyright (c) 2023 Advanced Micro Devices, Inc. + * All Rights Reserved. + * + * Author: Ben Cheatham + */ +#ifndef CXL_EINJ_H +#define CXL_EINJ_H +#include + +int einj_cxl_available_error_type_show(struct seq_file *m, void *v); +int einj_cxl_inject_error(struct pci_dev *dport_dev, u64 type); +int einj_cxl_inject_rch_error(u64 rcrb, u64 type); + +#if IS_ENABLED(CONFIG_CXL_EINJ) +static inline int cxl_einj_available_error_type_show(struct seq_file *m, + void *v) +{ + return einj_cxl_available_error_type_show(m, v); +} + +static inline int cxl_einj_inject_error(struct pci_dev *dport_dev, u64 type) +{ + return einj_cxl_inject_error(dport_dev, type); +} + +static inline int cxl_einj_inject_rch_error(u64 rcrb, u64 type) +{ + return einj_cxl_inject_rch_error(rcrb, type); +} + +#else +static inline int cxl_einj_available_error_type_show(struct seq_file *m, + void *v) +{ + return -ENXIO; +} + +static inline int cxl_einj_type_show(struct seq_file *m, void *data) +{ + return -ENXIO; +} + +static inline int cxl_einj_inject_error(struct pci_dev *dport_dev, u64 type) +{ + return -ENXIO; +} + +static inline int cxl_einj_inject_rch_error(u64 rcrb, u64 type) +{ + return -ENXIO; +} +#endif + +#endif From patchwork Wed Dec 13 22:37:02 2023 Content-Type: text/plain; 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Reviewed-by: Jonathan Cameron Signed-off-by: Ben Cheatham --- .../firmware-guide/acpi/apei/einj.rst | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/firmware-guide/acpi/apei/einj.rst b/Documentation/firmware-guide/acpi/apei/einj.rst index d6b61d22f525..a9d3f6926cae 100644 --- a/Documentation/firmware-guide/acpi/apei/einj.rst +++ b/Documentation/firmware-guide/acpi/apei/einj.rst @@ -181,6 +181,25 @@ You should see something like this in dmesg:: [22715.834759] EDAC sbridge MC3: PROCESSOR 0:306e7 TIME 1422553404 SOCKET 0 APIC 0 [22716.616173] EDAC MC3: 1 CE memory read error on CPU_SrcID#0_Channel#0_DIMM#0 (channel:0 slot:0 page:0x12345 offset:0x0 grain:32 syndrome:0x0 - area:DRAM err_code:0001:0090 socket:0 channel_mask:1 rank:0) +CXL error types are supported from ACPI 6.5 onwards. These error types +are not available in the legacy interface at /sys/kernel/debug/apei/einj, +and are instead at /sys/kernel/debug/cxl/. There is a file under debug/cxl +called "einj_type" that is analagous to available_error_type under debug/cxl. +There is also a "einj_inject" file in each $dport_dev directory under debug/cxl +that will inject a given error into the dport represented by $dport_dev. +For example, to inject a CXL.mem protocol correctable error into +$dport_dev=pci0000:0c:: + + # cd /sys/kernel/debug/cxl/ + # cat einj_type # See which error can be injected + 0x00008000 CXL.mem Protocol Correctable + 0x00010000 CXL.mem Protocol Uncorrectable non-fatal + 0x00020000 CXL.mem Protocol Uncorrectable fatal + # cd pci0000:0c # Navigate to dport to inject into + # echo 0x8000 > einj_inject # Inject error + +To use CXL error types, ``CONFIG_CXL_EINJ`` will need to be enabled. + Special notes for injection into SGX enclaves: There may be a separate BIOS setup option to enable SGX injection.