From patchwork Mon Dec 11 18:30:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gatien CHEVALLIER X-Patchwork-Id: 752664 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="yVdjOT1d" Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E7200AC; Mon, 11 Dec 2023 10:32:33 -0800 (PST) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3BBHxgm3023809; Mon, 11 Dec 2023 19:31:34 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=iI5H47zvcA4f2T9X0SOLjyUIMcFUo42eiKhj9yV6NCc=; b=yV djOT1deCHGOmPjNVxLwzgMLwCwQ8eecbXf1tx+Vfp57/qfxggvAGhk9UE5llAhDr Z9bFcVO1Nf/riQGFjnM9EOolVSSSO4Bc8rWaqjzOkKVskXlE2hYrhwAzz4nnU+2H yoiyZYT3PHXsbVKo6ksEG/gVUZecZ3MzWJY3kTpzE3/AibBogBB/MKP5YJ7+MHiQ +4aUF3qBMhoP8vhLuE/EUsdOPITtrk9iFTKOvrkkc98qt7S5U0HBunYsvi2cpivH UhyTx2CN5tBFEuP//aUNai5ktyybN4tn0nFoZ4w0Y9Vzragizj7Pc20kBVd0AVYL 0HaKp6ASnYUrAApj5+4Q== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3uve88r1mb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 11 Dec 2023 19:31:34 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 49BAC100064; Mon, 11 Dec 2023 19:31:31 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 3AFD922FA46; Mon, 11 Dec 2023 19:31:31 +0100 (CET) Received: from localhost (10.252.9.5) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 11 Dec 2023 19:31:30 +0100 From: Gatien Chevallier To: , , , , , , , , , , , , , , , , , , , , , , , , , Frank Rowand , , , , , CC: , , , , , , , , , , , , , , , , Gatien Chevallier Subject: [PATCH v7 03/13] dt-bindings: bus: document RIFSC Date: Mon, 11 Dec 2023 19:30:34 +0100 Message-ID: <20231211183044.808204-4-gatien.chevallier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231211183044.808204-1-gatien.chevallier@foss.st.com> References: <20231211183044.808204-1-gatien.chevallier@foss.st.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-11_08,2023-12-07_01,2023-05-22_02 Document RIFSC (RIF security controller). RIFSC is a firewall controller composed of different kinds of hardware resources. Signed-off-by: Gatien Chevallier --- Changes in V6: - Renamed access-controller to access-controllers - Removal of access-control-provider property - Removal of access-controller and access-controller-names declaration in the patternProperties field. Add additionalProperties: true in this field. Changes in V5: - Renamed feature-domain* to access-control* Changes in V2: - Corrected errors highlighted by Rob's robot - No longer define the maxItems for the "feature-domains" property - Fix example (node name, status) - Declare "feature-domain-names" as an optional property for child nodes - Fix description of "feature-domains" property .../bindings/bus/st,stm32mp25-rifsc.yaml | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml diff --git a/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml new file mode 100644 index 000000000000..95aa7f04c739 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STM32 Resource isolation framework security controller + +maintainers: + - Gatien Chevallier + +description: | + Resource isolation framework (RIF) is a comprehensive set of hardware blocks + designed to enforce and manage isolation of STM32 hardware resources like + memory and peripherals. + + The RIFSC (RIF security controller) is composed of three sets of registers, + each managing a specific set of hardware resources: + - RISC registers associated with RISUP logic (resource isolation device unit + for peripherals), assign all non-RIF aware peripherals to zero, one or + any security domains (secure, privilege, compartment). + - RIMC registers: associated with RIMU logic (resource isolation master + unit), assign all non RIF-aware bus master to one security domain by + setting secure, privileged and compartment information on the system bus. + Alternatively, the RISUP logic controlling the device port access to a + peripheral can assign target bus attributes to this peripheral master port + (supported attribute: CID). + - RISC registers associated with RISAL logic (resource isolation device unit + for address space - Lite version), assign address space subregions to one + security domains (secure, privilege, compartment). + +properties: + compatible: + contains: + const: st,stm32mp25-rifsc + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + + "#access-controller-cells": + const: 1 + description: + Contains the firewall ID associated to the peripheral. + +patternProperties: + "^.*@[0-9a-f]+$": + description: Peripherals + type: object + + additionalProperties: true + + required: + - access-controllers + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - "#access-controller-cells" + - ranges + +additionalProperties: false + +examples: + - | + // In this example, the usart2 device refers to rifsc as its domain + // controller. + // Access rights are verified before creating devices. + + #include + + rifsc: bus@42080000 { + compatible = "st,stm32mp25-rifsc"; + reg = <0x42080000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + #access-controller-cells = <1>; + ranges; + + usart2: serial@400e0000 { + compatible = "st,stm32h7-uart"; + reg = <0x400e0000 0x400>; + interrupts = ; + clocks = <&ck_flexgen_08>; + access-controllers = <&rifsc 32>; + }; + }; From patchwork Mon Dec 11 18:30:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gatien CHEVALLIER X-Patchwork-Id: 752662 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="YQOuVbeO" Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 08F18B8; Mon, 11 Dec 2023 10:33:26 -0800 (PST) Received: from pps.filterd (m0369458.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 3BBHuP9D013382; Mon, 11 Dec 2023 19:32:43 +0100 DKIM-Signature: v=1; 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Mon, 11 Dec 2023 19:32:43 +0100 (CET) Received: from localhost (10.252.9.5) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 11 Dec 2023 19:32:42 +0100 From: Gatien Chevallier To: , , , , , , , , , , , , , , , , , , , , , , , , , Frank Rowand , , , , , CC: , , , , , , , , , , , , , , , , Gatien Chevallier Subject: [PATCH v7 06/13] of: property: fw_devlink: Add support for "access-controller" Date: Mon, 11 Dec 2023 19:30:37 +0100 Message-ID: <20231211183044.808204-7-gatien.chevallier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231211183044.808204-1-gatien.chevallier@foss.st.com> References: <20231211183044.808204-1-gatien.chevallier@foss.st.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-11_08,2023-12-07_01,2023-05-22_02 Allows tracking dependencies between devices and their access controller. Signed-off-by: Gatien Chevallier --- Changes in V6: - Renamed access-controller to access-controllers Changes in V5: - Rename feature-domain* to access-control* Patch not present in V1 drivers/of/property.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/of/property.c b/drivers/of/property.c index afdaefbd03f6..7f737eac91b2 100644 --- a/drivers/of/property.c +++ b/drivers/of/property.c @@ -1268,6 +1268,7 @@ DEFINE_SIMPLE_PROP(leds, "leds", NULL) DEFINE_SIMPLE_PROP(backlight, "backlight", NULL) DEFINE_SIMPLE_PROP(panel, "panel", NULL) DEFINE_SIMPLE_PROP(msi_parent, "msi-parent", "#msi-cells") +DEFINE_SIMPLE_PROP(access_controllers, "access-controllers", "#access-controller-cells") DEFINE_SUFFIX_PROP(regulators, "-supply", NULL) DEFINE_SUFFIX_PROP(gpio, "-gpio", "#gpio-cells") @@ -1363,6 +1364,7 @@ static const struct supplier_bindings of_supplier_bindings[] = { { .parse_prop = parse_regulators, }, { .parse_prop = parse_gpio, }, { .parse_prop = parse_gpios, }, + { .parse_prop = parse_access_controllers, }, {} }; From patchwork Mon Dec 11 18:30:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gatien CHEVALLIER X-Patchwork-Id: 752661 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="DngPqoOq" Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EEBBFAC; Mon, 11 Dec 2023 10:33:34 -0800 (PST) Received: from pps.filterd (m0369458.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 3BBGv9lb032113; Mon, 11 Dec 2023 19:32:44 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=DiieVn9d7KbENVUVaHD9nfqKTKTU8p3WjCoDe+RaB88=; b=Dn gPqoOqdCwzx5VmPF/jeRbKrIv39LT/CTyVyH83QSh5xEvEMZ+w9ai+cbjS4INzpT DjHDNIGKS/jUwEIs0uB+/OUPr+lvV75AxIx24SZq7BhQJCkSW9fvExtGSOD9N29c ug7WTk3AhCe/9LhWHysj4b5E6v8RjNIpsW67+G2TgrgVpNKqpLN/UdcP2XLIwf6O Zj7ObIeEJm3+KGLhtnDObm3Mkk0M5mMSTZPDfZ7wyluxiqh2CgKj4EmODFMAvyMu U46TUk2tCamqWVv8RrsqViM0rYqVKv8O0XZ9q6beJmTFK3/bG6w1h6PTMxu4Qn04 5OTczoGT0IwEYG7T9Z4g== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3uw2p4p2qg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 11 Dec 2023 19:32:44 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id DB6C5100062; Mon, 11 Dec 2023 19:32:43 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id CE8A323BE03; Mon, 11 Dec 2023 19:32:43 +0100 (CET) Received: from localhost (10.252.9.5) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 11 Dec 2023 19:32:43 +0100 From: Gatien Chevallier To: , , , , , , , , , , , , , , , , , , , , , , , , , Frank Rowand , , , , , CC: , , , , , , , , , , , , , , , , Gatien Chevallier Subject: [PATCH v7 07/13] bus: rifsc: introduce RIFSC firewall controller driver Date: Mon, 11 Dec 2023 19:30:38 +0100 Message-ID: <20231211183044.808204-8-gatien.chevallier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231211183044.808204-1-gatien.chevallier@foss.st.com> References: <20231211183044.808204-1-gatien.chevallier@foss.st.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-11_08,2023-12-07_01,2023-05-22_02 RIFSC is a peripheral firewall controller that filter accesses based on Arm TrustZone secure state, Arm CPU privilege execution level and Compartment IDentification of the STM32 SoC subsystems. Signed-off-by: Gatien Chevallier --- Changes in V4: - Fix incorrect use of __set_bit() in - stm32_rif_acquire_semaphore() Changes in V2: - Add controller name - Driver is now a module_platform_driver - Use error code returned by stm32_firewall_populate_bus() - Fix license MAINTAINERS | 1 + drivers/bus/Makefile | 2 +- drivers/bus/stm32_rifsc.c | 252 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 254 insertions(+), 1 deletion(-) create mode 100644 drivers/bus/stm32_rifsc.c diff --git a/MAINTAINERS b/MAINTAINERS index 774c7e1601d8..a1152438b52d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20434,6 +20434,7 @@ ST STM32 FIREWALL M: Gatien Chevallier S: Maintained F: drivers/bus/stm32_firewall.c +F: drivers/bus/stm32_rifsc.c ST STM32 I2C/SMBUS DRIVER M: Pierre-Yves MORDRET diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index fc0511450ec2..e50d18e1d141 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -26,7 +26,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o obj-$(CONFIG_QCOM_SSC_BLOCK_BUS) += qcom-ssc-block-bus.o -obj-$(CONFIG_STM32_FIREWALL) += stm32_firewall.o +obj-$(CONFIG_STM32_FIREWALL) += stm32_firewall.o stm32_rifsc.o obj-$(CONFIG_SUN50I_DE2_BUS) += sun50i-de2.o obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o obj-$(CONFIG_OF) += simple-pm-bus.o diff --git a/drivers/bus/stm32_rifsc.c b/drivers/bus/stm32_rifsc.c new file mode 100644 index 000000000000..4cf1b60014b7 --- /dev/null +++ b/drivers/bus/stm32_rifsc.c @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "stm32_firewall.h" + +/* + * RIFSC offset register + */ +#define RIFSC_RISC_SECCFGR0 0x10 +#define RIFSC_RISC_PRIVCFGR0 0x30 +#define RIFSC_RISC_PER0_CIDCFGR 0x100 +#define RIFSC_RISC_PER0_SEMCR 0x104 +#define RIFSC_RISC_HWCFGR2 0xFEC + +/* + * SEMCR register + */ +#define SEMCR_MUTEX BIT(0) + +/* + * HWCFGR2 register + */ +#define HWCFGR2_CONF1_MASK GENMASK(15, 0) +#define HWCFGR2_CONF2_MASK GENMASK(23, 16) +#define HWCFGR2_CONF3_MASK GENMASK(31, 24) + +/* + * RIFSC miscellaneous + */ +#define RIFSC_RISC_CFEN_MASK BIT(0) +#define RIFSC_RISC_SEM_EN_MASK BIT(1) +#define RIFSC_RISC_SCID_MASK GENMASK(6, 4) +#define RIFSC_RISC_SEML_SHIFT 16 +#define RIFSC_RISC_SEMWL_MASK GENMASK(23, 16) +#define RIFSC_RISC_PER_ID_MASK GENMASK(31, 24) + +#define RIFSC_RISC_PERx_CID_MASK (RIFSC_RISC_CFEN_MASK | \ + RIFSC_RISC_SEM_EN_MASK | \ + RIFSC_RISC_SCID_MASK | \ + RIFSC_RISC_SEMWL_MASK) + +#define IDS_PER_RISC_SEC_PRIV_REGS 32 + +/* RIF miscellaneous */ +/* + * CIDCFGR register fields + */ +#define CIDCFGR_CFEN BIT(0) +#define CIDCFGR_SEMEN BIT(1) +#define CIDCFGR_SEMWL(x) BIT(RIFSC_RISC_SEML_SHIFT + (x)) + +#define SEMWL_SHIFT 16 + +/* Compartiment IDs */ +#define RIF_CID0 0x0 +#define RIF_CID1 0x1 + +static bool stm32_rifsc_is_semaphore_available(void __iomem *addr) +{ + return !(readl(addr) & SEMCR_MUTEX); +} + +static int stm32_rif_acquire_semaphore(struct stm32_firewall_controller *stm32_firewall_controller, + int id) +{ + void __iomem *addr = stm32_firewall_controller->mmio + RIFSC_RISC_PER0_SEMCR + 0x8 * id; + + writel(SEMCR_MUTEX, addr); + + /* Check that CID1 has the semaphore */ + if (stm32_rifsc_is_semaphore_available(addr) || + FIELD_GET(RIFSC_RISC_SCID_MASK, readl(addr)) != RIF_CID1) + return -EACCES; + + return 0; +} + +static void stm32_rif_release_semaphore(struct stm32_firewall_controller *stm32_firewall_controller, + int id) +{ + void __iomem *addr = stm32_firewall_controller->mmio + RIFSC_RISC_PER0_SEMCR + 0x8 * id; + + if (stm32_rifsc_is_semaphore_available(addr)) + return; + + writel(SEMCR_MUTEX, addr); + + /* Ok if another compartment takes the semaphore before the check */ + WARN_ON(!stm32_rifsc_is_semaphore_available(addr) && + FIELD_GET(RIFSC_RISC_SCID_MASK, readl(addr)) == RIF_CID1); +} + +static int stm32_rifsc_grant_access(struct stm32_firewall_controller *ctrl, u32 firewall_id) +{ + struct stm32_firewall_controller *rifsc_controller = ctrl; + u32 reg_offset, reg_id, sec_reg_value, cid_reg_value; + int rc; + + if (firewall_id >= rifsc_controller->max_entries) { + dev_err(rifsc_controller->dev, "Invalid sys bus ID %u", firewall_id); + return -EINVAL; + } + + /* + * RIFSC_RISC_PRIVCFGRx and RIFSC_RISC_SECCFGRx both handle configuration access for + * 32 peripherals. On the other hand, there is one _RIFSC_RISC_PERx_CIDCFGR register + * per peripheral + */ + reg_id = firewall_id / IDS_PER_RISC_SEC_PRIV_REGS; + reg_offset = firewall_id % IDS_PER_RISC_SEC_PRIV_REGS; + sec_reg_value = readl(rifsc_controller->mmio + RIFSC_RISC_SECCFGR0 + 0x4 * reg_id); + cid_reg_value = readl(rifsc_controller->mmio + RIFSC_RISC_PER0_CIDCFGR + 0x8 * firewall_id); + + /* First check conditions for semaphore mode, which doesn't take into account static CID. */ + if ((cid_reg_value & CIDCFGR_SEMEN) && (cid_reg_value & CIDCFGR_CFEN)) { + if (cid_reg_value & BIT(RIF_CID1 + SEMWL_SHIFT)) { + /* Static CID is irrelevant if semaphore mode */ + goto skip_cid_check; + } else { + dev_dbg(rifsc_controller->dev, + "Invalid bus semaphore configuration: index %d\n", firewall_id); + return -EACCES; + } + } + + /* + * Skip CID check if CID filtering isn't enabled or filtering is enabled on CID0, which + * corresponds to whatever CID. + */ + if (!(cid_reg_value & CIDCFGR_CFEN) || + FIELD_GET(RIFSC_RISC_SCID_MASK, cid_reg_value) == RIF_CID0) + goto skip_cid_check; + + /* Coherency check with the CID configuration */ + if (FIELD_GET(RIFSC_RISC_SCID_MASK, cid_reg_value) != RIF_CID1) { + dev_dbg(rifsc_controller->dev, "Invalid CID configuration for peripheral: %d\n", + firewall_id); + return -EACCES; + } + +skip_cid_check: + /* Check security configuration */ + if (sec_reg_value & BIT(reg_offset)) { + dev_dbg(rifsc_controller->dev, + "Invalid security configuration for peripheral: %d\n", firewall_id); + return -EACCES; + } + + /* + * If the peripheral is in semaphore mode, take the semaphore so that + * the CID1 has the ownership. + */ + if ((cid_reg_value & CIDCFGR_SEMEN) && (cid_reg_value & CIDCFGR_CFEN)) { + rc = stm32_rif_acquire_semaphore(rifsc_controller, firewall_id); + if (rc) { + dev_err(rifsc_controller->dev, + "Couldn't acquire semaphore for peripheral: %d\n", firewall_id); + return rc; + } + } + + return 0; +} + +static void stm32_rifsc_release_access(struct stm32_firewall_controller *ctrl, u32 firewall_id) +{ + stm32_rif_release_semaphore(ctrl, firewall_id); +} + +static int stm32_rifsc_probe(struct platform_device *pdev) +{ + struct stm32_firewall_controller *rifsc_controller; + struct device_node *np = pdev->dev.of_node; + u32 nb_risup, nb_rimu, nb_risal; + struct resource *res; + void __iomem *mmio; + int rc; + + rifsc_controller = devm_kzalloc(&pdev->dev, sizeof(*rifsc_controller), GFP_KERNEL); + if (!rifsc_controller) + return -ENOMEM; + + mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(mmio)) + return PTR_ERR(mmio); + + rifsc_controller->dev = &pdev->dev; + rifsc_controller->mmio = mmio; + rifsc_controller->name = dev_driver_string(rifsc_controller->dev); + rifsc_controller->type = STM32_PERIPHERAL_FIREWALL | STM32_MEMORY_FIREWALL; + rifsc_controller->grant_access = stm32_rifsc_grant_access; + rifsc_controller->release_access = stm32_rifsc_release_access; + + /* Get number of RIFSC entries*/ + nb_risup = readl(rifsc_controller->mmio + RIFSC_RISC_HWCFGR2) & HWCFGR2_CONF1_MASK; + nb_rimu = readl(rifsc_controller->mmio + RIFSC_RISC_HWCFGR2) & HWCFGR2_CONF2_MASK; + nb_risal = readl(rifsc_controller->mmio + RIFSC_RISC_HWCFGR2) & HWCFGR2_CONF3_MASK; + rifsc_controller->max_entries = nb_risup + nb_rimu + nb_risal; + + platform_set_drvdata(pdev, rifsc_controller); + + rc = stm32_firewall_controller_register(rifsc_controller); + if (rc) { + dev_err(rifsc_controller->dev, "Couldn't register as a firewall controller: %d", + rc); + return rc; + } + + rc = stm32_firewall_populate_bus(rifsc_controller); + if (rc) { + dev_err(rifsc_controller->dev, "Couldn't populate RIFSC bus: %d", + rc); + return rc; + } + + /* Populate all allowed nodes */ + return of_platform_populate(np, NULL, NULL, &pdev->dev); +} + +static const struct of_device_id stm32_rifsc_of_match[] = { + { .compatible = "st,stm32mp25-rifsc" }, + {} +}; +MODULE_DEVICE_TABLE(of, stm32_rifsc_of_match); + +static struct platform_driver stm32_rifsc_driver = { + .probe = stm32_rifsc_probe, + .driver = { + .name = "stm32-rifsc", + .of_match_table = stm32_rifsc_of_match, + }, +}; +module_platform_driver(stm32_rifsc_driver); + +MODULE_AUTHOR("Gatien Chevallier "); +MODULE_DESCRIPTION("STMicroelectronics RIFSC driver"); +MODULE_LICENSE("GPL"); From patchwork Mon Dec 11 18:30:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gatien CHEVALLIER X-Patchwork-Id: 752660 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="diSNNXuE" Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B1273F3; Mon, 11 Dec 2023 10:34:35 -0800 (PST) Received: from pps.filterd (m0369458.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 3BBGvwAD028269; Mon, 11 Dec 2023 19:33:55 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; 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Mon, 11 Dec 2023 19:33:54 +0100 From: Gatien Chevallier To: , , , , , , , , , , , , , , , , , , , , , , , , , Frank Rowand , , , , , CC: , , , , , , , , , , , , , , , , Gatien Chevallier Subject: [PATCH v7 09/13] bus: etzpc: introduce ETZPC firewall controller driver Date: Mon, 11 Dec 2023 19:30:40 +0100 Message-ID: <20231211183044.808204-10-gatien.chevallier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231211183044.808204-1-gatien.chevallier@foss.st.com> References: <20231211183044.808204-1-gatien.chevallier@foss.st.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-11_08,2023-12-07_01,2023-05-22_02 ETZPC is a peripheral and memory firewall controller that filter accesses based on Arm TrustZone secure state and Arm CPU privilege execution level. It handles MCU isolation as well. Signed-off-by: Gatien Chevallier --- Changes in V2: - Add controller name - Driver is now a module_platform_driver - Use error code returned by stm32_firewall_populate_bus() - Fix license MAINTAINERS | 1 + drivers/bus/Makefile | 2 +- drivers/bus/stm32_etzpc.c | 141 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 143 insertions(+), 1 deletion(-) create mode 100644 drivers/bus/stm32_etzpc.c diff --git a/MAINTAINERS b/MAINTAINERS index a1152438b52d..b83b471c8b73 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20433,6 +20433,7 @@ F: drivers/media/i2c/st-mipid02.c ST STM32 FIREWALL M: Gatien Chevallier S: Maintained +F: drivers/bus/stm32_etzpc.c F: drivers/bus/stm32_firewall.c F: drivers/bus/stm32_rifsc.c diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile index e50d18e1d141..cddd4984d6af 100644 --- a/drivers/bus/Makefile +++ b/drivers/bus/Makefile @@ -26,7 +26,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o obj-$(CONFIG_QCOM_SSC_BLOCK_BUS) += qcom-ssc-block-bus.o -obj-$(CONFIG_STM32_FIREWALL) += stm32_firewall.o stm32_rifsc.o +obj-$(CONFIG_STM32_FIREWALL) += stm32_firewall.o stm32_rifsc.o stm32_etzpc.o obj-$(CONFIG_SUN50I_DE2_BUS) += sun50i-de2.o obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o obj-$(CONFIG_OF) += simple-pm-bus.o diff --git a/drivers/bus/stm32_etzpc.c b/drivers/bus/stm32_etzpc.c new file mode 100644 index 000000000000..7fc0f16960be --- /dev/null +++ b/drivers/bus/stm32_etzpc.c @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "stm32_firewall.h" + +/* + * ETZPC registers + */ +#define ETZPC_DECPROT 0x10 +#define ETZPC_HWCFGR 0x3F0 + +/* + * HWCFGR register + */ +#define ETZPC_HWCFGR_NUM_TZMA GENMASK(7, 0) +#define ETZPC_HWCFGR_NUM_PER_SEC GENMASK(15, 8) +#define ETZPC_HWCFGR_NUM_AHB_SEC GENMASK(23, 16) +#define ETZPC_HWCFGR_CHUNKS1N4 GENMASK(31, 24) + +/* + * ETZPC miscellaneous + */ +#define ETZPC_PROT_MASK GENMASK(1, 0) +#define ETZPC_PROT_A7NS 0x3 +#define ETZPC_DECPROT_SHIFT 1 + +#define IDS_PER_DECPROT_REGS 16 + +static int stm32_etzpc_grant_access(struct stm32_firewall_controller *ctrl, u32 firewall_id) +{ + u32 offset, reg_offset, sec_val; + + if (firewall_id >= ctrl->max_entries) { + dev_err(ctrl->dev, "Invalid sys bus ID %u", firewall_id); + return -EINVAL; + } + + /* Check access configuration, 16 peripherals per register */ + reg_offset = ETZPC_DECPROT + 0x4 * (firewall_id / IDS_PER_DECPROT_REGS); + offset = (firewall_id % IDS_PER_DECPROT_REGS) << ETZPC_DECPROT_SHIFT; + + /* Verify peripheral is non-secure and attributed to cortex A7 */ + sec_val = (readl(ctrl->mmio + reg_offset) >> offset) & ETZPC_PROT_MASK; + if (sec_val != ETZPC_PROT_A7NS) { + dev_dbg(ctrl->dev, "Invalid bus configuration: reg_offset %#x, value %d\n", + reg_offset, sec_val); + return -EACCES; + } + + return 0; +} + +static void stm32_etzpc_release_access(struct stm32_firewall_controller *ctrl __maybe_unused, + u32 firewall_id __maybe_unused) +{ +} + +static int stm32_etzpc_probe(struct platform_device *pdev) +{ + struct stm32_firewall_controller *etzpc_controller; + struct device_node *np = pdev->dev.of_node; + u32 nb_per, nb_master; + struct resource *res; + void __iomem *mmio; + int rc; + + etzpc_controller = devm_kzalloc(&pdev->dev, sizeof(*etzpc_controller), GFP_KERNEL); + if (!etzpc_controller) + return -ENOMEM; + + mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(mmio)) + return PTR_ERR(mmio); + + etzpc_controller->dev = &pdev->dev; + etzpc_controller->mmio = mmio; + etzpc_controller->name = dev_driver_string(etzpc_controller->dev); + etzpc_controller->type = STM32_PERIPHERAL_FIREWALL | STM32_MEMORY_FIREWALL; + etzpc_controller->grant_access = stm32_etzpc_grant_access; + etzpc_controller->release_access = stm32_etzpc_release_access; + + /* Get number of etzpc entries*/ + nb_per = FIELD_GET(ETZPC_HWCFGR_NUM_PER_SEC, + readl(etzpc_controller->mmio + ETZPC_HWCFGR)); + nb_master = FIELD_GET(ETZPC_HWCFGR_NUM_AHB_SEC, + readl(etzpc_controller->mmio + ETZPC_HWCFGR)); + etzpc_controller->max_entries = nb_per + nb_master; + + platform_set_drvdata(pdev, etzpc_controller); + + rc = stm32_firewall_controller_register(etzpc_controller); + if (rc) { + dev_err(etzpc_controller->dev, "Couldn't register as a firewall controller: %d", + rc); + return rc; + } + + rc = stm32_firewall_populate_bus(etzpc_controller); + if (rc) { + dev_err(etzpc_controller->dev, "Couldn't populate ETZPC bus: %d", + rc); + return rc; + } + + /* Populate all allowed nodes */ + return of_platform_populate(np, NULL, NULL, &pdev->dev); +} + +static const struct of_device_id stm32_etzpc_of_match[] = { + { .compatible = "st,stm32-etzpc" }, + {} +}; +MODULE_DEVICE_TABLE(of, stm32_etzpc_of_match); + +static struct platform_driver stm32_etzpc_driver = { + .probe = stm32_etzpc_probe, + .driver = { + .name = "stm32-etzpc", + .of_match_table = stm32_etzpc_of_match, + }, +}; +module_platform_driver(stm32_etzpc_driver); + +MODULE_AUTHOR("Gatien Chevallier "); +MODULE_DESCRIPTION("STMicroelectronics ETZPC driver"); +MODULE_LICENSE("GPL"); From patchwork Mon Dec 11 18:30:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gatien CHEVALLIER X-Patchwork-Id: 752659 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="FqkMquXn" Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36928E3; Mon, 11 Dec 2023 10:34:40 -0800 (PST) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 3BBCDvQd030710; Mon, 11 Dec 2023 19:33:57 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=c26TH31/4e2LiuAI+Gz7srNwxMxulLxxevULaE0NoZE=; b=Fq kMquXnvCviz/Gs2CxW8UbbodYmSFqazemaEk4Yj8JqXmw/fNY2ybH/WgPmfwOgBe eimKnqqF0gsXDrDuK+o2qDSieR11uDyinHYDHGC4GNhfFceU9o5W7gWJ01Wv00Xd ReNnDuJm++n4+76rv+gNy6t5fwFBuWEPJ159A3mf1DK2nVkP4t2fvIyAD5d34iqK SwC8y6rjTA3AEB9DSIqwqggl1GpQZBy8fBJl4IcNhW6OrAS2YkHdH1ZRI5I7cs8k WrGmrdna8WhvK1PWb7skHHJi0mnq+PsghDjAra1Vb6uoxlGIY9/SZ+k14JplDyO5 1tyFHEj+zdCki/PJvN9w== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3uve88r1ts-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 11 Dec 2023 19:33:57 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id E293C100060; Mon, 11 Dec 2023 19:33:56 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id D4146257AA8; Mon, 11 Dec 2023 19:33:56 +0100 (CET) Received: from localhost (10.252.9.5) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 11 Dec 2023 19:33:56 +0100 From: Gatien Chevallier To: , , , , , , , , , , , , , , , , , , , , , , , , , Frank Rowand , , , , , CC: , , , , , , , , , , , , , , , , Gatien Chevallier Subject: [PATCH v7 11/13] ARM: dts: stm32: put ETZPC as an access controller for STM32MP15x boards Date: Mon, 11 Dec 2023 19:30:42 +0100 Message-ID: <20231211183044.808204-12-gatien.chevallier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231211183044.808204-1-gatien.chevallier@foss.st.com> References: <20231211183044.808204-1-gatien.chevallier@foss.st.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-11_08,2023-12-07_01,2023-05-22_02 Reference ETZPC as an access-control-provider. For more information on which peripheral is securable or supports MCU isolation, please read the STM32MP13 reference manual Signed-off-by: Gatien Chevallier --- Patch not present in V6 arch/arm/boot/dts/st/stm32mp151.dtsi | 64 +++++++++++++++++++++++++++ arch/arm/boot/dts/st/stm32mp153.dtsi | 2 + arch/arm/boot/dts/st/stm32mp15xc.dtsi | 1 + 3 files changed, 67 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi index 78c0d6ccdb09..e66970cd8745 100644 --- a/arch/arm/boot/dts/st/stm32mp151.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi @@ -334,6 +334,7 @@ etzpc: bus@5c007000 { reg = <0x5c007000 0x400>; #address-cells = <1>; #size-cells = <1>; + #access-controller-cells = <1>; ranges; timers2: timer@40000000 { @@ -351,6 +352,7 @@ timers2: timer@40000000 { <&dmamux1 21 0x400 0x1>, <&dmamux1 22 0x400 0x1>; dma-names = "ch1", "ch2", "ch3", "ch4", "up"; + access-controllers = <&etzpc 16>; status = "disabled"; pwm { @@ -387,6 +389,7 @@ timers3: timer@40001000 { <&dmamux1 27 0x400 0x1>, <&dmamux1 28 0x400 0x1>; dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; + access-controllers = <&etzpc 17>; status = "disabled"; pwm { @@ -421,6 +424,7 @@ timers4: timer@40002000 { <&dmamux1 31 0x400 0x1>, <&dmamux1 32 0x400 0x1>; dma-names = "ch1", "ch2", "ch3", "ch4"; + access-controllers = <&etzpc 18>; status = "disabled"; pwm { @@ -457,6 +461,7 @@ timers5: timer@40003000 { <&dmamux1 59 0x400 0x1>, <&dmamux1 60 0x400 0x1>; dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; + access-controllers = <&etzpc 19>; status = "disabled"; pwm { @@ -488,6 +493,7 @@ timers6: timer@40004000 { clock-names = "int"; dmas = <&dmamux1 69 0x400 0x1>; dma-names = "up"; + access-controllers = <&etzpc 20>; status = "disabled"; timer@5 { @@ -508,6 +514,7 @@ timers7: timer@40005000 { clock-names = "int"; dmas = <&dmamux1 70 0x400 0x1>; dma-names = "up"; + access-controllers = <&etzpc 21>; status = "disabled"; timer@6 { @@ -526,6 +533,7 @@ timers12: timer@40006000 { interrupt-names = "global"; clocks = <&rcc TIM12_K>; clock-names = "int"; + access-controllers = <&etzpc 22>; status = "disabled"; pwm { @@ -550,6 +558,7 @@ timers13: timer@40007000 { interrupt-names = "global"; clocks = <&rcc TIM13_K>; clock-names = "int"; + access-controllers = <&etzpc 23>; status = "disabled"; pwm { @@ -574,6 +583,7 @@ timers14: timer@40008000 { interrupt-names = "global"; clocks = <&rcc TIM14_K>; clock-names = "int"; + access-controllers = <&etzpc 24>; status = "disabled"; pwm { @@ -598,6 +608,7 @@ lptimer1: timer@40009000 { clocks = <&rcc LPTIM1_K>; clock-names = "mux"; wakeup-source; + access-controllers = <&etzpc 25>; status = "disabled"; pwm { @@ -626,6 +637,7 @@ i2s2: audio-controller@4000b000 { dmas = <&dmamux1 39 0x400 0x01>, <&dmamux1 40 0x400 0x01>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 27>; status = "disabled"; }; @@ -640,6 +652,7 @@ spi2: spi@4000b000 { dmas = <&dmamux1 39 0x400 0x05>, <&dmamux1 40 0x400 0x05>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 27>; status = "disabled"; }; @@ -651,6 +664,7 @@ i2s3: audio-controller@4000c000 { dmas = <&dmamux1 61 0x400 0x01>, <&dmamux1 62 0x400 0x01>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 28>; status = "disabled"; }; @@ -665,6 +679,7 @@ spi3: spi@4000c000 { dmas = <&dmamux1 61 0x400 0x05>, <&dmamux1 62 0x400 0x05>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 28>; status = "disabled"; }; @@ -678,6 +693,7 @@ spdifrx: audio-controller@4000d000 { dmas = <&dmamux1 93 0x400 0x01>, <&dmamux1 94 0x400 0x01>; dma-names = "rx", "rx-ctrl"; + access-controllers = <&etzpc 29>; status = "disabled"; }; @@ -690,6 +706,7 @@ usart2: serial@4000e000 { dmas = <&dmamux1 43 0x400 0x15>, <&dmamux1 44 0x400 0x11>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 30>; status = "disabled"; }; @@ -702,6 +719,7 @@ usart3: serial@4000f000 { dmas = <&dmamux1 45 0x400 0x15>, <&dmamux1 46 0x400 0x11>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 31>; status = "disabled"; }; @@ -714,6 +732,7 @@ uart4: serial@40010000 { dmas = <&dmamux1 63 0x400 0x15>, <&dmamux1 64 0x400 0x11>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 32>; status = "disabled"; }; @@ -726,6 +745,7 @@ uart5: serial@40011000 { dmas = <&dmamux1 65 0x400 0x15>, <&dmamux1 66 0x400 0x11>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 33>; status = "disabled"; }; @@ -742,6 +762,7 @@ i2c1: i2c@40012000 { st,syscfg-fmp = <&syscfg 0x4 0x1>; wakeup-source; i2c-analog-filter; + access-controllers = <&etzpc 34>; status = "disabled"; }; @@ -758,6 +779,7 @@ i2c2: i2c@40013000 { st,syscfg-fmp = <&syscfg 0x4 0x2>; wakeup-source; i2c-analog-filter; + access-controllers = <&etzpc 35>; status = "disabled"; }; @@ -774,6 +796,7 @@ i2c3: i2c@40014000 { st,syscfg-fmp = <&syscfg 0x4 0x4>; wakeup-source; i2c-analog-filter; + access-controllers = <&etzpc 36>; status = "disabled"; }; @@ -790,6 +813,7 @@ i2c5: i2c@40015000 { st,syscfg-fmp = <&syscfg 0x4 0x10>; wakeup-source; i2c-analog-filter; + access-controllers = <&etzpc 37>; status = "disabled"; }; @@ -799,6 +823,7 @@ cec: cec@40016000 { interrupts = ; clocks = <&rcc CEC_K>, <&rcc CEC>; clock-names = "cec", "hdmi-cec"; + access-controllers = <&etzpc 38>; status = "disabled"; }; @@ -809,6 +834,7 @@ dac: dac@40017000 { clock-names = "pclk"; #address-cells = <1>; #size-cells = <0>; + access-controllers = <&etzpc 39>; status = "disabled"; dac1: dac@1 { @@ -835,6 +861,7 @@ uart7: serial@40018000 { dmas = <&dmamux1 79 0x400 0x15>, <&dmamux1 80 0x400 0x11>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 40>; status = "disabled"; }; @@ -847,6 +874,7 @@ uart8: serial@40019000 { dmas = <&dmamux1 81 0x400 0x15>, <&dmamux1 82 0x400 0x11>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 41>; status = "disabled"; }; @@ -871,6 +899,7 @@ timers1: timer@44000000 { <&dmamux1 17 0x400 0x1>; dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig", "com"; + access-controllers = <&etzpc 48>; status = "disabled"; pwm { @@ -912,6 +941,7 @@ timers8: timer@44001000 { <&dmamux1 53 0x400 0x1>; dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig", "com"; + access-controllers = <&etzpc 49>; status = "disabled"; pwm { @@ -941,6 +971,7 @@ usart6: serial@44003000 { dmas = <&dmamux1 71 0x400 0x15>, <&dmamux1 72 0x400 0x11>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 51>; status = "disabled"; }; @@ -952,6 +983,7 @@ i2s1: audio-controller@44004000 { dmas = <&dmamux1 37 0x400 0x01>, <&dmamux1 38 0x400 0x01>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 52>; status = "disabled"; }; @@ -966,6 +998,7 @@ spi1: spi@44004000 { dmas = <&dmamux1 37 0x400 0x05>, <&dmamux1 38 0x400 0x05>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 52>; status = "disabled"; }; @@ -980,6 +1013,7 @@ spi4: spi@44005000 { dmas = <&dmamux1 83 0x400 0x05>, <&dmamux1 84 0x400 0x05>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 53>; status = "disabled"; }; @@ -997,6 +1031,7 @@ timers15: timer@44006000 { <&dmamux1 107 0x400 0x1>, <&dmamux1 108 0x400 0x1>; dma-names = "ch1", "up", "trig", "com"; + access-controllers = <&etzpc 54>; status = "disabled"; pwm { @@ -1024,6 +1059,7 @@ timers16: timer@44007000 { dmas = <&dmamux1 109 0x400 0x1>, <&dmamux1 110 0x400 0x1>; dma-names = "ch1", "up"; + access-controllers = <&etzpc 55>; status = "disabled"; pwm { @@ -1050,6 +1086,7 @@ timers17: timer@44008000 { dmas = <&dmamux1 111 0x400 0x1>, <&dmamux1 112 0x400 0x1>; dma-names = "ch1", "up"; + access-controllers = <&etzpc 56>; status = "disabled"; pwm { @@ -1076,6 +1113,7 @@ spi5: spi@44009000 { dmas = <&dmamux1 85 0x400 0x05>, <&dmamux1 86 0x400 0x05>; dma-names = "rx", "tx"; + access-controllers = <&etzpc 57>; status = "disabled"; }; @@ -1087,6 +1125,7 @@ sai1: sai@4400a000 { reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; interrupts = ; resets = <&rcc SAI1_R>; + access-controllers = <&etzpc 58>; status = "disabled"; sai1a: audio-controller@4400a004 { @@ -1119,6 +1158,7 @@ sai2: sai@4400b000 { reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; interrupts = ; resets = <&rcc SAI2_R>; + access-controllers = <&etzpc 59>; status = "disabled"; sai2a: audio-controller@4400b004 { @@ -1150,6 +1190,7 @@ sai3: sai@4400c000 { reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; interrupts = ; resets = <&rcc SAI3_R>; + access-controllers = <&etzpc 60>; status = "disabled"; sai3a: audio-controller@4400c004 { @@ -1180,6 +1221,7 @@ dfsdm: dfsdm@4400d000 { clock-names = "dfsdm"; #address-cells = <1>; #size-cells = <0>; + access-controllers = <&etzpc 61>; status = "disabled"; dfsdm0: filter@0 { @@ -1259,6 +1301,7 @@ dma1: dma-controller@48000000 { #dma-cells = <4>; st,mem2mem; dma-requests = <8>; + access-controllers = <&etzpc 88>; }; dma2: dma-controller@48001000 { @@ -1277,6 +1320,7 @@ dma2: dma-controller@48001000 { #dma-cells = <4>; st,mem2mem; dma-requests = <8>; + access-controllers = <&etzpc 89>; }; dmamux1: dma-router@48002000 { @@ -1288,6 +1332,7 @@ dmamux1: dma-router@48002000 { dma-channels = <16>; clocks = <&rcc DMAMUX>; resets = <&rcc DMAMUX_R>; + access-controllers = <&etzpc 90>; }; adc: adc@48003000 { @@ -1302,6 +1347,7 @@ adc: adc@48003000 { #interrupt-cells = <1>; #address-cells = <1>; #size-cells = <0>; + access-controllers = <&etzpc 72>; status = "disabled"; adc1: adc@0 { @@ -1352,6 +1398,7 @@ sdmmc3: mmc@48004000 { cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <120000000>; + access-controllers = <&etzpc 86>; status = "disabled"; }; @@ -1369,6 +1416,7 @@ usbotg_hs: usb-otg@49000000 { dr_mode = "otg"; otg-rev = <0x200>; usb33d-supply = <&usb33>; + access-controllers = <&etzpc 85>; status = "disabled"; }; @@ -1381,6 +1429,7 @@ dcmi: dcmi@4c006000 { clock-names = "mclk"; dmas = <&dmamux1 75 0x400 0x01>; dma-names = "tx"; + access-controllers = <&etzpc 70>; status = "disabled"; }; @@ -1393,6 +1442,7 @@ lptimer2: timer@50021000 { clocks = <&rcc LPTIM2_K>; clock-names = "mux"; wakeup-source; + access-controllers = <&etzpc 64>; status = "disabled"; pwm { @@ -1422,6 +1472,7 @@ lptimer3: timer@50022000 { clocks = <&rcc LPTIM3_K>; clock-names = "mux"; wakeup-source; + access-controllers = <&etzpc 65>; status = "disabled"; pwm { @@ -1444,6 +1495,7 @@ lptimer4: timer@50023000 { clocks = <&rcc LPTIM4_K>; clock-names = "mux"; wakeup-source; + access-controllers = <&etzpc 66>; status = "disabled"; pwm { @@ -1460,6 +1512,7 @@ lptimer5: timer@50024000 { clocks = <&rcc LPTIM5_K>; clock-names = "mux"; wakeup-source; + access-controllers = <&etzpc 67>; status = "disabled"; pwm { @@ -1475,6 +1528,7 @@ vrefbuf: vrefbuf@50025000 { regulator-min-microvolt = <1500000>; regulator-max-microvolt = <2500000>; clocks = <&rcc VREF>; + access-controllers = <&etzpc 69>; status = "disabled"; }; @@ -1486,6 +1540,7 @@ sai4: sai@50027000 { reg = <0x50027000 0x4>, <0x500273f0 0x10>; interrupts = ; resets = <&rcc SAI4_R>; + access-controllers = <&etzpc 68>; status = "disabled"; sai4a: audio-controller@50027004 { @@ -1518,6 +1573,7 @@ hash1: hash@54002000 { dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; dma-names = "in"; dma-maxburst = <2>; + access-controllers = <&etzpc 8>; status = "disabled"; }; @@ -1526,6 +1582,7 @@ rng1: rng@54003000 { reg = <0x54003000 0x400>; clocks = <&rcc RNG1_K>; resets = <&rcc RNG1_R>; + access-controllers = <&etzpc 7>; status = "okay"; }; @@ -1536,6 +1593,7 @@ fmc: memory-controller@58002000 { reg = <0x58002000 0x1000>; clocks = <&rcc FMC_K>; resets = <&rcc FMC_R>; + access-controllers = <&etzpc 91>; status = "disabled"; ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ @@ -1575,6 +1633,7 @@ qspi: spi@58003000 { resets = <&rcc QSPI_R>; #address-cells = <1>; #size-cells = <0>; + access-controllers = <&etzpc 92>; status = "disabled"; }; @@ -1602,6 +1661,7 @@ ethernet0: ethernet@5800a000 { snps,en-tx-lpi-clockgating; snps,axi-config = <&stmmac_axi_config_0>; snps,tso; + access-controllers = <&etzpc 94>; status = "disabled"; stmmac_axi_config_0: stmmac-axi-config { @@ -1617,6 +1677,7 @@ usart1: serial@5c000000 { interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc USART1_K>; wakeup-source; + access-controllers = <&etzpc 3>; status = "disabled"; }; @@ -1630,6 +1691,7 @@ spi6: spi@5c001000 { resets = <&rcc SPI6_R>; dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, <&mdma1 35 0x0 0x40002 0x0 0x0>; + access-controllers = <&etzpc 4>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -1647,6 +1709,7 @@ i2c4: i2c@5c002000 { st,syscfg-fmp = <&syscfg 0x4 0x8>; wakeup-source; i2c-analog-filter; + access-controllers = <&etzpc 5>; status = "disabled"; }; @@ -1663,6 +1726,7 @@ i2c6: i2c@5c009000 { st,syscfg-fmp = <&syscfg 0x4 0x20>; wakeup-source; i2c-analog-filter; + access-controllers = <&etzpc 12>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/st/stm32mp153.dtsi b/arch/arm/boot/dts/st/stm32mp153.dtsi index 36e17ea0b179..4640dafb1598 100644 --- a/arch/arm/boot/dts/st/stm32mp153.dtsi +++ b/arch/arm/boot/dts/st/stm32mp153.dtsi @@ -41,6 +41,7 @@ m_can1: can@4400e000 { clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; clock-names = "hclk", "cclk"; bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; + access-controllers = <&etzpc 62>; status = "disabled"; }; @@ -54,6 +55,7 @@ m_can2: can@4400f000 { clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; clock-names = "hclk", "cclk"; bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; + access-controllers = <&etzpc 62>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/st/stm32mp15xc.dtsi b/arch/arm/boot/dts/st/stm32mp15xc.dtsi index d36c3457451a..97465717f932 100644 --- a/arch/arm/boot/dts/st/stm32mp15xc.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xc.dtsi @@ -11,6 +11,7 @@ cryp1: cryp@54001000 { interrupts = ; clocks = <&rcc CRYP1>; resets = <&rcc CRYP1_R>; + access-controllers = <&etzpc 9>; status = "disabled"; }; }; From patchwork Mon Dec 11 18:30:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gatien CHEVALLIER X-Patchwork-Id: 752658 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="JRjU6w8F" Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 30A2EDB; Mon, 11 Dec 2023 10:35:58 -0800 (PST) Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 3BBCDL9W008948; Mon, 11 Dec 2023 19:35:09 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; 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Mon, 11 Dec 2023 19:35:07 +0100 From: Gatien Chevallier To: , , , , , , , , , , , , , , , , , , , , , , , , , Frank Rowand , , , , , CC: , , , , , , , , , , , , , , , , Gatien Chevallier Subject: [PATCH v7 12/13] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards Date: Mon, 11 Dec 2023 19:30:43 +0100 Message-ID: <20231211183044.808204-13-gatien.chevallier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231211183044.808204-1-gatien.chevallier@foss.st.com> References: <20231211183044.808204-1-gatien.chevallier@foss.st.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-11_08,2023-12-07_01,2023-05-22_02 ETZPC is a firewall controller. Put all peripherals filtered by the ETZPC as ETZPC subnodes and keep the "simple-bus" compatible for backward compatibility. Signed-off-by: Gatien Chevallier --- Changes in V7: - Keep simple-bus compatible - Remove access-controllers reference in this patch Changes in V6: - Renamed access-controller to access-controllers - Removal of access-control-provider property Changes in V5: - Renamed feature-domain* to access-control* arch/arm/boot/dts/st/stm32mp131.dtsi | 1037 +++++++++++++------------ arch/arm/boot/dts/st/stm32mp133.dtsi | 50 +- arch/arm/boot/dts/st/stm32mp13xc.dtsi | 18 +- arch/arm/boot/dts/st/stm32mp13xf.dtsi | 18 +- 4 files changed, 564 insertions(+), 559 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index b04d24c939c3..6ba8e3fd43b0 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -745,340 +745,6 @@ dmamux1: dma-router@48002000 { dma-channels = <16>; }; - adc_2: adc@48004000 { - compatible = "st,stm32mp13-adc-core"; - reg = <0x48004000 0x400>; - interrupts = ; - clocks = <&rcc ADC2>, <&rcc ADC2_K>; - clock-names = "bus", "adc"; - interrupt-controller; - #interrupt-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - adc2: adc@0 { - compatible = "st,stm32mp13-adc"; - #io-channel-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - interrupt-parent = <&adc_2>; - interrupts = <0>; - dmas = <&dmamux1 10 0x400 0x80000001>; - dma-names = "rx"; - status = "disabled"; - - channel@13 { - reg = <13>; - label = "vrefint"; - }; - channel@14 { - reg = <14>; - label = "vddcore"; - }; - channel@16 { - reg = <16>; - label = "vddcpu"; - }; - channel@17 { - reg = <17>; - label = "vddq_ddr"; - }; - }; - }; - - usbotg_hs: usb@49000000 { - compatible = "st,stm32mp15-hsotg", "snps,dwc2"; - reg = <0x49000000 0x40000>; - clocks = <&rcc USBO_K>; - clock-names = "otg"; - resets = <&rcc USBO_R>; - reset-names = "dwc2"; - interrupts = ; - g-rx-fifo-size = <512>; - g-np-tx-fifo-size = <32>; - g-tx-fifo-size = <256 16 16 16 16 16 16 16>; - dr_mode = "otg"; - otg-rev = <0x200>; - usb33d-supply = <&scmi_usb33>; - status = "disabled"; - }; - - usart1: serial@4c000000 { - compatible = "st,stm32h7-uart"; - reg = <0x4c000000 0x400>; - interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART1_K>; - resets = <&rcc USART1_R>; - wakeup-source; - dmas = <&dmamux1 41 0x400 0x5>, - <&dmamux1 42 0x400 0x1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - usart2: serial@4c001000 { - compatible = "st,stm32h7-uart"; - reg = <0x4c001000 0x400>; - interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART2_K>; - resets = <&rcc USART2_R>; - wakeup-source; - dmas = <&dmamux1 43 0x400 0x5>, - <&dmamux1 44 0x400 0x1>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2s4: audio-controller@4c002000 { - compatible = "st,stm32h7-i2s"; - reg = <0x4c002000 0x400>; - #sound-dai-cells = <0>; - interrupts = ; - dmas = <&dmamux1 83 0x400 0x01>, - <&dmamux1 84 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi4: spi@4c002000 { - compatible = "st,stm32h7-spi"; - reg = <0x4c002000 0x400>; - interrupts = ; - clocks = <&rcc SPI4_K>; - resets = <&rcc SPI4_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 83 0x400 0x01>, - <&dmamux1 84 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - spi5: spi@4c003000 { - compatible = "st,stm32h7-spi"; - reg = <0x4c003000 0x400>; - interrupts = ; - clocks = <&rcc SPI5_K>; - resets = <&rcc SPI5_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 85 0x400 0x01>, - <&dmamux1 86 0x400 0x01>; - dma-names = "rx", "tx"; - status = "disabled"; - }; - - i2c3: i2c@4c004000 { - compatible = "st,stm32mp13-i2c"; - reg = <0x4c004000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C3_K>; - resets = <&rcc I2C3_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 73 0x400 0x1>, - <&dmamux1 74 0x400 0x1>; - dma-names = "rx", "tx"; - st,syscfg-fmp = <&syscfg 0x4 0x4>; - i2c-analog-filter; - status = "disabled"; - }; - - i2c4: i2c@4c005000 { - compatible = "st,stm32mp13-i2c"; - reg = <0x4c005000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C4_K>; - resets = <&rcc I2C4_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 75 0x400 0x1>, - <&dmamux1 76 0x400 0x1>; - dma-names = "rx", "tx"; - st,syscfg-fmp = <&syscfg 0x4 0x8>; - i2c-analog-filter; - status = "disabled"; - }; - - i2c5: i2c@4c006000 { - compatible = "st,stm32mp13-i2c"; - reg = <0x4c006000 0x400>; - interrupt-names = "event", "error"; - interrupts = , - ; - clocks = <&rcc I2C5_K>; - resets = <&rcc I2C5_R>; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dmamux1 115 0x400 0x1>, - <&dmamux1 116 0x400 0x1>; - dma-names = "rx", "tx"; - st,syscfg-fmp = <&syscfg 0x4 0x10>; - i2c-analog-filter; - status = "disabled"; - }; - - timers12: timer@4c007000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x4c007000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM12_K>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@11 { - compatible = "st,stm32h7-timer-trigger"; - reg = <11>; - status = "disabled"; - }; - }; - - timers13: timer@4c008000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x4c008000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM13_K>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@12 { - compatible = "st,stm32h7-timer-trigger"; - reg = <12>; - status = "disabled"; - }; - }; - - timers14: timer@4c009000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x4c009000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM14_K>; - clock-names = "int"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@13 { - compatible = "st,stm32h7-timer-trigger"; - reg = <13>; - status = "disabled"; - }; - }; - - timers15: timer@4c00a000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x4c00a000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM15_K>; - clock-names = "int"; - dmas = <&dmamux1 105 0x400 0x1>, - <&dmamux1 106 0x400 0x1>, - <&dmamux1 107 0x400 0x1>, - <&dmamux1 108 0x400 0x1>; - dma-names = "ch1", "up", "trig", "com"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@14 { - compatible = "st,stm32h7-timer-trigger"; - reg = <14>; - status = "disabled"; - }; - }; - - timers16: timer@4c00b000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x4c00b000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM16_K>; - clock-names = "int"; - dmas = <&dmamux1 109 0x400 0x1>, - <&dmamux1 110 0x400 0x1>; - dma-names = "ch1", "up"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@15 { - compatible = "st,stm32h7-timer-trigger"; - reg = <15>; - status = "disabled"; - }; - }; - - timers17: timer@4c00c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-timers"; - reg = <0x4c00c000 0x400>; - interrupts = ; - interrupt-names = "global"; - clocks = <&rcc TIM17_K>; - clock-names = "int"; - dmas = <&dmamux1 111 0x400 0x1>, - <&dmamux1 112 0x400 0x1>; - dma-names = "ch1", "up"; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm"; - #pwm-cells = <3>; - status = "disabled"; - }; - - timer@16 { - compatible = "st,stm32h7-timer-trigger"; - reg = <16>; - status = "disabled"; - }; - }; - rcc: rcc@50000000 { compatible = "st,stm32mp13-rcc", "syscon"; reg = <0x50000000 0x1000>; @@ -1105,69 +771,6 @@ syscfg: syscon@50020000 { clocks = <&rcc SYSCFG>; }; - lptimer2: timer@50021000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x50021000 0x400>; - interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM2_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@1 { - compatible = "st,stm32-lptimer-trigger"; - reg = <1>; - status = "disabled"; - }; - - counter { - compatible = "st,stm32-lptimer-counter"; - status = "disabled"; - }; - - timer { - compatible = "st,stm32-lptimer-timer"; - status = "disabled"; - }; - }; - - lptimer3: timer@50022000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "st,stm32-lptimer"; - reg = <0x50022000 0x400>; - interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc LPTIM3_K>; - clock-names = "mux"; - wakeup-source; - status = "disabled"; - - pwm { - compatible = "st,stm32-pwm-lp"; - #pwm-cells = <3>; - status = "disabled"; - }; - - trigger@2 { - compatible = "st,stm32-lptimer-trigger"; - reg = <2>; - status = "disabled"; - }; - - timer { - compatible = "st,stm32-lptimer-timer"; - status = "disabled"; - }; - }; - lptimer4: timer@50023000 { compatible = "st,stm32-lptimer"; reg = <0x50023000 0x400>; @@ -1210,25 +813,6 @@ timer { }; }; - hash: hash@54003000 { - compatible = "st,stm32mp13-hash"; - reg = <0x54003000 0x400>; - interrupts = ; - clocks = <&rcc HASH1>; - resets = <&rcc HASH1_R>; - dmas = <&mdma 30 0x2 0x1000a02 0x0 0x0>; - dma-names = "in"; - status = "disabled"; - }; - - rng: rng@54004000 { - compatible = "st,stm32mp13-rng"; - reg = <0x54004000 0x400>; - clocks = <&rcc RNG1_K>; - resets = <&rcc RNG1_R>; - status = "disabled"; - }; - mdma: dma-controller@58000000 { compatible = "st,stm32h7-mdma"; reg = <0x58000000 0x1000>; @@ -1239,82 +823,6 @@ mdma: dma-controller@58000000 { dma-requests = <48>; }; - fmc: memory-controller@58002000 { - compatible = "st,stm32mp1-fmc2-ebi"; - reg = <0x58002000 0x1000>; - ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ - <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ - <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ - <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ - <4 0 0x80000000 0x10000000>; /* NAND */ - #address-cells = <2>; - #size-cells = <1>; - clocks = <&rcc FMC_K>; - resets = <&rcc FMC_R>; - status = "disabled"; - - nand-controller@4,0 { - compatible = "st,stm32mp1-fmc2-nfc"; - reg = <4 0x00000000 0x1000>, - <4 0x08010000 0x1000>, - <4 0x08020000 0x1000>, - <4 0x01000000 0x1000>, - <4 0x09010000 0x1000>, - <4 0x09020000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>, - <&mdma 24 0x2 0x12000a08 0x0 0x0>, - <&mdma 25 0x2 0x12000a0a 0x0 0x0>; - dma-names = "tx", "rx", "ecc"; - status = "disabled"; - }; - }; - - qspi: spi@58003000 { - compatible = "st,stm32f469-qspi"; - reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; - reg-names = "qspi", "qspi_mm"; - #address-cells = <1>; - #size-cells = <0>; - interrupts = ; - dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>, - <&mdma 26 0x2 0x10100008 0x0 0x0>; - dma-names = "tx", "rx"; - clocks = <&rcc QSPI_K>; - resets = <&rcc QSPI_R>; - status = "disabled"; - }; - - sdmmc1: mmc@58005000 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x20253180>; - reg = <0x58005000 0x1000>, <0x58006000 0x1000>; - interrupts = ; - clocks = <&rcc SDMMC1_K>; - clock-names = "apb_pclk"; - resets = <&rcc SDMMC1_R>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <130000000>; - status = "disabled"; - }; - - sdmmc2: mmc@58007000 { - compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; - arm,primecell-periphid = <0x20253180>; - reg = <0x58007000 0x1000>, <0x58008000 0x1000>; - interrupts = ; - clocks = <&rcc SDMMC2_K>; - clock-names = "apb_pclk"; - resets = <&rcc SDMMC2_R>; - cap-sd-highspeed; - cap-mmc-highspeed; - max-frequency = <130000000>; - status = "disabled"; - }; - usbh_ohci: usb@5800c000 { compatible = "generic-ohci"; reg = <0x5800c000 0x1000>; @@ -1342,29 +850,6 @@ iwdg2: watchdog@5a002000 { status = "disabled"; }; - usbphyc: usbphyc@5a006000 { - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <0>; - compatible = "st,stm32mp1-usbphyc"; - reg = <0x5a006000 0x1000>; - clocks = <&rcc USBPHY_K>; - resets = <&rcc USBPHY_R>; - vdda1v1-supply = <&scmi_reg11>; - vdda1v8-supply = <&scmi_reg18>; - status = "disabled"; - - usbphyc_port0: usb-phy@0 { - #phy-cells = <0>; - reg = <0>; - }; - - usbphyc_port1: usb-phy@1 { - #phy-cells = <1>; - reg = <1>; - }; - }; - rtc: rtc@5c004000 { compatible = "st,stm32mp1-rtc"; reg = <0x5c004000 0x400>; @@ -1393,6 +878,527 @@ ts_cal2: calib@5e { }; }; + etzpc: bus@5c007000 { + compatible = "st,stm32-etzpc", "simple-bus"; + reg = <0x5c007000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + adc_2: adc@48004000 { + compatible = "st,stm32mp13-adc-core"; + reg = <0x48004000 0x400>; + interrupts = ; + clocks = <&rcc ADC2>, <&rcc ADC2_K>; + clock-names = "bus", "adc"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + adc2: adc@0 { + compatible = "st,stm32mp13-adc"; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + interrupt-parent = <&adc_2>; + interrupts = <0>; + dmas = <&dmamux1 10 0x400 0x80000001>; + dma-names = "rx"; + status = "disabled"; + + channel@13 { + reg = <13>; + label = "vrefint"; + }; + channel@14 { + reg = <14>; + label = "vddcore"; + }; + channel@16 { + reg = <16>; + label = "vddcpu"; + }; + channel@17 { + reg = <17>; + label = "vddq_ddr"; + }; + }; + }; + + usbotg_hs: usb@49000000 { + compatible = "st,stm32mp15-hsotg", "snps,dwc2"; + reg = <0x49000000 0x40000>; + clocks = <&rcc USBO_K>; + clock-names = "otg"; + resets = <&rcc USBO_R>; + reset-names = "dwc2"; + interrupts = ; + g-rx-fifo-size = <512>; + g-np-tx-fifo-size = <32>; + g-tx-fifo-size = <256 16 16 16 16 16 16 16>; + dr_mode = "otg"; + otg-rev = <0x200>; + usb33d-supply = <&scmi_usb33>; + status = "disabled"; + }; + + usart1: serial@4c000000 { + compatible = "st,stm32h7-uart"; + reg = <0x4c000000 0x400>; + interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART1_K>; + resets = <&rcc USART1_R>; + wakeup-source; + dmas = <&dmamux1 41 0x400 0x5>, + <&dmamux1 42 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + usart2: serial@4c001000 { + compatible = "st,stm32h7-uart"; + reg = <0x4c001000 0x400>; + interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART2_K>; + resets = <&rcc USART2_R>; + wakeup-source; + dmas = <&dmamux1 43 0x400 0x5>, + <&dmamux1 44 0x400 0x1>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s4: audio-controller@4c002000 { + compatible = "st,stm32h7-i2s"; + reg = <0x4c002000 0x400>; + #sound-dai-cells = <0>; + interrupts = ; + dmas = <&dmamux1 83 0x400 0x01>, + <&dmamux1 84 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi4: spi@4c002000 { + compatible = "st,stm32h7-spi"; + reg = <0x4c002000 0x400>; + interrupts = ; + clocks = <&rcc SPI4_K>; + resets = <&rcc SPI4_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 83 0x400 0x01>, + <&dmamux1 84 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi5: spi@4c003000 { + compatible = "st,stm32h7-spi"; + reg = <0x4c003000 0x400>; + interrupts = ; + clocks = <&rcc SPI5_K>; + resets = <&rcc SPI5_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 85 0x400 0x01>, + <&dmamux1 86 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c3: i2c@4c004000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c004000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C3_K>; + resets = <&rcc I2C3_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 73 0x400 0x1>, + <&dmamux1 74 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x4>; + i2c-analog-filter; + status = "disabled"; + }; + + i2c4: i2c@4c005000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c005000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C4_K>; + resets = <&rcc I2C4_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 75 0x400 0x1>, + <&dmamux1 76 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x8>; + i2c-analog-filter; + status = "disabled"; + }; + + i2c5: i2c@4c006000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c006000 0x400>; + interrupt-names = "event", "error"; + interrupts = , + ; + clocks = <&rcc I2C5_K>; + resets = <&rcc I2C5_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 115 0x400 0x1>, + <&dmamux1 116 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x10>; + i2c-analog-filter; + status = "disabled"; + }; + + timers12: timer@4c007000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c007000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM12_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@11 { + compatible = "st,stm32h7-timer-trigger"; + reg = <11>; + status = "disabled"; + }; + }; + + timers13: timer@4c008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c008000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM13_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@12 { + compatible = "st,stm32h7-timer-trigger"; + reg = <12>; + status = "disabled"; + }; + }; + + timers14: timer@4c009000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c009000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM14_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@13 { + compatible = "st,stm32h7-timer-trigger"; + reg = <13>; + status = "disabled"; + }; + }; + + timers15: timer@4c00a000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c00a000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM15_K>; + clock-names = "int"; + dmas = <&dmamux1 105 0x400 0x1>, + <&dmamux1 106 0x400 0x1>, + <&dmamux1 107 0x400 0x1>, + <&dmamux1 108 0x400 0x1>; + dma-names = "ch1", "up", "trig", "com"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@14 { + compatible = "st,stm32h7-timer-trigger"; + reg = <14>; + status = "disabled"; + }; + }; + + timers16: timer@4c00b000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c00b000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM16_K>; + clock-names = "int"; + dmas = <&dmamux1 109 0x400 0x1>, + <&dmamux1 110 0x400 0x1>; + dma-names = "ch1", "up"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@15 { + compatible = "st,stm32h7-timer-trigger"; + reg = <15>; + status = "disabled"; + }; + }; + + timers17: timer@4c00c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c00c000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM17_K>; + clock-names = "int"; + dmas = <&dmamux1 111 0x400 0x1>, + <&dmamux1 112 0x400 0x1>; + dma-names = "ch1", "up"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@16 { + compatible = "st,stm32h7-timer-trigger"; + reg = <16>; + status = "disabled"; + }; + }; + + lptimer2: timer@50021000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x50021000 0x400>; + interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM2_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@1 { + compatible = "st,stm32-lptimer-trigger"; + reg = <1>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + + lptimer3: timer@50022000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x50022000 0x400>; + interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM3_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@2 { + compatible = "st,stm32-lptimer-trigger"; + reg = <2>; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + + hash: hash@54003000 { + compatible = "st,stm32mp13-hash"; + reg = <0x54003000 0x400>; + interrupts = ; + clocks = <&rcc HASH1>; + resets = <&rcc HASH1_R>; + dmas = <&mdma 30 0x2 0x1000a02 0x0 0x0>; + dma-names = "in"; + }; + + rng: rng@54004000 { + compatible = "st,stm32mp13-rng"; + reg = <0x54004000 0x400>; + clocks = <&rcc RNG1_K>; + resets = <&rcc RNG1_R>; + }; + + fmc: memory-controller@58002000 { + compatible = "st,stm32mp1-fmc2-ebi"; + reg = <0x58002000 0x1000>; + ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ + <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ + <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ + <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ + <4 0 0x80000000 0x10000000>; /* NAND */ + #address-cells = <2>; + #size-cells = <1>; + clocks = <&rcc FMC_K>; + resets = <&rcc FMC_R>; + status = "disabled"; + + nand-controller@4,0 { + compatible = "st,stm32mp1-fmc2-nfc"; + reg = <4 0x00000000 0x1000>, + <4 0x08010000 0x1000>, + <4 0x08020000 0x1000>, + <4 0x01000000 0x1000>, + <4 0x09010000 0x1000>, + <4 0x09020000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>, + <&mdma 24 0x2 0x12000a08 0x0 0x0>, + <&mdma 25 0x2 0x12000a0a 0x0 0x0>; + dma-names = "tx", "rx", "ecc"; + status = "disabled"; + }; + }; + + qspi: spi@58003000 { + compatible = "st,stm32f469-qspi"; + reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; + reg-names = "qspi", "qspi_mm"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>, + <&mdma 26 0x2 0x10100008 0x0 0x0>; + dma-names = "tx", "rx"; + clocks = <&rcc QSPI_K>; + resets = <&rcc QSPI_R>; + status = "disabled"; + }; + + sdmmc1: mmc@58005000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x20253180>; + reg = <0x58005000 0x1000>, <0x58006000 0x1000>; + interrupts = ; + clocks = <&rcc SDMMC1_K>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC1_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <130000000>; + status = "disabled"; + }; + + sdmmc2: mmc@58007000 { + compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x20253180>; + reg = <0x58007000 0x1000>, <0x58008000 0x1000>; + interrupts = ; + clocks = <&rcc SDMMC2_K>; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC2_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <130000000>; + status = "disabled"; + }; + + usbphyc: usbphyc@5a006000 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "st,stm32mp1-usbphyc"; + reg = <0x5a006000 0x1000>; + clocks = <&rcc USBPHY_K>; + resets = <&rcc USBPHY_R>; + vdda1v1-supply = <&scmi_reg11>; + vdda1v8-supply = <&scmi_reg18>; + status = "disabled"; + + usbphyc_port0: usb-phy@0 { + #phy-cells = <0>; + reg = <0>; + }; + + usbphyc_port1: usb-phy@1 { + #phy-cells = <1>; + reg = <1>; + }; + }; + }; + /* * Break node order to solve dependency probe issue between * pinctrl and exti. @@ -1404,6 +1410,7 @@ pinctrl: pinctrl@50002000 { ranges = <0 0x50002000 0x8400>; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; + pins-are-numbered; gpioa: gpio@50002000 { gpio-controller; diff --git a/arch/arm/boot/dts/st/stm32mp133.dtsi b/arch/arm/boot/dts/st/stm32mp133.dtsi index df451c3c2a26..c4d3a520c14b 100644 --- a/arch/arm/boot/dts/st/stm32mp133.dtsi +++ b/arch/arm/boot/dts/st/stm32mp133.dtsi @@ -33,35 +33,37 @@ m_can2: can@4400f000 { bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; status = "disabled"; }; + }; +}; - adc_1: adc@48003000 { - compatible = "st,stm32mp13-adc-core"; - reg = <0x48003000 0x400>; - interrupts = ; - clocks = <&rcc ADC1>, <&rcc ADC1_K>; - clock-names = "bus", "adc"; - interrupt-controller; - #interrupt-cells = <1>; +&etzpc { + adc_1: adc@48003000 { + compatible = "st,stm32mp13-adc-core"; + reg = <0x48003000 0x400>; + interrupts = ; + clocks = <&rcc ADC1>, <&rcc ADC1_K>; + clock-names = "bus", "adc"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + adc1: adc@0 { + compatible = "st,stm32mp13-adc"; + #io-channel-cells = <1>; #address-cells = <1>; #size-cells = <0>; + reg = <0x0>; + interrupt-parent = <&adc_1>; + interrupts = <0>; + dmas = <&dmamux1 9 0x400 0x80000001>; + dma-names = "rx"; status = "disabled"; - adc1: adc@0 { - compatible = "st,stm32mp13-adc"; - #io-channel-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0>; - interrupt-parent = <&adc_1>; - interrupts = <0>; - dmas = <&dmamux1 9 0x400 0x80000001>; - dma-names = "rx"; - status = "disabled"; - - channel@18 { - reg = <18>; - label = "vrefint"; - }; + channel@18 { + reg = <18>; + label = "vrefint"; }; }; }; diff --git a/arch/arm/boot/dts/st/stm32mp13xc.dtsi b/arch/arm/boot/dts/st/stm32mp13xc.dtsi index 4d00e7592882..b9fb071a1471 100644 --- a/arch/arm/boot/dts/st/stm32mp13xc.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13xc.dtsi @@ -4,15 +4,13 @@ * Author: Alexandre Torgue for STMicroelectronics. */ -/ { - soc { - cryp: crypto@54002000 { - compatible = "st,stm32mp1-cryp"; - reg = <0x54002000 0x400>; - interrupts = ; - clocks = <&rcc CRYP1>; - resets = <&rcc CRYP1_R>; - status = "disabled"; - }; +&etzpc { + cryp: crypto@54002000 { + compatible = "st,stm32mp1-cryp"; + reg = <0x54002000 0x400>; + interrupts = ; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; + status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/st/stm32mp13xf.dtsi b/arch/arm/boot/dts/st/stm32mp13xf.dtsi index 4d00e7592882..b9fb071a1471 100644 --- a/arch/arm/boot/dts/st/stm32mp13xf.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13xf.dtsi @@ -4,15 +4,13 @@ * Author: Alexandre Torgue for STMicroelectronics. */ -/ { - soc { - cryp: crypto@54002000 { - compatible = "st,stm32mp1-cryp"; - reg = <0x54002000 0x400>; - interrupts = ; - clocks = <&rcc CRYP1>; - resets = <&rcc CRYP1_R>; - status = "disabled"; - }; +&etzpc { + cryp: crypto@54002000 { + compatible = "st,stm32mp1-cryp"; + reg = <0x54002000 0x400>; + interrupts = ; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; + status = "disabled"; }; };