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Wed, 28 Aug 2019 12:10:12 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eusmtrp2.samsung.com (KnoxPortal) with ESMTP id 20190828121011eusmtrp2414f2f20728718b823ab82b9d166bf84~-FO7ycf1h1346013460eusmtrp2E; Wed, 28 Aug 2019 12:10:11 +0000 (GMT) X-AuditID: cbfec7f5-4f7ff70000001116-3b-5d666f242839 Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 89.03.04166.32F666D5; Wed, 28 Aug 2019 13:10:11 +0100 (BST) Received: from AMDC2765.DIGITAL.local (unknown [106.120.51.73]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20190828121011eusmtip1679343d1fe73ad3f1873b0802628d60b~-FO7cLPx32343323433eusmtip1V; Wed, 28 Aug 2019 12:10:11 +0000 (GMT) From: Marek Szyprowski To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Marek Szyprowski , Krzysztof Kozlowski , Chanwoo Choi , Bartlomiej Zolnierkiewicz , Marc Zyngier Subject: [PATCH v3 1/2] ARM: dts: exynos: Add support ARM architected timers on Exynos5 Date: Wed, 28 Aug 2019 14:10:04 +0200 Message-Id: <20190828121005.29368-2-m.szyprowski@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828121005.29368-1-m.szyprowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrGIsWRmVeSWpSXmKPExsWy7djP87oq+WmxBn83KFlsnLGe1eL6l+es FufPb2C32PT4GqvFjPP7mCzWHrnLbrFzzklWB3aPTas62Tw2L6n36NuyitHj8ya5AJYoLpuU 1JzMstQifbsErowd/44yFjwQqmjpbGZsYLzF38XIwSEhYCIx80RhFyMXh5DACkaJn8deMkI4 Xxgltv2+ww7hfGaUWLRgO2sXIydYx7XG+WwQieWMEq9aD7DBtUzY8oYJpIpNwFCi620XG4gt IuAtMfnMX7BRzAJXGSWWXvvEApIQFoiU2PP6KSPIISwCqhJPJ4eAhHkFbCVmvZ/PDLFNXmL1 hgNgNqeAncShTZ0sIHMkBJ6zSWzY0sECUeQi0f75P9R5whKvjm9hh7BlJP7vnM8E0dDMKPHw 3Fp2CKeHUeJy0wxGiCpricPHL7KCXMEsoCmxfpc+RNhR4vWvTYyQUOKTuPFWECTMDGRO2jad GSLMK9HRJgRRrSYx6/g6uLUHL1yCut9D4sHe59AwncgosaNjM/sERvlZCMsWMDKuYhRPLS3O TU8tNs5LLdcrTswtLs1L10vOz93ECEwNp/8d/7qDcd+fpEOMAhyMSjy8CclpsUKsiWXFlbmH GCU4mJVEeB+ppMYK8aYkVlalFuXHF5XmpBYfYpTmYFES561meBAtJJCeWJKanZpakFoEk2Xi 4JRqYGzQfSGzobzwS3hDs7Jep8oS7UMyW9jSPeeJxYnxfQk9KeLOu6k7/2uc+4nN0oyMem5y M+Zb8KwItD6w5nDvzgsNhlrqVd4rT0dqcFqZOe487Rn3INz5fKzIdv7N9kELZj598bj+Hq/8 p+1/r3zJ8jqxYAlfj7PWlq72lZPd3k9w2/H6aODK00osxRmJhlrMRcWJAJJ3USUJAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrGLMWRmVeSWpSXmKPExsVy+t/xu7rK+WmxBtNfGllsnLGe1eL6l+es FufPb2C32PT4GqvFjPP7mCzWHrnLbrFzzklWB3aPTas62Tw2L6n36NuyitHj8ya5AJYoPZui /NKSVIWM/OISW6VoQwsjPUNLCz0jE0s9Q2PzWCsjUyV9O5uU1JzMstQifbsEvYwd/44yFjwQ qmjpbGZsYLzF38XIySEhYCJxrXE+WxcjF4eQwFJGicPfd7FCJGQkTk5rgLKFJf5c64Iq+sQo cWrrRiaQBJuAoUTXW5AEJ4eIgK/E4zcrWUBsZoGbjBI772iA2MIC4RIv92xl7mLk4GARUJV4 OjkEJMwrYCsx6/18Zoj58hKrNxwAszkF7CQObeoEGyMEVPPg2S7GCYx8CxgZVjGKpJYW56bn FhvqFSfmFpfmpesl5+duYgSG6bZjPzfvYLy0MfgQowAHoxIPb0JyWqwQa2JZcWXuIUYJDmYl Ed5HKqmxQrwpiZVVqUX58UWlOanFhxhNgW6ayCwlmpwPjKG8knhDU0NzC0tDc2NzYzMLJXHe DoGDMUIC6YklqdmpqQWpRTB9TBycUg2M0bM2WlawPLdTVLx0VMrZNHnxBeu9lc7L/0+6eOBo rLrNhkeatqtjQ6+tnxuY8CjTSY/dxvLrj+M+k3/yK2rtX3lkZYdLd/q9qXtSYuJnmG6dl973 meOCRPXu4t32rqlXr3s1/hcvCdzUkH798om3lfs2bDoa4ajqeieKa0Ws25yljvWtigJsSizF GYmGWsxFxYkA3Si0sGkCAAA= X-CMS-MailID: 20190828121012eucas1p10bac7ebb742d968bca251f21dd3aad11 X-Msg-Generator: CA X-RootMTR: 20190828121012eucas1p10bac7ebb742d968bca251f21dd3aad11 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190828121012eucas1p10bac7ebb742d968bca251f21dd3aad11 References: <20190828121005.29368-1-m.szyprowski@samsung.com> Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org All CortexA7/A15 based Exynos5 SoCs have ARM architected timers, so enable support for them directly in the base dtsi. None of the known firmware properly configures CNTFRQ arch timer register, so force clock frequency to 24MHz, which is the only configuration supported by the remaining clock drivers so far. Stock firmware for Peach Pit and Pi Chromebooks also doesn't reset properly other arch timer registers, so add respective properties indicating that. Other Exynos5-based boards behaves correctly in this area, what finally allows to enable support for KVM-based virtualization. Signed-off-by: Marek Szyprowski --- arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 ++++ arch/arm/boot/dts/exynos54xx.dtsi | 9 +++++++++ arch/arm/boot/dts/exynos5800-peach-pi.dts | 4 ++++ 3 files changed, 17 insertions(+) -- 2.17.1 Tested-by: Chanwoo Choi Reviewed-by: Chanwoo Choi diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index f78db6809cca..77e08a4c7300 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -1064,6 +1064,10 @@ status = "okay"; }; +&timer { + arm,cpu-registers-not-fw-configured; +}; + &tmu_cpu0 { vtmu-supply = <&ldo10_reg>; }; diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index 9c3b63b7cac6..02d34957cd83 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -45,6 +45,15 @@ status = "disabled"; }; + timer: timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + }; + soc: soc { sysram@2020000 { compatible = "mmio-sram"; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index e0f470fe54c8..5e8cec736444 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -1033,6 +1033,10 @@ status = "okay"; }; +&timer { + arm,cpu-registers-not-fw-configured; +}; + &tmu_cpu0 { vtmu-supply = <&ldo10_reg>; }; From patchwork Wed Aug 28 12:10:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 172364 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp659611ily; Wed, 28 Aug 2019 05:10:16 -0700 (PDT) X-Google-Smtp-Source: APXvYqzIyluZGN8k83me0S52qZOkrOa8LqgrrqAremPrcfAg1gVqcQnuHG3y8s6R5TZz9rFKRDZ5 X-Received: by 2002:a17:902:b604:: with SMTP id b4mr3921723pls.94.1566994216863; Wed, 28 Aug 2019 05:10:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566994216; cv=none; d=google.com; s=arc-20160816; b=DrRNoMiJ8WABBr8Yo45gTSrKHcg9ULSRajmJ1gw1SaIRnyyP9bWZaXgtfK3FMEBaxO OgjTfnwXJdYKOA49JquZSVZSdhmAg43iuhan33R55n3woApl+zmqYxUdw8F2va0EOCJm xnIWfXEYfJrawU761bQ3EVF41uLBCFwCQyTKbBCPZXsbpFfJJf3PAM6YmbMGSisNtAdH suNQPx+UP14cr2mWUcT9pgvPGvhKj0tJ36wMqxhhpPgntJfeh+L6YDTG1M+5w/bzw4Iz wSzFPD6ECWVriW7ydP9bKZMPldfFbdCM6S972aHosaY/ebc00CUI3SeYKxMx/X0F4hez 6dSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:cms-type:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature:dkim-filter; bh=hbM0dbFub5dilWQZiDNc2NPkK2MLXSDTzGjKbpMBxSE=; b=Ir4jezvHEcg4xNAL0z+l9ep5izd/vwAbRov83b/8MgMF1/UxG8Q+bqpZmSdE9aXXOG AKGrLsO6+f2LEbgQijMKYuvJ7Eo6yrPzjxMAWkEUs7P5UxTUSYk5N0+tQuQ7WdPRDbzw U5zX7S8kb6HwdFfqpj+JzbSc65wCT+4/nWNoDb0WyR4tB+7RSkSnjvCmXhlVvKkienXv DF3CfZmIgSfzTuPKrm5Y7/M8Ey3ylesy1UjoPB2U/2AWEIPPmXoICafovpmcj7st+Fto roDJD1bRA9vyiwQchCW6eY50Xm/T/jGuSfuT8v0sCi3CCpMohRpM3YvlJDANYSkImI2Y Ofmw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@samsung.com header.s=mail20170921 header.b=XVATmfyn; spf=pass (google.com: best guess record for domain of linux-samsung-soc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-samsung-soc-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=samsung.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Support for ARM architected timers is essential for enabling proper KVM support. Signed-off-by: Marek Szyprowski --- arch/arm/mach-exynos/Kconfig | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 Reviewed-by: Chanwoo Choi diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index f83786640f94..9dab1f50a02f 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -19,6 +19,7 @@ menuconfig ARCH_EXYNOS select EXYNOS_SROM select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS select GPIOLIB + select HAVE_ARM_ARCH_TIMER if ARCH_EXYNOS5 && VIRTUALIZATION select HAVE_ARM_SCU if SMP select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG