From patchwork Wed Aug 28 07:19:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 172327 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp364835ily; Wed, 28 Aug 2019 00:20:06 -0700 (PDT) X-Google-Smtp-Source: APXvYqyyUeArOMJP2tyqv/UJ2ZAVLdDxm4jJyr0TnU8QE4x4bHYZaDeX6D4w3gFhbhosNUgWC5O2 X-Received: by 2002:a17:902:fe0f:: with SMTP id g15mr2570442plj.2.1566976806220; Wed, 28 Aug 2019 00:20:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566976806; cv=none; d=google.com; s=arc-20160816; b=fRqthQz3eozVc5PVEVG7Bf6qStnr5wCiijITCQXVhYkf3UXePHo9AX/9XBxwTBAnn+ E9/duIwmaLFvmufDTvSJncYzpm+gRJJoDFJqAhY4AH5Q8r1Bxq++WR1JVouJVA3AC7MN 3x9NfeG6p4vkHzoU3dqxuQO39rRBMfGb9ZDLqwhPkDr8jNOxRUzX5NWA79rGlJSQRgl7 zX6zgNBuyX4u6LkyWYWANwxu3hGRwwRxn2DhM2MurgkB6KmS8/1X65G1q5MSQCAQPbst hYOQhko/H7JOjK5jG4qaIH/6ylOiwoXdxlU1JH5ELM6F8CVNaOqvMF7CyVbiOVkcJxqE fAWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=4/vn3nShvBSwpELcXgs5bhAcnH64+34+9f0PSBWUDWs=; b=ylHJMzBPOgRufv2k0vGv8G1b3yRUuzz67NiFMx1n3gB3escp9BV01OgkNx+wXuj+U3 HbvjXz2daH1P/qyl3LLwB4mDIIicm0M/mQjHF5uy9wUp0Lje8c1YtGTd9MN/w5cTCt3U jSdqAAXh8vdYg7u12pgTUYbcsm5iXZvJJ4hggVKsplqHNTi4OgVzJtzkJYef6iKKxcch BmwO4j6sKHbM2Ah2v2MUE8lseWqApIODbGeQxNjP2keC+eA809QwDLXNdI6937cloV4i mWuqJB9Y1o5Ro7yqfGZY73DWKhBZeYBzguXBHGh9XbPHgEAptwQpGn3Kyl0lXLGwAIH+ Z6xg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=LraKS8Tz; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f9si1222986plo.306.2019.08.28.00.20.05; Wed, 28 Aug 2019 00:20:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=LraKS8Tz; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726258AbfH1HUF (ORCPT + 8 others); Wed, 28 Aug 2019 03:20:05 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:33448 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726232AbfH1HUF (ORCPT ); Wed, 28 Aug 2019 03:20:05 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7S7JsW1126646; Wed, 28 Aug 2019 02:19:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1566976794; bh=4/vn3nShvBSwpELcXgs5bhAcnH64+34+9f0PSBWUDWs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=LraKS8TzgEzeYPHL4snMeE1o84L1wckgIsDr7E6wpgeU5JfDuCio95vxBJ+W4EcHp uHfalLNWZHAaRjdkaub4waGf9pv9M8ZaaQiMFO1vVP+d17PfmzDODyFRup8BrF2JKi wo2Cz+w2REE1unixyoxLKytENSJoyyrLIZr6xtmo= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7S7Js4E025032 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Aug 2019 02:19:54 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 28 Aug 2019 02:19:53 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 28 Aug 2019 02:19:53 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7S7JmfD052201; Wed, 28 Aug 2019 02:19:51 -0500 From: Tero Kristo To: , , , , CC: , , Subject: [PATCHv2 01/11] dt-bindings: omap: add new binding for PRM instances Date: Wed, 28 Aug 2019 10:19:31 +0300 Message-ID: <20190828071941.32378-2-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828071941.32378-1-t-kristo@ti.com> References: <20190828071941.32378-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add new binding for OMAP PRM (Power and Reset Manager) instances. Each of these will act as a power domain controller and potentially as a reset provider. Signed-off-by: Tero Kristo --- .../devicetree/bindings/arm/omap/prm-inst.txt | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/omap/prm-inst.txt -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/Documentation/devicetree/bindings/arm/omap/prm-inst.txt b/Documentation/devicetree/bindings/arm/omap/prm-inst.txt new file mode 100644 index 000000000000..7c7527c37734 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/prm-inst.txt @@ -0,0 +1,31 @@ +OMAP PRM instance bindings + +Power and Reset Manager is an IP block on OMAP family of devices which +handle the power domains and their current state, and provide reset +handling for the domains and/or separate IP blocks under the power domain +hierarchy. + +Required properties: +- compatible: Must be one of: + "ti,am3-prm-inst" + "ti,am4-prm-inst" + "ti,omap4-prm-inst" + "ti,omap5-prm-inst" + "ti,dra7-prm-inst" +- reg: Contains PRM instance register address range + (base address and length) + +Optional properties: +- #reset-cells: Should be 1 if the PRM instance in question supports resets. +- clocks: Associated clocks for the reset signals if any. Certain reset + signals can't be toggled properly without functional clock + being active for them. + +Example: + +prm_dsp2: prm@1b00 { + compatible = "ti,dra7-prm-inst"; + reg = <0x1b00 0x40>; + #reset-cells = <1>; + clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>; +}; From patchwork Wed Aug 28 07:19:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 172338 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp366607ily; Wed, 28 Aug 2019 00:22:09 -0700 (PDT) X-Google-Smtp-Source: APXvYqyl2NtGDIJKPFy8/LsswzHoXW4dwQ0qISSX2kOUdXGbuUitWcXPRjcRXKDcSJcd8jj6C39y X-Received: by 2002:a17:902:5a08:: with SMTP id q8mr2918880pli.234.1566976807514; Wed, 28 Aug 2019 00:20:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566976807; cv=none; d=google.com; s=arc-20160816; b=aX18QLXW1s+5yuFcAnRPpKnTGIN44rI+uIaZKa0GuxmT8UxvFKbJGI8EFMj025zu8I ZKDmGdpRxIrKQPOTPorr8qVfbo6e02lbRmoSZbDWtQdVZluL5XN6oxG8FGFvEPu/yCSn sDpvWFG/54kRKLSHRqA8FfKZiCUKtfLVXOxJ7cvFuw/okB0JpwP01dV5ueadLWol0NBe cIchd+R2doWv8NtHNtze5w1h/H5rE4uaQ3vhh8EIq/u1teQM4/p2Ek6lpFF62yl04e8V CLxlZPqLT+BMPSrqP6lYurjCdAIi2KN2HyoBpwQsP4Ng/37/RczIAOovJhmqxosp2S8N u7AA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=lun/IihhVZD0SSuBuE72idtwD4SSrSW8blVhgZgqk2U=; b=XeXHZFF03Sk7yCgr8S0rD02Kl5BhCu9gPbmPbyvjiEw+U1TuFXFheU4enWPmYSC+LD JA8rUF/J1tdch6Cd63OhbBYP4kFYFyaWWjgFtJb3G+x9DrBozvz6IBh4Q62rsZwohxm0 NDBtey/rSvixAircR3kUKZXeL4BHNmkulEJ92Dlc9GMFto+j79tMPmAlxIfyI4iIrXSc gYOgyeI6QK/T79i4pOHxt5ZO4RwHSfDADSAw/o57TB9yS/C9YLCPntLQ1SpzbSh6RwsI EbBZ3+2juyzrYL5WWreaPsfJ6gO1uTy4WgDm44JFOrU8dYl6pe9izDPT1f4tPcJuYXOA DniA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=sE5yNRtk; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f9si1222986plo.306.2019.08.28.00.20.07; Wed, 28 Aug 2019 00:20:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=sE5yNRtk; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726397AbfH1HUG (ORCPT + 8 others); Wed, 28 Aug 2019 03:20:06 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:59396 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726252AbfH1HUG (ORCPT ); Wed, 28 Aug 2019 03:20:06 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7S7JxAl116149; Wed, 28 Aug 2019 02:19:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1566976799; bh=lun/IihhVZD0SSuBuE72idtwD4SSrSW8blVhgZgqk2U=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=sE5yNRtkvGyAPqmNv20ep8YkcF+5JLPMY4UC7vGG9gyEVOtYrxe3ZN0AU5DmyGY6/ jqSEMF1M0TASDP6kp4ALgZV6Ov++akIxnWCuuC/MoHaIBbxQ1iqskeaJUYqHoHP9VC XtWuhxZg1vfdeNP0W+tjXKfRDMKSUHBgzvKNoTRg= Received: from DLEE110.ent.ti.com (dlee110.ent.ti.com [157.170.170.21]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7S7Jxsw078153 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Aug 2019 02:19:59 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 28 Aug 2019 02:19:57 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 28 Aug 2019 02:19:57 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7S7JmfF052201; Wed, 28 Aug 2019 02:19:55 -0500 From: Tero Kristo To: , , , , CC: , , Subject: [PATCHv2 03/11] soc: ti: omap-prm: poll for reset complete during de-assert Date: Wed, 28 Aug 2019 10:19:33 +0300 Message-ID: <20190828071941.32378-4-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828071941.32378-1-t-kristo@ti.com> References: <20190828071941.32378-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Poll for reset completion status during de-assertion of reset, otherwise the IP in question might be accessed before it has left reset properly. Signed-off-by: Tero Kristo --- drivers/soc/ti/omap_prm.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index fd5c431f8736..afeb70761b27 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -127,6 +127,7 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, u32 v; int st_bit; bool has_rstst; + int timeout = 0; if (!_is_valid_reset(reset, id)) return -EINVAL; @@ -153,6 +154,25 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, v &= ~(1 << id); writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl); + if (!has_rstst) + return 0; + + /* wait for the status to be set */ + while (1) { + v = readl_relaxed(reset->prm->base + reset->prm->data->rstst); + v &= 1 << st_bit; + if (v) + break; + timeout++; + if (timeout > OMAP_RESET_MAX_WAIT) { + pr_err("%s: timedout waiting for %s:%lu\n", __func__, + dev_name(rcdev->dev), id); + return -EBUSY; + } + + udelay(1); + } + return 0; } From patchwork Wed Aug 28 07:19:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 172333 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp364911ily; Wed, 28 Aug 2019 00:20:10 -0700 (PDT) X-Google-Smtp-Source: APXvYqw0XxXEv4srRKKPY5SinH3enPdtI39S98592PBAtwwB497D7IrvMyuJuhs1mr2dJ6o7nA2K X-Received: by 2002:a65:528d:: with SMTP id y13mr2298511pgp.120.1566976810059; Wed, 28 Aug 2019 00:20:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566976810; cv=none; d=google.com; s=arc-20160816; b=YnJgwavo3vHwbdeZN87uZjsPRWf3Mc0RSv/PydVs5fPgwO2KkPRF3sbVFD2P3Z0sDa 2ppZeg5TN4q1HXDoeoo/XxumXptwc6JERA9I61chNUU5vI4eeE4ZXqGbjjXRkBv+1Quk 4cvhAYcLbhhQCDzaWoCBOUSYjvnv/ImWhw2Od+5zMzzjY2xU6OQ7Aqnb/mpdCmNsQLSx QP6L/QiarF/GOdhWlv/eIAEasvLkK+G5j59uzB3MG4ifr4Iodlnp6UkZ5nWX3lMXRalZ 65qFX67kjvSH+9z9abCpNU1HG9xYM+oZgHd9AUpiKMkeLkJFqAlecYX7pNZYCTu5flyc 5SDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=MaJKqEmPi2ARgN2dmtUrxd+FuRc6LkB83YP9HuVdTr8=; b=VhTVEmef+ePfLfOkGYquuP6XK5WfquiGEMiiRCIf9N4s9o0h9debG7EznXw+mI5AXa WqEaOAzN/sHEz7ZEEGwboA9Sa6UHFmdkep3tVgXe5jFlfhFrtRfWPaGjIcZ70I5io+6I /OHhH0/jfog1kb1MMEhfN5iFQ6x5LmQrGCvbj7QVbi5X/qhVFXLWNLrRG+MBzuI4cxl0 DyzuTspYku5fhELuPC4tzJGuW6dKmHe9Kmt3g23Ux+zRJI9FvuwA3vw603ZRcmCkEojN ODyjAehDXhnDNw7JCIFnRZC/6AJgrCYRGdEQIY9Ut9bQw/UE+0+oOmbOBjHyMdcNu7OV S18w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=TKgJcyum; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f9si1222986plo.306.2019.08.28.00.20.09; Wed, 28 Aug 2019 00:20:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=TKgJcyum; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726341AbfH1HUI (ORCPT + 8 others); Wed, 28 Aug 2019 03:20:08 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:52982 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726252AbfH1HUI (ORCPT ); Wed, 28 Aug 2019 03:20:08 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7S7Jxwa112292; Wed, 28 Aug 2019 02:19:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1566976799; bh=MaJKqEmPi2ARgN2dmtUrxd+FuRc6LkB83YP9HuVdTr8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=TKgJcyumN+Uh48ci5bfK/qWgiynhCaRHxNXvrefoTDyGRNN4Bp01ddpml62kxyZFt 6ycXiTl9BSFNjZSdAHx/W/o6kAYn7EkAFJdrOp9zbUfgNbxqIK83qWT2cO+O7KLeM0 D7+sn99CefCR7PoeW19GC2oD6bOz8zfvSBNpqHDY= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7S7Jxoe082890 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Aug 2019 02:19:59 -0500 Received: from DLEE106.ent.ti.com (157.170.170.36) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 28 Aug 2019 02:19:59 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 28 Aug 2019 02:19:59 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7S7JmfG052201; Wed, 28 Aug 2019 02:19:57 -0500 From: Tero Kristo To: , , , , CC: , , Subject: [PATCHv2 04/11] soc: ti: omap-prm: add support for denying idle for reset clockdomain Date: Wed, 28 Aug 2019 10:19:34 +0300 Message-ID: <20190828071941.32378-5-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828071941.32378-1-t-kristo@ti.com> References: <20190828071941.32378-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org TI SoCs hardware reset signals require the parent clockdomain to be in force wakeup mode while de-asserting the reset, otherwise it may never complete. To support this, add pdata hooks to control the clockdomain directly. Signed-off-by: Tero Kristo --- drivers/soc/ti/omap_prm.c | 34 +++++++++++++++++++++++++--- include/linux/platform_data/ti-prm.h | 21 +++++++++++++++++ 2 files changed, 52 insertions(+), 3 deletions(-) create mode 100644 include/linux/platform_data/ti-prm.h -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index afeb70761b27..38998ce19c71 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -16,6 +16,8 @@ #include #include +#include + struct omap_rst_map { s8 rst; s8 st; @@ -24,6 +26,7 @@ struct omap_rst_map { struct omap_prm_data { u32 base; const char *name; + const char *clkdm_name; u16 rstctrl; u16 rstst; const struct omap_rst_map *rstmap; @@ -38,6 +41,8 @@ struct omap_prm { struct omap_reset_data { struct reset_controller_dev rcdev; struct omap_prm *prm; + struct clockdomain *clkdm; + struct device *dev; }; #define to_omap_reset_data(p) container_of((p), struct omap_reset_data, rcdev) @@ -128,6 +133,8 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, int st_bit; bool has_rstst; int timeout = 0; + struct ti_prm_platform_data *pdata = dev_get_platdata(reset->dev); + int ret = 0; if (!_is_valid_reset(reset, id)) return -EINVAL; @@ -149,13 +156,15 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, writel_relaxed(v, reset->prm->base + reset->prm->data->rstst); } + pdata->clkdm_deny_idle(reset->clkdm); + /* de-assert the reset control line */ v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); v &= ~(1 << id); writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl); if (!has_rstst) - return 0; + goto exit; /* wait for the status to be set */ while (1) { @@ -167,13 +176,17 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, if (timeout > OMAP_RESET_MAX_WAIT) { pr_err("%s: timedout waiting for %s:%lu\n", __func__, dev_name(rcdev->dev), id); - return -EBUSY; + ret = -EBUSY; + goto exit; } udelay(1); } - return 0; +exit: + pdata->clkdm_allow_idle(reset->clkdm); + + return ret; } static const struct reset_control_ops omap_reset_ops = { @@ -186,6 +199,8 @@ static int omap_prm_reset_init(struct platform_device *pdev, struct omap_prm *prm) { struct omap_reset_data *reset; + struct ti_prm_platform_data *pdata = dev_get_platdata(&pdev->dev); + char buf[32]; /* * Check if we have controllable resets. If either rstctrl is non-zero @@ -195,6 +210,11 @@ static int omap_prm_reset_init(struct platform_device *pdev, if (!prm->data->rstctrl && !(prm->data->flags & OMAP_PRM_HAS_RSTCTRL)) return 0; + /* Check if we have the pdata callbacks in place */ + if (!pdata->clkdm_lookup || !pdata->clkdm_deny_idle || + !pdata->clkdm_allow_idle) + return -EINVAL; + reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL); if (!reset) return -ENOMEM; @@ -203,9 +223,17 @@ static int omap_prm_reset_init(struct platform_device *pdev, reset->rcdev.ops = &omap_reset_ops; reset->rcdev.of_node = pdev->dev.of_node; reset->rcdev.nr_resets = OMAP_MAX_RESETS; + reset->dev = &pdev->dev; reset->prm = prm; + sprintf(buf, "%s_clkdm", prm->data->clkdm_name ? prm->data->clkdm_name : + prm->data->name); + + reset->clkdm = pdata->clkdm_lookup(buf); + if (!reset->clkdm) + return -EINVAL; + return devm_reset_controller_register(&pdev->dev, &reset->rcdev); } diff --git a/include/linux/platform_data/ti-prm.h b/include/linux/platform_data/ti-prm.h new file mode 100644 index 000000000000..28154c3226c2 --- /dev/null +++ b/include/linux/platform_data/ti-prm.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * TI PRM (Power & Reset Manager) platform data + * + * Copyright (C) 2019 Texas Instruments, Inc. + * + * Tero Kristo + */ + +#ifndef _LINUX_PLATFORM_DATA_TI_PRM_H +#define _LINUX_PLATFORM_DATA_TI_PRM_H + +struct clockdomain; + +struct ti_prm_platform_data { + void (*clkdm_deny_idle)(struct clockdomain *clkdm); + void (*clkdm_allow_idle)(struct clockdomain *clkdm); + struct clockdomain * (*clkdm_lookup)(const char *name); +}; + +#endif /* _LINUX_PLATFORM_DATA_TI_PRM_H */ From patchwork Wed Aug 28 07:19:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 172334 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp364924ily; Wed, 28 Aug 2019 00:20:10 -0700 (PDT) X-Google-Smtp-Source: APXvYqxVxKXU6gn1n0XkKOKozkZARs/FjrXS4AUDFOspJ3KY0xrawwnnrlVErWyx6RXF4eXLYDlb X-Received: by 2002:a17:902:fe0f:: with SMTP id g15mr2570693plj.2.1566976810757; Wed, 28 Aug 2019 00:20:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566976810; cv=none; d=google.com; s=arc-20160816; b=V6BaQIrLvL4NGg63g6BGgRhWz5Nv5Lhp7GkBUKuC6xWO1dDe7lFDnb6F/raR6CcPP4 MI1UEpHa6OBhsXgM6Tw0+0vXHZKfF8Kp70ECNUqZmNmtZHW59PCCTIk6vk6eL1sQ7rrW 8gGSXcS74F6c1Z+CD+QuBVlVSd5+NuFHngUZJxZS9Ao7Zj6l6qsOYnvZIo3doNGBfa6k onrNklhRWaeGkJSuc0gWdJlrOkaE5mLgZwpu2w8j15CcxrA2eo2JWgvgbS9Qy5p7069b CLRUbposXHbigLNunIblB/hMF3k2KCsgz+569LOErP/GY9UX4BQ/M0756B+n3p9TtFck KeYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=+t+/Qiw1iCU7XUNdlc5BaxCXhjDYvL050wWa31KgFc0=; b=0KcsrcdJHfis1+HvPL0k35vPDt3Wt6uGtwWVHN7Y6nV46VhRRqMHoBt2+b6MK1YycN fkRmjpgqzzxt7UaMJ86s6ugq2zAKjnrAyt6WgBw+dsNT7iybPY2GPasucqlGL3Eu56RI kLV2Q/dbmMUcs++PxDvcRIspeUgyDNfeR47O1RHxpudr9f63XOymox1PBOCZZ3Xzhhhj KSVo5QC8nFRdarInizKdxrrM4+qjNMYlm666bS4Hdr3UkIRtf1wavHuXz8E87HOKBNfh zIKcKorpS9g+vXMFRGmMwBCr/3TyxPPuvrO4ik8If08ZSCNiWlPnNTpT6TrCQzi8tzvj C/sg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=pR+wdsTO; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f9si1222986plo.306.2019.08.28.00.20.10; Wed, 28 Aug 2019 00:20:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=pR+wdsTO; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726297AbfH1HUJ (ORCPT + 8 others); Wed, 28 Aug 2019 03:20:09 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:33462 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726252AbfH1HUJ (ORCPT ); Wed, 28 Aug 2019 03:20:09 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x7S7K2Wd126743; Wed, 28 Aug 2019 02:20:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1566976802; bh=+t+/Qiw1iCU7XUNdlc5BaxCXhjDYvL050wWa31KgFc0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=pR+wdsTOST4GukDQCINVeAcrz2zTzejQrJd9AQ2G9iO5rwcQB2CFPxQ36jpiT+7WW zSOrf5v6nnoAKY3I7gmxI1cB3Z+ebhOTbDB/NHXRCXt1nxrsmSU/pVFsB0epeBHDk5 eRN2O4lil2W3s25+Z2pc9z5sxIm8LeJzidrvWpZY= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x7S7K1ch081901 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 28 Aug 2019 02:20:02 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 28 Aug 2019 02:20:01 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 28 Aug 2019 02:20:01 -0500 Received: from sokoban.bb.dnainternet.fi (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x7S7JmfH052201; Wed, 28 Aug 2019 02:19:59 -0500 From: Tero Kristo To: , , , , CC: , , Subject: [PATCHv2 05/11] soc: ti: omap-prm: sync func clock status with resets Date: Wed, 28 Aug 2019 10:19:35 +0300 Message-ID: <20190828071941.32378-6-t-kristo@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190828071941.32378-1-t-kristo@ti.com> References: <20190828071941.32378-1-t-kristo@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hardware reset signals are tightly coupled with associated clocks, and basically de-asserting a reset won't succeed properly if the clock is not enabled, and vice-versa. Also, disabling a clock won't fully succeed if the associated hardware resets are not asserted. Add status sync functionality between these two for TI drivers so that the situations can be handled properly without generating any timeouts. Signed-off-by: Tero Kristo --- drivers/soc/ti/omap_prm.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index 38998ce19c71..e876bad8f8d5 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -15,6 +15,8 @@ #include #include #include +#include +#include #include @@ -42,7 +44,9 @@ struct omap_reset_data { struct reset_controller_dev rcdev; struct omap_prm *prm; struct clockdomain *clkdm; + struct clk *clk; struct device *dev; + u32 mask; }; #define to_omap_reset_data(p) container_of((p), struct omap_reset_data, rcdev) @@ -102,6 +106,8 @@ static int omap_reset_assert(struct reset_controller_dev *rcdev, v |= 1 << id; writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl); + ti_clk_notify_resets(reset->clk, v == reset->mask); + return 0; } @@ -163,9 +169,19 @@ static int omap_reset_deassert(struct reset_controller_dev *rcdev, v &= ~(1 << id); writel_relaxed(v, reset->prm->base + reset->prm->data->rstctrl); + ti_clk_notify_resets(reset->clk, v == reset->mask); + if (!has_rstst) goto exit; + /* If associated clock is disabled, we can't poll completion status */ + if (reset->clk) { + struct clk_hw *hw = __clk_get_hw(reset->clk); + + if (!clk_hw_is_enabled(hw)) + return ret; + } + /* wait for the status to be set */ while (1) { v = readl_relaxed(reset->prm->base + reset->prm->data->rstst); @@ -199,8 +215,10 @@ static int omap_prm_reset_init(struct platform_device *pdev, struct omap_prm *prm) { struct omap_reset_data *reset; + const struct omap_rst_map *map; struct ti_prm_platform_data *pdata = dev_get_platdata(&pdev->dev); char buf[32]; + u32 v; /* * Check if we have controllable resets. If either rstctrl is non-zero @@ -215,6 +233,10 @@ static int omap_prm_reset_init(struct platform_device *pdev, !pdata->clkdm_allow_idle) return -EINVAL; + map = prm->data->rstmap; + if (!map) + return -EINVAL; + reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL); if (!reset) return -ENOMEM; @@ -224,6 +246,10 @@ static int omap_prm_reset_init(struct platform_device *pdev, reset->rcdev.of_node = pdev->dev.of_node; reset->rcdev.nr_resets = OMAP_MAX_RESETS; reset->dev = &pdev->dev; + reset->clk = of_clk_get(pdev->dev.of_node, 0); + + if (IS_ERR(reset->clk)) + reset->clk = NULL; reset->prm = prm; @@ -234,6 +260,16 @@ static int omap_prm_reset_init(struct platform_device *pdev, if (!reset->clkdm) return -EINVAL; + while (map->rst >= 0) { + reset->mask |= BIT(map->rst); + map++; + } + + if (reset->clk) { + v = readl_relaxed(reset->prm->base + reset->prm->data->rstctrl); + ti_clk_notify_resets(reset->clk, v == reset->mask); + } + return devm_reset_controller_register(&pdev->dev, &reset->rcdev); } From patchwork Wed Aug 28 07:19:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 172337 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp366596ily; Wed, 28 Aug 2019 00:22:08 -0700 (PDT) X-Google-Smtp-Source: APXvYqwC8AT1RFiBSjGNzcYuIOAQ/2G2mUEdJTyA/lrzMXJ3817bvRYKBTPcZzPTutNMeNZWKyzA X-Received: by 2002:a63:6097:: with SMTP id u145mr104945pgb.227.1566976815747; Wed, 28 Aug 2019 00:20:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566976815; cv=none; d=google.com; s=arc-20160816; b=E9jM7gwlvs+sVO8lwNeHgyJxDUnM0HmQOwonNXW4A5ouk/nJfsvlQ32u91jMj09H0J CFCEXtngwUeIElIa9snEi7GYD331d5Cv5pVK+SAo9vDc1dKYgUREuiqt58XvamlN/VIq xhOehvsVtSLVgpirnEKpcMFzktjQjhezivhVA5fZG0RWuEQySKK/iOUyrEN7DSVMuZyR lCdyH94ykaUVA2KnItDQQNphPk0O7jU2G1uN3yQqyyNdFXBoIx5oYlFej6DcQcGl+LAN veHSpkxju46z7Bv3/uX62vOVUAmXzldFuSDXCPYDEmTkWYL5AYUy0EaFTpsehVoL0Dma hZzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=H3gWYOUu1IxnMBzQnYaDY16nQ5OnXii/NZ37NGeparY=; b=b8UkKy7vIFpDT0niYU0QTmV2SolFQD1EHEy8m+8i7tgFBj2HP1C5m2L61/n+//s1+B gp1Z0JBcvdQYIRC76ZAV3IwrGbMfAOmCx0KGicO0s2Cf/HoX3sx/dSNDhbuzBkFrAcSF 7eeY7XggehpVBQt6KNqTQXBPEfhX7RYvaOpfRB3uXXZn/+yPgo4w6Vv0qkpu4NaoY+nW hAPMB8jt1bMBYudvvfjuvDETy9Ytr6dzJ/gAsGC2rNWk8pX/CGkgliwCUWqL6x13ndqj K/qwXaSL8e5g1vs9dnP7TW/1Pwe8ii1G7/5bL5Lj381gJeHgiYyZe14WVweQe5Iy/T8j Y9hg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=NwWwH8X6; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Initially this is just used to provide reset support. Signed-off-by: Tero Kristo --- drivers/soc/ti/omap_prm.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index d7a29e282788..192eeae67dfc 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -60,7 +60,29 @@ struct omap_reset_data { #define OMAP_PRM_HAS_RESETS (OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_RSTST) +static const struct omap_rst_map rst_map_01[] = { + { .rst = 0, .st = 0 }, + { .rst = 1, .st = 1 }, + { .rst = -1 }, +}; + +static const struct omap_rst_map rst_map_012[] = { + { .rst = 0, .st = 0 }, + { .rst = 1, .st = 1 }, + { .rst = 2, .st = 2 }, + { .rst = -1 }, +}; + +static const struct omap_prm_data omap4_prm_data[] = { + { .name = "tesla", .base = 0x4a306400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, + { .name = "core", .base = 0x4a306700, .rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ducati", .rstmap = rst_map_012 }, + { .name = "ivahd", .base = 0x4a306f00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012 }, + { .name = "device", .base = 0x4a307b00, .rstctrl = 0x0, .rstst = 0x4, .rstmap = rst_map_01, .flags = OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_NO_CLKDM }, + { }, +}; + static const struct of_device_id omap_prm_id_table[] = { + { .compatible = "ti,omap4-prm-inst", .data = omap4_prm_data }, { }, }; From patchwork Wed Aug 28 07:19:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tero Kristo X-Patchwork-Id: 172335 Delivered-To: patch@linaro.org Received: by 2002:a92:d204:0:0:0:0:0 with SMTP id y4csp366252ily; Wed, 28 Aug 2019 00:21:44 -0700 (PDT) X-Google-Smtp-Source: APXvYqzSvM0gI/MWHS2Tg6LrTytIhAt2J0eX1V4Ilk5+RAeWSUWb59ZcVW/Ayq9XX7Nr/IGem84w X-Received: by 2002:a62:1ad4:: with SMTP id a203mr2969985pfa.210.1566976818737; Wed, 28 Aug 2019 00:20:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566976818; cv=none; d=google.com; s=arc-20160816; b=m68bBZ0NGcowdlWWrOvfG2hchDm0p+exln6YMURngJs+Ej3znRW5wwG7Q2fNJ0hiTi VPO5nTXtxgUatkaixSNpN96PHAviU+1e5DLYGcJjOwYMtcA9A0uxidSbT2Md++J3f8Mg sVr2PtRHKchA+bkWhaeCJFgXt0vlq9yoaZeDC4A5mEwi5n0kGESofnkL7P5TJltIsMY0 8qj+3i8bKkTsPA8AXcHj3bcCkq5djB+iZ1VVvs7FHEgP8y7UOJmj46cUFJ3ceIap/I5C 33hUKoSvM+i+E1urRaeTwk6g40TyHx+yAphRXkQtzgz/8lMB0jwmS6dmZjfId6OlsvAl b0AA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=LG7XOMd3X8KORp948KL5SdMjDvzk087XF2Wob74XRRY=; b=oxlYkK7+yDfhjujlU3n3/U8OzeJzlEm2qENHhEtjkxKkjaIb9+F6cec9BpnvH11rL3 lB2A2DMsN0IL+oAO0gGLzatw0GoyrNCrCHqQhhNQLhCKzLVhI47z4t7yS8j9ni0FyECq v/E+q08myPi3YQc/pXsZTJEL0VQptrjrbpdEp9/87+Zg7bGgvYoAden5LLnjoNOp4oWf xyMwVtmu6VvdgJOhgbfIZR0CdijYjLjxyTM97cqKm7uM//GC5bXlC0VEqn9xJumCh0D1 iqSSAvq8RqlTyJHDr/q0UNuxr2kjDWvNx3CLmPv2hIJwesabSwxmRl7tBoqZbIYNit+G 35Pw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=aVC1ZoaB; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Initially this is just used to provide reset support. Signed-off-by: Tero Kristo --- drivers/soc/ti/omap_prm.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -- 2.17.1 -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index c4b33214bce1..a54c2e556b7a 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -86,6 +86,19 @@ static const struct omap_prm_data omap4_prm_data[] = { { }, }; +static const struct omap_prm_data dra7_prm_data[] = { + { .name = "dsp1", .base = 0x4ae06400, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, + { .name = "ipu", .base = 0x4ae06500, .rstctrl = 0x10, .rstst = 0x14, .clkdm_name = "ipu1", .rstmap = rst_map_012 }, + { .name = "core", .base = 0x4ae06700, .rstctrl = 0x210, .rstst = 0x214, .clkdm_name = "ipu2", .rstmap = rst_map_012 }, + { .name = "iva", .base = 0x4ae06f00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_012 }, + { .name = "dsp2", .base = 0x4ae07b00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, + { .name = "eve1", .base = 0x4ae07b40, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, + { .name = "eve2", .base = 0x4ae07b80, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, + { .name = "eve3", .base = 0x4ae07bc0, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, + { .name = "eve4", .base = 0x4ae07c00, .rstctrl = 0x10, .rstst = 0x14, .rstmap = rst_map_01 }, + { }, +}; + static const struct omap_rst_map am3_per_rst_map[] = { { .rst = 1 }, { .rst = -1 }, @@ -106,6 +119,7 @@ static const struct omap_prm_data am3_prm_data[] = { static const struct of_device_id omap_prm_id_table[] = { { .compatible = "ti,omap4-prm-inst", .data = omap4_prm_data }, + { .compatible = "ti,dra7-prm-inst", .data = dra7_prm_data }, { .compatible = "ti,am3-prm-inst", .data = am3_prm_data }, { }, };