From patchwork Fri Dec 8 17:12:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 752107 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 691071DDF8; Fri, 8 Dec 2023 17:12:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VABdvc3X" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C4568C433CD; Fri, 8 Dec 2023 17:12:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1702055576; bh=iSOH3A5QgqhsUj9+GFj8Hb2u5gLp0VTCfaRJ8xMnQ1s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VABdvc3X+HfnTcOrHRSGRUAlP3Uu1ZxOXC3BOmQniPEwEvKAIf8IoNlcMYa50lrJz 16uCHntwA8hPcEbJoeoKu2M++xYwFNPcdVp1/y8/HTN/E6lut08HsKyVl+uuSvVlXE C+M8qRtJipr+GhcqeMabuac5x1ckqTkeFgLuZc7xPGkQut7S3o+BFoZuqiPKK9TAeP 4/+rkiXDgyE6I3nrkkmkb26s1+916Xhb7XXKxph1y0nTUeqD/7sbFNZv5jtCAvPo6/ 78anyRettPtws0obn4n8Q4SbOIYDTUSqHTZFRm2oYjHO8u3R+T/++NxLql6pVxT7ec hwCqrh4TCECJg== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , Wolfgang Grandegger , Marc Kleine-Budde , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Michael Turquette , Stephen Boyd , linux-can@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH RESEND v1 1/7] dt-bindings: clock: mpfs: add more MSSPLL output definitions Date: Fri, 8 Dec 2023 17:12:23 +0000 Message-Id: <20231208-unripe-maximum-fc77f4967561@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231208-reenter-ajar-b6223e5134b3@spud> References: <20231208-reenter-ajar-b6223e5134b3@spud> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=880; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=IbMe5Hhtp7MV7Ctc98IUVkgW0I0cOo4e8OWx+9g0CX8=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDKnFfuU+JieKTecHfDe752ckWn/icPKJfy8j7nDpGagsS b4oX2DdUcrCIMbBICumyJJ4u69Fav0flx3OPW9h5rAygQxh4OIUgInYaTP895jzPVshhKlxzoHU gpCrj+ZY3rrPoMV6z5xjYsLJe2rc3xn+KfKuLrouzmB/5vnhywLhrufmzys1Y37vX5fz11SfwWI ROwA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C From: Conor Dooley There are 3 undocumented outputs of the MSSPLL that are used for the CAN bus, "user crypto" module and eMMC. Add their clock IDs so that they can be hooked up in DT. Signed-off-by: Conor Dooley --- include/dt-bindings/clock/microchip,mpfs-clock.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/dt-bindings/clock/microchip,mpfs-clock.h b/include/dt-bindings/clock/microchip,mpfs-clock.h index 79775a5134ca..b52f19a2b480 100644 --- a/include/dt-bindings/clock/microchip,mpfs-clock.h +++ b/include/dt-bindings/clock/microchip,mpfs-clock.h @@ -44,6 +44,11 @@ #define CLK_RTCREF 33 #define CLK_MSSPLL 34 +#define CLK_MSSPLL0 34 +#define CLK_MSSPLL1 35 +#define CLK_MSSPLL2 36 +#define CLK_MSSPLL3 37 +/* 38 is reserved for MSS PLL internals */ /* Clock Conditioning Circuitry Clock IDs */ From patchwork Fri Dec 8 17:12:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 751730 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E03F51DDF8; Fri, 8 Dec 2023 17:13:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KHk8a5tZ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 56995C433B9; Fri, 8 Dec 2023 17:12:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1702055581; bh=eOwkSq/WwMGsBDJxIoKyyiwasgmQQYpNauvY4yRRwsE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KHk8a5tZwx6HzsT8T5BnndKAcsPltUq64Ek4Pr5fovixj2Aq/i9OEQXYhY+w6CuIB iQ713l1de5Asz5Ax4hK6RGHX7DC9QEYGeaWRNgbiDq3hDTLN7j1D5mgaj0jjqzZ7Xu 1aB87nlMv7p+TlIYR4E4rcHY/JiUJpxGIg++fsAWcK87pRUKQYMBgZHsDiDJ5g+U8/ GtwCtIK7kY0TJZE4KCj4b6NFP89gICI5qYZkGl0Ja20tWFXDy8Y3/wQVROVliaZjzC KkeyJScyQ+CQ8bkVKg1sPQwblR2SFrf4hHKg9DAsw6n0GcGtDVGerkBdQMiMAiG08l NfWbBDmM8zYqQ== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , Wolfgang Grandegger , Marc Kleine-Budde , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Michael Turquette , Stephen Boyd , linux-can@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH RESEND v1 2/7] dt-bindings: can: mpfs: add missing required clock Date: Fri, 8 Dec 2023 17:12:24 +0000 Message-Id: <20231208-palpitate-passable-c79bacf2036c@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231208-reenter-ajar-b6223e5134b3@spud> References: <20231208-reenter-ajar-b6223e5134b3@spud> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1442; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=t/lsdJsWux+0djN2ESjLKlgMF40rkcl8R8FM1XRhzgA=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDKnFfuUPWvbyRO6Tbtj3XqD4/x2h2j8HPA3+TjArX7qZR 3nqsvs/O0pZGMQ4GGTFFFkSb/e1SK3/47LDuectzBxWJpAhDFycAjCR9GaGP9yJsZf/zW2rSddd 9SykPKmwPsXIv9vR85b+VLVjN0PVQxn++zcH+hXx6GgvW2xp8sDt9Pna46/0LFtPtVv3PxGL+zW bAQA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C From: Conor Dooley The CAN controller on PolarFire SoC has an AHB peripheral clock _and_ a CAN bus clock. The bus clock was omitted when the binding was written, but is required for operation. Make up for lost time and add it. Cautionary tale in adding bindings without having implemented a real user for them perhaps. Fixes: c878d518d7b6 ("dt-bindings: can: mpfs: document the mpfs CAN controller") Signed-off-by: Conor Dooley --- .../devicetree/bindings/net/can/microchip,mpfs-can.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml b/Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml index 45aa3de7cf01..05f680f15b17 100644 --- a/Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml +++ b/Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml @@ -24,7 +24,10 @@ properties: maxItems: 1 clocks: - maxItems: 1 + maxItems: 2 + items: + - description: AHB peripheral clock + - description: CAN bus clock required: - compatible @@ -39,7 +42,7 @@ examples: can@2010c000 { compatible = "microchip,mpfs-can"; reg = <0x2010c000 0x1000>; - clocks = <&clkcfg 17>; + clocks = <&clkcfg 17>, <&clkcfg 37>; interrupt-parent = <&plic>; interrupts = <56>; }; From patchwork Fri Dec 8 17:12:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 752106 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8EB381DDF8; Fri, 8 Dec 2023 17:13:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nVnI1uxN" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DCBEDC433C8; Fri, 8 Dec 2023 17:13:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1702055586; bh=k641xO4S6rZ07oG/ZPMOg0OdXInn1b9tfMjVyJWM8hs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nVnI1uxNwOzJvHfVd2al8nVTX1RK3HdlLC1QcltVR0AUaFSGUjJFP5CHRcQDo7hwq oHWX0oswDsCJ5tbxseGg3Ol8oi7ZvW9lj5euq6yYHuejTEild9LPFvgI8rYwszI980 AgUZOkLKIT4FMb9eXrQvBlYlT12V2a+zDjqKaPrSktom/YLLSmOiue+XyEtg+QAFEc qjdZwGYTDDeTk2dRdxkCn94wrz8JP4VMyRzJ7eF4pmZZBNdvq0raiPPRJxinCaTR13 G1SxWSuQvMPIh5donNcOg1UImvSHBwceabGwT3p3qi7plaYZxQcwHbJfJkzPE1YZ0+ FxcTdEPc7pBBw== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , Wolfgang Grandegger , Marc Kleine-Budde , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Michael Turquette , Stephen Boyd , linux-can@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH RESEND v1 3/7] clk: microchip: mpfs: split MSSPLL in two Date: Fri, 8 Dec 2023 17:12:25 +0000 Message-Id: <20231208-grab-conjuror-3ced7f366d70@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231208-reenter-ajar-b6223e5134b3@spud> References: <20231208-reenter-ajar-b6223e5134b3@spud> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=10024; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=NRUa1qYUK0JELxAGivzxtKy665djDR3m4OsIk9VTjD8=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDKnFfuVf5sjUml/U+cl268rVfXf+Z1/yP2YTtiq2a+asM JGQyCmJHaUsDGIcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZjI/JOMDA8Xaeg9jb9zbFq1 +1xHS854gzm7Dgi/X5V24VwQy/nly9UYGfbrJgkGTijR/vuCyZZZae9/hrgLsjFtZ56IyS4WklM zYgIA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C From: Conor Dooley The MSSPLL is really two stages - there's the PLL itself and 4 outputs, each with their own divider. The current driver models this as a single entity, outputting a single clock, used for both the CPU and AHB/AXI buses. The other 3 outputs are used for the eMMC, "user crypto" and CAN controller. Split the MSSPLL in two, as a precursor to adding support for the other 3 outputs, with the PLL itself as one "hw" clock and the output divider stage as another. Signed-off-by: Conor Dooley --- drivers/clk/microchip/clk-mpfs.c | 188 ++++++++++++++++++++----------- 1 file changed, 123 insertions(+), 65 deletions(-) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c index c8ffa755b58d..b05bdab10cdc 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -30,6 +30,13 @@ #define MSSPLL_POSTDIV_WIDTH 0x07u #define MSSPLL_FIXED_DIV 4u +/* + * This clock ID is defined here, rather than the binding headers, as it is an + * internal clock only, and therefore has no consumers in other peripheral + * blocks. + */ +#define CLK_MSSPLL_INTERNAL 38u + struct mpfs_clock_data { struct device *dev; void __iomem *base; @@ -39,17 +46,27 @@ struct mpfs_clock_data { struct mpfs_msspll_hw_clock { void __iomem *base; + struct clk_hw hw; + struct clk_init_data init; unsigned int id; u32 reg_offset; u32 shift; u32 width; u32 flags; - struct clk_hw hw; - struct clk_init_data init; }; #define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw) +struct mpfs_msspll_out_hw_clock { + void __iomem *base; + struct clk_hw hw; + struct clk_init_data init; + unsigned int id; + u32 flags; +}; + +#define to_mpfs_msspll_out_clk(_hw) container_of(_hw, struct mpfs_msspll_out_hw_clock, hw) + struct mpfs_cfg_hw_clock { struct clk_divider cfg; struct clk_init_data init; @@ -93,93 +110,40 @@ static const struct clk_div_table mpfs_div_rtcref_table[] = { { 0, 0 } }; +/* + * MSS PLL internal clock + */ + static unsigned long mpfs_clk_msspll_recalc_rate(struct clk_hw *hw, unsigned long prate) -{ - struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); - void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; - void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; - void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; - u32 mult, ref_div, postdiv; - - mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; - mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); - ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; - ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); - postdiv = readl_relaxed(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT; - postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH); - - return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv); -} - -static long mpfs_clk_msspll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; u32 mult, ref_div; - unsigned long rate_before_ctrl; mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); - rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult; - - return divider_round_rate(hw, rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH, - msspll_hw->flags); -} - -static int mpfs_clk_msspll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) -{ - struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); - void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; - void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; - void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; - u32 mult, ref_div, postdiv; - int divider_setting; - unsigned long rate_before_ctrl, flags; - - mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; - mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); - ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; - ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); - - rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult; - divider_setting = divider_get_val(rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH, - msspll_hw->flags); - - if (divider_setting < 0) - return divider_setting; - - spin_lock_irqsave(&mpfs_clk_lock, flags); - - postdiv = readl_relaxed(postdiv_addr); - postdiv &= ~(clk_div_mask(MSSPLL_POSTDIV_WIDTH) << MSSPLL_POSTDIV_SHIFT); - writel_relaxed(postdiv, postdiv_addr); - - spin_unlock_irqrestore(&mpfs_clk_lock, flags); - - return 0; + return prate * mult / (ref_div * MSSPLL_FIXED_DIV); } static const struct clk_ops mpfs_clk_msspll_ops = { .recalc_rate = mpfs_clk_msspll_recalc_rate, - .round_rate = mpfs_clk_msspll_round_rate, - .set_rate = mpfs_clk_msspll_set_rate, }; #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \ .id = _id, \ + .flags = _flags, \ .shift = _shift, \ .width = _width, \ .reg_offset = _offset, \ - .flags = _flags, \ .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, &mpfs_clk_msspll_ops, 0), \ } static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = { - CLK_PLL(CLK_MSSPLL, "clk_msspll", mpfs_ext_ref, MSSPLL_FBDIV_SHIFT, + CLK_PLL(CLK_MSSPLL_INTERNAL, "clk_msspll_internal", mpfs_ext_ref, MSSPLL_FBDIV_SHIFT, MSSPLL_FBDIV_WIDTH, 0, REG_MSSPLL_SSCG_2_CR), }; @@ -196,7 +160,7 @@ static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_c ret = devm_clk_hw_register(dev, &msspll_hw->hw); if (ret) return dev_err_probe(dev, ret, "failed to register msspll id: %d\n", - CLK_MSSPLL); + CLK_MSSPLL_INTERNAL); data->hw_data.hws[msspll_hw->id] = &msspll_hw->hw; } @@ -204,6 +168,94 @@ static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_c return 0; } +/* + * MSS PLL output clocks + */ + +static unsigned long mpfs_clk_msspll_out_recalc_rate(struct clk_hw *hw, unsigned long prate) +{ + struct mpfs_msspll_out_hw_clock *msspll_out_hw = to_mpfs_msspll_out_clk(hw); + void __iomem *postdiv_addr = msspll_out_hw->base + REG_MSSPLL_POSTDIV_CR; + u32 postdiv; + + postdiv = readl_relaxed(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT; + postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH); + + return prate / postdiv; +} + +static long mpfs_clk_msspll_out_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct mpfs_msspll_out_hw_clock *msspll_out_hw = to_mpfs_msspll_out_clk(hw); + + return divider_round_rate(hw, rate, prate, NULL, MSSPLL_POSTDIV_WIDTH, + msspll_out_hw->flags); +} + +static int mpfs_clk_msspll_out_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) +{ + struct mpfs_msspll_out_hw_clock *msspll_out_hw = to_mpfs_msspll_out_clk(hw); + void __iomem *postdiv_addr = msspll_out_hw->base + REG_MSSPLL_POSTDIV_CR; + u32 postdiv; + int divider_setting; + unsigned long flags; + + divider_setting = divider_get_val(rate, prate, NULL, MSSPLL_POSTDIV_WIDTH, + msspll_out_hw->flags); + + if (divider_setting < 0) + return divider_setting; + + spin_lock_irqsave(&mpfs_clk_lock, flags); + + postdiv = readl_relaxed(postdiv_addr); + postdiv &= ~(clk_div_mask(MSSPLL_POSTDIV_WIDTH) << MSSPLL_POSTDIV_SHIFT); + writel_relaxed(postdiv, postdiv_addr); + + spin_unlock_irqrestore(&mpfs_clk_lock, flags); + + return 0; +} + +static const struct clk_ops mpfs_clk_msspll_out_ops = { + .recalc_rate = mpfs_clk_msspll_out_recalc_rate, + .round_rate = mpfs_clk_msspll_out_round_rate, + .set_rate = mpfs_clk_msspll_out_set_rate, +}; + +#define CLK_PLL_OUT(_id, _name, _parent, _flags) { \ + .id = _id, \ + .flags = _flags, \ + .hw.init = CLK_HW_INIT(_name, _parent, &mpfs_clk_msspll_out_ops, 0), \ +} + +static struct mpfs_msspll_out_hw_clock mpfs_msspll_out_clks[] = { + CLK_PLL_OUT(CLK_MSSPLL, "clk_msspll", "clk_msspll_internal", 0), +}; + +static int mpfs_clk_register_msspll_outs(struct device *dev, + struct mpfs_msspll_out_hw_clock *msspll_out_hws, + unsigned int num_clks, struct mpfs_clock_data *data) +{ + unsigned int i; + int ret; + + for (i = 0; i < num_clks; i++) { + struct mpfs_msspll_out_hw_clock *msspll_out_hw = &msspll_out_hws[i]; + + msspll_out_hw->base = data->msspll_base; + ret = devm_clk_hw_register(dev, &msspll_out_hw->hw); + if (ret) + return dev_err_probe(dev, ret, "failed to register msspll out id: %d\n", + msspll_out_hw->id); + + data->hw_data.hws[msspll_out_hw->id] = &msspll_out_hw->hw; + } + + return 0; +} + /* * "CFG" clocks */ @@ -442,8 +494,8 @@ static int mpfs_clk_probe(struct platform_device *pdev) int ret; /* CLK_RESERVED is not part of clock arrays, so add 1 */ - num_clks = ARRAY_SIZE(mpfs_msspll_clks) + ARRAY_SIZE(mpfs_cfg_clks) - + ARRAY_SIZE(mpfs_periph_clks) + 1; + num_clks = ARRAY_SIZE(mpfs_msspll_clks) + ARRAY_SIZE(mpfs_msspll_out_clks) + + ARRAY_SIZE(mpfs_cfg_clks) + ARRAY_SIZE(mpfs_periph_clks) + 1; clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws, num_clks), GFP_KERNEL); if (!clk_data) @@ -466,6 +518,12 @@ static int mpfs_clk_probe(struct platform_device *pdev) if (ret) return ret; + ret = mpfs_clk_register_msspll_outs(dev, mpfs_msspll_out_clks, + ARRAY_SIZE(mpfs_msspll_out_clks), + clk_data); + if (ret) + return ret; + ret = mpfs_clk_register_cfgs(dev, mpfs_cfg_clks, ARRAY_SIZE(mpfs_cfg_clks), clk_data); if (ret) return ret; From patchwork Fri Dec 8 17:12:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 751729 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B6AE1DDF8; Fri, 8 Dec 2023 17:13:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KeimEb55" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6FD8DC433C7; Fri, 8 Dec 2023 17:13:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1702055590; bh=wG0PAtBtH29YD+lEgHJslL6TUhE1P+xWs/z1DwA9XNA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KeimEb55QS0RBD1y0yZvPtNBR07bwY4SF9exDzMfpH+5NK86HZoaoHLOXVgnOrUBe rCkza+XSi/QYu7+pUpIpsmoPuHWt/VTtQms//XcM8NzIPfbGWtMju0rXo6LqCItzce s01EMiGQFZ+fg3eejyhFKAmAVZttDtrnRIwRPwPgz5RtQxTRrX9mkUWGubY9XlbSmd bvqceIUyj57SaOAMbzdzkTi7+/6sA8yrlm5WqabgmK1RnfgllPZx+4dzwZJmd35m/8 sE+krSDjcEEoc/iuH8hcAowq7T/YLE0nXQ/CBZom8IGc0YIkpk/H/J5SCT0tUr8fiO P7zpxZtU67OkA== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , Wolfgang Grandegger , Marc Kleine-Budde , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Michael Turquette , Stephen Boyd , linux-can@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH RESEND v1 4/7] clk: microchip: mpfs: setup for using other mss pll outputs Date: Fri, 8 Dec 2023 17:12:26 +0000 Message-Id: <20231208-manlike-stainless-95a21ee4ee67@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231208-reenter-ajar-b6223e5134b3@spud> References: <20231208-reenter-ajar-b6223e5134b3@spud> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4670; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=jajlzfigpFa1OeGxZYgOSuQlL+g05VMYN2svv3ZkxAg=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDKnFfhUP76XOD+Su0/mW+uS7Z93b2N5La7d9OK/B27Krz H/ZF7+/HaUsDGIcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZiI2UaG/wmfTpwOVq+Yufbu 8Xss1i/eKlU+YZGUk1+WcdxxyaNol3xGhgUfvPWz7Q7zqjmc6Y6P+tRk49B/xE0+4031X8t1qeq 7uAE= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C From: Conor Dooley Now that the MSSPLL is split, and the "postdiv" divider of the cpu/AHB/AXI bus clock is represented by its own "hw" struct, make the shifts, register offset and width a parameter of the initialisation macro, rather than using defines that only work for one of the four outputs. Configuring this at initialisaion paves the way for using the other three output clocks, where the register offset, and the bit shift within that register, will differ. Signed-off-by: Conor Dooley --- drivers/clk/microchip/clk-mpfs.c | 30 +++++++++++++++++++----------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c index b05bdab10cdc..9edd0333e693 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -15,7 +15,8 @@ /* address offset of control registers */ #define REG_MSSPLL_REF_CR 0x08u -#define REG_MSSPLL_POSTDIV_CR 0x10u +#define REG_MSSPLL_POSTDIV01_CR 0x10u +#define REG_MSSPLL_POSTDIV23_CR 0x14u #define REG_MSSPLL_SSCG_2_CR 0x2Cu #define REG_CLOCK_CONFIG_CR 0x08u #define REG_RTC_CLOCK_CR 0x0Cu @@ -26,7 +27,7 @@ #define MSSPLL_FBDIV_WIDTH 0x0Cu #define MSSPLL_REFDIV_SHIFT 0x08u #define MSSPLL_REFDIV_WIDTH 0x06u -#define MSSPLL_POSTDIV_SHIFT 0x08u +#define MSSPLL_POSTDIV02_SHIFT 0x08u #define MSSPLL_POSTDIV_WIDTH 0x07u #define MSSPLL_FIXED_DIV 4u @@ -62,6 +63,9 @@ struct mpfs_msspll_out_hw_clock { struct clk_hw hw; struct clk_init_data init; unsigned int id; + u32 reg_offset; + u32 shift; + u32 width; u32 flags; }; @@ -175,11 +179,11 @@ static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_c static unsigned long mpfs_clk_msspll_out_recalc_rate(struct clk_hw *hw, unsigned long prate) { struct mpfs_msspll_out_hw_clock *msspll_out_hw = to_mpfs_msspll_out_clk(hw); - void __iomem *postdiv_addr = msspll_out_hw->base + REG_MSSPLL_POSTDIV_CR; + void __iomem *postdiv_addr = msspll_out_hw->base + msspll_out_hw->reg_offset; u32 postdiv; - postdiv = readl_relaxed(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT; - postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH); + postdiv = readl_relaxed(postdiv_addr) >> msspll_out_hw->shift; + postdiv &= clk_div_mask(msspll_out_hw->width); return prate / postdiv; } @@ -189,19 +193,19 @@ static long mpfs_clk_msspll_out_round_rate(struct clk_hw *hw, unsigned long rate { struct mpfs_msspll_out_hw_clock *msspll_out_hw = to_mpfs_msspll_out_clk(hw); - return divider_round_rate(hw, rate, prate, NULL, MSSPLL_POSTDIV_WIDTH, + return divider_round_rate(hw, rate, prate, NULL, msspll_out_hw->width, msspll_out_hw->flags); } static int mpfs_clk_msspll_out_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) { struct mpfs_msspll_out_hw_clock *msspll_out_hw = to_mpfs_msspll_out_clk(hw); - void __iomem *postdiv_addr = msspll_out_hw->base + REG_MSSPLL_POSTDIV_CR; + void __iomem *postdiv_addr = msspll_out_hw->base + msspll_out_hw->reg_offset; u32 postdiv; int divider_setting; unsigned long flags; - divider_setting = divider_get_val(rate, prate, NULL, MSSPLL_POSTDIV_WIDTH, + divider_setting = divider_get_val(rate, prate, NULL, msspll_out_hw->width, msspll_out_hw->flags); if (divider_setting < 0) @@ -210,7 +214,7 @@ static int mpfs_clk_msspll_out_set_rate(struct clk_hw *hw, unsigned long rate, u spin_lock_irqsave(&mpfs_clk_lock, flags); postdiv = readl_relaxed(postdiv_addr); - postdiv &= ~(clk_div_mask(MSSPLL_POSTDIV_WIDTH) << MSSPLL_POSTDIV_SHIFT); + postdiv &= ~(clk_div_mask(msspll_out_hw->width) << msspll_out_hw->shift); writel_relaxed(postdiv, postdiv_addr); spin_unlock_irqrestore(&mpfs_clk_lock, flags); @@ -224,14 +228,18 @@ static const struct clk_ops mpfs_clk_msspll_out_ops = { .set_rate = mpfs_clk_msspll_out_set_rate, }; -#define CLK_PLL_OUT(_id, _name, _parent, _flags) { \ +#define CLK_PLL_OUT(_id, _name, _parent, _flags, _shift, _width, _offset) { \ .id = _id, \ + .shift = _shift, \ + .width = _width, \ + .reg_offset = _offset, \ .flags = _flags, \ .hw.init = CLK_HW_INIT(_name, _parent, &mpfs_clk_msspll_out_ops, 0), \ } static struct mpfs_msspll_out_hw_clock mpfs_msspll_out_clks[] = { - CLK_PLL_OUT(CLK_MSSPLL, "clk_msspll", "clk_msspll_internal", 0), + CLK_PLL_OUT(CLK_MSSPLL, "clk_msspll", "clk_msspll_internal", 0, + MSSPLL_POSTDIV02_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV01_CR), }; static int mpfs_clk_register_msspll_outs(struct device *dev, From patchwork Fri Dec 8 17:12:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 752105 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 98B851DDF8; Fri, 8 Dec 2023 17:13:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Gve4KbqH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0285CC433CC; Fri, 8 Dec 2023 17:13:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1702055595; bh=cvHj0CJs3ephVaZuvj3Ux2wXR9Tblc/RuJQlfKnG8ug=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Gve4KbqHqOssmkDZ0lw8ymDKMQGoo2hi5IvNvbBdYPjCb3N0MKm0HtT5z2J0Xec+V jsldg0umkd1P0PGCydELajMD+g11QVTmT+ZCKGU1DqS7lfq4bMiNkeYNJydojFQnrX fbLZ+llObV7Hnw1r+l/J9tKCfCiYjgC6Fp9tzo73Z/Bih3EUYKkxfCAEEWV16yC8XI cOFdDJuAje5S8gzRjZR4QUgOnjDk6ZuDGOX6liDYgXjKW/BoD3641OscVp+RdukCxe x3HB/TZMI8RmAs2tDvDKdCv15mYB8hpeSj3ZgtozHUx9XcaZn1f1ZuIwyaX3e65mZe g/gUPqUGqWKHw== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , Wolfgang Grandegger , Marc Kleine-Budde , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Michael Turquette , Stephen Boyd , linux-can@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH RESEND v1 5/7] clk: microchip: mpfs: add missing MSSPLL outputs Date: Fri, 8 Dec 2023 17:12:27 +0000 Message-Id: <20231208-amends-thus-6d7963f33357@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231208-reenter-ajar-b6223e5134b3@spud> References: <20231208-reenter-ajar-b6223e5134b3@spud> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1721; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=3gU1OSn3YxaVElJ8X4nK41xe7sOdS/RS/naYsgWnvQ0=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDKnFfhVMKVsmuZetDbTUDZL5e2sNq1ATU89FrqKJ5d1Sv 880r+TpKGVhEONgkBVTZEm83dcitf6Pyw7nnrcwc1iZQIYwcHEKwESunWdkmH8shfl5/ZHcvAzX 0P8n5nlE2v7NeDtL/dW0+waXXMreL2T4p9EuZOO/6pfdAu8zClO0ba7Ibjx9zeIBx5SIXRP392o W8AEA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C From: Conor Dooley The MSSPLL has 4 outputs, of which only the cpu/axi/ahb clock parent is currently implemented. Add the CAN clock too, as that'll be needed by the driver for the CAN controller and uses output 3. While we are here, the other two missing clocks, used by the eMMC/SD controller and by the "user crypto". Signed-off-by: Conor Dooley --- drivers/clk/microchip/clk-mpfs.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c index 9edd0333e693..f62269320b2a 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -28,6 +28,7 @@ #define MSSPLL_REFDIV_SHIFT 0x08u #define MSSPLL_REFDIV_WIDTH 0x06u #define MSSPLL_POSTDIV02_SHIFT 0x08u +#define MSSPLL_POSTDIV13_SHIFT 0x18u #define MSSPLL_POSTDIV_WIDTH 0x07u #define MSSPLL_FIXED_DIV 4u @@ -240,6 +241,12 @@ static const struct clk_ops mpfs_clk_msspll_out_ops = { static struct mpfs_msspll_out_hw_clock mpfs_msspll_out_clks[] = { CLK_PLL_OUT(CLK_MSSPLL, "clk_msspll", "clk_msspll_internal", 0, MSSPLL_POSTDIV02_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV01_CR), + CLK_PLL_OUT(CLK_MSSPLL1, "clk_msspll1", "clk_msspll_internal", 0, + MSSPLL_POSTDIV13_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV01_CR), + CLK_PLL_OUT(CLK_MSSPLL2, "clk_msspll2", "clk_msspll_internal", 0, + MSSPLL_POSTDIV02_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV23_CR), + CLK_PLL_OUT(CLK_MSSPLL3, "clk_msspll3", "clk_msspll_internal", 0, + MSSPLL_POSTDIV13_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV23_CR), }; static int mpfs_clk_register_msspll_outs(struct device *dev, From patchwork Fri Dec 8 17:12:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 751728 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CEF643984F; Fri, 8 Dec 2023 17:13:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="i6PY/hgl" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8994CC433B7; Fri, 8 Dec 2023 17:13:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1702055599; bh=ZCkEJKSbYO46WRnXwuUSBhBTUa4iqWLls9v1ii/IqNc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=i6PY/hglhQ1w3JJZwNubtebDN+QbGV6LA1LoPfwI0WujxyOH4OrJFVK+dWlL9YHSA E5dVL/CuzfK+ds/e/JeBs2+J6uBCQZDK8ZIXrVHtNQ9ai/HF2sLpSJusrpI+tTz67Z wwzkxlyQzTPUwxnjwoRa3N3+A6RGI68qUhKC0IHFcXPBTZMp7MFI3lrXaZFBcdh2gk coaaIxeNY+HvADMolicYnMMkgg9qAW3FroiDzPIJMyNQphAiyO/mZTTWXK8hb0rTOj H5ElzpGGh2JvPpOiJ72C6gseih85L1fyi+Qda7KzJg6CrAHGk8pcFuzxYdamtbz1Xo nCHLtBbLJg8YA== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , Wolfgang Grandegger , Marc Kleine-Budde , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Michael Turquette , Stephen Boyd , linux-can@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH RESEND v1 6/7] clk: microchip: mpfs: convert MSSPLL outputs to clk_divider Date: Fri, 8 Dec 2023 17:12:28 +0000 Message-Id: <20231208-pretender-curtsy-3a04d8969c2b@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231208-reenter-ajar-b6223e5134b3@spud> References: <20231208-reenter-ajar-b6223e5134b3@spud> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5152; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=VdSF/MzrZnEXeRp1s66NVbnm6dEZIEnZVEN9BkdHG34=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDKnFfhUlSa+aLuqfPc7mXNo1b5rKr5UlH1PtJvXaNS/+4 Jn/yra2o5SFQYyDQVZMkSXxdl+L1Po/Ljuce97CzGFlAhnCwMUpABO56MTwV9zxmL7epMbta98U GzlfyD8nemHdqi7Jx5t2ci4VnDuHcT3Db9YWtV2b11UeLtBlXbZyRo+mU8ApoTTe78q5we+vTxN n5gYA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C From: Conor Dooley After splitting the MSSPLL in two, the PLL outputs have become open-coded versions of clk_divider. Drop the custom clk ops structs, and instead use the generic clk_divider_ops. Signed-off-by: Conor Dooley --- drivers/clk/microchip/clk-mpfs.c | 81 ++++++-------------------------- 1 file changed, 14 insertions(+), 67 deletions(-) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c index f62269320b2a..ef4511186a23 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -61,13 +61,10 @@ struct mpfs_msspll_hw_clock { struct mpfs_msspll_out_hw_clock { void __iomem *base; - struct clk_hw hw; + struct clk_divider output; struct clk_init_data init; unsigned int id; u32 reg_offset; - u32 shift; - u32 width; - u32 flags; }; #define to_mpfs_msspll_out_clk(_hw) container_of(_hw, struct mpfs_msspll_out_hw_clock, hw) @@ -177,75 +174,25 @@ static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_c * MSS PLL output clocks */ -static unsigned long mpfs_clk_msspll_out_recalc_rate(struct clk_hw *hw, unsigned long prate) -{ - struct mpfs_msspll_out_hw_clock *msspll_out_hw = to_mpfs_msspll_out_clk(hw); - void __iomem *postdiv_addr = msspll_out_hw->base + msspll_out_hw->reg_offset; - u32 postdiv; - - postdiv = readl_relaxed(postdiv_addr) >> msspll_out_hw->shift; - postdiv &= clk_div_mask(msspll_out_hw->width); - - return prate / postdiv; -} - -static long mpfs_clk_msspll_out_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - struct mpfs_msspll_out_hw_clock *msspll_out_hw = to_mpfs_msspll_out_clk(hw); - - return divider_round_rate(hw, rate, prate, NULL, msspll_out_hw->width, - msspll_out_hw->flags); -} - -static int mpfs_clk_msspll_out_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) -{ - struct mpfs_msspll_out_hw_clock *msspll_out_hw = to_mpfs_msspll_out_clk(hw); - void __iomem *postdiv_addr = msspll_out_hw->base + msspll_out_hw->reg_offset; - u32 postdiv; - int divider_setting; - unsigned long flags; - - divider_setting = divider_get_val(rate, prate, NULL, msspll_out_hw->width, - msspll_out_hw->flags); - - if (divider_setting < 0) - return divider_setting; - - spin_lock_irqsave(&mpfs_clk_lock, flags); - - postdiv = readl_relaxed(postdiv_addr); - postdiv &= ~(clk_div_mask(msspll_out_hw->width) << msspll_out_hw->shift); - writel_relaxed(postdiv, postdiv_addr); - - spin_unlock_irqrestore(&mpfs_clk_lock, flags); - - return 0; -} - -static const struct clk_ops mpfs_clk_msspll_out_ops = { - .recalc_rate = mpfs_clk_msspll_out_recalc_rate, - .round_rate = mpfs_clk_msspll_out_round_rate, - .set_rate = mpfs_clk_msspll_out_set_rate, -}; - #define CLK_PLL_OUT(_id, _name, _parent, _flags, _shift, _width, _offset) { \ .id = _id, \ - .shift = _shift, \ - .width = _width, \ + .output.shift = _shift, \ + .output.width = _width, \ + .output.table = NULL, \ .reg_offset = _offset, \ - .flags = _flags, \ - .hw.init = CLK_HW_INIT(_name, _parent, &mpfs_clk_msspll_out_ops, 0), \ + .output.flags = _flags, \ + .output.hw.init = CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \ + .output.lock = &mpfs_clk_lock, \ } static struct mpfs_msspll_out_hw_clock mpfs_msspll_out_clks[] = { - CLK_PLL_OUT(CLK_MSSPLL, "clk_msspll", "clk_msspll_internal", 0, + CLK_PLL_OUT(CLK_MSSPLL, "clk_msspll", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED, MSSPLL_POSTDIV02_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV01_CR), - CLK_PLL_OUT(CLK_MSSPLL1, "clk_msspll1", "clk_msspll_internal", 0, + CLK_PLL_OUT(CLK_MSSPLL1, "clk_msspll1", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED, MSSPLL_POSTDIV13_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV01_CR), - CLK_PLL_OUT(CLK_MSSPLL2, "clk_msspll2", "clk_msspll_internal", 0, + CLK_PLL_OUT(CLK_MSSPLL2, "clk_msspll2", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED, MSSPLL_POSTDIV02_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV23_CR), - CLK_PLL_OUT(CLK_MSSPLL3, "clk_msspll3", "clk_msspll_internal", 0, + CLK_PLL_OUT(CLK_MSSPLL3, "clk_msspll3", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED, MSSPLL_POSTDIV13_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV23_CR), }; @@ -259,13 +206,13 @@ static int mpfs_clk_register_msspll_outs(struct device *dev, for (i = 0; i < num_clks; i++) { struct mpfs_msspll_out_hw_clock *msspll_out_hw = &msspll_out_hws[i]; - msspll_out_hw->base = data->msspll_base; - ret = devm_clk_hw_register(dev, &msspll_out_hw->hw); + msspll_out_hw->output.reg = data->msspll_base + msspll_out_hw->reg_offset; + ret = devm_clk_hw_register(dev, &msspll_out_hw->output.hw); if (ret) return dev_err_probe(dev, ret, "failed to register msspll out id: %d\n", msspll_out_hw->id); - data->hw_data.hws[msspll_out_hw->id] = &msspll_out_hw->hw; + data->hw_data.hws[msspll_out_hw->id] = &msspll_out_hw->output.hw; } return 0; From patchwork Fri Dec 8 17:12:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 752104 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A12001DDF8; Fri, 8 Dec 2023 17:13:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TAmcUMkQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1C14FC433CA; Fri, 8 Dec 2023 17:13:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1702055604; bh=8ebnwItR1hA/vG3C99K441+Vr5JnEbuXL+hnQjJvrlA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TAmcUMkQgVIofiBroeXwmP8mYZXdKSioXvQqiTLBvW9FPtTQyLwDLPGNmlvNVFqQR +uvda5arfvyt8eCWgXSMAye8qqDTSZ+PSAkqV9bZW28SldC4Mw0RJeD6uu91Vjcriu apQz1mzct1m0LYg4klTqSlxLE6qgOEHKpKekm9fZgg4X2Zh7EVsseQWYA+a6yR/TF1 9zSisp+eO+ecV1QL2SW4sMhh42lDxErTvJ0MQZ+UB4l9Ja+swIeeXTfyFUjtrSV1Hb Mt1jyhNSDg3fI/xKqdCPocb/CmYyU61CqN5q/3jKVB5H2LdS812ZRlZ1R57I/HbuXA alZ+axg3839rw== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , Wolfgang Grandegger , Marc Kleine-Budde , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Michael Turquette , Stephen Boyd , linux-can@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH RESEND v1 7/7] riscv: dts: microchip: add missing CAN bus clocks Date: Fri, 8 Dec 2023 17:12:29 +0000 Message-Id: <20231208-resample-selection-3c2c8cecc489@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231208-reenter-ajar-b6223e5134b3@spud> References: <20231208-reenter-ajar-b6223e5134b3@spud> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1347; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=RYPfJmYcs7V5ACe/34q2uMhx5X6TiyQw/MbNSCCgx2w=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDKnFfhWd25pCLOOPcTcWOnLsarjXMGNLbUqY/C/Nuy4uX ksOVJ3pKGVhEONgkBVTZEm83dcitf6Pyw7nnrcwc1iZQIYwcHEKwEQazzL84f1mHnxx+6Gvt77X 30v2q376f8XhnOeVFya7hUQJGGkFrmb4H/WOae21x1cDEzZY1l1xvbswMWRqwJp1er9vPps4sey TOzMA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C From: Conor Dooley The CAN controller on PolarFire SoC has an AHB peripheral clock _and_ a CAN bus clock. The bus clock was omitted when the binding was written, but is required for operation. Make up for lost time and add to the DT. Fixes: 38a71fc04895 ("riscv: dts: microchip: add mpfs's CAN controllers") Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 266489d43912..4d70df0f908c 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -416,7 +416,7 @@ i2c1: i2c@2010b000 { can0: can@2010c000 { compatible = "microchip,mpfs-can"; reg = <0x0 0x2010c000 0x0 0x1000>; - clocks = <&clkcfg CLK_CAN0>; + clocks = <&clkcfg CLK_CAN0>, <&clkcfg CLK_MSSPLL3>; interrupt-parent = <&plic>; interrupts = <56>; status = "disabled"; @@ -425,7 +425,7 @@ can0: can@2010c000 { can1: can@2010d000 { compatible = "microchip,mpfs-can"; reg = <0x0 0x2010d000 0x0 0x1000>; - clocks = <&clkcfg CLK_CAN1>; + clocks = <&clkcfg CLK_CAN1>, <&clkcfg CLK_MSSPLL3>; interrupt-parent = <&plic>; interrupts = <57>; status = "disabled";