From patchwork Fri Dec 8 00:44:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 751704 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="beMCmWRy" Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [IPv6:2a00:1450:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D31741710 for ; Thu, 7 Dec 2023 16:44:20 -0800 (PST) Received: by mail-lj1-x231.google.com with SMTP id 38308e7fff4ca-2c9f9db9567so16972721fa.3 for ; Thu, 07 Dec 2023 16:44:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701996259; x=1702601059; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QilGo2cKamjRbsFJs2rg0xLXZ8zR1vTxwGMlWkCLlFo=; b=beMCmWRyIp4ip+i3Kgt4V1/0XzGh1KZUftLk/Dp0uFrS5Q5TalWA7+IgpHEU9q6Ylz TdTskZ07Ae/5oUEsshTwZeG5IVe8UEX0JXiVr5+qCbF/TyHZqPjpfpu9VecxR8SD6S46 PDHblTg9D/xu/swnzZxbszcJee1B++Syhveir1tfQ8fe3ksoyPOm+bF/Owqzlbt6Nx4B W2kYvV9lMfIThK+G7WhndfV410Vbdppg4D5umDSGms7db26MPXf97dnMDs7W1Cq+LZB1 hga+wv6xMBIVV58dppmcfSDFKYV7CwIrel8B7OIG65Mm7NjnWOFT3O/7y4uWIxsYXxiH mcNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701996259; x=1702601059; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QilGo2cKamjRbsFJs2rg0xLXZ8zR1vTxwGMlWkCLlFo=; b=EAp8PecL0pvh8EMGT7OBNVP7bQiYo1bVQ7Y5YVSWE/Pa4R4Uf50uvEptQJjEqYZ587 Hy51gNSjNXlJqsVIOiNH0ulHLNXrBqI+cfCT6Wz1dg+bo96hJTBogwvPDuHo1zZCoT5B 6aLj/NWqld9HMfAZFKzq9yoNByWBK/zivkIxhYcWjqG8YcOes4zA42EGvvezPmMyo23W 986g5f+gO7KiqFqF1n0nfmNA9SYxwPXr2OJDbv5bvdmTLqQaU3wh2SluaamwbolGxx/3 G7N2mVKZLFwQ7/98nTUpuIkOZAuSvrkMe5RgB2N6lI3/MeAJx+aF+Nj3oyX8s+l1V20t xatA== X-Gm-Message-State: AOJu0YwgM2bBwErbLEK2zQoBVuIKWXR6LzrQ3UhIvQcu5Avy8jXSGFRA lmPJexWQhHWDlqCRymcPicH803/9Gxc3jGSBReU= X-Google-Smtp-Source: AGHT+IHGFM8aYwvSIyUYlKFiY7aIJ9Lc6/7HAd3Bf09+DJjIRY9YRRbIwND2zd2aPx8yIS4p/MsOIw== X-Received: by 2002:a2e:9f48:0:b0:2ca:1923:13a0 with SMTP id v8-20020a2e9f48000000b002ca192313a0mr1951201ljk.14.1701996258987; Thu, 07 Dec 2023 16:44:18 -0800 (PST) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id d1-20020a2eb041000000b002c9f2c7cdecsm82645ljl.22.2023.12.07.16.44.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Dec 2023 16:44:18 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring Subject: [PATCH v6 01/11] dt-bindings: soc: qcom: merge qcom,saw2.txt into qcom,spm.yaml Date: Fri, 8 Dec 2023 03:44:07 +0300 Message-Id: <20231208004417.3393299-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231208004417.3393299-1-dmitry.baryshkov@linaro.org> References: <20231208004417.3393299-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The Qualcomm SPM / SAW2 device is described in two bindigns files: arm/msm/qcom,saw2.txt and soc/qcom/qcom,spm.yaml. Merge the former into the latter, adding detailed device node description. While we are at it, also rename qcom,spm.yaml to qcom,saw2.yaml to follow the actual compatible used for these devices. The regulator property is retained as is. It will be changed in the later patches. Reviewed-by: Rob Herring Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/arm/msm/qcom,saw2.txt | 58 ------------------- .../qcom/{qcom,spm.yaml => qcom,saw2.yaml} | 26 +++++++-- 2 files changed, 20 insertions(+), 64 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt rename Documentation/devicetree/bindings/soc/qcom/{qcom,spm.yaml => qcom,saw2.yaml} (64%) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt deleted file mode 100644 index c0e3c3a42bea..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt +++ /dev/null @@ -1,58 +0,0 @@ -SPM AVS Wrapper 2 (SAW2) - -The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the -Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable -power-controller that transitions a piece of hardware (like a processor or -subsystem) into and out of low power modes via a direct connection to -the PMIC. It can also be wired up to interact with other processors in the -system, notifying them when a low power state is entered or exited. - -Multiple revisions of the SAW hardware are supported using these Device Nodes. -SAW2 revisions differ in the register offset and configuration data. Also, the -same revision of the SAW in different SoCs may have different configuration -data due the differences in hardware capabilities. Hence the SoC name, the -version of the SAW hardware in that SoC and the distinction between cpu (big -or Little) or cache, may be needed to uniquely identify the SAW register -configuration and initialization data. The compatible string is used to -indicate this parameter. - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: Must have - "qcom,saw2" - A more specific value could be one of: - "qcom,apq8064-saw2-v1.1-cpu" - "qcom,msm8226-saw2-v2.1-cpu" - "qcom,msm8974-saw2-v2.1-cpu" - "qcom,apq8084-saw2-v2.1-cpu" - -- reg: - Usage: required - Value type: - Definition: the first element specifies the base address and size of - the register region. An optional second element specifies - the base address and size of the alias register region. - -- regulator: - Usage: optional - Value type: boolean - Definition: Indicates that this SPM device acts as a regulator device - device for the core (CPU or Cache) the SPM is attached - to. - -Example 1: - - power-controller@2099000 { - compatible = "qcom,saw2"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - -Example 2: - saw0: power-controller@f9089000 { - compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml similarity index 64% rename from Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml rename to Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml index 20c8cd38ff0d..84b3f01d590c 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml @@ -1,18 +1,25 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/soc/qcom/qcom,spm.yaml# +$id: http://devicetree.org/schemas/soc/qcom/qcom,saw2.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Subsystem Power Manager +title: Qualcomm Subsystem Power Manager / SPM AVS Wrapper 2 (SAW2) maintainers: - Andy Gross - Bjorn Andersson description: | - This binding describes the Qualcomm Subsystem Power Manager, used to control - the peripheral logic surrounding the application cores in Qualcomm platforms. + The Qualcomm Subsystem Power Manager is used to control the peripheral logic + surrounding the application cores in Qualcomm platforms. + + The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the + Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable + power-controller that transitions a piece of hardware (like a processor or + subsystem) into and out of low power modes via a direct connection to + the PMIC. It can also be wired up to interact with other processors in the + system, notifying them when a low power state is entered or exited. properties: compatible: @@ -34,8 +41,15 @@ properties: - const: qcom,saw2 reg: - description: Base address and size of the SPM register region - maxItems: 1 + items: + - description: Base address and size of the SPM register region + - description: Base address and size of the alias register region + minItems: 1 + + regulator: + type: boolean + description: Indicates that this SPM device acts as a regulator device + device for the core (CPU or Cache) the SPM is attached to. required: - compatible From patchwork Fri Dec 8 00:44:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 751705 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="eb61o3P1" Received: from mail-lj1-x233.google.com (mail-lj1-x233.google.com [IPv6:2a00:1450:4864:20::233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 301C81713 for ; Thu, 7 Dec 2023 16:44:21 -0800 (PST) Received: by mail-lj1-x233.google.com with SMTP id 38308e7fff4ca-2c9f9db9567so16972811fa.3 for ; Thu, 07 Dec 2023 16:44:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701996259; x=1702601059; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ca1lCqRiuB+dn4eD6wRvmXrlOFXjwi+eXsVfOaPlfrY=; b=eb61o3P11+4hXCPfjAGjtVv/CxX5TePchhwBx/7zPho3UH2DRSit6wUQ9+4n/AtYk/ ik77Guv033ItRiYe4mOHc+Pi+5YSmo7md0hBDtllXXUCW5fKBdLVBeq438ZS9sH5Ndm0 5/5eSbdnEe2+Mhqd+VcTYSxSyS8IkQU3l8aZzOwkulNZ3vranqWQCfDUfUlZF8gf3FAK Cv7k+OiK1z0Q8zNicLfh9QjJBjMkVc8DO3o+Q9gJTRGo9C/KqiE0xMPtvQ2/hAf4piIn voAuzZluTN+RyEvdF/VmncMPbKnbgHmetzHvjPKw0dP6WS0LlTNkM6JxNAZQQns2unUq +QLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701996259; x=1702601059; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ca1lCqRiuB+dn4eD6wRvmXrlOFXjwi+eXsVfOaPlfrY=; b=nIKuU5iQ/0fep6O2os4u0H0K77bsTHkE1cr0symzAx0F8tQBu1zXhCKK1NUEaMrEg0 D3Q9ipubI4eqRTi3AlY0X74ySC8hG0znCvb6Pzq2tHsHpwFdhEriPfkLOYewtmJsf1wI FhXAeCxqvk6YxwI8xT4Zok/o6WJb1Imtc2EKVbARUdIAs0H+EJjxf41UHVejo4xc+osX q1hIuTA0Y9JBSr7UkgE0p0gMwH+PpMo3wLeVVSTtWRzzPlQTzAHVJqyutzUJJHkkqSrp CvXzws/g0IY0G5/VT+P/qUl1X7BpFGtJWqxMKM6pd2923CnhkptuEmFhiFvrkS4B+M6q /mEQ== X-Gm-Message-State: AOJu0YzOjCAMkkc+mKV71U/QnMKj0JVyAts0cP1cuA8vMR9JPowZKjga Ey4osgxQMzrYrJ1M1K3WoUfcLg== X-Google-Smtp-Source: AGHT+IEFazNrnvYA5a3Guuj3KHXNNT/+RZQ+KRsB3cEPCIUHghag79B7oCAMRCi4Bxov3H1KQll3jw== X-Received: by 2002:a2e:a40c:0:b0:2c9:fa34:332d with SMTP id p12-20020a2ea40c000000b002c9fa34332dmr1967525ljn.12.1701996259568; Thu, 07 Dec 2023 16:44:19 -0800 (PST) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id d1-20020a2eb041000000b002c9f2c7cdecsm82645ljl.22.2023.12.07.16.44.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Dec 2023 16:44:19 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Rob Herring Subject: [PATCH v6 02/11] dt-bindings: soc: qcom: qcom,saw2: define optional regulator node Date: Fri, 8 Dec 2023 03:44:08 +0300 Message-Id: <20231208004417.3393299-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231208004417.3393299-1-dmitry.baryshkov@linaro.org> References: <20231208004417.3393299-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The SAW2 device can optionally provide a voltage regulator supplying the CPU core, cluster or L2 cache. Change the boolean 'regulator' property into a proper regulator description. This breaks schema compatibility for the sake of properly describing the regulator. Reviewed-by: Rob Herring Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/soc/qcom/qcom,saw2.yaml | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml index 84b3f01d590c..a2d871ba8c45 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml @@ -47,7 +47,7 @@ properties: minItems: 1 regulator: - type: boolean + $ref: /schemas/regulator/regulator.yaml# description: Indicates that this SPM device acts as a regulator device device for the core (CPU or Cache) the SPM is attached to. @@ -96,4 +96,17 @@ examples: reg = <0x17912000 0x1000>; }; + - | + /* + * Example 3: SAW2 with the bundled regulator definition. + */ + power-manager@2089000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; + + regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; + }; ... 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The CPUidle driver doesn't use them at all. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/soc/qcom/spm.c | 20 ++++++++++++++++++++ include/soc/qcom/spm.h | 23 +---------------------- 2 files changed, 21 insertions(+), 22 deletions(-) diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c index 2f0b1bfe7658..b15435f7cb0d 100644 --- a/drivers/soc/qcom/spm.c +++ b/drivers/soc/qcom/spm.c @@ -36,6 +36,26 @@ enum spm_reg { SPM_REG_NR, }; +#define MAX_PMIC_DATA 2 +#define MAX_SEQ_DATA 64 + +struct spm_reg_data { + const u16 *reg_offset; + u32 spm_cfg; + u32 spm_dly; + u32 pmic_dly; + u32 pmic_data[MAX_PMIC_DATA]; + u32 avs_ctl; + u32 avs_limit; + u8 seq[MAX_SEQ_DATA]; + u8 start_index[PM_SLEEP_MODE_NR]; +}; + +struct spm_driver_data { + void __iomem *reg_base; + const struct spm_reg_data *reg_data; +}; + static const u16 spm_reg_offset_v4_1[SPM_REG_NR] = { [SPM_REG_AVS_CTL] = 0x904, [SPM_REG_AVS_LIMIT] = 0x908, diff --git a/include/soc/qcom/spm.h b/include/soc/qcom/spm.h index 4951f9d8b0bd..5b263c685812 100644 --- a/include/soc/qcom/spm.h +++ b/include/soc/qcom/spm.h @@ -7,11 +7,6 @@ #ifndef __SPM_H__ #define __SPM_H__ -#include - -#define MAX_PMIC_DATA 2 -#define MAX_SEQ_DATA 64 - enum pm_sleep_mode { PM_SLEEP_MODE_STBY, PM_SLEEP_MODE_RET, @@ -20,23 +15,7 @@ enum pm_sleep_mode { PM_SLEEP_MODE_NR, }; -struct spm_reg_data { - const u16 *reg_offset; - u32 spm_cfg; - u32 spm_dly; - u32 pmic_dly; - u32 pmic_data[MAX_PMIC_DATA]; - u32 avs_ctl; - u32 avs_limit; - u8 seq[MAX_SEQ_DATA]; - u8 start_index[PM_SLEEP_MODE_NR]; -}; - -struct spm_driver_data { - void __iomem *reg_base; - const struct spm_reg_data *reg_data; -}; - +struct spm_driver_data; void spm_set_low_power_mode(struct spm_driver_data *drv, enum pm_sleep_mode mode); From patchwork Fri Dec 8 00:44:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 751703 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="sPRabcSP" Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9FF8C1720 for ; Thu, 7 Dec 2023 16:44:22 -0800 (PST) Received: by mail-lj1-x22e.google.com with SMTP id 38308e7fff4ca-2c9f72176cfso18335381fa.2 for ; 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The exact register sequence and voltage ranges differs from device to device. Signed-off-by: Dmitry Baryshkov --- drivers/soc/qcom/spm.c | 234 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 229 insertions(+), 5 deletions(-) diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c index b15435f7cb0d..5eefaec72a13 100644 --- a/drivers/soc/qcom/spm.c +++ b/drivers/soc/qcom/spm.c @@ -6,20 +6,40 @@ * SAW power controller driver */ -#include +#include +#include #include #include +#include +#include +#include #include -#include #include -#include #include +#include +#include + +#include + #include +#define FIELD_SET(current, mask, val) \ + (((current) & ~(mask)) | FIELD_PREP((mask), (val))) + #define SPM_CTL_INDEX 0x7f #define SPM_CTL_INDEX_SHIFT 4 #define SPM_CTL_EN BIT(0) +/* These registers might be specific to SPM 1.1 */ +#define SPM_VCTL_VLVL GENMASK(7, 0) +#define SPM_PMIC_DATA_0_VLVL GENMASK(7, 0) +#define SPM_PMIC_DATA_1_MIN_VSEL GENMASK(5, 0) +#define SPM_PMIC_DATA_1_MAX_VSEL GENMASK(21, 16) + +#define SPM_1_1_AVS_CTL_AVS_ENABLED BIT(27) +#define SPM_AVS_CTL_MAX_VLVL GENMASK(22, 17) +#define SPM_AVS_CTL_MIN_VLVL GENMASK(15, 10) + enum spm_reg { SPM_REG_CFG, SPM_REG_SPM_CTL, @@ -29,10 +49,12 @@ enum spm_reg { SPM_REG_PMIC_DATA_1, SPM_REG_VCTL, SPM_REG_SEQ_ENTRY, - SPM_REG_SPM_STS, + SPM_REG_STS0, + SPM_REG_STS1, SPM_REG_PMIC_STS, SPM_REG_AVS_CTL, SPM_REG_AVS_LIMIT, + SPM_REG_RST, SPM_REG_NR, }; @@ -49,11 +71,20 @@ struct spm_reg_data { u32 avs_limit; u8 seq[MAX_SEQ_DATA]; u8 start_index[PM_SLEEP_MODE_NR]; + + smp_call_func_t set_vdd; + /* for now we support only a single range */ + struct linear_range *range; + unsigned int ramp_delay; + unsigned int init_uV; }; struct spm_driver_data { void __iomem *reg_base; const struct spm_reg_data *reg_data; + struct device *dev; + unsigned int volt_sel; + int reg_cpu; }; static const u16 spm_reg_offset_v4_1[SPM_REG_NR] = { @@ -189,6 +220,10 @@ static const struct spm_reg_data spm_reg_8226_cpu = { static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = { [SPM_REG_CFG] = 0x08, + [SPM_REG_STS0] = 0x0c, + [SPM_REG_STS1] = 0x10, + [SPM_REG_VCTL] = 0x14, + [SPM_REG_AVS_CTL] = 0x18, [SPM_REG_SPM_CTL] = 0x20, [SPM_REG_PMIC_DLY] = 0x24, [SPM_REG_PMIC_DATA_0] = 0x28, @@ -196,7 +231,12 @@ static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = { [SPM_REG_SEQ_ENTRY] = 0x80, }; +static void smp_set_vdd_v1_1(void *data); + /* SPM register data for 8064 */ +static struct linear_range spm_v1_1_regulator_range = + REGULATOR_LINEAR_RANGE(700000, 0, 56, 12500); + static const struct spm_reg_data spm_reg_8064_cpu = { .reg_offset = spm_reg_offset_v1_1, .spm_cfg = 0x1F, @@ -207,6 +247,10 @@ static const struct spm_reg_data spm_reg_8064_cpu = { 0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F }, .start_index[PM_SLEEP_MODE_STBY] = 0, .start_index[PM_SLEEP_MODE_SPC] = 2, + .set_vdd = smp_set_vdd_v1_1, + .range = &spm_v1_1_regulator_range, + .init_uV = 1300000, + .ramp_delay = 1250, }; static inline void spm_register_write(struct spm_driver_data *drv, @@ -258,6 +302,185 @@ void spm_set_low_power_mode(struct spm_driver_data *drv, spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val); } +static int spm_set_voltage_sel(struct regulator_dev *rdev, unsigned int selector) +{ + struct spm_driver_data *drv = rdev_get_drvdata(rdev); + + drv->volt_sel = selector; + + /* Always do the SAW register writes on the corresponding CPU */ + return smp_call_function_single(drv->reg_cpu, drv->reg_data->set_vdd, drv, true); +} + +static int spm_get_voltage_sel(struct regulator_dev *rdev) +{ + struct spm_driver_data *drv = rdev_get_drvdata(rdev); + + return drv->volt_sel; +} + +static const struct regulator_ops spm_reg_ops = { + .set_voltage_sel = spm_set_voltage_sel, + .get_voltage_sel = spm_get_voltage_sel, + .list_voltage = regulator_list_voltage_linear_range, + .set_voltage_time_sel = regulator_set_voltage_time_sel, +}; + +static void smp_set_vdd_v1_1(void *data) +{ + struct spm_driver_data *drv = data; + unsigned int vctl, data0, data1, avs_ctl, sts; + unsigned int vlevel, volt_sel; + bool avs_enabled; + + volt_sel = drv->volt_sel; + vlevel = volt_sel | 0x80; /* band */ + + avs_ctl = spm_register_read(drv, SPM_REG_AVS_CTL); + vctl = spm_register_read(drv, SPM_REG_VCTL); + data0 = spm_register_read(drv, SPM_REG_PMIC_DATA_0); + data1 = spm_register_read(drv, SPM_REG_PMIC_DATA_1); + + avs_enabled = avs_ctl & SPM_1_1_AVS_CTL_AVS_ENABLED; + + /* If AVS is enabled, switch it off during the voltage change */ + if (avs_enabled) { + avs_ctl &= ~SPM_1_1_AVS_CTL_AVS_ENABLED; + spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl); + } + + /* Kick the state machine back to idle */ + spm_register_write(drv, SPM_REG_RST, 1); + + vctl = FIELD_SET(vctl, SPM_VCTL_VLVL, vlevel); + data0 = FIELD_SET(data0, SPM_PMIC_DATA_0_VLVL, vlevel); + data1 = FIELD_SET(data1, SPM_PMIC_DATA_1_MIN_VSEL, volt_sel); + data1 = FIELD_SET(data1, SPM_PMIC_DATA_1_MAX_VSEL, volt_sel); + + spm_register_write(drv, SPM_REG_VCTL, vctl); + spm_register_write(drv, SPM_REG_PMIC_DATA_0, data0); + spm_register_write(drv, SPM_REG_PMIC_DATA_1, data1); + + if (read_poll_timeout_atomic(spm_register_read, + sts, sts == vlevel, + 1, 200, false, + drv, SPM_REG_STS1)) { + dev_err_ratelimited(drv->dev, "timeout setting the voltage (%x %x)!\n", sts, vlevel); + goto enable_avs; + } + + if (avs_enabled) { + unsigned int max_avs = volt_sel; + unsigned int min_avs = max(max_avs, 4U) - 4; + + avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MIN_VLVL, min_avs); + avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MAX_VLVL, max_avs); + spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl); + } + +enable_avs: + if (avs_enabled) { + avs_ctl |= SPM_1_1_AVS_CTL_AVS_ENABLED; + spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl); + } +} + +static int spm_get_cpu(struct device *dev) +{ + int cpu; + bool found; + + for_each_possible_cpu(cpu) { + struct device_node *cpu_node, *saw_node; + + cpu_node = of_cpu_device_node_get(cpu); + if (!cpu_node) + continue; + + saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0); + found = (saw_node == dev->of_node); + of_node_put(saw_node); + of_node_put(cpu_node); + + if (found) + return cpu; + } + + /* L2 SPM is not bound to any CPU, voltage setting is not supported */ + + return -EOPNOTSUPP; +} + +#ifdef CONFIG_REGULATOR +static int spm_register_regulator(struct device *dev, struct spm_driver_data *drv) +{ + struct regulator_config config = { + .dev = dev, + .driver_data = drv, + }; + struct regulator_desc *rdesc; + struct regulator_dev *rdev; + int ret; + bool found; + + if (!drv->reg_data->set_vdd) + return 0; + + rdesc = devm_kzalloc(dev, sizeof(*rdesc), GFP_KERNEL); + if (!rdesc) + return -ENOMEM; + + rdesc->name = "spm"; + rdesc->of_match = of_match_ptr("regulator"); + rdesc->type = REGULATOR_VOLTAGE; + rdesc->owner = THIS_MODULE; + rdesc->ops = &spm_reg_ops; + + rdesc->linear_ranges = drv->reg_data->range; + rdesc->n_linear_ranges = 1; + rdesc->n_voltages = rdesc->linear_ranges[rdesc->n_linear_ranges - 1].max_sel + 1; + rdesc->ramp_delay = drv->reg_data->ramp_delay; + + ret = spm_get_cpu(dev); + if (ret < 0) + return ret; + + drv->reg_cpu = ret; + dev_dbg(dev, "SAW2 bound to CPU %d\n", drv->reg_cpu); + + /* + * Program initial voltage, otherwise registration will also try + * setting the voltage, which might result in undervolting the CPU. + */ + drv->volt_sel = DIV_ROUND_UP(drv->reg_data->init_uV - rdesc->min_uV, + rdesc->uV_step); + ret = linear_range_get_selector_high(drv->reg_data->range, + drv->reg_data->init_uV, + &drv->volt_sel, + &found); + if (ret) { + dev_err(dev, "Initial uV value out of bounds\n"); + return ret; + } + + /* Always do the SAW register writes on the corresponding CPU */ + smp_call_function_single(drv->reg_cpu, drv->reg_data->set_vdd, drv, true); + + rdev = devm_regulator_register(dev, rdesc, &config); + if (IS_ERR(rdev)) { + dev_err(dev, "failed to register regulator\n"); + return PTR_ERR(rdev); + } + + return 0; +} +#else +static int spm_register_regulator(struct device *dev, struct spm_driver_data *drv) +{ + return 0; +} +#endif + static const struct of_device_id spm_match_table[] = { { .compatible = "qcom,sdm660-gold-saw2-v4.1-l2", .data = &spm_reg_660_gold_l2 }, @@ -308,6 +531,7 @@ static int spm_dev_probe(struct platform_device *pdev) return -ENODEV; drv->reg_data = match_id->data; + drv->dev = &pdev->dev; platform_set_drvdata(pdev, drv); /* Write the SPM sequences first.. */ @@ -335,7 +559,7 @@ static int spm_dev_probe(struct platform_device *pdev) if (drv->reg_data->reg_offset[SPM_REG_SPM_CTL]) spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY); - return 0; + return spm_register_regulator(&pdev->dev, drv); } static struct platform_driver spm_driver = { From patchwork Fri Dec 8 00:44:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 752358 Authentication-Results: smtp.subspace.kernel.org; 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Thu, 07 Dec 2023 16:44:21 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 05/11] ARM: dts: qcom: apq8064: rename SAW nodes to power-manager Date: Fri, 8 Dec 2023 03:44:11 +0300 Message-Id: <20231208004417.3393299-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231208004417.3393299-1-dmitry.baryshkov@linaro.org> References: <20231208004417.3393299-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Per the power-domain.yaml, the power-controller node name is reserved for power-domain providers. Rename SAW2 nodes to 'power-manager', the name which is suggested by qcom,spm.yaml Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 95ac25e1a3b4..6832030c2c88 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -365,25 +365,25 @@ acc3: clock-controller@20b8000 { #clock-cells = <0>; }; - saw0: power-controller@2089000 { + saw0: power-manager@2089000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw1: power-controller@2099000 { + saw1: power-manager@2099000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw2: power-controller@20a9000 { + saw2: power-manager@20a9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw3: power-controller@20b9000 { + saw3: power-manager@20b9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; regulator; From patchwork Fri Dec 8 00:44:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 751702 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Xk/EcsOz" Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E430510DE for ; Thu, 7 Dec 2023 16:44:23 -0800 (PST) Received: by mail-lj1-x22a.google.com with SMTP id 38308e7fff4ca-2ca00dffc23so18066701fa.2 for ; Thu, 07 Dec 2023 16:44:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701996262; x=1702601062; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ofurekj2GsV9pEulhYImkibXZVuPtz//iePjOLcLr1Y=; b=Xk/EcsOzmwLaWyUXy8IOqAO/7ENgqfkiovtHGfgplXx/MJAzTveSl0JOz4Ne0/dW+5 i7rNCZHEMx11uYys4pAqWpLb/WqZJKdKkNo3NhN21KzBZtJ75MuP8TZKPHyWTaaKk9Zt fx7hwzdL8oCX2ugkthdS6yet0zedJlohSXb4ldGvbYxG+GwkE/OWPGKTfMurZSdgYoME dszWZvwXztkNugvL71IKpqUQzqxOVp7tCMWjpDzL7LD4TzjzXNgHRN2dBpqkfRvWzcFE 1nLlv0JM7MSfJqq4iWI/bSKHdWI9fn7GyIh1LHn1a5OIk787oF9O/p70/LD7kjfyeviT qf3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701996262; x=1702601062; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ofurekj2GsV9pEulhYImkibXZVuPtz//iePjOLcLr1Y=; b=tyPyI+CY5SJtxwtZYI3QkomVF5faVWFZL8XeuK/oxZL9dC0IF0EtaElbvydSAsgrOW s6iEC3JAPba0pSTOpQkyFPawa8y7F4AXMtIn/iHIC0GefGxxt606eVgvrUV0mIW/su3i Csb1Ugj/s35knGpbXn1g4B0Fcp19Ux7aGr5OP4rFD4HS/A+ChdeWCHgt+n3jJnRRvk+l c/dfaDEXMkgFALEE8aJsdm3Q+nw4gyOFg8YlWE92/zvSgg/JQl6LMqVNpfvcZDOPgdNO zXiqq+I3WtoqAFc4AgiXe6eKj3hE91OwzDbJcuJ44f0LAo8zaiNUXcwtu+COcOurg673 NnlQ== X-Gm-Message-State: AOJu0YwIJ/t9xA3fm/rwHEod82RP8UmGHcT5DeJ4RaqmGFJJnLEmdxoW K32UTicvZ0TiQoZe0i4VS/+lhw== X-Google-Smtp-Source: AGHT+IEBki9ttzCfRNVVwIMSzeAndy7rLC9U4cqS870qRJL6yRAoMlY2KMPJWYfS5uxq8AePiNMjuQ== X-Received: by 2002:a2e:700b:0:b0:2ca:3591:6667 with SMTP id l11-20020a2e700b000000b002ca35916667mr724880ljc.82.1701996262324; Thu, 07 Dec 2023 16:44:22 -0800 (PST) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id d1-20020a2eb041000000b002c9f2c7cdecsm82645ljl.22.2023.12.07.16.44.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Dec 2023 16:44:21 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 06/11] ARM: dts: qcom: apq8064: declare SAW2 regulators Date: Fri, 8 Dec 2023 03:44:12 +0300 Message-Id: <20231208004417.3393299-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231208004417.3393299-1-dmitry.baryshkov@linaro.org> References: <20231208004417.3393299-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The SAW2 (SPM and AVS Wrapper) among other things is yet another way to handle CPU-related PMIC regulators. Provide a way to control voltage of these regulators. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 6832030c2c88..44c65ebf6c73 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -368,25 +368,41 @@ acc3: clock-controller@20b8000 { saw0: power-manager@2089000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw0_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; saw1: power-manager@2099000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw1_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; saw2: power-manager@20a9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw2_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; saw3: power-manager@20b9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw3_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; sps_sic_non_secure: sps-sic-non-secure@12100000 { From patchwork Fri Dec 8 00:44:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 752356 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ZuGB66Er" Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7B3FB1724 for ; Thu, 7 Dec 2023 16:44:24 -0800 (PST) Received: by mail-lj1-x234.google.com with SMTP id 38308e7fff4ca-2ca02def690so18086481fa.3 for ; Thu, 07 Dec 2023 16:44:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701996263; x=1702601063; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tRH0ltu/8xOeCYgi26zDqsTtGrYZ67tsC2xGcsHS4PY=; b=ZuGB66Erbwu7e2NdgoM4TcEDf0RobP0fogwVYjJ4twA+I7eugTTZP1Edmu0ZXzgDtl 32U61LV++2Aa0uZmvDfhTTeIW2qfg4ONxHeZqSZE398u4eJ6ChkS905pFmAJzUTfMLfC xjtx3zT/Lo3lPIs1vOHExr2/c6PrFStNE0AqtqOJuz3pt+GYB2Sv/YLPTtgw9TVYFP/4 LK71TJ++vcMjjsN41IXqoqu81BFlHiOErRMORonvkSiT3a2X2DgvO5DXuZmJDo6lSwsI yIWy2hmTatuOeZIQVHzFYoeloSXf2ApkpdWDff8CPVQhcfVYKIMgVFwofFrRV2spqZxX Ae3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701996263; x=1702601063; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tRH0ltu/8xOeCYgi26zDqsTtGrYZ67tsC2xGcsHS4PY=; b=xAQEQKeVwz4uV06Bz4AodEuNciEF0ZbENgvXqYDiUvnhKC79DYu8/eZhMNi6eQQ0LR xuk3n4nTk6L0i3k2xDPK4kqYeJssFZ9zjGfVMbcJ1+yvzaNt/vkPE+NeZySSI86lxPVI zhlNggZlsDgTCLNgu74PUjry71+l5YYycYBCjMIdrdkFqnBTrOuUzfEF+1MAK0BlP4hv VYL4+YNcJ+52QdpJR43QNah3IChHv/t1JtRIP+3ywK8KStEfHhU6JWCoUlmw87xrlsqm FS6DnBytm++Hjfh1ZxeMwcpLN2Wh+BBUwgjGjd7UNeTC5mImXL1ifANIWTlxG2W6xa62 Msfw== X-Gm-Message-State: AOJu0YyivuWcNjwov8b6RKT9UX8ftnBV/RPydc/dMP5HHF3RUZi4MppS 5i7bRf9m/HIquRkCuqSThJ5UyytpfupEN5I+60g= X-Google-Smtp-Source: AGHT+IHwybtxoLl4yQz0bsTFhOLvQQldFboYc0ShfFu2bASqXKvHxCiansYhsBkwtWa9B9cKK1N46w== X-Received: by 2002:a2e:808a:0:b0:2ca:1ddf:cbf5 with SMTP id i10-20020a2e808a000000b002ca1ddfcbf5mr2116960ljg.36.1701996262916; Thu, 07 Dec 2023 16:44:22 -0800 (PST) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id d1-20020a2eb041000000b002c9f2c7cdecsm82645ljl.22.2023.12.07.16.44.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Dec 2023 16:44:22 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 07/11] ARM: dts: qcom: msm8960: declare SAW2 regulators Date: Fri, 8 Dec 2023 03:44:13 +0300 Message-Id: <20231208004417.3393299-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231208004417.3393299-1-dmitry.baryshkov@linaro.org> References: <20231208004417.3393299-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The SAW2 (SPM and AVS Wrapper) among other things is yet another way to handle CPU-related PMIC regulators. Provide a way to control voltage of these regulators. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index f420740e068e..0ab340405784 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -223,13 +223,21 @@ acc1: clock-controller@2098000 { saw0: regulator@2089000 { compatible = "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw0_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; saw1: regulator@2099000 { compatible = "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw1_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; gsbi5: gsbi@16400000 { From patchwork Fri Dec 8 00:44:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 752357 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="G55mQKy3" Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 358EE1728 for ; Thu, 7 Dec 2023 16:44:25 -0800 (PST) Received: by mail-lj1-x236.google.com with SMTP id 38308e7fff4ca-2ca0715f0faso20601481fa.0 for ; Thu, 07 Dec 2023 16:44:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701996263; x=1702601063; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uwm1Y1yKYRC2h+rKhVRBCueR16O0EXSdEm7pH6xao2g=; b=G55mQKy3UBjZmpOuxIMW1qs/CAb3Z4m7pvDMTahJ8MTLFrtQ4DE/oR7ge+s8b78OGP w/xMX5yzINAv3oPxsyXLEuMgsjnSuffYoT2bwow6chfSgecEW9PaKhHD52QEFIgaQRzU CbCFNBVKCFqkpl0xBDoke801M5mP6OAVD4pAkcrTcyFUeE8QYh4OXRiu1tec/e+09nbh ptyOo16/QbYY+i8BSR/XZFM0tG+i/DZixrzf2JECy2zIcvX8iihnmkuNslIEiKX62rIc 15tPyOdk/8VloDzcBGc0tcB89u97deQiJMDx86SmD0++g3oYtjiuvQIPTTznP39U4v6o KIfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701996263; x=1702601063; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uwm1Y1yKYRC2h+rKhVRBCueR16O0EXSdEm7pH6xao2g=; b=JtFmbbh3jmTG32P2G5rswQp1gD+Jt7RdlOEqSA2HLOF4uDHmuP7gErVVyR97qTn4tA iUxxdR1ThvS9r0v4mCgFADogApitWh/Qc2OUNQjDF+ct/guhhNX66kSm9Mjc+/wYo2ta RANWacccNthxmmXtkrbruh9hYEY7tiQupx8jQR2Iq45E6b4AQDbaudUj4dtsXIyoM9s3 dgNrHc1KP7EzHbcurbnb6ydgbckaKsZrVxzE1T/y9u4C6vjQb4QR7ijP/RPChmbB1Q24 7ZfltoVlcMiuCktWLyx/Jd84pdv4x/wPrzSwkqA2o/Mis58ei/4oadZaH+j7Zh7ERtgB mkQQ== X-Gm-Message-State: AOJu0YzN8V8mNw7hem1Znv+LfSvkatLWj47VkulroEVVhhZIhx4XdYlM BLuvDM7YXP/NweYao9OpB2sGtA== X-Google-Smtp-Source: AGHT+IHUefP4Jrg94iDnLS0stHHgDvD4HNy/qj0dUGqx4NW4/IAk1u/17g711mCa/ZXkgaoWRe+MzQ== X-Received: by 2002:a2e:9847:0:b0:2c9:f71f:c00f with SMTP id e7-20020a2e9847000000b002c9f71fc00fmr1738750ljj.30.1701996263530; Thu, 07 Dec 2023 16:44:23 -0800 (PST) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id d1-20020a2eb041000000b002c9f2c7cdecsm82645ljl.22.2023.12.07.16.44.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Dec 2023 16:44:23 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 08/11] ARM: dts: qcom: apq8084: drop 'regulator' property from SAW2 device Date: Fri, 8 Dec 2023 03:44:14 +0300 Message-Id: <20231208004417.3393299-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231208004417.3393299-1-dmitry.baryshkov@linaro.org> References: <20231208004417.3393299-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The SAW2 device should describe the regulator constraints rather than just declaring that it has the regulator. Drop the 'regulator' property. If/when CPU voltage scaling is implemented for this platform, proper regulator node show be added instead. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-apq8084.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi index 2b1f9d0fb510..24bc2cbfbd96 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi @@ -652,7 +652,6 @@ saw3: power-controller@f90b9000 { saw_l2: power-controller@f9012000 { compatible = "qcom,saw2"; reg = <0xf9012000 0x1000>; - regulator; }; acc0: power-manager@f9088000 { From patchwork Fri Dec 8 00:44:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 751701 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="dXh0XOCK" Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB53E10F1 for ; Thu, 7 Dec 2023 16:44:25 -0800 (PST) Received: by mail-lj1-x22f.google.com with SMTP id 38308e7fff4ca-2c9c18e7990so20426031fa.2 for ; Thu, 07 Dec 2023 16:44:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701996264; x=1702601064; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=o0J8cjOv5k8AIvIFhvZ5YWOKOlem3yXviyX9wh+j9fA=; b=dXh0XOCKyw8w0dFTSjYKRx1lZ/m5UjO4RkKPZrcaGAD5QDwIuH2rYd3BA/wNArl/5g v+H5LvXSSba24m11Ozewk/QXbF3FrCXJFSa2DQ+wz0yXmrz1rRutLldl9yFjcbJyQa6E 2YnqZjjZexPT1CKZWS4MPqckZ0Z+/Owv6zbKtTK6jJE5TEtlaUnE07oSt8MOVwLzo+vu P0TiEmjPynPsUI/+JjNOPNjafAt3UfWNHHACphwhs796wdlQs4+0CaMT09J8HIsJyvFz IAIAASM/552vAuwqkDfKDls1NjKiFvKGFtcm925J+NCZsCY+ut2jND7om0m4h95ZcuWF 8zmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701996264; x=1702601064; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=o0J8cjOv5k8AIvIFhvZ5YWOKOlem3yXviyX9wh+j9fA=; b=CBEqKdndOzIfSB1Ajl6K+hFoyUa4mqtoPjlKX+U+SY09EhGYIRppvvBmfz1q+tUto5 uPCkUiEH2kareTlLq+EnNGy7vJzbpWZoLy/OVzLwLj2qTZZP21HP+ObVVZ50A9MVGSw7 rTT5HPVYf9uM5UCesKUUyh/89PgtVjqthxREXUmwuEqI1o84/zwuZjLBm6BjI3O6j6Ve hjuveg+3H0Wt+D/oF9pfYkteiRnZX91E/FMbJPCtnv3Ct/ncoWMGh5O9qvi2ZfVrXjia 0+KQYQm0VWJPQPxm0Bxu3hfsErJ8w8UVgupbtNwCA8Vb9UBjLzVNfdoAsfvPe/H4hIb6 4QuQ== X-Gm-Message-State: AOJu0YyG3QwNgZiJtRTZjE8iJUZOWxlm1BuyifBFPM15SspzR0FXpBty XjsAlPd/sa7a48eXrurLQjx3hw== X-Google-Smtp-Source: AGHT+IGYu+cg77dg5gaAt49n8XWkheQjTjDEp7wT2CxZ4HVGA8RukUV5/g6B4yxBqBXBtUe0cnCuaw== X-Received: by 2002:a2e:a410:0:b0:2ca:1009:7afe with SMTP id p16-20020a2ea410000000b002ca10097afemr1825777ljn.60.1701996264333; Thu, 07 Dec 2023 16:44:24 -0800 (PST) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id d1-20020a2eb041000000b002c9f2c7cdecsm82645ljl.22.2023.12.07.16.44.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Dec 2023 16:44:23 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 09/11] ARM: dts: qcom: msm8974: drop 'regulator' property from SAW2 device Date: Fri, 8 Dec 2023 03:44:15 +0300 Message-Id: <20231208004417.3393299-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231208004417.3393299-1-dmitry.baryshkov@linaro.org> References: <20231208004417.3393299-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The SAW2 device should describe the regulator constraints rather than just declaring that it has the regulator. Drop the 'regulator' property. If/when CPU voltage scaling is implemented for this platform, proper regulator node show be added instead. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index ee202f3f161e..3e1e88d69c2e 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -349,7 +349,6 @@ apcs: syscon@f9011000 { saw_l2: power-controller@f9012000 { compatible = "qcom,saw2"; reg = <0xf9012000 0x1000>; - regulator; }; watchdog@f9017000 { From patchwork Fri Dec 8 00:44:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 752355 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="r7UxQK7S" Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C498F171E for ; Thu, 7 Dec 2023 16:44:26 -0800 (PST) Received: by mail-lj1-x236.google.com with SMTP id 38308e7fff4ca-2c9f7fe6623so18014961fa.3 for ; Thu, 07 Dec 2023 16:44:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701996265; x=1702601065; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/WTwDERDtHj3CTZ7wFbbvBEJPnjqFeRCht0k5iEHuFc=; b=r7UxQK7S39mIyGi8ZGc/XCH0LTv90ROFcm/vzWC97qLiRvAWfcfk9/VjM9plD+aDy/ qkZatxaW/kNY/RVt7eGg83KfNOME1QY28v5s8d9cah/AtX0Pze3IfHtpKYWboODtY9aV 6lTNpiB22nu6JJBR8fWJyD7wfEKj8sHYnC6Cxn28DN58lKvQEaUhJVoQ4wK8FRiDABn2 5lAMnhD0qLgNGA3LNCPCGgxejn4fdpHorVcfeVsgKvcTSm/H4fzWT1l8llphbYHErE7I 9SYF7D1FVrjNGbCciZWhuF5xZWIXb5NJ3AGKeJiRtQ8gFkOQQ+uxFUSmRFha+H8LLaNd 6foA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701996265; x=1702601065; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/WTwDERDtHj3CTZ7wFbbvBEJPnjqFeRCht0k5iEHuFc=; b=R43g3GxwZFTqHHBFBA6PAvf+3/Vb2LqsWdM9vqSclmHqI7Z4/Br/7OTWSxfgTA+wKn S5FKyGL78eBch+X6FsXMH5mBSFp4OVN71SfnejIirE2iKl0n4QNBPuXWjmT2Pyo/g+Aj 3tTpKH2T0BTqi/EwXi4WkipC+WRzToDYgTc5ZAt72x6iya8H0XmrK6vuHDP6OrbBt1u9 W5xsSA/dFBMvLyofkXfYlWz3LBWRZSKi4KwO6/+qiKU7JQvAy/VJw004arRZSdbOxugU Zaw7p6Jq8rwCMv5qdVbiwW6tEhc6x27SQUvNshU78odcAO8nViUJVUfVt4gNG0AaQYmt DlNg== X-Gm-Message-State: AOJu0Ywm/aCgBU21THh58jSi7sgOcEgBRIJOhaT3Ez9q1hV99xOL/V0f 3HJLwBhnwbd5YDqLt0Vq6DzJNA== X-Google-Smtp-Source: AGHT+IGO+O/Dh1t5pJH2yLuU8I982uAcr7rj19scL1UU5jVVmx2oU9Ztp/hjMOUeeAYWbsJR1/WXqQ== X-Received: by 2002:a2e:80d9:0:b0:2c9:fa32:4261 with SMTP id r25-20020a2e80d9000000b002c9fa324261mr1390118ljg.60.1701996265060; Thu, 07 Dec 2023 16:44:25 -0800 (PST) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id d1-20020a2eb041000000b002c9f2c7cdecsm82645ljl.22.2023.12.07.16.44.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Dec 2023 16:44:24 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 10/11] ARM: dts: qcom: ipq4019: drop 'regulator' property from SAW2 devices Date: Fri, 8 Dec 2023 03:44:16 +0300 Message-Id: <20231208004417.3393299-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231208004417.3393299-1-dmitry.baryshkov@linaro.org> References: <20231208004417.3393299-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The SAW2 device should describe the regulator constraints rather than just declaring that it has the regulator. Drop the 'regulator' property. If/when CPU voltage scaling is implemented for this platform, proper regulator nodes show be added instead. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index 9844e0b7cff9..d7bd97997ff9 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -353,31 +353,26 @@ acc3: power-manager@b0b8000 { saw0: regulator@b089000 { compatible = "qcom,saw2"; reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>; - regulator; }; saw1: regulator@b099000 { compatible = "qcom,saw2"; reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; - regulator; }; saw2: regulator@b0a9000 { compatible = "qcom,saw2"; reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; - regulator; }; saw3: regulator@b0b9000 { compatible = "qcom,saw2"; reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; - regulator; }; saw_l2: regulator@b012000 { compatible = "qcom,saw2"; reg = <0xb012000 0x1000>; - regulator; }; blsp1_uart1: serial@78af000 { From patchwork Fri Dec 8 00:44:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 751700 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="gx81vl4m" Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 69E07172A for ; Thu, 7 Dec 2023 16:44:27 -0800 (PST) Received: by mail-lj1-x232.google.com with SMTP id 38308e7fff4ca-2c9fdf53abcso13938881fa.1 for ; Thu, 07 Dec 2023 16:44:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1701996265; x=1702601065; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Rzx9Bm824S2wRWYFO7S2MdJvHvf/jzSVekqRFumNr7k=; b=gx81vl4mbnjYuvyTzPM8r+NXJe1fKk7JyIs3MJKI9q5TtkIywPCn9CSFOlROaIWGmW yvcGNSXk31876aDx4MPYAsztBbxCwqcNC13twV7TSOALib6LRGeujh8N6BFUghubdXKF LW+SKElddZtB2nmXjau441qSKJ9llyvWdjLTjM4mzNB3tnSS7NuSa2Ay8uq+7k2tYuT4 ZvXASk5YTI6DaSMBZbBRH9f/WNxWYK2Vy0gbt96P2/1GePSyZYfuLsSVoYPR4C9TOO/Y RzoyEcQD+p1hOZp9UStVvPq8wLJFTB81LBalJL2+F1f/TOWGblmPy1/TXtAzx0SvmBms Y+NA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701996265; x=1702601065; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Rzx9Bm824S2wRWYFO7S2MdJvHvf/jzSVekqRFumNr7k=; b=Az0oOA15q47wbNrhgT9FyPE5/Bn8q+i5LXlQK6k+7QoEHN6yx2Rmg+Q36Mive6FoXJ EIFINIE83oYo0OstgE4PJjdski4VVRHBpi4rA6qe18PL1+IzKFK3w3xn2Hh2qom+yKnT 3bh0ud6kGrQH9G9ylZ2QQxJJJS4g83bEnQt5xWtDjV+22cDbHozCdmbFlFjZWMYYi9rL mS5qYh285icZZNEUTd9WLTzudCEXqZLt8H4B5NlC+j4LCPSXMN9Vsw5wvBG2TNo6drvm /kvY7wNUOpPIaW9ANJ6mEajM1T5T4mi5nZjDg4JPHVNfdxJ84SIAsl7fSNb8pBX2qDyv 6FPA== X-Gm-Message-State: AOJu0Yw0zLW8qZZr4MIwsQCfBpL5lgYxKmX6Oyb4JIRWj8XjqtHgD0JL D7Ed9CwkctCgB6QzPjMhvQQG9tK28ns62eQWitA= X-Google-Smtp-Source: AGHT+IEkooQEzU6pVeFzojl2VJJrOAtyIQajir1ICI20uMrx+iVRPimyAZGrVwQtJd87ZGXaQb4sWg== X-Received: by 2002:a2e:3512:0:b0:2c9:f803:7c05 with SMTP id z18-20020a2e3512000000b002c9f8037c05mr35588ljz.1.1701996265804; Thu, 07 Dec 2023 16:44:25 -0800 (PST) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id d1-20020a2eb041000000b002c9f2c7cdecsm82645ljl.22.2023.12.07.16.44.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Dec 2023 16:44:25 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v6 11/11] ARM: dts: qcom: ipq8064: drop 'regulator' property from SAW2 devices Date: Fri, 8 Dec 2023 03:44:17 +0300 Message-Id: <20231208004417.3393299-12-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231208004417.3393299-1-dmitry.baryshkov@linaro.org> References: <20231208004417.3393299-1-dmitry.baryshkov@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 The SAW2 device should describe the regulator constraints rather than just declaring that it has the regulator. Drop the 'regulator' property. If/when CPU voltage scaling is implemented for this platform, proper regulator nodes show be added instead. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi index c3677440b786..191d1cb27cb7 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi @@ -589,7 +589,6 @@ acc0: clock-controller@2088000 { saw0: regulator@2089000 { compatible = "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; }; acc1: clock-controller@2098000 { @@ -604,7 +603,6 @@ acc1: clock-controller@2098000 { saw1: regulator@2099000 { compatible = "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; }; nss_common: syscon@3000000 {